1 /* 2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips: 3 * - BMC150 4 * - BMI055 5 * - BMA255 6 * - BMA250E 7 * - BMA222E 8 * - BMA280 9 * 10 * Copyright (c) 2014, Intel Corporation. 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms and conditions of the GNU General Public License, 14 * version 2, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 */ 21 22 #include <linux/module.h> 23 #include <linux/i2c.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/acpi.h> 28 #include <linux/pm.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/iio/iio.h> 31 #include <linux/iio/sysfs.h> 32 #include <linux/iio/buffer.h> 33 #include <linux/iio/events.h> 34 #include <linux/iio/trigger.h> 35 #include <linux/iio/trigger_consumer.h> 36 #include <linux/iio/triggered_buffer.h> 37 #include <linux/regmap.h> 38 39 #include "bmc150-accel.h" 40 41 #define BMC150_ACCEL_DRV_NAME "bmc150_accel" 42 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" 43 44 #define BMC150_ACCEL_REG_CHIP_ID 0x00 45 46 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B 47 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07 48 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) 49 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) 50 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) 51 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) 52 53 #define BMC150_ACCEL_REG_PMU_LPW 0x11 54 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0 55 #define BMC150_ACCEL_PMU_MODE_SHIFT 5 56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 58 59 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F 60 61 #define BMC150_ACCEL_DEF_RANGE_2G 0x03 62 #define BMC150_ACCEL_DEF_RANGE_4G 0x05 63 #define BMC150_ACCEL_DEF_RANGE_8G 0x08 64 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C 65 66 /* Default BW: 125Hz */ 67 #define BMC150_ACCEL_REG_PMU_BW 0x10 68 #define BMC150_ACCEL_DEF_BW 125 69 70 #define BMC150_ACCEL_REG_RESET 0x14 71 #define BMC150_ACCEL_RESET_VAL 0xB6 72 73 #define BMC150_ACCEL_REG_INT_MAP_0 0x19 74 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) 75 76 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A 77 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) 78 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) 79 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) 80 81 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 82 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 83 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F 84 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 85 86 #define BMC150_ACCEL_REG_INT_EN_0 0x16 87 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) 88 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) 89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) 90 91 #define BMC150_ACCEL_REG_INT_EN_1 0x17 92 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) 93 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) 94 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) 95 96 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 97 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) 98 99 #define BMC150_ACCEL_REG_INT_5 0x27 100 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 101 102 #define BMC150_ACCEL_REG_INT_6 0x28 103 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF 104 105 /* Slope duration in terms of number of samples */ 106 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1 107 /* in terms of multiples of g's/LSB, based on range */ 108 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 109 110 #define BMC150_ACCEL_REG_XOUT_L 0x02 111 112 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 113 114 /* Sleep Duration values */ 115 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05 116 #define BMC150_ACCEL_SLEEP_1_MS 0x06 117 #define BMC150_ACCEL_SLEEP_2_MS 0x07 118 #define BMC150_ACCEL_SLEEP_4_MS 0x08 119 #define BMC150_ACCEL_SLEEP_6_MS 0x09 120 #define BMC150_ACCEL_SLEEP_10_MS 0x0A 121 #define BMC150_ACCEL_SLEEP_25_MS 0x0B 122 #define BMC150_ACCEL_SLEEP_50_MS 0x0C 123 #define BMC150_ACCEL_SLEEP_100_MS 0x0D 124 #define BMC150_ACCEL_SLEEP_500_MS 0x0E 125 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F 126 127 #define BMC150_ACCEL_REG_TEMP 0x08 128 #define BMC150_ACCEL_TEMP_CENTER_VAL 24 129 130 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) 131 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 132 133 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E 134 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 135 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E 136 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F 137 #define BMC150_ACCEL_FIFO_LENGTH 32 138 139 enum bmc150_accel_axis { 140 AXIS_X, 141 AXIS_Y, 142 AXIS_Z, 143 AXIS_MAX, 144 }; 145 146 enum bmc150_power_modes { 147 BMC150_ACCEL_SLEEP_MODE_NORMAL, 148 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 149 BMC150_ACCEL_SLEEP_MODE_LPM, 150 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, 151 }; 152 153 struct bmc150_scale_info { 154 int scale; 155 u8 reg_range; 156 }; 157 158 struct bmc150_accel_chip_info { 159 const char *name; 160 u8 chip_id; 161 const struct iio_chan_spec *channels; 162 int num_channels; 163 const struct bmc150_scale_info scale_table[4]; 164 }; 165 166 struct bmc150_accel_interrupt { 167 const struct bmc150_accel_interrupt_info *info; 168 atomic_t users; 169 }; 170 171 struct bmc150_accel_trigger { 172 struct bmc150_accel_data *data; 173 struct iio_trigger *indio_trig; 174 int (*setup)(struct bmc150_accel_trigger *t, bool state); 175 int intr; 176 bool enabled; 177 }; 178 179 enum bmc150_accel_interrupt_id { 180 BMC150_ACCEL_INT_DATA_READY, 181 BMC150_ACCEL_INT_ANY_MOTION, 182 BMC150_ACCEL_INT_WATERMARK, 183 BMC150_ACCEL_INTERRUPTS, 184 }; 185 186 enum bmc150_accel_trigger_id { 187 BMC150_ACCEL_TRIGGER_DATA_READY, 188 BMC150_ACCEL_TRIGGER_ANY_MOTION, 189 BMC150_ACCEL_TRIGGERS, 190 }; 191 192 struct bmc150_accel_data { 193 struct regmap *regmap; 194 int irq; 195 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS]; 196 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; 197 struct mutex mutex; 198 u8 fifo_mode, watermark; 199 s16 buffer[8]; 200 u8 bw_bits; 201 u32 slope_dur; 202 u32 slope_thres; 203 u32 range; 204 int ev_enable_state; 205 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 206 const struct bmc150_accel_chip_info *chip_info; 207 struct iio_mount_matrix orientation; 208 }; 209 210 static const struct { 211 int val; 212 int val2; 213 u8 bw_bits; 214 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08}, 215 {31, 260000, 0x09}, 216 {62, 500000, 0x0A}, 217 {125, 0, 0x0B}, 218 {250, 0, 0x0C}, 219 {500, 0, 0x0D}, 220 {1000, 0, 0x0E}, 221 {2000, 0, 0x0F} }; 222 223 static const struct { 224 int bw_bits; 225 int msec; 226 } bmc150_accel_sample_upd_time[] = { {0x08, 64}, 227 {0x09, 32}, 228 {0x0A, 16}, 229 {0x0B, 8}, 230 {0x0C, 4}, 231 {0x0D, 2}, 232 {0x0E, 1}, 233 {0x0F, 1} }; 234 235 static const struct { 236 int sleep_dur; 237 u8 reg_value; 238 } bmc150_accel_sleep_value_table[] = { {0, 0}, 239 {500, BMC150_ACCEL_SLEEP_500_MICRO}, 240 {1000, BMC150_ACCEL_SLEEP_1_MS}, 241 {2000, BMC150_ACCEL_SLEEP_2_MS}, 242 {4000, BMC150_ACCEL_SLEEP_4_MS}, 243 {6000, BMC150_ACCEL_SLEEP_6_MS}, 244 {10000, BMC150_ACCEL_SLEEP_10_MS}, 245 {25000, BMC150_ACCEL_SLEEP_25_MS}, 246 {50000, BMC150_ACCEL_SLEEP_50_MS}, 247 {100000, BMC150_ACCEL_SLEEP_100_MS}, 248 {500000, BMC150_ACCEL_SLEEP_500_MS}, 249 {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; 250 251 const struct regmap_config bmc150_regmap_conf = { 252 .reg_bits = 8, 253 .val_bits = 8, 254 .max_register = 0x3f, 255 }; 256 EXPORT_SYMBOL_GPL(bmc150_regmap_conf); 257 258 static int bmc150_accel_set_mode(struct bmc150_accel_data *data, 259 enum bmc150_power_modes mode, 260 int dur_us) 261 { 262 struct device *dev = regmap_get_device(data->regmap); 263 int i; 264 int ret; 265 u8 lpw_bits; 266 int dur_val = -1; 267 268 if (dur_us > 0) { 269 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); 270 ++i) { 271 if (bmc150_accel_sleep_value_table[i].sleep_dur == 272 dur_us) 273 dur_val = 274 bmc150_accel_sleep_value_table[i].reg_value; 275 } 276 } else { 277 dur_val = 0; 278 } 279 280 if (dur_val < 0) 281 return -EINVAL; 282 283 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; 284 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); 285 286 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits); 287 288 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits); 289 if (ret < 0) { 290 dev_err(dev, "Error writing reg_pmu_lpw\n"); 291 return ret; 292 } 293 294 return 0; 295 } 296 297 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, 298 int val2) 299 { 300 int i; 301 int ret; 302 303 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 304 if (bmc150_accel_samp_freq_table[i].val == val && 305 bmc150_accel_samp_freq_table[i].val2 == val2) { 306 ret = regmap_write(data->regmap, 307 BMC150_ACCEL_REG_PMU_BW, 308 bmc150_accel_samp_freq_table[i].bw_bits); 309 if (ret < 0) 310 return ret; 311 312 data->bw_bits = 313 bmc150_accel_samp_freq_table[i].bw_bits; 314 return 0; 315 } 316 } 317 318 return -EINVAL; 319 } 320 321 static int bmc150_accel_update_slope(struct bmc150_accel_data *data) 322 { 323 struct device *dev = regmap_get_device(data->regmap); 324 int ret; 325 326 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6, 327 data->slope_thres); 328 if (ret < 0) { 329 dev_err(dev, "Error writing reg_int_6\n"); 330 return ret; 331 } 332 333 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5, 334 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur); 335 if (ret < 0) { 336 dev_err(dev, "Error updating reg_int_5\n"); 337 return ret; 338 } 339 340 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur); 341 342 return ret; 343 } 344 345 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t, 346 bool state) 347 { 348 if (state) 349 return bmc150_accel_update_slope(t->data); 350 351 return 0; 352 } 353 354 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, 355 int *val2) 356 { 357 int i; 358 359 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 360 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { 361 *val = bmc150_accel_samp_freq_table[i].val; 362 *val2 = bmc150_accel_samp_freq_table[i].val2; 363 return IIO_VAL_INT_PLUS_MICRO; 364 } 365 } 366 367 return -EINVAL; 368 } 369 370 #ifdef CONFIG_PM 371 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) 372 { 373 int i; 374 375 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { 376 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) 377 return bmc150_accel_sample_upd_time[i].msec; 378 } 379 380 return BMC150_ACCEL_MAX_STARTUP_TIME_MS; 381 } 382 383 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 384 { 385 struct device *dev = regmap_get_device(data->regmap); 386 int ret; 387 388 if (on) { 389 ret = pm_runtime_get_sync(dev); 390 } else { 391 pm_runtime_mark_last_busy(dev); 392 ret = pm_runtime_put_autosuspend(dev); 393 } 394 395 if (ret < 0) { 396 dev_err(dev, 397 "Failed: %s for %d\n", __func__, on); 398 if (on) 399 pm_runtime_put_noidle(dev); 400 401 return ret; 402 } 403 404 return 0; 405 } 406 #else 407 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 408 { 409 return 0; 410 } 411 #endif 412 413 static const struct bmc150_accel_interrupt_info { 414 u8 map_reg; 415 u8 map_bitmask; 416 u8 en_reg; 417 u8 en_bitmask; 418 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = { 419 { /* data ready interrupt */ 420 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 421 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA, 422 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 423 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, 424 }, 425 { /* motion interrupt */ 426 .map_reg = BMC150_ACCEL_REG_INT_MAP_0, 427 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE, 428 .en_reg = BMC150_ACCEL_REG_INT_EN_0, 429 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | 430 BMC150_ACCEL_INT_EN_BIT_SLP_Y | 431 BMC150_ACCEL_INT_EN_BIT_SLP_Z 432 }, 433 { /* fifo watermark interrupt */ 434 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 435 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM, 436 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 437 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, 438 }, 439 }; 440 441 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, 442 struct bmc150_accel_data *data) 443 { 444 int i; 445 446 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++) 447 data->interrupts[i].info = &bmc150_accel_interrupts[i]; 448 } 449 450 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, 451 bool state) 452 { 453 struct device *dev = regmap_get_device(data->regmap); 454 struct bmc150_accel_interrupt *intr = &data->interrupts[i]; 455 const struct bmc150_accel_interrupt_info *info = intr->info; 456 int ret; 457 458 if (state) { 459 if (atomic_inc_return(&intr->users) > 1) 460 return 0; 461 } else { 462 if (atomic_dec_return(&intr->users) > 0) 463 return 0; 464 } 465 466 /* 467 * We will expect the enable and disable to do operation in reverse 468 * order. This will happen here anyway, as our resume operation uses 469 * sync mode runtime pm calls. The suspend operation will be delayed 470 * by autosuspend delay. 471 * So the disable operation will still happen in reverse order of 472 * enable operation. When runtime pm is disabled the mode is always on, 473 * so sequence doesn't matter. 474 */ 475 ret = bmc150_accel_set_power_state(data, state); 476 if (ret < 0) 477 return ret; 478 479 /* map the interrupt to the appropriate pins */ 480 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask, 481 (state ? info->map_bitmask : 0)); 482 if (ret < 0) { 483 dev_err(dev, "Error updating reg_int_map\n"); 484 goto out_fix_power_state; 485 } 486 487 /* enable/disable the interrupt */ 488 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask, 489 (state ? info->en_bitmask : 0)); 490 if (ret < 0) { 491 dev_err(dev, "Error updating reg_int_en\n"); 492 goto out_fix_power_state; 493 } 494 495 return 0; 496 497 out_fix_power_state: 498 bmc150_accel_set_power_state(data, false); 499 return ret; 500 } 501 502 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) 503 { 504 struct device *dev = regmap_get_device(data->regmap); 505 int ret, i; 506 507 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { 508 if (data->chip_info->scale_table[i].scale == val) { 509 ret = regmap_write(data->regmap, 510 BMC150_ACCEL_REG_PMU_RANGE, 511 data->chip_info->scale_table[i].reg_range); 512 if (ret < 0) { 513 dev_err(dev, "Error writing pmu_range\n"); 514 return ret; 515 } 516 517 data->range = data->chip_info->scale_table[i].reg_range; 518 return 0; 519 } 520 } 521 522 return -EINVAL; 523 } 524 525 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) 526 { 527 struct device *dev = regmap_get_device(data->regmap); 528 int ret; 529 unsigned int value; 530 531 mutex_lock(&data->mutex); 532 533 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value); 534 if (ret < 0) { 535 dev_err(dev, "Error reading reg_temp\n"); 536 mutex_unlock(&data->mutex); 537 return ret; 538 } 539 *val = sign_extend32(value, 7); 540 541 mutex_unlock(&data->mutex); 542 543 return IIO_VAL_INT; 544 } 545 546 static int bmc150_accel_get_axis(struct bmc150_accel_data *data, 547 struct iio_chan_spec const *chan, 548 int *val) 549 { 550 struct device *dev = regmap_get_device(data->regmap); 551 int ret; 552 int axis = chan->scan_index; 553 __le16 raw_val; 554 555 mutex_lock(&data->mutex); 556 ret = bmc150_accel_set_power_state(data, true); 557 if (ret < 0) { 558 mutex_unlock(&data->mutex); 559 return ret; 560 } 561 562 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis), 563 &raw_val, sizeof(raw_val)); 564 if (ret < 0) { 565 dev_err(dev, "Error reading axis %d\n", axis); 566 bmc150_accel_set_power_state(data, false); 567 mutex_unlock(&data->mutex); 568 return ret; 569 } 570 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift, 571 chan->scan_type.realbits - 1); 572 ret = bmc150_accel_set_power_state(data, false); 573 mutex_unlock(&data->mutex); 574 if (ret < 0) 575 return ret; 576 577 return IIO_VAL_INT; 578 } 579 580 static int bmc150_accel_read_raw(struct iio_dev *indio_dev, 581 struct iio_chan_spec const *chan, 582 int *val, int *val2, long mask) 583 { 584 struct bmc150_accel_data *data = iio_priv(indio_dev); 585 int ret; 586 587 switch (mask) { 588 case IIO_CHAN_INFO_RAW: 589 switch (chan->type) { 590 case IIO_TEMP: 591 return bmc150_accel_get_temp(data, val); 592 case IIO_ACCEL: 593 if (iio_buffer_enabled(indio_dev)) 594 return -EBUSY; 595 else 596 return bmc150_accel_get_axis(data, chan, val); 597 default: 598 return -EINVAL; 599 } 600 case IIO_CHAN_INFO_OFFSET: 601 if (chan->type == IIO_TEMP) { 602 *val = BMC150_ACCEL_TEMP_CENTER_VAL; 603 return IIO_VAL_INT; 604 } else { 605 return -EINVAL; 606 } 607 case IIO_CHAN_INFO_SCALE: 608 *val = 0; 609 switch (chan->type) { 610 case IIO_TEMP: 611 *val2 = 500000; 612 return IIO_VAL_INT_PLUS_MICRO; 613 case IIO_ACCEL: 614 { 615 int i; 616 const struct bmc150_scale_info *si; 617 int st_size = ARRAY_SIZE(data->chip_info->scale_table); 618 619 for (i = 0; i < st_size; ++i) { 620 si = &data->chip_info->scale_table[i]; 621 if (si->reg_range == data->range) { 622 *val2 = si->scale; 623 return IIO_VAL_INT_PLUS_MICRO; 624 } 625 } 626 return -EINVAL; 627 } 628 default: 629 return -EINVAL; 630 } 631 case IIO_CHAN_INFO_SAMP_FREQ: 632 mutex_lock(&data->mutex); 633 ret = bmc150_accel_get_bw(data, val, val2); 634 mutex_unlock(&data->mutex); 635 return ret; 636 default: 637 return -EINVAL; 638 } 639 } 640 641 static int bmc150_accel_write_raw(struct iio_dev *indio_dev, 642 struct iio_chan_spec const *chan, 643 int val, int val2, long mask) 644 { 645 struct bmc150_accel_data *data = iio_priv(indio_dev); 646 int ret; 647 648 switch (mask) { 649 case IIO_CHAN_INFO_SAMP_FREQ: 650 mutex_lock(&data->mutex); 651 ret = bmc150_accel_set_bw(data, val, val2); 652 mutex_unlock(&data->mutex); 653 break; 654 case IIO_CHAN_INFO_SCALE: 655 if (val) 656 return -EINVAL; 657 658 mutex_lock(&data->mutex); 659 ret = bmc150_accel_set_scale(data, val2); 660 mutex_unlock(&data->mutex); 661 return ret; 662 default: 663 ret = -EINVAL; 664 } 665 666 return ret; 667 } 668 669 static int bmc150_accel_read_event(struct iio_dev *indio_dev, 670 const struct iio_chan_spec *chan, 671 enum iio_event_type type, 672 enum iio_event_direction dir, 673 enum iio_event_info info, 674 int *val, int *val2) 675 { 676 struct bmc150_accel_data *data = iio_priv(indio_dev); 677 678 *val2 = 0; 679 switch (info) { 680 case IIO_EV_INFO_VALUE: 681 *val = data->slope_thres; 682 break; 683 case IIO_EV_INFO_PERIOD: 684 *val = data->slope_dur; 685 break; 686 default: 687 return -EINVAL; 688 } 689 690 return IIO_VAL_INT; 691 } 692 693 static int bmc150_accel_write_event(struct iio_dev *indio_dev, 694 const struct iio_chan_spec *chan, 695 enum iio_event_type type, 696 enum iio_event_direction dir, 697 enum iio_event_info info, 698 int val, int val2) 699 { 700 struct bmc150_accel_data *data = iio_priv(indio_dev); 701 702 if (data->ev_enable_state) 703 return -EBUSY; 704 705 switch (info) { 706 case IIO_EV_INFO_VALUE: 707 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; 708 break; 709 case IIO_EV_INFO_PERIOD: 710 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; 711 break; 712 default: 713 return -EINVAL; 714 } 715 716 return 0; 717 } 718 719 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, 720 const struct iio_chan_spec *chan, 721 enum iio_event_type type, 722 enum iio_event_direction dir) 723 { 724 struct bmc150_accel_data *data = iio_priv(indio_dev); 725 726 return data->ev_enable_state; 727 } 728 729 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, 730 const struct iio_chan_spec *chan, 731 enum iio_event_type type, 732 enum iio_event_direction dir, 733 int state) 734 { 735 struct bmc150_accel_data *data = iio_priv(indio_dev); 736 int ret; 737 738 if (state == data->ev_enable_state) 739 return 0; 740 741 mutex_lock(&data->mutex); 742 743 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION, 744 state); 745 if (ret < 0) { 746 mutex_unlock(&data->mutex); 747 return ret; 748 } 749 750 data->ev_enable_state = state; 751 mutex_unlock(&data->mutex); 752 753 return 0; 754 } 755 756 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, 757 struct iio_trigger *trig) 758 { 759 struct bmc150_accel_data *data = iio_priv(indio_dev); 760 int i; 761 762 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 763 if (data->triggers[i].indio_trig == trig) 764 return 0; 765 } 766 767 return -EINVAL; 768 } 769 770 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, 771 struct device_attribute *attr, 772 char *buf) 773 { 774 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 775 struct bmc150_accel_data *data = iio_priv(indio_dev); 776 int wm; 777 778 mutex_lock(&data->mutex); 779 wm = data->watermark; 780 mutex_unlock(&data->mutex); 781 782 return sprintf(buf, "%d\n", wm); 783 } 784 785 static ssize_t bmc150_accel_get_fifo_state(struct device *dev, 786 struct device_attribute *attr, 787 char *buf) 788 { 789 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 790 struct bmc150_accel_data *data = iio_priv(indio_dev); 791 bool state; 792 793 mutex_lock(&data->mutex); 794 state = data->fifo_mode; 795 mutex_unlock(&data->mutex); 796 797 return sprintf(buf, "%d\n", state); 798 } 799 800 static const struct iio_mount_matrix * 801 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev, 802 const struct iio_chan_spec *chan) 803 { 804 struct bmc150_accel_data *data = iio_priv(indio_dev); 805 806 return &data->orientation; 807 } 808 809 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = { 810 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix), 811 { } 812 }; 813 814 static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 815 static IIO_CONST_ATTR(hwfifo_watermark_max, 816 __stringify(BMC150_ACCEL_FIFO_LENGTH)); 817 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, 818 bmc150_accel_get_fifo_state, NULL, 0); 819 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, 820 bmc150_accel_get_fifo_watermark, NULL, 0); 821 822 static const struct attribute *bmc150_accel_fifo_attributes[] = { 823 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 824 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 825 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 826 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 827 NULL, 828 }; 829 830 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) 831 { 832 struct bmc150_accel_data *data = iio_priv(indio_dev); 833 834 if (val > BMC150_ACCEL_FIFO_LENGTH) 835 val = BMC150_ACCEL_FIFO_LENGTH; 836 837 mutex_lock(&data->mutex); 838 data->watermark = val; 839 mutex_unlock(&data->mutex); 840 841 return 0; 842 } 843 844 /* 845 * We must read at least one full frame in one burst, otherwise the rest of the 846 * frame data is discarded. 847 */ 848 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data, 849 char *buffer, int samples) 850 { 851 struct device *dev = regmap_get_device(data->regmap); 852 int sample_length = 3 * 2; 853 int ret; 854 int total_length = samples * sample_length; 855 856 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA, 857 buffer, total_length); 858 if (ret) 859 dev_err(dev, 860 "Error transferring data from fifo: %d\n", ret); 861 862 return ret; 863 } 864 865 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, 866 unsigned samples, bool irq) 867 { 868 struct bmc150_accel_data *data = iio_priv(indio_dev); 869 struct device *dev = regmap_get_device(data->regmap); 870 int ret, i; 871 u8 count; 872 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; 873 int64_t tstamp; 874 uint64_t sample_period; 875 unsigned int val; 876 877 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val); 878 if (ret < 0) { 879 dev_err(dev, "Error reading reg_fifo_status\n"); 880 return ret; 881 } 882 883 count = val & 0x7F; 884 885 if (!count) 886 return 0; 887 888 /* 889 * If we getting called from IRQ handler we know the stored timestamp is 890 * fairly accurate for the last stored sample. Otherwise, if we are 891 * called as a result of a read operation from userspace and hence 892 * before the watermark interrupt was triggered, take a timestamp 893 * now. We can fall anywhere in between two samples so the error in this 894 * case is at most one sample period. 895 */ 896 if (!irq) { 897 data->old_timestamp = data->timestamp; 898 data->timestamp = iio_get_time_ns(indio_dev); 899 } 900 901 /* 902 * Approximate timestamps for each of the sample based on the sampling 903 * frequency, timestamp for last sample and number of samples. 904 * 905 * Note that we can't use the current bandwidth settings to compute the 906 * sample period because the sample rate varies with the device 907 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That 908 * small variation adds when we store a large number of samples and 909 * creates significant jitter between the last and first samples in 910 * different batches (e.g. 32ms vs 21ms). 911 * 912 * To avoid this issue we compute the actual sample period ourselves 913 * based on the timestamp delta between the last two flush operations. 914 */ 915 sample_period = (data->timestamp - data->old_timestamp); 916 do_div(sample_period, count); 917 tstamp = data->timestamp - (count - 1) * sample_period; 918 919 if (samples && count > samples) 920 count = samples; 921 922 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count); 923 if (ret) 924 return ret; 925 926 /* 927 * Ideally we want the IIO core to handle the demux when running in fifo 928 * mode but not when running in triggered buffer mode. Unfortunately 929 * this does not seem to be possible, so stick with driver demux for 930 * now. 931 */ 932 for (i = 0; i < count; i++) { 933 u16 sample[8]; 934 int j, bit; 935 936 j = 0; 937 for_each_set_bit(bit, indio_dev->active_scan_mask, 938 indio_dev->masklength) 939 memcpy(&sample[j++], &buffer[i * 3 + bit], 2); 940 941 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp); 942 943 tstamp += sample_period; 944 } 945 946 return count; 947 } 948 949 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) 950 { 951 struct bmc150_accel_data *data = iio_priv(indio_dev); 952 int ret; 953 954 mutex_lock(&data->mutex); 955 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); 956 mutex_unlock(&data->mutex); 957 958 return ret; 959 } 960 961 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 962 "15.620000 31.260000 62.50000 125 250 500 1000 2000"); 963 964 static struct attribute *bmc150_accel_attributes[] = { 965 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 966 NULL, 967 }; 968 969 static const struct attribute_group bmc150_accel_attrs_group = { 970 .attrs = bmc150_accel_attributes, 971 }; 972 973 static const struct iio_event_spec bmc150_accel_event = { 974 .type = IIO_EV_TYPE_ROC, 975 .dir = IIO_EV_DIR_EITHER, 976 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 977 BIT(IIO_EV_INFO_ENABLE) | 978 BIT(IIO_EV_INFO_PERIOD) 979 }; 980 981 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \ 982 .type = IIO_ACCEL, \ 983 .modified = 1, \ 984 .channel2 = IIO_MOD_##_axis, \ 985 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 986 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 987 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 988 .scan_index = AXIS_##_axis, \ 989 .scan_type = { \ 990 .sign = 's', \ 991 .realbits = (bits), \ 992 .storagebits = 16, \ 993 .shift = 16 - (bits), \ 994 .endianness = IIO_LE, \ 995 }, \ 996 .ext_info = bmc150_accel_ext_info, \ 997 .event_spec = &bmc150_accel_event, \ 998 .num_event_specs = 1 \ 999 } 1000 1001 #define BMC150_ACCEL_CHANNELS(bits) { \ 1002 { \ 1003 .type = IIO_TEMP, \ 1004 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1005 BIT(IIO_CHAN_INFO_SCALE) | \ 1006 BIT(IIO_CHAN_INFO_OFFSET), \ 1007 .scan_index = -1, \ 1008 }, \ 1009 BMC150_ACCEL_CHANNEL(X, bits), \ 1010 BMC150_ACCEL_CHANNEL(Y, bits), \ 1011 BMC150_ACCEL_CHANNEL(Z, bits), \ 1012 IIO_CHAN_SOFT_TIMESTAMP(3), \ 1013 } 1014 1015 static const struct iio_chan_spec bma222e_accel_channels[] = 1016 BMC150_ACCEL_CHANNELS(8); 1017 static const struct iio_chan_spec bma250e_accel_channels[] = 1018 BMC150_ACCEL_CHANNELS(10); 1019 static const struct iio_chan_spec bmc150_accel_channels[] = 1020 BMC150_ACCEL_CHANNELS(12); 1021 static const struct iio_chan_spec bma280_accel_channels[] = 1022 BMC150_ACCEL_CHANNELS(14); 1023 1024 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { 1025 [bmc150] = { 1026 .name = "BMC150A", 1027 .chip_id = 0xFA, 1028 .channels = bmc150_accel_channels, 1029 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1030 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1031 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1032 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1033 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1034 }, 1035 [bmi055] = { 1036 .name = "BMI055A", 1037 .chip_id = 0xFA, 1038 .channels = bmc150_accel_channels, 1039 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1040 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1041 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1042 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1043 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1044 }, 1045 [bma255] = { 1046 .name = "BMA0255", 1047 .chip_id = 0xFA, 1048 .channels = bmc150_accel_channels, 1049 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1050 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1051 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1052 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1053 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1054 }, 1055 [bma250e] = { 1056 .name = "BMA250E", 1057 .chip_id = 0xF9, 1058 .channels = bma250e_accel_channels, 1059 .num_channels = ARRAY_SIZE(bma250e_accel_channels), 1060 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G}, 1061 {76590, BMC150_ACCEL_DEF_RANGE_4G}, 1062 {153277, BMC150_ACCEL_DEF_RANGE_8G}, 1063 {306457, BMC150_ACCEL_DEF_RANGE_16G} }, 1064 }, 1065 [bma222e] = { 1066 .name = "BMA222E", 1067 .chip_id = 0xF8, 1068 .channels = bma222e_accel_channels, 1069 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 1070 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G}, 1071 {306457, BMC150_ACCEL_DEF_RANGE_4G}, 1072 {612915, BMC150_ACCEL_DEF_RANGE_8G}, 1073 {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, 1074 }, 1075 [bma280] = { 1076 .name = "BMA0280", 1077 .chip_id = 0xFB, 1078 .channels = bma280_accel_channels, 1079 .num_channels = ARRAY_SIZE(bma280_accel_channels), 1080 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G}, 1081 {4785, BMC150_ACCEL_DEF_RANGE_4G}, 1082 {9581, BMC150_ACCEL_DEF_RANGE_8G}, 1083 {19152, BMC150_ACCEL_DEF_RANGE_16G} }, 1084 }, 1085 }; 1086 1087 static const struct iio_info bmc150_accel_info = { 1088 .attrs = &bmc150_accel_attrs_group, 1089 .read_raw = bmc150_accel_read_raw, 1090 .write_raw = bmc150_accel_write_raw, 1091 .read_event_value = bmc150_accel_read_event, 1092 .write_event_value = bmc150_accel_write_event, 1093 .write_event_config = bmc150_accel_write_event_config, 1094 .read_event_config = bmc150_accel_read_event_config, 1095 }; 1096 1097 static const struct iio_info bmc150_accel_info_fifo = { 1098 .attrs = &bmc150_accel_attrs_group, 1099 .read_raw = bmc150_accel_read_raw, 1100 .write_raw = bmc150_accel_write_raw, 1101 .read_event_value = bmc150_accel_read_event, 1102 .write_event_value = bmc150_accel_write_event, 1103 .write_event_config = bmc150_accel_write_event_config, 1104 .read_event_config = bmc150_accel_read_event_config, 1105 .validate_trigger = bmc150_accel_validate_trigger, 1106 .hwfifo_set_watermark = bmc150_accel_set_watermark, 1107 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, 1108 }; 1109 1110 static const unsigned long bmc150_accel_scan_masks[] = { 1111 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 1112 0}; 1113 1114 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) 1115 { 1116 struct iio_poll_func *pf = p; 1117 struct iio_dev *indio_dev = pf->indio_dev; 1118 struct bmc150_accel_data *data = iio_priv(indio_dev); 1119 int ret; 1120 1121 mutex_lock(&data->mutex); 1122 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L, 1123 data->buffer, AXIS_MAX * 2); 1124 mutex_unlock(&data->mutex); 1125 if (ret < 0) 1126 goto err_read; 1127 1128 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 1129 pf->timestamp); 1130 err_read: 1131 iio_trigger_notify_done(indio_dev->trig); 1132 1133 return IRQ_HANDLED; 1134 } 1135 1136 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig) 1137 { 1138 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1139 struct bmc150_accel_data *data = t->data; 1140 struct device *dev = regmap_get_device(data->regmap); 1141 int ret; 1142 1143 /* new data interrupts don't need ack */ 1144 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY]) 1145 return 0; 1146 1147 mutex_lock(&data->mutex); 1148 /* clear any latched interrupt */ 1149 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1150 BMC150_ACCEL_INT_MODE_LATCH_INT | 1151 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1152 mutex_unlock(&data->mutex); 1153 if (ret < 0) { 1154 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1155 return ret; 1156 } 1157 1158 return 0; 1159 } 1160 1161 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, 1162 bool state) 1163 { 1164 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1165 struct bmc150_accel_data *data = t->data; 1166 int ret; 1167 1168 mutex_lock(&data->mutex); 1169 1170 if (t->enabled == state) { 1171 mutex_unlock(&data->mutex); 1172 return 0; 1173 } 1174 1175 if (t->setup) { 1176 ret = t->setup(t, state); 1177 if (ret < 0) { 1178 mutex_unlock(&data->mutex); 1179 return ret; 1180 } 1181 } 1182 1183 ret = bmc150_accel_set_interrupt(data, t->intr, state); 1184 if (ret < 0) { 1185 mutex_unlock(&data->mutex); 1186 return ret; 1187 } 1188 1189 t->enabled = state; 1190 1191 mutex_unlock(&data->mutex); 1192 1193 return ret; 1194 } 1195 1196 static const struct iio_trigger_ops bmc150_accel_trigger_ops = { 1197 .set_trigger_state = bmc150_accel_trigger_set_state, 1198 .try_reenable = bmc150_accel_trig_try_reen, 1199 }; 1200 1201 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) 1202 { 1203 struct bmc150_accel_data *data = iio_priv(indio_dev); 1204 struct device *dev = regmap_get_device(data->regmap); 1205 int dir; 1206 int ret; 1207 unsigned int val; 1208 1209 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val); 1210 if (ret < 0) { 1211 dev_err(dev, "Error reading reg_int_status_2\n"); 1212 return ret; 1213 } 1214 1215 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) 1216 dir = IIO_EV_DIR_FALLING; 1217 else 1218 dir = IIO_EV_DIR_RISING; 1219 1220 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X) 1221 iio_push_event(indio_dev, 1222 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1223 0, 1224 IIO_MOD_X, 1225 IIO_EV_TYPE_ROC, 1226 dir), 1227 data->timestamp); 1228 1229 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y) 1230 iio_push_event(indio_dev, 1231 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1232 0, 1233 IIO_MOD_Y, 1234 IIO_EV_TYPE_ROC, 1235 dir), 1236 data->timestamp); 1237 1238 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z) 1239 iio_push_event(indio_dev, 1240 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1241 0, 1242 IIO_MOD_Z, 1243 IIO_EV_TYPE_ROC, 1244 dir), 1245 data->timestamp); 1246 1247 return ret; 1248 } 1249 1250 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) 1251 { 1252 struct iio_dev *indio_dev = private; 1253 struct bmc150_accel_data *data = iio_priv(indio_dev); 1254 struct device *dev = regmap_get_device(data->regmap); 1255 bool ack = false; 1256 int ret; 1257 1258 mutex_lock(&data->mutex); 1259 1260 if (data->fifo_mode) { 1261 ret = __bmc150_accel_fifo_flush(indio_dev, 1262 BMC150_ACCEL_FIFO_LENGTH, true); 1263 if (ret > 0) 1264 ack = true; 1265 } 1266 1267 if (data->ev_enable_state) { 1268 ret = bmc150_accel_handle_roc_event(indio_dev); 1269 if (ret > 0) 1270 ack = true; 1271 } 1272 1273 if (ack) { 1274 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1275 BMC150_ACCEL_INT_MODE_LATCH_INT | 1276 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1277 if (ret) 1278 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1279 1280 ret = IRQ_HANDLED; 1281 } else { 1282 ret = IRQ_NONE; 1283 } 1284 1285 mutex_unlock(&data->mutex); 1286 1287 return ret; 1288 } 1289 1290 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) 1291 { 1292 struct iio_dev *indio_dev = private; 1293 struct bmc150_accel_data *data = iio_priv(indio_dev); 1294 bool ack = false; 1295 int i; 1296 1297 data->old_timestamp = data->timestamp; 1298 data->timestamp = iio_get_time_ns(indio_dev); 1299 1300 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1301 if (data->triggers[i].enabled) { 1302 iio_trigger_poll(data->triggers[i].indio_trig); 1303 ack = true; 1304 break; 1305 } 1306 } 1307 1308 if (data->ev_enable_state || data->fifo_mode) 1309 return IRQ_WAKE_THREAD; 1310 1311 if (ack) 1312 return IRQ_HANDLED; 1313 1314 return IRQ_NONE; 1315 } 1316 1317 static const struct { 1318 int intr; 1319 const char *name; 1320 int (*setup)(struct bmc150_accel_trigger *t, bool state); 1321 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = { 1322 { 1323 .intr = 0, 1324 .name = "%s-dev%d", 1325 }, 1326 { 1327 .intr = 1, 1328 .name = "%s-any-motion-dev%d", 1329 .setup = bmc150_accel_any_motion_setup, 1330 }, 1331 }; 1332 1333 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data, 1334 int from) 1335 { 1336 int i; 1337 1338 for (i = from; i >= 0; i--) { 1339 if (data->triggers[i].indio_trig) { 1340 iio_trigger_unregister(data->triggers[i].indio_trig); 1341 data->triggers[i].indio_trig = NULL; 1342 } 1343 } 1344 } 1345 1346 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, 1347 struct bmc150_accel_data *data) 1348 { 1349 struct device *dev = regmap_get_device(data->regmap); 1350 int i, ret; 1351 1352 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1353 struct bmc150_accel_trigger *t = &data->triggers[i]; 1354 1355 t->indio_trig = devm_iio_trigger_alloc(dev, 1356 bmc150_accel_triggers[i].name, 1357 indio_dev->name, 1358 indio_dev->id); 1359 if (!t->indio_trig) { 1360 ret = -ENOMEM; 1361 break; 1362 } 1363 1364 t->indio_trig->dev.parent = dev; 1365 t->indio_trig->ops = &bmc150_accel_trigger_ops; 1366 t->intr = bmc150_accel_triggers[i].intr; 1367 t->data = data; 1368 t->setup = bmc150_accel_triggers[i].setup; 1369 iio_trigger_set_drvdata(t->indio_trig, t); 1370 1371 ret = iio_trigger_register(t->indio_trig); 1372 if (ret) 1373 break; 1374 } 1375 1376 if (ret) 1377 bmc150_accel_unregister_triggers(data, i - 1); 1378 1379 return ret; 1380 } 1381 1382 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 1383 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 1384 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 1385 1386 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) 1387 { 1388 struct device *dev = regmap_get_device(data->regmap); 1389 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; 1390 int ret; 1391 1392 ret = regmap_write(data->regmap, reg, data->fifo_mode); 1393 if (ret < 0) { 1394 dev_err(dev, "Error writing reg_fifo_config1\n"); 1395 return ret; 1396 } 1397 1398 if (!data->fifo_mode) 1399 return 0; 1400 1401 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0, 1402 data->watermark); 1403 if (ret < 0) 1404 dev_err(dev, "Error writing reg_fifo_config0\n"); 1405 1406 return ret; 1407 } 1408 1409 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev) 1410 { 1411 struct bmc150_accel_data *data = iio_priv(indio_dev); 1412 1413 return bmc150_accel_set_power_state(data, true); 1414 } 1415 1416 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) 1417 { 1418 struct bmc150_accel_data *data = iio_priv(indio_dev); 1419 int ret = 0; 1420 1421 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1422 return iio_triggered_buffer_postenable(indio_dev); 1423 1424 mutex_lock(&data->mutex); 1425 1426 if (!data->watermark) 1427 goto out; 1428 1429 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1430 true); 1431 if (ret) 1432 goto out; 1433 1434 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; 1435 1436 ret = bmc150_accel_fifo_set_mode(data); 1437 if (ret) { 1438 data->fifo_mode = 0; 1439 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1440 false); 1441 } 1442 1443 out: 1444 mutex_unlock(&data->mutex); 1445 1446 return ret; 1447 } 1448 1449 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) 1450 { 1451 struct bmc150_accel_data *data = iio_priv(indio_dev); 1452 1453 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1454 return iio_triggered_buffer_predisable(indio_dev); 1455 1456 mutex_lock(&data->mutex); 1457 1458 if (!data->fifo_mode) 1459 goto out; 1460 1461 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); 1462 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); 1463 data->fifo_mode = 0; 1464 bmc150_accel_fifo_set_mode(data); 1465 1466 out: 1467 mutex_unlock(&data->mutex); 1468 1469 return 0; 1470 } 1471 1472 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev) 1473 { 1474 struct bmc150_accel_data *data = iio_priv(indio_dev); 1475 1476 return bmc150_accel_set_power_state(data, false); 1477 } 1478 1479 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { 1480 .preenable = bmc150_accel_buffer_preenable, 1481 .postenable = bmc150_accel_buffer_postenable, 1482 .predisable = bmc150_accel_buffer_predisable, 1483 .postdisable = bmc150_accel_buffer_postdisable, 1484 }; 1485 1486 static int bmc150_accel_chip_init(struct bmc150_accel_data *data) 1487 { 1488 struct device *dev = regmap_get_device(data->regmap); 1489 int ret, i; 1490 unsigned int val; 1491 1492 /* 1493 * Reset chip to get it in a known good state. A delay of 1.8ms after 1494 * reset is required according to the data sheets of supported chips. 1495 */ 1496 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET, 1497 BMC150_ACCEL_RESET_VAL); 1498 usleep_range(1800, 2500); 1499 1500 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val); 1501 if (ret < 0) { 1502 dev_err(dev, "Error: Reading chip id\n"); 1503 return ret; 1504 } 1505 1506 dev_dbg(dev, "Chip Id %x\n", val); 1507 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) { 1508 if (bmc150_accel_chip_info_tbl[i].chip_id == val) { 1509 data->chip_info = &bmc150_accel_chip_info_tbl[i]; 1510 break; 1511 } 1512 } 1513 1514 if (!data->chip_info) { 1515 dev_err(dev, "Invalid chip %x\n", val); 1516 return -ENODEV; 1517 } 1518 1519 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1520 if (ret < 0) 1521 return ret; 1522 1523 /* Set Bandwidth */ 1524 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); 1525 if (ret < 0) 1526 return ret; 1527 1528 /* Set Default Range */ 1529 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE, 1530 BMC150_ACCEL_DEF_RANGE_4G); 1531 if (ret < 0) { 1532 dev_err(dev, "Error writing reg_pmu_range\n"); 1533 return ret; 1534 } 1535 1536 data->range = BMC150_ACCEL_DEF_RANGE_4G; 1537 1538 /* Set default slope duration and thresholds */ 1539 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; 1540 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION; 1541 ret = bmc150_accel_update_slope(data); 1542 if (ret < 0) 1543 return ret; 1544 1545 /* Set default as latched interrupts */ 1546 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1547 BMC150_ACCEL_INT_MODE_LATCH_INT | 1548 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1549 if (ret < 0) { 1550 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1551 return ret; 1552 } 1553 1554 return 0; 1555 } 1556 1557 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq, 1558 const char *name, bool block_supported) 1559 { 1560 struct bmc150_accel_data *data; 1561 struct iio_dev *indio_dev; 1562 int ret; 1563 1564 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1565 if (!indio_dev) 1566 return -ENOMEM; 1567 1568 data = iio_priv(indio_dev); 1569 dev_set_drvdata(dev, indio_dev); 1570 data->irq = irq; 1571 1572 data->regmap = regmap; 1573 1574 ret = iio_read_mount_matrix(dev, "mount-matrix", 1575 &data->orientation); 1576 if (ret) 1577 return ret; 1578 1579 ret = bmc150_accel_chip_init(data); 1580 if (ret < 0) 1581 return ret; 1582 1583 mutex_init(&data->mutex); 1584 1585 indio_dev->dev.parent = dev; 1586 indio_dev->channels = data->chip_info->channels; 1587 indio_dev->num_channels = data->chip_info->num_channels; 1588 indio_dev->name = name ? name : data->chip_info->name; 1589 indio_dev->available_scan_masks = bmc150_accel_scan_masks; 1590 indio_dev->modes = INDIO_DIRECT_MODE; 1591 indio_dev->info = &bmc150_accel_info; 1592 1593 ret = iio_triggered_buffer_setup(indio_dev, 1594 &iio_pollfunc_store_time, 1595 bmc150_accel_trigger_handler, 1596 &bmc150_accel_buffer_ops); 1597 if (ret < 0) { 1598 dev_err(dev, "Failed: iio triggered buffer setup\n"); 1599 return ret; 1600 } 1601 1602 if (data->irq > 0) { 1603 ret = devm_request_threaded_irq( 1604 dev, data->irq, 1605 bmc150_accel_irq_handler, 1606 bmc150_accel_irq_thread_handler, 1607 IRQF_TRIGGER_RISING, 1608 BMC150_ACCEL_IRQ_NAME, 1609 indio_dev); 1610 if (ret) 1611 goto err_buffer_cleanup; 1612 1613 /* 1614 * Set latched mode interrupt. While certain interrupts are 1615 * non-latched regardless of this settings (e.g. new data) we 1616 * want to use latch mode when we can to prevent interrupt 1617 * flooding. 1618 */ 1619 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1620 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1621 if (ret < 0) { 1622 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1623 goto err_buffer_cleanup; 1624 } 1625 1626 bmc150_accel_interrupts_setup(indio_dev, data); 1627 1628 ret = bmc150_accel_triggers_setup(indio_dev, data); 1629 if (ret) 1630 goto err_buffer_cleanup; 1631 1632 if (block_supported) { 1633 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 1634 indio_dev->info = &bmc150_accel_info_fifo; 1635 iio_buffer_set_attrs(indio_dev->buffer, 1636 bmc150_accel_fifo_attributes); 1637 } 1638 } 1639 1640 ret = pm_runtime_set_active(dev); 1641 if (ret) 1642 goto err_trigger_unregister; 1643 1644 pm_runtime_enable(dev); 1645 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS); 1646 pm_runtime_use_autosuspend(dev); 1647 1648 ret = iio_device_register(indio_dev); 1649 if (ret < 0) { 1650 dev_err(dev, "Unable to register iio device\n"); 1651 goto err_trigger_unregister; 1652 } 1653 1654 return 0; 1655 1656 err_trigger_unregister: 1657 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1658 err_buffer_cleanup: 1659 iio_triggered_buffer_cleanup(indio_dev); 1660 1661 return ret; 1662 } 1663 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe); 1664 1665 int bmc150_accel_core_remove(struct device *dev) 1666 { 1667 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1668 struct bmc150_accel_data *data = iio_priv(indio_dev); 1669 1670 iio_device_unregister(indio_dev); 1671 1672 pm_runtime_disable(dev); 1673 pm_runtime_set_suspended(dev); 1674 pm_runtime_put_noidle(dev); 1675 1676 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1677 1678 iio_triggered_buffer_cleanup(indio_dev); 1679 1680 mutex_lock(&data->mutex); 1681 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); 1682 mutex_unlock(&data->mutex); 1683 1684 return 0; 1685 } 1686 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove); 1687 1688 #ifdef CONFIG_PM_SLEEP 1689 static int bmc150_accel_suspend(struct device *dev) 1690 { 1691 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1692 struct bmc150_accel_data *data = iio_priv(indio_dev); 1693 1694 mutex_lock(&data->mutex); 1695 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1696 mutex_unlock(&data->mutex); 1697 1698 return 0; 1699 } 1700 1701 static int bmc150_accel_resume(struct device *dev) 1702 { 1703 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1704 struct bmc150_accel_data *data = iio_priv(indio_dev); 1705 1706 mutex_lock(&data->mutex); 1707 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1708 bmc150_accel_fifo_set_mode(data); 1709 mutex_unlock(&data->mutex); 1710 1711 return 0; 1712 } 1713 #endif 1714 1715 #ifdef CONFIG_PM 1716 static int bmc150_accel_runtime_suspend(struct device *dev) 1717 { 1718 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1719 struct bmc150_accel_data *data = iio_priv(indio_dev); 1720 int ret; 1721 1722 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1723 if (ret < 0) 1724 return -EAGAIN; 1725 1726 return 0; 1727 } 1728 1729 static int bmc150_accel_runtime_resume(struct device *dev) 1730 { 1731 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1732 struct bmc150_accel_data *data = iio_priv(indio_dev); 1733 int ret; 1734 int sleep_val; 1735 1736 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1737 if (ret < 0) 1738 return ret; 1739 ret = bmc150_accel_fifo_set_mode(data); 1740 if (ret < 0) 1741 return ret; 1742 1743 sleep_val = bmc150_accel_get_startup_times(data); 1744 if (sleep_val < 20) 1745 usleep_range(sleep_val * 1000, 20000); 1746 else 1747 msleep_interruptible(sleep_val); 1748 1749 return 0; 1750 } 1751 #endif 1752 1753 const struct dev_pm_ops bmc150_accel_pm_ops = { 1754 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) 1755 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, 1756 bmc150_accel_runtime_resume, NULL) 1757 }; 1758 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops); 1759 1760 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1761 MODULE_LICENSE("GPL v2"); 1762 MODULE_DESCRIPTION("BMC150 accelerometer driver"); 1763