1 /* 2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips: 3 * - BMC150 4 * - BMI055 5 * - BMA255 6 * - BMA250E 7 * - BMA222E 8 * - BMA280 9 * 10 * Copyright (c) 2014, Intel Corporation. 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms and conditions of the GNU General Public License, 14 * version 2, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 */ 21 22 #include <linux/module.h> 23 #include <linux/i2c.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/acpi.h> 28 #include <linux/pm.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/iio/iio.h> 31 #include <linux/iio/sysfs.h> 32 #include <linux/iio/buffer.h> 33 #include <linux/iio/events.h> 34 #include <linux/iio/trigger.h> 35 #include <linux/iio/trigger_consumer.h> 36 #include <linux/iio/triggered_buffer.h> 37 #include <linux/regmap.h> 38 39 #include "bmc150-accel.h" 40 41 #define BMC150_ACCEL_DRV_NAME "bmc150_accel" 42 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" 43 44 #define BMC150_ACCEL_REG_CHIP_ID 0x00 45 46 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B 47 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07 48 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) 49 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) 50 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) 51 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) 52 53 #define BMC150_ACCEL_REG_PMU_LPW 0x11 54 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0 55 #define BMC150_ACCEL_PMU_MODE_SHIFT 5 56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 58 59 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F 60 61 #define BMC150_ACCEL_DEF_RANGE_2G 0x03 62 #define BMC150_ACCEL_DEF_RANGE_4G 0x05 63 #define BMC150_ACCEL_DEF_RANGE_8G 0x08 64 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C 65 66 /* Default BW: 125Hz */ 67 #define BMC150_ACCEL_REG_PMU_BW 0x10 68 #define BMC150_ACCEL_DEF_BW 125 69 70 #define BMC150_ACCEL_REG_INT_MAP_0 0x19 71 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) 72 73 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A 74 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) 75 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) 76 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) 77 78 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 79 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 80 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F 81 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 82 83 #define BMC150_ACCEL_REG_INT_EN_0 0x16 84 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) 85 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) 86 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) 87 88 #define BMC150_ACCEL_REG_INT_EN_1 0x17 89 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) 90 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) 91 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) 92 93 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 94 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) 95 96 #define BMC150_ACCEL_REG_INT_5 0x27 97 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 98 99 #define BMC150_ACCEL_REG_INT_6 0x28 100 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF 101 102 /* Slope duration in terms of number of samples */ 103 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1 104 /* in terms of multiples of g's/LSB, based on range */ 105 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 106 107 #define BMC150_ACCEL_REG_XOUT_L 0x02 108 109 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 110 111 /* Sleep Duration values */ 112 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05 113 #define BMC150_ACCEL_SLEEP_1_MS 0x06 114 #define BMC150_ACCEL_SLEEP_2_MS 0x07 115 #define BMC150_ACCEL_SLEEP_4_MS 0x08 116 #define BMC150_ACCEL_SLEEP_6_MS 0x09 117 #define BMC150_ACCEL_SLEEP_10_MS 0x0A 118 #define BMC150_ACCEL_SLEEP_25_MS 0x0B 119 #define BMC150_ACCEL_SLEEP_50_MS 0x0C 120 #define BMC150_ACCEL_SLEEP_100_MS 0x0D 121 #define BMC150_ACCEL_SLEEP_500_MS 0x0E 122 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F 123 124 #define BMC150_ACCEL_REG_TEMP 0x08 125 #define BMC150_ACCEL_TEMP_CENTER_VAL 24 126 127 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) 128 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 129 130 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E 131 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 132 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E 133 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F 134 #define BMC150_ACCEL_FIFO_LENGTH 32 135 136 enum bmc150_accel_axis { 137 AXIS_X, 138 AXIS_Y, 139 AXIS_Z, 140 AXIS_MAX, 141 }; 142 143 enum bmc150_power_modes { 144 BMC150_ACCEL_SLEEP_MODE_NORMAL, 145 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 146 BMC150_ACCEL_SLEEP_MODE_LPM, 147 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, 148 }; 149 150 struct bmc150_scale_info { 151 int scale; 152 u8 reg_range; 153 }; 154 155 struct bmc150_accel_chip_info { 156 const char *name; 157 u8 chip_id; 158 const struct iio_chan_spec *channels; 159 int num_channels; 160 const struct bmc150_scale_info scale_table[4]; 161 }; 162 163 struct bmc150_accel_interrupt { 164 const struct bmc150_accel_interrupt_info *info; 165 atomic_t users; 166 }; 167 168 struct bmc150_accel_trigger { 169 struct bmc150_accel_data *data; 170 struct iio_trigger *indio_trig; 171 int (*setup)(struct bmc150_accel_trigger *t, bool state); 172 int intr; 173 bool enabled; 174 }; 175 176 enum bmc150_accel_interrupt_id { 177 BMC150_ACCEL_INT_DATA_READY, 178 BMC150_ACCEL_INT_ANY_MOTION, 179 BMC150_ACCEL_INT_WATERMARK, 180 BMC150_ACCEL_INTERRUPTS, 181 }; 182 183 enum bmc150_accel_trigger_id { 184 BMC150_ACCEL_TRIGGER_DATA_READY, 185 BMC150_ACCEL_TRIGGER_ANY_MOTION, 186 BMC150_ACCEL_TRIGGERS, 187 }; 188 189 struct bmc150_accel_data { 190 struct regmap *regmap; 191 int irq; 192 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS]; 193 atomic_t active_intr; 194 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; 195 struct mutex mutex; 196 u8 fifo_mode, watermark; 197 s16 buffer[8]; 198 u8 bw_bits; 199 u32 slope_dur; 200 u32 slope_thres; 201 u32 range; 202 int ev_enable_state; 203 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 204 const struct bmc150_accel_chip_info *chip_info; 205 }; 206 207 static const struct { 208 int val; 209 int val2; 210 u8 bw_bits; 211 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08}, 212 {31, 260000, 0x09}, 213 {62, 500000, 0x0A}, 214 {125, 0, 0x0B}, 215 {250, 0, 0x0C}, 216 {500, 0, 0x0D}, 217 {1000, 0, 0x0E}, 218 {2000, 0, 0x0F} }; 219 220 static const struct { 221 int bw_bits; 222 int msec; 223 } bmc150_accel_sample_upd_time[] = { {0x08, 64}, 224 {0x09, 32}, 225 {0x0A, 16}, 226 {0x0B, 8}, 227 {0x0C, 4}, 228 {0x0D, 2}, 229 {0x0E, 1}, 230 {0x0F, 1} }; 231 232 static const struct { 233 int sleep_dur; 234 u8 reg_value; 235 } bmc150_accel_sleep_value_table[] = { {0, 0}, 236 {500, BMC150_ACCEL_SLEEP_500_MICRO}, 237 {1000, BMC150_ACCEL_SLEEP_1_MS}, 238 {2000, BMC150_ACCEL_SLEEP_2_MS}, 239 {4000, BMC150_ACCEL_SLEEP_4_MS}, 240 {6000, BMC150_ACCEL_SLEEP_6_MS}, 241 {10000, BMC150_ACCEL_SLEEP_10_MS}, 242 {25000, BMC150_ACCEL_SLEEP_25_MS}, 243 {50000, BMC150_ACCEL_SLEEP_50_MS}, 244 {100000, BMC150_ACCEL_SLEEP_100_MS}, 245 {500000, BMC150_ACCEL_SLEEP_500_MS}, 246 {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; 247 248 const struct regmap_config bmc150_regmap_conf = { 249 .reg_bits = 8, 250 .val_bits = 8, 251 .max_register = 0x3f, 252 }; 253 EXPORT_SYMBOL_GPL(bmc150_regmap_conf); 254 255 static int bmc150_accel_set_mode(struct bmc150_accel_data *data, 256 enum bmc150_power_modes mode, 257 int dur_us) 258 { 259 struct device *dev = regmap_get_device(data->regmap); 260 int i; 261 int ret; 262 u8 lpw_bits; 263 int dur_val = -1; 264 265 if (dur_us > 0) { 266 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); 267 ++i) { 268 if (bmc150_accel_sleep_value_table[i].sleep_dur == 269 dur_us) 270 dur_val = 271 bmc150_accel_sleep_value_table[i].reg_value; 272 } 273 } else { 274 dur_val = 0; 275 } 276 277 if (dur_val < 0) 278 return -EINVAL; 279 280 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; 281 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); 282 283 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits); 284 285 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits); 286 if (ret < 0) { 287 dev_err(dev, "Error writing reg_pmu_lpw\n"); 288 return ret; 289 } 290 291 return 0; 292 } 293 294 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, 295 int val2) 296 { 297 int i; 298 int ret; 299 300 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 301 if (bmc150_accel_samp_freq_table[i].val == val && 302 bmc150_accel_samp_freq_table[i].val2 == val2) { 303 ret = regmap_write(data->regmap, 304 BMC150_ACCEL_REG_PMU_BW, 305 bmc150_accel_samp_freq_table[i].bw_bits); 306 if (ret < 0) 307 return ret; 308 309 data->bw_bits = 310 bmc150_accel_samp_freq_table[i].bw_bits; 311 return 0; 312 } 313 } 314 315 return -EINVAL; 316 } 317 318 static int bmc150_accel_update_slope(struct bmc150_accel_data *data) 319 { 320 struct device *dev = regmap_get_device(data->regmap); 321 int ret; 322 323 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6, 324 data->slope_thres); 325 if (ret < 0) { 326 dev_err(dev, "Error writing reg_int_6\n"); 327 return ret; 328 } 329 330 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5, 331 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur); 332 if (ret < 0) { 333 dev_err(dev, "Error updating reg_int_5\n"); 334 return ret; 335 } 336 337 dev_dbg(dev, "%s: %x %x\n", __func__, data->slope_thres, 338 data->slope_dur); 339 340 return ret; 341 } 342 343 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t, 344 bool state) 345 { 346 if (state) 347 return bmc150_accel_update_slope(t->data); 348 349 return 0; 350 } 351 352 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, 353 int *val2) 354 { 355 int i; 356 357 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 358 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { 359 *val = bmc150_accel_samp_freq_table[i].val; 360 *val2 = bmc150_accel_samp_freq_table[i].val2; 361 return IIO_VAL_INT_PLUS_MICRO; 362 } 363 } 364 365 return -EINVAL; 366 } 367 368 #ifdef CONFIG_PM 369 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) 370 { 371 int i; 372 373 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { 374 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) 375 return bmc150_accel_sample_upd_time[i].msec; 376 } 377 378 return BMC150_ACCEL_MAX_STARTUP_TIME_MS; 379 } 380 381 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 382 { 383 struct device *dev = regmap_get_device(data->regmap); 384 int ret; 385 386 if (on) { 387 ret = pm_runtime_get_sync(dev); 388 } else { 389 pm_runtime_mark_last_busy(dev); 390 ret = pm_runtime_put_autosuspend(dev); 391 } 392 393 if (ret < 0) { 394 dev_err(dev, 395 "Failed: bmc150_accel_set_power_state for %d\n", on); 396 if (on) 397 pm_runtime_put_noidle(dev); 398 399 return ret; 400 } 401 402 return 0; 403 } 404 #else 405 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 406 { 407 return 0; 408 } 409 #endif 410 411 static const struct bmc150_accel_interrupt_info { 412 u8 map_reg; 413 u8 map_bitmask; 414 u8 en_reg; 415 u8 en_bitmask; 416 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = { 417 { /* data ready interrupt */ 418 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 419 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA, 420 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 421 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, 422 }, 423 { /* motion interrupt */ 424 .map_reg = BMC150_ACCEL_REG_INT_MAP_0, 425 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE, 426 .en_reg = BMC150_ACCEL_REG_INT_EN_0, 427 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | 428 BMC150_ACCEL_INT_EN_BIT_SLP_Y | 429 BMC150_ACCEL_INT_EN_BIT_SLP_Z 430 }, 431 { /* fifo watermark interrupt */ 432 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 433 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM, 434 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 435 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, 436 }, 437 }; 438 439 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, 440 struct bmc150_accel_data *data) 441 { 442 int i; 443 444 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++) 445 data->interrupts[i].info = &bmc150_accel_interrupts[i]; 446 } 447 448 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, 449 bool state) 450 { 451 struct device *dev = regmap_get_device(data->regmap); 452 struct bmc150_accel_interrupt *intr = &data->interrupts[i]; 453 const struct bmc150_accel_interrupt_info *info = intr->info; 454 int ret; 455 456 if (state) { 457 if (atomic_inc_return(&intr->users) > 1) 458 return 0; 459 } else { 460 if (atomic_dec_return(&intr->users) > 0) 461 return 0; 462 } 463 464 /* 465 * We will expect the enable and disable to do operation in reverse 466 * order. This will happen here anyway, as our resume operation uses 467 * sync mode runtime pm calls. The suspend operation will be delayed 468 * by autosuspend delay. 469 * So the disable operation will still happen in reverse order of 470 * enable operation. When runtime pm is disabled the mode is always on, 471 * so sequence doesn't matter. 472 */ 473 ret = bmc150_accel_set_power_state(data, state); 474 if (ret < 0) 475 return ret; 476 477 /* map the interrupt to the appropriate pins */ 478 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask, 479 (state ? info->map_bitmask : 0)); 480 if (ret < 0) { 481 dev_err(dev, "Error updating reg_int_map\n"); 482 goto out_fix_power_state; 483 } 484 485 /* enable/disable the interrupt */ 486 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask, 487 (state ? info->en_bitmask : 0)); 488 if (ret < 0) { 489 dev_err(dev, "Error updating reg_int_en\n"); 490 goto out_fix_power_state; 491 } 492 493 if (state) 494 atomic_inc(&data->active_intr); 495 else 496 atomic_dec(&data->active_intr); 497 498 return 0; 499 500 out_fix_power_state: 501 bmc150_accel_set_power_state(data, false); 502 return ret; 503 } 504 505 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) 506 { 507 struct device *dev = regmap_get_device(data->regmap); 508 int ret, i; 509 510 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { 511 if (data->chip_info->scale_table[i].scale == val) { 512 ret = regmap_write(data->regmap, 513 BMC150_ACCEL_REG_PMU_RANGE, 514 data->chip_info->scale_table[i].reg_range); 515 if (ret < 0) { 516 dev_err(dev, "Error writing pmu_range\n"); 517 return ret; 518 } 519 520 data->range = data->chip_info->scale_table[i].reg_range; 521 return 0; 522 } 523 } 524 525 return -EINVAL; 526 } 527 528 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) 529 { 530 struct device *dev = regmap_get_device(data->regmap); 531 int ret; 532 unsigned int value; 533 534 mutex_lock(&data->mutex); 535 536 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value); 537 if (ret < 0) { 538 dev_err(dev, "Error reading reg_temp\n"); 539 mutex_unlock(&data->mutex); 540 return ret; 541 } 542 *val = sign_extend32(value, 7); 543 544 mutex_unlock(&data->mutex); 545 546 return IIO_VAL_INT; 547 } 548 549 static int bmc150_accel_get_axis(struct bmc150_accel_data *data, 550 struct iio_chan_spec const *chan, 551 int *val) 552 { 553 struct device *dev = regmap_get_device(data->regmap); 554 int ret; 555 int axis = chan->scan_index; 556 __le16 raw_val; 557 558 mutex_lock(&data->mutex); 559 ret = bmc150_accel_set_power_state(data, true); 560 if (ret < 0) { 561 mutex_unlock(&data->mutex); 562 return ret; 563 } 564 565 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis), 566 &raw_val, sizeof(raw_val)); 567 if (ret < 0) { 568 dev_err(dev, "Error reading axis %d\n", axis); 569 bmc150_accel_set_power_state(data, false); 570 mutex_unlock(&data->mutex); 571 return ret; 572 } 573 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift, 574 chan->scan_type.realbits - 1); 575 ret = bmc150_accel_set_power_state(data, false); 576 mutex_unlock(&data->mutex); 577 if (ret < 0) 578 return ret; 579 580 return IIO_VAL_INT; 581 } 582 583 static int bmc150_accel_read_raw(struct iio_dev *indio_dev, 584 struct iio_chan_spec const *chan, 585 int *val, int *val2, long mask) 586 { 587 struct bmc150_accel_data *data = iio_priv(indio_dev); 588 int ret; 589 590 switch (mask) { 591 case IIO_CHAN_INFO_RAW: 592 switch (chan->type) { 593 case IIO_TEMP: 594 return bmc150_accel_get_temp(data, val); 595 case IIO_ACCEL: 596 if (iio_buffer_enabled(indio_dev)) 597 return -EBUSY; 598 else 599 return bmc150_accel_get_axis(data, chan, val); 600 default: 601 return -EINVAL; 602 } 603 case IIO_CHAN_INFO_OFFSET: 604 if (chan->type == IIO_TEMP) { 605 *val = BMC150_ACCEL_TEMP_CENTER_VAL; 606 return IIO_VAL_INT; 607 } else { 608 return -EINVAL; 609 } 610 case IIO_CHAN_INFO_SCALE: 611 *val = 0; 612 switch (chan->type) { 613 case IIO_TEMP: 614 *val2 = 500000; 615 return IIO_VAL_INT_PLUS_MICRO; 616 case IIO_ACCEL: 617 { 618 int i; 619 const struct bmc150_scale_info *si; 620 int st_size = ARRAY_SIZE(data->chip_info->scale_table); 621 622 for (i = 0; i < st_size; ++i) { 623 si = &data->chip_info->scale_table[i]; 624 if (si->reg_range == data->range) { 625 *val2 = si->scale; 626 return IIO_VAL_INT_PLUS_MICRO; 627 } 628 } 629 return -EINVAL; 630 } 631 default: 632 return -EINVAL; 633 } 634 case IIO_CHAN_INFO_SAMP_FREQ: 635 mutex_lock(&data->mutex); 636 ret = bmc150_accel_get_bw(data, val, val2); 637 mutex_unlock(&data->mutex); 638 return ret; 639 default: 640 return -EINVAL; 641 } 642 } 643 644 static int bmc150_accel_write_raw(struct iio_dev *indio_dev, 645 struct iio_chan_spec const *chan, 646 int val, int val2, long mask) 647 { 648 struct bmc150_accel_data *data = iio_priv(indio_dev); 649 int ret; 650 651 switch (mask) { 652 case IIO_CHAN_INFO_SAMP_FREQ: 653 mutex_lock(&data->mutex); 654 ret = bmc150_accel_set_bw(data, val, val2); 655 mutex_unlock(&data->mutex); 656 break; 657 case IIO_CHAN_INFO_SCALE: 658 if (val) 659 return -EINVAL; 660 661 mutex_lock(&data->mutex); 662 ret = bmc150_accel_set_scale(data, val2); 663 mutex_unlock(&data->mutex); 664 return ret; 665 default: 666 ret = -EINVAL; 667 } 668 669 return ret; 670 } 671 672 static int bmc150_accel_read_event(struct iio_dev *indio_dev, 673 const struct iio_chan_spec *chan, 674 enum iio_event_type type, 675 enum iio_event_direction dir, 676 enum iio_event_info info, 677 int *val, int *val2) 678 { 679 struct bmc150_accel_data *data = iio_priv(indio_dev); 680 681 *val2 = 0; 682 switch (info) { 683 case IIO_EV_INFO_VALUE: 684 *val = data->slope_thres; 685 break; 686 case IIO_EV_INFO_PERIOD: 687 *val = data->slope_dur; 688 break; 689 default: 690 return -EINVAL; 691 } 692 693 return IIO_VAL_INT; 694 } 695 696 static int bmc150_accel_write_event(struct iio_dev *indio_dev, 697 const struct iio_chan_spec *chan, 698 enum iio_event_type type, 699 enum iio_event_direction dir, 700 enum iio_event_info info, 701 int val, int val2) 702 { 703 struct bmc150_accel_data *data = iio_priv(indio_dev); 704 705 if (data->ev_enable_state) 706 return -EBUSY; 707 708 switch (info) { 709 case IIO_EV_INFO_VALUE: 710 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; 711 break; 712 case IIO_EV_INFO_PERIOD: 713 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; 714 break; 715 default: 716 return -EINVAL; 717 } 718 719 return 0; 720 } 721 722 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, 723 const struct iio_chan_spec *chan, 724 enum iio_event_type type, 725 enum iio_event_direction dir) 726 { 727 struct bmc150_accel_data *data = iio_priv(indio_dev); 728 729 return data->ev_enable_state; 730 } 731 732 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, 733 const struct iio_chan_spec *chan, 734 enum iio_event_type type, 735 enum iio_event_direction dir, 736 int state) 737 { 738 struct bmc150_accel_data *data = iio_priv(indio_dev); 739 int ret; 740 741 if (state == data->ev_enable_state) 742 return 0; 743 744 mutex_lock(&data->mutex); 745 746 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION, 747 state); 748 if (ret < 0) { 749 mutex_unlock(&data->mutex); 750 return ret; 751 } 752 753 data->ev_enable_state = state; 754 mutex_unlock(&data->mutex); 755 756 return 0; 757 } 758 759 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, 760 struct iio_trigger *trig) 761 { 762 struct bmc150_accel_data *data = iio_priv(indio_dev); 763 int i; 764 765 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 766 if (data->triggers[i].indio_trig == trig) 767 return 0; 768 } 769 770 return -EINVAL; 771 } 772 773 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, 774 struct device_attribute *attr, 775 char *buf) 776 { 777 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 778 struct bmc150_accel_data *data = iio_priv(indio_dev); 779 int wm; 780 781 mutex_lock(&data->mutex); 782 wm = data->watermark; 783 mutex_unlock(&data->mutex); 784 785 return sprintf(buf, "%d\n", wm); 786 } 787 788 static ssize_t bmc150_accel_get_fifo_state(struct device *dev, 789 struct device_attribute *attr, 790 char *buf) 791 { 792 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 793 struct bmc150_accel_data *data = iio_priv(indio_dev); 794 bool state; 795 796 mutex_lock(&data->mutex); 797 state = data->fifo_mode; 798 mutex_unlock(&data->mutex); 799 800 return sprintf(buf, "%d\n", state); 801 } 802 803 static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 804 static IIO_CONST_ATTR(hwfifo_watermark_max, 805 __stringify(BMC150_ACCEL_FIFO_LENGTH)); 806 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, 807 bmc150_accel_get_fifo_state, NULL, 0); 808 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, 809 bmc150_accel_get_fifo_watermark, NULL, 0); 810 811 static const struct attribute *bmc150_accel_fifo_attributes[] = { 812 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 813 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 814 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 815 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 816 NULL, 817 }; 818 819 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) 820 { 821 struct bmc150_accel_data *data = iio_priv(indio_dev); 822 823 if (val > BMC150_ACCEL_FIFO_LENGTH) 824 val = BMC150_ACCEL_FIFO_LENGTH; 825 826 mutex_lock(&data->mutex); 827 data->watermark = val; 828 mutex_unlock(&data->mutex); 829 830 return 0; 831 } 832 833 /* 834 * We must read at least one full frame in one burst, otherwise the rest of the 835 * frame data is discarded. 836 */ 837 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data, 838 char *buffer, int samples) 839 { 840 struct device *dev = regmap_get_device(data->regmap); 841 int sample_length = 3 * 2; 842 int ret; 843 int total_length = samples * sample_length; 844 int i; 845 size_t step = regmap_get_raw_read_max(data->regmap); 846 847 if (!step || step > total_length) 848 step = total_length; 849 else if (step < total_length) 850 step = sample_length; 851 852 /* 853 * Seems we have a bus with size limitation so we have to execute 854 * multiple reads 855 */ 856 for (i = 0; i < total_length; i += step) { 857 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA, 858 &buffer[i], step); 859 if (ret) 860 break; 861 } 862 863 if (ret) 864 dev_err(dev, 865 "Error transferring data from fifo in single steps of %zu\n", 866 step); 867 868 return ret; 869 } 870 871 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, 872 unsigned samples, bool irq) 873 { 874 struct bmc150_accel_data *data = iio_priv(indio_dev); 875 struct device *dev = regmap_get_device(data->regmap); 876 int ret, i; 877 u8 count; 878 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; 879 int64_t tstamp; 880 uint64_t sample_period; 881 unsigned int val; 882 883 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val); 884 if (ret < 0) { 885 dev_err(dev, "Error reading reg_fifo_status\n"); 886 return ret; 887 } 888 889 count = val & 0x7F; 890 891 if (!count) 892 return 0; 893 894 /* 895 * If we getting called from IRQ handler we know the stored timestamp is 896 * fairly accurate for the last stored sample. Otherwise, if we are 897 * called as a result of a read operation from userspace and hence 898 * before the watermark interrupt was triggered, take a timestamp 899 * now. We can fall anywhere in between two samples so the error in this 900 * case is at most one sample period. 901 */ 902 if (!irq) { 903 data->old_timestamp = data->timestamp; 904 data->timestamp = iio_get_time_ns(indio_dev); 905 } 906 907 /* 908 * Approximate timestamps for each of the sample based on the sampling 909 * frequency, timestamp for last sample and number of samples. 910 * 911 * Note that we can't use the current bandwidth settings to compute the 912 * sample period because the sample rate varies with the device 913 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That 914 * small variation adds when we store a large number of samples and 915 * creates significant jitter between the last and first samples in 916 * different batches (e.g. 32ms vs 21ms). 917 * 918 * To avoid this issue we compute the actual sample period ourselves 919 * based on the timestamp delta between the last two flush operations. 920 */ 921 sample_period = (data->timestamp - data->old_timestamp); 922 do_div(sample_period, count); 923 tstamp = data->timestamp - (count - 1) * sample_period; 924 925 if (samples && count > samples) 926 count = samples; 927 928 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count); 929 if (ret) 930 return ret; 931 932 /* 933 * Ideally we want the IIO core to handle the demux when running in fifo 934 * mode but not when running in triggered buffer mode. Unfortunately 935 * this does not seem to be possible, so stick with driver demux for 936 * now. 937 */ 938 for (i = 0; i < count; i++) { 939 u16 sample[8]; 940 int j, bit; 941 942 j = 0; 943 for_each_set_bit(bit, indio_dev->active_scan_mask, 944 indio_dev->masklength) 945 memcpy(&sample[j++], &buffer[i * 3 + bit], 2); 946 947 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp); 948 949 tstamp += sample_period; 950 } 951 952 return count; 953 } 954 955 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) 956 { 957 struct bmc150_accel_data *data = iio_priv(indio_dev); 958 int ret; 959 960 mutex_lock(&data->mutex); 961 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); 962 mutex_unlock(&data->mutex); 963 964 return ret; 965 } 966 967 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 968 "15.620000 31.260000 62.50000 125 250 500 1000 2000"); 969 970 static struct attribute *bmc150_accel_attributes[] = { 971 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 972 NULL, 973 }; 974 975 static const struct attribute_group bmc150_accel_attrs_group = { 976 .attrs = bmc150_accel_attributes, 977 }; 978 979 static const struct iio_event_spec bmc150_accel_event = { 980 .type = IIO_EV_TYPE_ROC, 981 .dir = IIO_EV_DIR_EITHER, 982 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 983 BIT(IIO_EV_INFO_ENABLE) | 984 BIT(IIO_EV_INFO_PERIOD) 985 }; 986 987 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \ 988 .type = IIO_ACCEL, \ 989 .modified = 1, \ 990 .channel2 = IIO_MOD_##_axis, \ 991 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 992 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 993 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 994 .scan_index = AXIS_##_axis, \ 995 .scan_type = { \ 996 .sign = 's', \ 997 .realbits = (bits), \ 998 .storagebits = 16, \ 999 .shift = 16 - (bits), \ 1000 .endianness = IIO_LE, \ 1001 }, \ 1002 .event_spec = &bmc150_accel_event, \ 1003 .num_event_specs = 1 \ 1004 } 1005 1006 #define BMC150_ACCEL_CHANNELS(bits) { \ 1007 { \ 1008 .type = IIO_TEMP, \ 1009 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1010 BIT(IIO_CHAN_INFO_SCALE) | \ 1011 BIT(IIO_CHAN_INFO_OFFSET), \ 1012 .scan_index = -1, \ 1013 }, \ 1014 BMC150_ACCEL_CHANNEL(X, bits), \ 1015 BMC150_ACCEL_CHANNEL(Y, bits), \ 1016 BMC150_ACCEL_CHANNEL(Z, bits), \ 1017 IIO_CHAN_SOFT_TIMESTAMP(3), \ 1018 } 1019 1020 static const struct iio_chan_spec bma222e_accel_channels[] = 1021 BMC150_ACCEL_CHANNELS(8); 1022 static const struct iio_chan_spec bma250e_accel_channels[] = 1023 BMC150_ACCEL_CHANNELS(10); 1024 static const struct iio_chan_spec bmc150_accel_channels[] = 1025 BMC150_ACCEL_CHANNELS(12); 1026 static const struct iio_chan_spec bma280_accel_channels[] = 1027 BMC150_ACCEL_CHANNELS(14); 1028 1029 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { 1030 [bmc150] = { 1031 .name = "BMC150A", 1032 .chip_id = 0xFA, 1033 .channels = bmc150_accel_channels, 1034 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1035 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1036 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1037 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1038 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1039 }, 1040 [bmi055] = { 1041 .name = "BMI055A", 1042 .chip_id = 0xFA, 1043 .channels = bmc150_accel_channels, 1044 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1045 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1046 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1047 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1048 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1049 }, 1050 [bma255] = { 1051 .name = "BMA0255", 1052 .chip_id = 0xFA, 1053 .channels = bmc150_accel_channels, 1054 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1055 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1056 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1057 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1058 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1059 }, 1060 [bma250e] = { 1061 .name = "BMA250E", 1062 .chip_id = 0xF9, 1063 .channels = bma250e_accel_channels, 1064 .num_channels = ARRAY_SIZE(bma250e_accel_channels), 1065 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G}, 1066 {76590, BMC150_ACCEL_DEF_RANGE_4G}, 1067 {153277, BMC150_ACCEL_DEF_RANGE_8G}, 1068 {306457, BMC150_ACCEL_DEF_RANGE_16G} }, 1069 }, 1070 [bma222e] = { 1071 .name = "BMA222E", 1072 .chip_id = 0xF8, 1073 .channels = bma222e_accel_channels, 1074 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 1075 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G}, 1076 {306457, BMC150_ACCEL_DEF_RANGE_4G}, 1077 {612915, BMC150_ACCEL_DEF_RANGE_8G}, 1078 {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, 1079 }, 1080 [bma280] = { 1081 .name = "BMA0280", 1082 .chip_id = 0xFB, 1083 .channels = bma280_accel_channels, 1084 .num_channels = ARRAY_SIZE(bma280_accel_channels), 1085 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G}, 1086 {4785, BMC150_ACCEL_DEF_RANGE_4G}, 1087 {9581, BMC150_ACCEL_DEF_RANGE_8G}, 1088 {19152, BMC150_ACCEL_DEF_RANGE_16G} }, 1089 }, 1090 }; 1091 1092 static const struct iio_info bmc150_accel_info = { 1093 .attrs = &bmc150_accel_attrs_group, 1094 .read_raw = bmc150_accel_read_raw, 1095 .write_raw = bmc150_accel_write_raw, 1096 .read_event_value = bmc150_accel_read_event, 1097 .write_event_value = bmc150_accel_write_event, 1098 .write_event_config = bmc150_accel_write_event_config, 1099 .read_event_config = bmc150_accel_read_event_config, 1100 .driver_module = THIS_MODULE, 1101 }; 1102 1103 static const struct iio_info bmc150_accel_info_fifo = { 1104 .attrs = &bmc150_accel_attrs_group, 1105 .read_raw = bmc150_accel_read_raw, 1106 .write_raw = bmc150_accel_write_raw, 1107 .read_event_value = bmc150_accel_read_event, 1108 .write_event_value = bmc150_accel_write_event, 1109 .write_event_config = bmc150_accel_write_event_config, 1110 .read_event_config = bmc150_accel_read_event_config, 1111 .validate_trigger = bmc150_accel_validate_trigger, 1112 .hwfifo_set_watermark = bmc150_accel_set_watermark, 1113 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, 1114 .driver_module = THIS_MODULE, 1115 }; 1116 1117 static const unsigned long bmc150_accel_scan_masks[] = { 1118 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 1119 0}; 1120 1121 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) 1122 { 1123 struct iio_poll_func *pf = p; 1124 struct iio_dev *indio_dev = pf->indio_dev; 1125 struct bmc150_accel_data *data = iio_priv(indio_dev); 1126 int ret; 1127 1128 mutex_lock(&data->mutex); 1129 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L, 1130 data->buffer, AXIS_MAX * 2); 1131 mutex_unlock(&data->mutex); 1132 if (ret < 0) 1133 goto err_read; 1134 1135 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 1136 pf->timestamp); 1137 err_read: 1138 iio_trigger_notify_done(indio_dev->trig); 1139 1140 return IRQ_HANDLED; 1141 } 1142 1143 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig) 1144 { 1145 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1146 struct bmc150_accel_data *data = t->data; 1147 struct device *dev = regmap_get_device(data->regmap); 1148 int ret; 1149 1150 /* new data interrupts don't need ack */ 1151 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY]) 1152 return 0; 1153 1154 mutex_lock(&data->mutex); 1155 /* clear any latched interrupt */ 1156 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1157 BMC150_ACCEL_INT_MODE_LATCH_INT | 1158 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1159 mutex_unlock(&data->mutex); 1160 if (ret < 0) { 1161 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1162 return ret; 1163 } 1164 1165 return 0; 1166 } 1167 1168 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, 1169 bool state) 1170 { 1171 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1172 struct bmc150_accel_data *data = t->data; 1173 int ret; 1174 1175 mutex_lock(&data->mutex); 1176 1177 if (t->enabled == state) { 1178 mutex_unlock(&data->mutex); 1179 return 0; 1180 } 1181 1182 if (t->setup) { 1183 ret = t->setup(t, state); 1184 if (ret < 0) { 1185 mutex_unlock(&data->mutex); 1186 return ret; 1187 } 1188 } 1189 1190 ret = bmc150_accel_set_interrupt(data, t->intr, state); 1191 if (ret < 0) { 1192 mutex_unlock(&data->mutex); 1193 return ret; 1194 } 1195 1196 t->enabled = state; 1197 1198 mutex_unlock(&data->mutex); 1199 1200 return ret; 1201 } 1202 1203 static const struct iio_trigger_ops bmc150_accel_trigger_ops = { 1204 .set_trigger_state = bmc150_accel_trigger_set_state, 1205 .try_reenable = bmc150_accel_trig_try_reen, 1206 .owner = THIS_MODULE, 1207 }; 1208 1209 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) 1210 { 1211 struct bmc150_accel_data *data = iio_priv(indio_dev); 1212 struct device *dev = regmap_get_device(data->regmap); 1213 int dir; 1214 int ret; 1215 unsigned int val; 1216 1217 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val); 1218 if (ret < 0) { 1219 dev_err(dev, "Error reading reg_int_status_2\n"); 1220 return ret; 1221 } 1222 1223 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) 1224 dir = IIO_EV_DIR_FALLING; 1225 else 1226 dir = IIO_EV_DIR_RISING; 1227 1228 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X) 1229 iio_push_event(indio_dev, 1230 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1231 0, 1232 IIO_MOD_X, 1233 IIO_EV_TYPE_ROC, 1234 dir), 1235 data->timestamp); 1236 1237 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y) 1238 iio_push_event(indio_dev, 1239 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1240 0, 1241 IIO_MOD_Y, 1242 IIO_EV_TYPE_ROC, 1243 dir), 1244 data->timestamp); 1245 1246 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z) 1247 iio_push_event(indio_dev, 1248 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1249 0, 1250 IIO_MOD_Z, 1251 IIO_EV_TYPE_ROC, 1252 dir), 1253 data->timestamp); 1254 1255 return ret; 1256 } 1257 1258 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) 1259 { 1260 struct iio_dev *indio_dev = private; 1261 struct bmc150_accel_data *data = iio_priv(indio_dev); 1262 struct device *dev = regmap_get_device(data->regmap); 1263 bool ack = false; 1264 int ret; 1265 1266 mutex_lock(&data->mutex); 1267 1268 if (data->fifo_mode) { 1269 ret = __bmc150_accel_fifo_flush(indio_dev, 1270 BMC150_ACCEL_FIFO_LENGTH, true); 1271 if (ret > 0) 1272 ack = true; 1273 } 1274 1275 if (data->ev_enable_state) { 1276 ret = bmc150_accel_handle_roc_event(indio_dev); 1277 if (ret > 0) 1278 ack = true; 1279 } 1280 1281 if (ack) { 1282 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1283 BMC150_ACCEL_INT_MODE_LATCH_INT | 1284 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1285 if (ret) 1286 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1287 1288 ret = IRQ_HANDLED; 1289 } else { 1290 ret = IRQ_NONE; 1291 } 1292 1293 mutex_unlock(&data->mutex); 1294 1295 return ret; 1296 } 1297 1298 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) 1299 { 1300 struct iio_dev *indio_dev = private; 1301 struct bmc150_accel_data *data = iio_priv(indio_dev); 1302 bool ack = false; 1303 int i; 1304 1305 data->old_timestamp = data->timestamp; 1306 data->timestamp = iio_get_time_ns(indio_dev); 1307 1308 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1309 if (data->triggers[i].enabled) { 1310 iio_trigger_poll(data->triggers[i].indio_trig); 1311 ack = true; 1312 break; 1313 } 1314 } 1315 1316 if (data->ev_enable_state || data->fifo_mode) 1317 return IRQ_WAKE_THREAD; 1318 1319 if (ack) 1320 return IRQ_HANDLED; 1321 1322 return IRQ_NONE; 1323 } 1324 1325 static const struct { 1326 int intr; 1327 const char *name; 1328 int (*setup)(struct bmc150_accel_trigger *t, bool state); 1329 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = { 1330 { 1331 .intr = 0, 1332 .name = "%s-dev%d", 1333 }, 1334 { 1335 .intr = 1, 1336 .name = "%s-any-motion-dev%d", 1337 .setup = bmc150_accel_any_motion_setup, 1338 }, 1339 }; 1340 1341 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data, 1342 int from) 1343 { 1344 int i; 1345 1346 for (i = from; i >= 0; i--) { 1347 if (data->triggers[i].indio_trig) { 1348 iio_trigger_unregister(data->triggers[i].indio_trig); 1349 data->triggers[i].indio_trig = NULL; 1350 } 1351 } 1352 } 1353 1354 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, 1355 struct bmc150_accel_data *data) 1356 { 1357 struct device *dev = regmap_get_device(data->regmap); 1358 int i, ret; 1359 1360 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1361 struct bmc150_accel_trigger *t = &data->triggers[i]; 1362 1363 t->indio_trig = devm_iio_trigger_alloc(dev, 1364 bmc150_accel_triggers[i].name, 1365 indio_dev->name, 1366 indio_dev->id); 1367 if (!t->indio_trig) { 1368 ret = -ENOMEM; 1369 break; 1370 } 1371 1372 t->indio_trig->dev.parent = dev; 1373 t->indio_trig->ops = &bmc150_accel_trigger_ops; 1374 t->intr = bmc150_accel_triggers[i].intr; 1375 t->data = data; 1376 t->setup = bmc150_accel_triggers[i].setup; 1377 iio_trigger_set_drvdata(t->indio_trig, t); 1378 1379 ret = iio_trigger_register(t->indio_trig); 1380 if (ret) 1381 break; 1382 } 1383 1384 if (ret) 1385 bmc150_accel_unregister_triggers(data, i - 1); 1386 1387 return ret; 1388 } 1389 1390 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 1391 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 1392 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 1393 1394 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) 1395 { 1396 struct device *dev = regmap_get_device(data->regmap); 1397 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; 1398 int ret; 1399 1400 ret = regmap_write(data->regmap, reg, data->fifo_mode); 1401 if (ret < 0) { 1402 dev_err(dev, "Error writing reg_fifo_config1\n"); 1403 return ret; 1404 } 1405 1406 if (!data->fifo_mode) 1407 return 0; 1408 1409 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0, 1410 data->watermark); 1411 if (ret < 0) 1412 dev_err(dev, "Error writing reg_fifo_config0\n"); 1413 1414 return ret; 1415 } 1416 1417 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev) 1418 { 1419 struct bmc150_accel_data *data = iio_priv(indio_dev); 1420 1421 return bmc150_accel_set_power_state(data, true); 1422 } 1423 1424 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) 1425 { 1426 struct bmc150_accel_data *data = iio_priv(indio_dev); 1427 int ret = 0; 1428 1429 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1430 return iio_triggered_buffer_postenable(indio_dev); 1431 1432 mutex_lock(&data->mutex); 1433 1434 if (!data->watermark) 1435 goto out; 1436 1437 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1438 true); 1439 if (ret) 1440 goto out; 1441 1442 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; 1443 1444 ret = bmc150_accel_fifo_set_mode(data); 1445 if (ret) { 1446 data->fifo_mode = 0; 1447 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1448 false); 1449 } 1450 1451 out: 1452 mutex_unlock(&data->mutex); 1453 1454 return ret; 1455 } 1456 1457 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) 1458 { 1459 struct bmc150_accel_data *data = iio_priv(indio_dev); 1460 1461 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1462 return iio_triggered_buffer_predisable(indio_dev); 1463 1464 mutex_lock(&data->mutex); 1465 1466 if (!data->fifo_mode) 1467 goto out; 1468 1469 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); 1470 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); 1471 data->fifo_mode = 0; 1472 bmc150_accel_fifo_set_mode(data); 1473 1474 out: 1475 mutex_unlock(&data->mutex); 1476 1477 return 0; 1478 } 1479 1480 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev) 1481 { 1482 struct bmc150_accel_data *data = iio_priv(indio_dev); 1483 1484 return bmc150_accel_set_power_state(data, false); 1485 } 1486 1487 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { 1488 .preenable = bmc150_accel_buffer_preenable, 1489 .postenable = bmc150_accel_buffer_postenable, 1490 .predisable = bmc150_accel_buffer_predisable, 1491 .postdisable = bmc150_accel_buffer_postdisable, 1492 }; 1493 1494 static int bmc150_accel_chip_init(struct bmc150_accel_data *data) 1495 { 1496 struct device *dev = regmap_get_device(data->regmap); 1497 int ret, i; 1498 unsigned int val; 1499 1500 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val); 1501 if (ret < 0) { 1502 dev_err(dev, "Error: Reading chip id\n"); 1503 return ret; 1504 } 1505 1506 dev_dbg(dev, "Chip Id %x\n", val); 1507 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) { 1508 if (bmc150_accel_chip_info_tbl[i].chip_id == val) { 1509 data->chip_info = &bmc150_accel_chip_info_tbl[i]; 1510 break; 1511 } 1512 } 1513 1514 if (!data->chip_info) { 1515 dev_err(dev, "Invalid chip %x\n", val); 1516 return -ENODEV; 1517 } 1518 1519 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1520 if (ret < 0) 1521 return ret; 1522 1523 /* Set Bandwidth */ 1524 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); 1525 if (ret < 0) 1526 return ret; 1527 1528 /* Set Default Range */ 1529 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE, 1530 BMC150_ACCEL_DEF_RANGE_4G); 1531 if (ret < 0) { 1532 dev_err(dev, "Error writing reg_pmu_range\n"); 1533 return ret; 1534 } 1535 1536 data->range = BMC150_ACCEL_DEF_RANGE_4G; 1537 1538 /* Set default slope duration and thresholds */ 1539 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; 1540 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION; 1541 ret = bmc150_accel_update_slope(data); 1542 if (ret < 0) 1543 return ret; 1544 1545 /* Set default as latched interrupts */ 1546 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1547 BMC150_ACCEL_INT_MODE_LATCH_INT | 1548 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1549 if (ret < 0) { 1550 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1551 return ret; 1552 } 1553 1554 return 0; 1555 } 1556 1557 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq, 1558 const char *name, bool block_supported) 1559 { 1560 struct bmc150_accel_data *data; 1561 struct iio_dev *indio_dev; 1562 int ret; 1563 1564 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1565 if (!indio_dev) 1566 return -ENOMEM; 1567 1568 data = iio_priv(indio_dev); 1569 dev_set_drvdata(dev, indio_dev); 1570 data->irq = irq; 1571 1572 data->regmap = regmap; 1573 1574 ret = bmc150_accel_chip_init(data); 1575 if (ret < 0) 1576 return ret; 1577 1578 mutex_init(&data->mutex); 1579 1580 indio_dev->dev.parent = dev; 1581 indio_dev->channels = data->chip_info->channels; 1582 indio_dev->num_channels = data->chip_info->num_channels; 1583 indio_dev->name = name ? name : data->chip_info->name; 1584 indio_dev->available_scan_masks = bmc150_accel_scan_masks; 1585 indio_dev->modes = INDIO_DIRECT_MODE; 1586 indio_dev->info = &bmc150_accel_info; 1587 1588 ret = iio_triggered_buffer_setup(indio_dev, 1589 &iio_pollfunc_store_time, 1590 bmc150_accel_trigger_handler, 1591 &bmc150_accel_buffer_ops); 1592 if (ret < 0) { 1593 dev_err(dev, "Failed: iio triggered buffer setup\n"); 1594 return ret; 1595 } 1596 1597 if (data->irq > 0) { 1598 ret = devm_request_threaded_irq( 1599 dev, data->irq, 1600 bmc150_accel_irq_handler, 1601 bmc150_accel_irq_thread_handler, 1602 IRQF_TRIGGER_RISING, 1603 BMC150_ACCEL_IRQ_NAME, 1604 indio_dev); 1605 if (ret) 1606 goto err_buffer_cleanup; 1607 1608 /* 1609 * Set latched mode interrupt. While certain interrupts are 1610 * non-latched regardless of this settings (e.g. new data) we 1611 * want to use latch mode when we can to prevent interrupt 1612 * flooding. 1613 */ 1614 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1615 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1616 if (ret < 0) { 1617 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1618 goto err_buffer_cleanup; 1619 } 1620 1621 bmc150_accel_interrupts_setup(indio_dev, data); 1622 1623 ret = bmc150_accel_triggers_setup(indio_dev, data); 1624 if (ret) 1625 goto err_buffer_cleanup; 1626 1627 if (block_supported) { 1628 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 1629 indio_dev->info = &bmc150_accel_info_fifo; 1630 indio_dev->buffer->attrs = bmc150_accel_fifo_attributes; 1631 } 1632 } 1633 1634 ret = pm_runtime_set_active(dev); 1635 if (ret) 1636 goto err_trigger_unregister; 1637 1638 pm_runtime_enable(dev); 1639 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS); 1640 pm_runtime_use_autosuspend(dev); 1641 1642 ret = iio_device_register(indio_dev); 1643 if (ret < 0) { 1644 dev_err(dev, "Unable to register iio device\n"); 1645 goto err_trigger_unregister; 1646 } 1647 1648 return 0; 1649 1650 err_trigger_unregister: 1651 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1652 err_buffer_cleanup: 1653 iio_triggered_buffer_cleanup(indio_dev); 1654 1655 return ret; 1656 } 1657 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe); 1658 1659 int bmc150_accel_core_remove(struct device *dev) 1660 { 1661 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1662 struct bmc150_accel_data *data = iio_priv(indio_dev); 1663 1664 iio_device_unregister(indio_dev); 1665 1666 pm_runtime_disable(dev); 1667 pm_runtime_set_suspended(dev); 1668 pm_runtime_put_noidle(dev); 1669 1670 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1671 1672 iio_triggered_buffer_cleanup(indio_dev); 1673 1674 mutex_lock(&data->mutex); 1675 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); 1676 mutex_unlock(&data->mutex); 1677 1678 return 0; 1679 } 1680 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove); 1681 1682 #ifdef CONFIG_PM_SLEEP 1683 static int bmc150_accel_suspend(struct device *dev) 1684 { 1685 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1686 struct bmc150_accel_data *data = iio_priv(indio_dev); 1687 1688 mutex_lock(&data->mutex); 1689 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1690 mutex_unlock(&data->mutex); 1691 1692 return 0; 1693 } 1694 1695 static int bmc150_accel_resume(struct device *dev) 1696 { 1697 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1698 struct bmc150_accel_data *data = iio_priv(indio_dev); 1699 1700 mutex_lock(&data->mutex); 1701 if (atomic_read(&data->active_intr)) 1702 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1703 bmc150_accel_fifo_set_mode(data); 1704 mutex_unlock(&data->mutex); 1705 1706 return 0; 1707 } 1708 #endif 1709 1710 #ifdef CONFIG_PM 1711 static int bmc150_accel_runtime_suspend(struct device *dev) 1712 { 1713 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1714 struct bmc150_accel_data *data = iio_priv(indio_dev); 1715 int ret; 1716 1717 dev_dbg(dev, __func__); 1718 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1719 if (ret < 0) 1720 return -EAGAIN; 1721 1722 return 0; 1723 } 1724 1725 static int bmc150_accel_runtime_resume(struct device *dev) 1726 { 1727 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1728 struct bmc150_accel_data *data = iio_priv(indio_dev); 1729 int ret; 1730 int sleep_val; 1731 1732 dev_dbg(dev, __func__); 1733 1734 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1735 if (ret < 0) 1736 return ret; 1737 ret = bmc150_accel_fifo_set_mode(data); 1738 if (ret < 0) 1739 return ret; 1740 1741 sleep_val = bmc150_accel_get_startup_times(data); 1742 if (sleep_val < 20) 1743 usleep_range(sleep_val * 1000, 20000); 1744 else 1745 msleep_interruptible(sleep_val); 1746 1747 return 0; 1748 } 1749 #endif 1750 1751 const struct dev_pm_ops bmc150_accel_pm_ops = { 1752 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) 1753 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, 1754 bmc150_accel_runtime_resume, NULL) 1755 }; 1756 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops); 1757 1758 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1759 MODULE_LICENSE("GPL v2"); 1760 MODULE_DESCRIPTION("BMC150 accelerometer driver"); 1761