1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips: 4 * - BMC150 5 * - BMI055 6 * - BMA255 7 * - BMA250E 8 * - BMA222 9 * - BMA222E 10 * - BMA280 11 * 12 * Copyright (c) 2014, Intel Corporation. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/slab.h> 20 #include <linux/acpi.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/events.h> 27 #include <linux/iio/trigger.h> 28 #include <linux/iio/trigger_consumer.h> 29 #include <linux/iio/triggered_buffer.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 33 #include "bmc150-accel.h" 34 35 #define BMC150_ACCEL_DRV_NAME "bmc150_accel" 36 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" 37 38 #define BMC150_ACCEL_REG_CHIP_ID 0x00 39 40 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B 41 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07 42 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) 43 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) 44 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) 45 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) 46 47 #define BMC150_ACCEL_REG_PMU_LPW 0x11 48 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0 49 #define BMC150_ACCEL_PMU_MODE_SHIFT 5 50 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 51 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 52 53 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F 54 55 #define BMC150_ACCEL_DEF_RANGE_2G 0x03 56 #define BMC150_ACCEL_DEF_RANGE_4G 0x05 57 #define BMC150_ACCEL_DEF_RANGE_8G 0x08 58 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C 59 60 /* Default BW: 125Hz */ 61 #define BMC150_ACCEL_REG_PMU_BW 0x10 62 #define BMC150_ACCEL_DEF_BW 125 63 64 #define BMC150_ACCEL_REG_RESET 0x14 65 #define BMC150_ACCEL_RESET_VAL 0xB6 66 67 #define BMC150_ACCEL_REG_INT_MAP_0 0x19 68 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) 69 70 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A 71 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) 72 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) 73 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) 74 75 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 76 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 77 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F 78 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 79 80 #define BMC150_ACCEL_REG_INT_EN_0 0x16 81 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) 82 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) 83 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) 84 85 #define BMC150_ACCEL_REG_INT_EN_1 0x17 86 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) 87 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) 88 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) 89 90 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 91 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) 92 93 #define BMC150_ACCEL_REG_INT_5 0x27 94 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 95 96 #define BMC150_ACCEL_REG_INT_6 0x28 97 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF 98 99 /* Slope duration in terms of number of samples */ 100 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1 101 /* in terms of multiples of g's/LSB, based on range */ 102 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 103 104 #define BMC150_ACCEL_REG_XOUT_L 0x02 105 106 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 107 108 /* Sleep Duration values */ 109 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05 110 #define BMC150_ACCEL_SLEEP_1_MS 0x06 111 #define BMC150_ACCEL_SLEEP_2_MS 0x07 112 #define BMC150_ACCEL_SLEEP_4_MS 0x08 113 #define BMC150_ACCEL_SLEEP_6_MS 0x09 114 #define BMC150_ACCEL_SLEEP_10_MS 0x0A 115 #define BMC150_ACCEL_SLEEP_25_MS 0x0B 116 #define BMC150_ACCEL_SLEEP_50_MS 0x0C 117 #define BMC150_ACCEL_SLEEP_100_MS 0x0D 118 #define BMC150_ACCEL_SLEEP_500_MS 0x0E 119 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F 120 121 #define BMC150_ACCEL_REG_TEMP 0x08 122 #define BMC150_ACCEL_TEMP_CENTER_VAL 23 123 124 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) 125 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 126 127 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E 128 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 129 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E 130 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F 131 #define BMC150_ACCEL_FIFO_LENGTH 32 132 133 enum bmc150_accel_axis { 134 AXIS_X, 135 AXIS_Y, 136 AXIS_Z, 137 AXIS_MAX, 138 }; 139 140 enum bmc150_power_modes { 141 BMC150_ACCEL_SLEEP_MODE_NORMAL, 142 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 143 BMC150_ACCEL_SLEEP_MODE_LPM, 144 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, 145 }; 146 147 struct bmc150_scale_info { 148 int scale; 149 u8 reg_range; 150 }; 151 152 struct bmc150_accel_chip_info { 153 const char *name; 154 u8 chip_id; 155 const struct iio_chan_spec *channels; 156 int num_channels; 157 const struct bmc150_scale_info scale_table[4]; 158 }; 159 160 struct bmc150_accel_interrupt { 161 const struct bmc150_accel_interrupt_info *info; 162 atomic_t users; 163 }; 164 165 struct bmc150_accel_trigger { 166 struct bmc150_accel_data *data; 167 struct iio_trigger *indio_trig; 168 int (*setup)(struct bmc150_accel_trigger *t, bool state); 169 int intr; 170 bool enabled; 171 }; 172 173 enum bmc150_accel_interrupt_id { 174 BMC150_ACCEL_INT_DATA_READY, 175 BMC150_ACCEL_INT_ANY_MOTION, 176 BMC150_ACCEL_INT_WATERMARK, 177 BMC150_ACCEL_INTERRUPTS, 178 }; 179 180 enum bmc150_accel_trigger_id { 181 BMC150_ACCEL_TRIGGER_DATA_READY, 182 BMC150_ACCEL_TRIGGER_ANY_MOTION, 183 BMC150_ACCEL_TRIGGERS, 184 }; 185 186 struct bmc150_accel_data { 187 struct regmap *regmap; 188 struct regulator_bulk_data regulators[2]; 189 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS]; 190 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; 191 struct mutex mutex; 192 u8 fifo_mode, watermark; 193 s16 buffer[8]; 194 /* 195 * Ensure there is sufficient space and correct alignment for 196 * the timestamp if enabled 197 */ 198 struct { 199 __le16 channels[3]; 200 s64 ts __aligned(8); 201 } scan; 202 u8 bw_bits; 203 u32 slope_dur; 204 u32 slope_thres; 205 u32 range; 206 int ev_enable_state; 207 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 208 const struct bmc150_accel_chip_info *chip_info; 209 struct i2c_client *second_device; 210 struct iio_mount_matrix orientation; 211 }; 212 213 static const struct { 214 int val; 215 int val2; 216 u8 bw_bits; 217 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08}, 218 {31, 260000, 0x09}, 219 {62, 500000, 0x0A}, 220 {125, 0, 0x0B}, 221 {250, 0, 0x0C}, 222 {500, 0, 0x0D}, 223 {1000, 0, 0x0E}, 224 {2000, 0, 0x0F} }; 225 226 static const struct { 227 int bw_bits; 228 int msec; 229 } bmc150_accel_sample_upd_time[] = { {0x08, 64}, 230 {0x09, 32}, 231 {0x0A, 16}, 232 {0x0B, 8}, 233 {0x0C, 4}, 234 {0x0D, 2}, 235 {0x0E, 1}, 236 {0x0F, 1} }; 237 238 static const struct { 239 int sleep_dur; 240 u8 reg_value; 241 } bmc150_accel_sleep_value_table[] = { {0, 0}, 242 {500, BMC150_ACCEL_SLEEP_500_MICRO}, 243 {1000, BMC150_ACCEL_SLEEP_1_MS}, 244 {2000, BMC150_ACCEL_SLEEP_2_MS}, 245 {4000, BMC150_ACCEL_SLEEP_4_MS}, 246 {6000, BMC150_ACCEL_SLEEP_6_MS}, 247 {10000, BMC150_ACCEL_SLEEP_10_MS}, 248 {25000, BMC150_ACCEL_SLEEP_25_MS}, 249 {50000, BMC150_ACCEL_SLEEP_50_MS}, 250 {100000, BMC150_ACCEL_SLEEP_100_MS}, 251 {500000, BMC150_ACCEL_SLEEP_500_MS}, 252 {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; 253 254 const struct regmap_config bmc150_regmap_conf = { 255 .reg_bits = 8, 256 .val_bits = 8, 257 .max_register = 0x3f, 258 }; 259 EXPORT_SYMBOL_GPL(bmc150_regmap_conf); 260 261 static int bmc150_accel_set_mode(struct bmc150_accel_data *data, 262 enum bmc150_power_modes mode, 263 int dur_us) 264 { 265 struct device *dev = regmap_get_device(data->regmap); 266 int i; 267 int ret; 268 u8 lpw_bits; 269 int dur_val = -1; 270 271 if (dur_us > 0) { 272 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); 273 ++i) { 274 if (bmc150_accel_sleep_value_table[i].sleep_dur == 275 dur_us) 276 dur_val = 277 bmc150_accel_sleep_value_table[i].reg_value; 278 } 279 } else { 280 dur_val = 0; 281 } 282 283 if (dur_val < 0) 284 return -EINVAL; 285 286 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; 287 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); 288 289 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits); 290 291 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits); 292 if (ret < 0) { 293 dev_err(dev, "Error writing reg_pmu_lpw\n"); 294 return ret; 295 } 296 297 return 0; 298 } 299 300 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, 301 int val2) 302 { 303 int i; 304 int ret; 305 306 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 307 if (bmc150_accel_samp_freq_table[i].val == val && 308 bmc150_accel_samp_freq_table[i].val2 == val2) { 309 ret = regmap_write(data->regmap, 310 BMC150_ACCEL_REG_PMU_BW, 311 bmc150_accel_samp_freq_table[i].bw_bits); 312 if (ret < 0) 313 return ret; 314 315 data->bw_bits = 316 bmc150_accel_samp_freq_table[i].bw_bits; 317 return 0; 318 } 319 } 320 321 return -EINVAL; 322 } 323 324 static int bmc150_accel_update_slope(struct bmc150_accel_data *data) 325 { 326 struct device *dev = regmap_get_device(data->regmap); 327 int ret; 328 329 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6, 330 data->slope_thres); 331 if (ret < 0) { 332 dev_err(dev, "Error writing reg_int_6\n"); 333 return ret; 334 } 335 336 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5, 337 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur); 338 if (ret < 0) { 339 dev_err(dev, "Error updating reg_int_5\n"); 340 return ret; 341 } 342 343 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur); 344 345 return ret; 346 } 347 348 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t, 349 bool state) 350 { 351 if (state) 352 return bmc150_accel_update_slope(t->data); 353 354 return 0; 355 } 356 357 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, 358 int *val2) 359 { 360 int i; 361 362 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 363 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { 364 *val = bmc150_accel_samp_freq_table[i].val; 365 *val2 = bmc150_accel_samp_freq_table[i].val2; 366 return IIO_VAL_INT_PLUS_MICRO; 367 } 368 } 369 370 return -EINVAL; 371 } 372 373 #ifdef CONFIG_PM 374 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) 375 { 376 int i; 377 378 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { 379 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) 380 return bmc150_accel_sample_upd_time[i].msec; 381 } 382 383 return BMC150_ACCEL_MAX_STARTUP_TIME_MS; 384 } 385 386 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 387 { 388 struct device *dev = regmap_get_device(data->regmap); 389 int ret; 390 391 if (on) { 392 ret = pm_runtime_get_sync(dev); 393 } else { 394 pm_runtime_mark_last_busy(dev); 395 ret = pm_runtime_put_autosuspend(dev); 396 } 397 398 if (ret < 0) { 399 dev_err(dev, 400 "Failed: %s for %d\n", __func__, on); 401 if (on) 402 pm_runtime_put_noidle(dev); 403 404 return ret; 405 } 406 407 return 0; 408 } 409 #else 410 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 411 { 412 return 0; 413 } 414 #endif 415 416 #ifdef CONFIG_ACPI 417 /* 418 * Support for getting accelerometer information from BOSC0200 ACPI nodes. 419 * 420 * There are 2 variants of the BOSC0200 ACPI node. Some 2-in-1s with 360 degree 421 * hinges declare 2 I2C ACPI-resources for 2 accelerometers, 1 in the display 422 * and 1 in the base of the 2-in-1. On these 2-in-1s the ROMS ACPI object 423 * contains the mount-matrix for the sensor in the display and ROMK contains 424 * the mount-matrix for the sensor in the base. On devices using a single 425 * sensor there is a ROTM ACPI object which contains the mount-matrix. 426 * 427 * Here is an incomplete list of devices known to use 1 of these setups: 428 * 429 * Yoga devices with 2 accelerometers using ROMS + ROMK for the mount-matrices: 430 * Lenovo Thinkpad Yoga 11e 3th gen 431 * Lenovo Thinkpad Yoga 11e 4th gen 432 * 433 * Tablets using a single accelerometer using ROTM for the mount-matrix: 434 * Chuwi Hi8 Pro (CWI513) 435 * Chuwi Vi8 Plus (CWI519) 436 * Chuwi Hi13 437 * Irbis TW90 438 * Jumper EZpad mini 3 439 * Onda V80 plus 440 * Predia Basic Tablet 441 */ 442 static bool bmc150_apply_acpi_orientation(struct device *dev, 443 struct iio_mount_matrix *orientation) 444 { 445 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 446 struct iio_dev *indio_dev = dev_get_drvdata(dev); 447 struct acpi_device *adev = ACPI_COMPANION(dev); 448 char *name, *alt_name, *label, *str; 449 union acpi_object *obj, *elements; 450 acpi_status status; 451 int i, j, val[3]; 452 453 if (!adev || !acpi_dev_hid_uid_match(adev, "BOSC0200", NULL)) 454 return false; 455 456 if (strcmp(dev_name(dev), "i2c-BOSC0200:base") == 0) { 457 alt_name = "ROMK"; 458 label = "accel-base"; 459 } else { 460 alt_name = "ROMS"; 461 label = "accel-display"; 462 } 463 464 if (acpi_has_method(adev->handle, "ROTM")) { 465 name = "ROTM"; 466 } else if (acpi_has_method(adev->handle, alt_name)) { 467 name = alt_name; 468 indio_dev->label = label; 469 } else { 470 return false; 471 } 472 473 status = acpi_evaluate_object(adev->handle, name, NULL, &buffer); 474 if (ACPI_FAILURE(status)) { 475 dev_warn(dev, "Failed to get ACPI mount matrix: %d\n", status); 476 return false; 477 } 478 479 obj = buffer.pointer; 480 if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count != 3) 481 goto unknown_format; 482 483 elements = obj->package.elements; 484 for (i = 0; i < 3; i++) { 485 if (elements[i].type != ACPI_TYPE_STRING) 486 goto unknown_format; 487 488 str = elements[i].string.pointer; 489 if (sscanf(str, "%d %d %d", &val[0], &val[1], &val[2]) != 3) 490 goto unknown_format; 491 492 for (j = 0; j < 3; j++) { 493 switch (val[j]) { 494 case -1: str = "-1"; break; 495 case 0: str = "0"; break; 496 case 1: str = "1"; break; 497 default: goto unknown_format; 498 } 499 orientation->rotation[i * 3 + j] = str; 500 } 501 } 502 503 kfree(buffer.pointer); 504 return true; 505 506 unknown_format: 507 dev_warn(dev, "Unknown ACPI mount matrix format, ignoring\n"); 508 kfree(buffer.pointer); 509 return false; 510 } 511 #else 512 static bool bmc150_apply_acpi_orientation(struct device *dev, 513 struct iio_mount_matrix *orientation) 514 { 515 return false; 516 } 517 #endif 518 519 static const struct bmc150_accel_interrupt_info { 520 u8 map_reg; 521 u8 map_bitmask; 522 u8 en_reg; 523 u8 en_bitmask; 524 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = { 525 { /* data ready interrupt */ 526 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 527 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA, 528 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 529 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, 530 }, 531 { /* motion interrupt */ 532 .map_reg = BMC150_ACCEL_REG_INT_MAP_0, 533 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE, 534 .en_reg = BMC150_ACCEL_REG_INT_EN_0, 535 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | 536 BMC150_ACCEL_INT_EN_BIT_SLP_Y | 537 BMC150_ACCEL_INT_EN_BIT_SLP_Z 538 }, 539 { /* fifo watermark interrupt */ 540 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 541 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM, 542 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 543 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, 544 }, 545 }; 546 547 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, 548 struct bmc150_accel_data *data) 549 { 550 int i; 551 552 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++) 553 data->interrupts[i].info = &bmc150_accel_interrupts[i]; 554 } 555 556 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, 557 bool state) 558 { 559 struct device *dev = regmap_get_device(data->regmap); 560 struct bmc150_accel_interrupt *intr = &data->interrupts[i]; 561 const struct bmc150_accel_interrupt_info *info = intr->info; 562 int ret; 563 564 if (state) { 565 if (atomic_inc_return(&intr->users) > 1) 566 return 0; 567 } else { 568 if (atomic_dec_return(&intr->users) > 0) 569 return 0; 570 } 571 572 /* 573 * We will expect the enable and disable to do operation in reverse 574 * order. This will happen here anyway, as our resume operation uses 575 * sync mode runtime pm calls. The suspend operation will be delayed 576 * by autosuspend delay. 577 * So the disable operation will still happen in reverse order of 578 * enable operation. When runtime pm is disabled the mode is always on, 579 * so sequence doesn't matter. 580 */ 581 ret = bmc150_accel_set_power_state(data, state); 582 if (ret < 0) 583 return ret; 584 585 /* map the interrupt to the appropriate pins */ 586 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask, 587 (state ? info->map_bitmask : 0)); 588 if (ret < 0) { 589 dev_err(dev, "Error updating reg_int_map\n"); 590 goto out_fix_power_state; 591 } 592 593 /* enable/disable the interrupt */ 594 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask, 595 (state ? info->en_bitmask : 0)); 596 if (ret < 0) { 597 dev_err(dev, "Error updating reg_int_en\n"); 598 goto out_fix_power_state; 599 } 600 601 return 0; 602 603 out_fix_power_state: 604 bmc150_accel_set_power_state(data, false); 605 return ret; 606 } 607 608 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) 609 { 610 struct device *dev = regmap_get_device(data->regmap); 611 int ret, i; 612 613 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { 614 if (data->chip_info->scale_table[i].scale == val) { 615 ret = regmap_write(data->regmap, 616 BMC150_ACCEL_REG_PMU_RANGE, 617 data->chip_info->scale_table[i].reg_range); 618 if (ret < 0) { 619 dev_err(dev, "Error writing pmu_range\n"); 620 return ret; 621 } 622 623 data->range = data->chip_info->scale_table[i].reg_range; 624 return 0; 625 } 626 } 627 628 return -EINVAL; 629 } 630 631 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) 632 { 633 struct device *dev = regmap_get_device(data->regmap); 634 int ret; 635 unsigned int value; 636 637 mutex_lock(&data->mutex); 638 639 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value); 640 if (ret < 0) { 641 dev_err(dev, "Error reading reg_temp\n"); 642 mutex_unlock(&data->mutex); 643 return ret; 644 } 645 *val = sign_extend32(value, 7); 646 647 mutex_unlock(&data->mutex); 648 649 return IIO_VAL_INT; 650 } 651 652 static int bmc150_accel_get_axis(struct bmc150_accel_data *data, 653 struct iio_chan_spec const *chan, 654 int *val) 655 { 656 struct device *dev = regmap_get_device(data->regmap); 657 int ret; 658 int axis = chan->scan_index; 659 __le16 raw_val; 660 661 mutex_lock(&data->mutex); 662 ret = bmc150_accel_set_power_state(data, true); 663 if (ret < 0) { 664 mutex_unlock(&data->mutex); 665 return ret; 666 } 667 668 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis), 669 &raw_val, sizeof(raw_val)); 670 if (ret < 0) { 671 dev_err(dev, "Error reading axis %d\n", axis); 672 bmc150_accel_set_power_state(data, false); 673 mutex_unlock(&data->mutex); 674 return ret; 675 } 676 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift, 677 chan->scan_type.realbits - 1); 678 ret = bmc150_accel_set_power_state(data, false); 679 mutex_unlock(&data->mutex); 680 if (ret < 0) 681 return ret; 682 683 return IIO_VAL_INT; 684 } 685 686 static int bmc150_accel_read_raw(struct iio_dev *indio_dev, 687 struct iio_chan_spec const *chan, 688 int *val, int *val2, long mask) 689 { 690 struct bmc150_accel_data *data = iio_priv(indio_dev); 691 int ret; 692 693 switch (mask) { 694 case IIO_CHAN_INFO_RAW: 695 switch (chan->type) { 696 case IIO_TEMP: 697 return bmc150_accel_get_temp(data, val); 698 case IIO_ACCEL: 699 if (iio_buffer_enabled(indio_dev)) 700 return -EBUSY; 701 else 702 return bmc150_accel_get_axis(data, chan, val); 703 default: 704 return -EINVAL; 705 } 706 case IIO_CHAN_INFO_OFFSET: 707 if (chan->type == IIO_TEMP) { 708 *val = BMC150_ACCEL_TEMP_CENTER_VAL; 709 return IIO_VAL_INT; 710 } else { 711 return -EINVAL; 712 } 713 case IIO_CHAN_INFO_SCALE: 714 *val = 0; 715 switch (chan->type) { 716 case IIO_TEMP: 717 *val2 = 500000; 718 return IIO_VAL_INT_PLUS_MICRO; 719 case IIO_ACCEL: 720 { 721 int i; 722 const struct bmc150_scale_info *si; 723 int st_size = ARRAY_SIZE(data->chip_info->scale_table); 724 725 for (i = 0; i < st_size; ++i) { 726 si = &data->chip_info->scale_table[i]; 727 if (si->reg_range == data->range) { 728 *val2 = si->scale; 729 return IIO_VAL_INT_PLUS_MICRO; 730 } 731 } 732 return -EINVAL; 733 } 734 default: 735 return -EINVAL; 736 } 737 case IIO_CHAN_INFO_SAMP_FREQ: 738 mutex_lock(&data->mutex); 739 ret = bmc150_accel_get_bw(data, val, val2); 740 mutex_unlock(&data->mutex); 741 return ret; 742 default: 743 return -EINVAL; 744 } 745 } 746 747 static int bmc150_accel_write_raw(struct iio_dev *indio_dev, 748 struct iio_chan_spec const *chan, 749 int val, int val2, long mask) 750 { 751 struct bmc150_accel_data *data = iio_priv(indio_dev); 752 int ret; 753 754 switch (mask) { 755 case IIO_CHAN_INFO_SAMP_FREQ: 756 mutex_lock(&data->mutex); 757 ret = bmc150_accel_set_bw(data, val, val2); 758 mutex_unlock(&data->mutex); 759 break; 760 case IIO_CHAN_INFO_SCALE: 761 if (val) 762 return -EINVAL; 763 764 mutex_lock(&data->mutex); 765 ret = bmc150_accel_set_scale(data, val2); 766 mutex_unlock(&data->mutex); 767 return ret; 768 default: 769 ret = -EINVAL; 770 } 771 772 return ret; 773 } 774 775 static int bmc150_accel_read_event(struct iio_dev *indio_dev, 776 const struct iio_chan_spec *chan, 777 enum iio_event_type type, 778 enum iio_event_direction dir, 779 enum iio_event_info info, 780 int *val, int *val2) 781 { 782 struct bmc150_accel_data *data = iio_priv(indio_dev); 783 784 *val2 = 0; 785 switch (info) { 786 case IIO_EV_INFO_VALUE: 787 *val = data->slope_thres; 788 break; 789 case IIO_EV_INFO_PERIOD: 790 *val = data->slope_dur; 791 break; 792 default: 793 return -EINVAL; 794 } 795 796 return IIO_VAL_INT; 797 } 798 799 static int bmc150_accel_write_event(struct iio_dev *indio_dev, 800 const struct iio_chan_spec *chan, 801 enum iio_event_type type, 802 enum iio_event_direction dir, 803 enum iio_event_info info, 804 int val, int val2) 805 { 806 struct bmc150_accel_data *data = iio_priv(indio_dev); 807 808 if (data->ev_enable_state) 809 return -EBUSY; 810 811 switch (info) { 812 case IIO_EV_INFO_VALUE: 813 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; 814 break; 815 case IIO_EV_INFO_PERIOD: 816 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; 817 break; 818 default: 819 return -EINVAL; 820 } 821 822 return 0; 823 } 824 825 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, 826 const struct iio_chan_spec *chan, 827 enum iio_event_type type, 828 enum iio_event_direction dir) 829 { 830 struct bmc150_accel_data *data = iio_priv(indio_dev); 831 832 return data->ev_enable_state; 833 } 834 835 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, 836 const struct iio_chan_spec *chan, 837 enum iio_event_type type, 838 enum iio_event_direction dir, 839 int state) 840 { 841 struct bmc150_accel_data *data = iio_priv(indio_dev); 842 int ret; 843 844 if (state == data->ev_enable_state) 845 return 0; 846 847 mutex_lock(&data->mutex); 848 849 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION, 850 state); 851 if (ret < 0) { 852 mutex_unlock(&data->mutex); 853 return ret; 854 } 855 856 data->ev_enable_state = state; 857 mutex_unlock(&data->mutex); 858 859 return 0; 860 } 861 862 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, 863 struct iio_trigger *trig) 864 { 865 struct bmc150_accel_data *data = iio_priv(indio_dev); 866 int i; 867 868 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 869 if (data->triggers[i].indio_trig == trig) 870 return 0; 871 } 872 873 return -EINVAL; 874 } 875 876 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, 877 struct device_attribute *attr, 878 char *buf) 879 { 880 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 881 struct bmc150_accel_data *data = iio_priv(indio_dev); 882 int wm; 883 884 mutex_lock(&data->mutex); 885 wm = data->watermark; 886 mutex_unlock(&data->mutex); 887 888 return sprintf(buf, "%d\n", wm); 889 } 890 891 static ssize_t bmc150_accel_get_fifo_state(struct device *dev, 892 struct device_attribute *attr, 893 char *buf) 894 { 895 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 896 struct bmc150_accel_data *data = iio_priv(indio_dev); 897 bool state; 898 899 mutex_lock(&data->mutex); 900 state = data->fifo_mode; 901 mutex_unlock(&data->mutex); 902 903 return sprintf(buf, "%d\n", state); 904 } 905 906 static const struct iio_mount_matrix * 907 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev, 908 const struct iio_chan_spec *chan) 909 { 910 struct bmc150_accel_data *data = iio_priv(indio_dev); 911 912 return &data->orientation; 913 } 914 915 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = { 916 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix), 917 { } 918 }; 919 920 static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 921 static IIO_CONST_ATTR(hwfifo_watermark_max, 922 __stringify(BMC150_ACCEL_FIFO_LENGTH)); 923 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, 924 bmc150_accel_get_fifo_state, NULL, 0); 925 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, 926 bmc150_accel_get_fifo_watermark, NULL, 0); 927 928 static const struct attribute *bmc150_accel_fifo_attributes[] = { 929 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 930 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 931 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 932 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 933 NULL, 934 }; 935 936 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) 937 { 938 struct bmc150_accel_data *data = iio_priv(indio_dev); 939 940 if (val > BMC150_ACCEL_FIFO_LENGTH) 941 val = BMC150_ACCEL_FIFO_LENGTH; 942 943 mutex_lock(&data->mutex); 944 data->watermark = val; 945 mutex_unlock(&data->mutex); 946 947 return 0; 948 } 949 950 /* 951 * We must read at least one full frame in one burst, otherwise the rest of the 952 * frame data is discarded. 953 */ 954 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data, 955 char *buffer, int samples) 956 { 957 struct device *dev = regmap_get_device(data->regmap); 958 int sample_length = 3 * 2; 959 int ret; 960 int total_length = samples * sample_length; 961 962 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA, 963 buffer, total_length); 964 if (ret) 965 dev_err(dev, 966 "Error transferring data from fifo: %d\n", ret); 967 968 return ret; 969 } 970 971 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, 972 unsigned samples, bool irq) 973 { 974 struct bmc150_accel_data *data = iio_priv(indio_dev); 975 struct device *dev = regmap_get_device(data->regmap); 976 int ret, i; 977 u8 count; 978 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; 979 int64_t tstamp; 980 uint64_t sample_period; 981 unsigned int val; 982 983 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val); 984 if (ret < 0) { 985 dev_err(dev, "Error reading reg_fifo_status\n"); 986 return ret; 987 } 988 989 count = val & 0x7F; 990 991 if (!count) 992 return 0; 993 994 /* 995 * If we getting called from IRQ handler we know the stored timestamp is 996 * fairly accurate for the last stored sample. Otherwise, if we are 997 * called as a result of a read operation from userspace and hence 998 * before the watermark interrupt was triggered, take a timestamp 999 * now. We can fall anywhere in between two samples so the error in this 1000 * case is at most one sample period. 1001 */ 1002 if (!irq) { 1003 data->old_timestamp = data->timestamp; 1004 data->timestamp = iio_get_time_ns(indio_dev); 1005 } 1006 1007 /* 1008 * Approximate timestamps for each of the sample based on the sampling 1009 * frequency, timestamp for last sample and number of samples. 1010 * 1011 * Note that we can't use the current bandwidth settings to compute the 1012 * sample period because the sample rate varies with the device 1013 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That 1014 * small variation adds when we store a large number of samples and 1015 * creates significant jitter between the last and first samples in 1016 * different batches (e.g. 32ms vs 21ms). 1017 * 1018 * To avoid this issue we compute the actual sample period ourselves 1019 * based on the timestamp delta between the last two flush operations. 1020 */ 1021 sample_period = (data->timestamp - data->old_timestamp); 1022 do_div(sample_period, count); 1023 tstamp = data->timestamp - (count - 1) * sample_period; 1024 1025 if (samples && count > samples) 1026 count = samples; 1027 1028 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count); 1029 if (ret) 1030 return ret; 1031 1032 /* 1033 * Ideally we want the IIO core to handle the demux when running in fifo 1034 * mode but not when running in triggered buffer mode. Unfortunately 1035 * this does not seem to be possible, so stick with driver demux for 1036 * now. 1037 */ 1038 for (i = 0; i < count; i++) { 1039 int j, bit; 1040 1041 j = 0; 1042 for_each_set_bit(bit, indio_dev->active_scan_mask, 1043 indio_dev->masklength) 1044 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 1045 sizeof(data->scan.channels[0])); 1046 1047 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 1048 tstamp); 1049 1050 tstamp += sample_period; 1051 } 1052 1053 return count; 1054 } 1055 1056 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) 1057 { 1058 struct bmc150_accel_data *data = iio_priv(indio_dev); 1059 int ret; 1060 1061 mutex_lock(&data->mutex); 1062 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); 1063 mutex_unlock(&data->mutex); 1064 1065 return ret; 1066 } 1067 1068 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 1069 "15.620000 31.260000 62.50000 125 250 500 1000 2000"); 1070 1071 static struct attribute *bmc150_accel_attributes[] = { 1072 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1073 NULL, 1074 }; 1075 1076 static const struct attribute_group bmc150_accel_attrs_group = { 1077 .attrs = bmc150_accel_attributes, 1078 }; 1079 1080 static const struct iio_event_spec bmc150_accel_event = { 1081 .type = IIO_EV_TYPE_ROC, 1082 .dir = IIO_EV_DIR_EITHER, 1083 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 1084 BIT(IIO_EV_INFO_ENABLE) | 1085 BIT(IIO_EV_INFO_PERIOD) 1086 }; 1087 1088 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \ 1089 .type = IIO_ACCEL, \ 1090 .modified = 1, \ 1091 .channel2 = IIO_MOD_##_axis, \ 1092 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 1093 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 1094 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1095 .scan_index = AXIS_##_axis, \ 1096 .scan_type = { \ 1097 .sign = 's', \ 1098 .realbits = (bits), \ 1099 .storagebits = 16, \ 1100 .shift = 16 - (bits), \ 1101 .endianness = IIO_LE, \ 1102 }, \ 1103 .ext_info = bmc150_accel_ext_info, \ 1104 .event_spec = &bmc150_accel_event, \ 1105 .num_event_specs = 1 \ 1106 } 1107 1108 #define BMC150_ACCEL_CHANNELS(bits) { \ 1109 { \ 1110 .type = IIO_TEMP, \ 1111 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1112 BIT(IIO_CHAN_INFO_SCALE) | \ 1113 BIT(IIO_CHAN_INFO_OFFSET), \ 1114 .scan_index = -1, \ 1115 }, \ 1116 BMC150_ACCEL_CHANNEL(X, bits), \ 1117 BMC150_ACCEL_CHANNEL(Y, bits), \ 1118 BMC150_ACCEL_CHANNEL(Z, bits), \ 1119 IIO_CHAN_SOFT_TIMESTAMP(3), \ 1120 } 1121 1122 static const struct iio_chan_spec bma222e_accel_channels[] = 1123 BMC150_ACCEL_CHANNELS(8); 1124 static const struct iio_chan_spec bma250e_accel_channels[] = 1125 BMC150_ACCEL_CHANNELS(10); 1126 static const struct iio_chan_spec bmc150_accel_channels[] = 1127 BMC150_ACCEL_CHANNELS(12); 1128 static const struct iio_chan_spec bma280_accel_channels[] = 1129 BMC150_ACCEL_CHANNELS(14); 1130 1131 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { 1132 [bmc150] = { 1133 .name = "BMC150A", 1134 .chip_id = 0xFA, 1135 .channels = bmc150_accel_channels, 1136 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1137 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1138 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1139 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1140 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1141 }, 1142 [bmi055] = { 1143 .name = "BMI055A", 1144 .chip_id = 0xFA, 1145 .channels = bmc150_accel_channels, 1146 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1147 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1148 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1149 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1150 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1151 }, 1152 [bma255] = { 1153 .name = "BMA0255", 1154 .chip_id = 0xFA, 1155 .channels = bmc150_accel_channels, 1156 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1157 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1158 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1159 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1160 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1161 }, 1162 [bma250e] = { 1163 .name = "BMA250E", 1164 .chip_id = 0xF9, 1165 .channels = bma250e_accel_channels, 1166 .num_channels = ARRAY_SIZE(bma250e_accel_channels), 1167 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G}, 1168 {76590, BMC150_ACCEL_DEF_RANGE_4G}, 1169 {153277, BMC150_ACCEL_DEF_RANGE_8G}, 1170 {306457, BMC150_ACCEL_DEF_RANGE_16G} }, 1171 }, 1172 [bma222] = { 1173 .name = "BMA222", 1174 .chip_id = 0x03, 1175 .channels = bma222e_accel_channels, 1176 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 1177 /* 1178 * The datasheet page 17 says: 1179 * 15.6, 31.3, 62.5 and 125 mg per LSB. 1180 */ 1181 .scale_table = { {156000, BMC150_ACCEL_DEF_RANGE_2G}, 1182 {313000, BMC150_ACCEL_DEF_RANGE_4G}, 1183 {625000, BMC150_ACCEL_DEF_RANGE_8G}, 1184 {1250000, BMC150_ACCEL_DEF_RANGE_16G} }, 1185 }, 1186 [bma222e] = { 1187 .name = "BMA222E", 1188 .chip_id = 0xF8, 1189 .channels = bma222e_accel_channels, 1190 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 1191 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G}, 1192 {306457, BMC150_ACCEL_DEF_RANGE_4G}, 1193 {612915, BMC150_ACCEL_DEF_RANGE_8G}, 1194 {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, 1195 }, 1196 [bma280] = { 1197 .name = "BMA0280", 1198 .chip_id = 0xFB, 1199 .channels = bma280_accel_channels, 1200 .num_channels = ARRAY_SIZE(bma280_accel_channels), 1201 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G}, 1202 {4785, BMC150_ACCEL_DEF_RANGE_4G}, 1203 {9581, BMC150_ACCEL_DEF_RANGE_8G}, 1204 {19152, BMC150_ACCEL_DEF_RANGE_16G} }, 1205 }, 1206 }; 1207 1208 static const struct iio_info bmc150_accel_info = { 1209 .attrs = &bmc150_accel_attrs_group, 1210 .read_raw = bmc150_accel_read_raw, 1211 .write_raw = bmc150_accel_write_raw, 1212 .read_event_value = bmc150_accel_read_event, 1213 .write_event_value = bmc150_accel_write_event, 1214 .write_event_config = bmc150_accel_write_event_config, 1215 .read_event_config = bmc150_accel_read_event_config, 1216 }; 1217 1218 static const struct iio_info bmc150_accel_info_fifo = { 1219 .attrs = &bmc150_accel_attrs_group, 1220 .read_raw = bmc150_accel_read_raw, 1221 .write_raw = bmc150_accel_write_raw, 1222 .read_event_value = bmc150_accel_read_event, 1223 .write_event_value = bmc150_accel_write_event, 1224 .write_event_config = bmc150_accel_write_event_config, 1225 .read_event_config = bmc150_accel_read_event_config, 1226 .validate_trigger = bmc150_accel_validate_trigger, 1227 .hwfifo_set_watermark = bmc150_accel_set_watermark, 1228 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, 1229 }; 1230 1231 static const unsigned long bmc150_accel_scan_masks[] = { 1232 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 1233 0}; 1234 1235 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) 1236 { 1237 struct iio_poll_func *pf = p; 1238 struct iio_dev *indio_dev = pf->indio_dev; 1239 struct bmc150_accel_data *data = iio_priv(indio_dev); 1240 int ret; 1241 1242 mutex_lock(&data->mutex); 1243 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L, 1244 data->buffer, AXIS_MAX * 2); 1245 mutex_unlock(&data->mutex); 1246 if (ret < 0) 1247 goto err_read; 1248 1249 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 1250 pf->timestamp); 1251 err_read: 1252 iio_trigger_notify_done(indio_dev->trig); 1253 1254 return IRQ_HANDLED; 1255 } 1256 1257 static void bmc150_accel_trig_reen(struct iio_trigger *trig) 1258 { 1259 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1260 struct bmc150_accel_data *data = t->data; 1261 struct device *dev = regmap_get_device(data->regmap); 1262 int ret; 1263 1264 /* new data interrupts don't need ack */ 1265 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY]) 1266 return; 1267 1268 mutex_lock(&data->mutex); 1269 /* clear any latched interrupt */ 1270 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1271 BMC150_ACCEL_INT_MODE_LATCH_INT | 1272 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1273 mutex_unlock(&data->mutex); 1274 if (ret < 0) 1275 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1276 } 1277 1278 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, 1279 bool state) 1280 { 1281 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1282 struct bmc150_accel_data *data = t->data; 1283 int ret; 1284 1285 mutex_lock(&data->mutex); 1286 1287 if (t->enabled == state) { 1288 mutex_unlock(&data->mutex); 1289 return 0; 1290 } 1291 1292 if (t->setup) { 1293 ret = t->setup(t, state); 1294 if (ret < 0) { 1295 mutex_unlock(&data->mutex); 1296 return ret; 1297 } 1298 } 1299 1300 ret = bmc150_accel_set_interrupt(data, t->intr, state); 1301 if (ret < 0) { 1302 mutex_unlock(&data->mutex); 1303 return ret; 1304 } 1305 1306 t->enabled = state; 1307 1308 mutex_unlock(&data->mutex); 1309 1310 return ret; 1311 } 1312 1313 static const struct iio_trigger_ops bmc150_accel_trigger_ops = { 1314 .set_trigger_state = bmc150_accel_trigger_set_state, 1315 .reenable = bmc150_accel_trig_reen, 1316 }; 1317 1318 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) 1319 { 1320 struct bmc150_accel_data *data = iio_priv(indio_dev); 1321 struct device *dev = regmap_get_device(data->regmap); 1322 int dir; 1323 int ret; 1324 unsigned int val; 1325 1326 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val); 1327 if (ret < 0) { 1328 dev_err(dev, "Error reading reg_int_status_2\n"); 1329 return ret; 1330 } 1331 1332 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) 1333 dir = IIO_EV_DIR_FALLING; 1334 else 1335 dir = IIO_EV_DIR_RISING; 1336 1337 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X) 1338 iio_push_event(indio_dev, 1339 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1340 0, 1341 IIO_MOD_X, 1342 IIO_EV_TYPE_ROC, 1343 dir), 1344 data->timestamp); 1345 1346 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y) 1347 iio_push_event(indio_dev, 1348 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1349 0, 1350 IIO_MOD_Y, 1351 IIO_EV_TYPE_ROC, 1352 dir), 1353 data->timestamp); 1354 1355 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z) 1356 iio_push_event(indio_dev, 1357 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1358 0, 1359 IIO_MOD_Z, 1360 IIO_EV_TYPE_ROC, 1361 dir), 1362 data->timestamp); 1363 1364 return ret; 1365 } 1366 1367 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) 1368 { 1369 struct iio_dev *indio_dev = private; 1370 struct bmc150_accel_data *data = iio_priv(indio_dev); 1371 struct device *dev = regmap_get_device(data->regmap); 1372 bool ack = false; 1373 int ret; 1374 1375 mutex_lock(&data->mutex); 1376 1377 if (data->fifo_mode) { 1378 ret = __bmc150_accel_fifo_flush(indio_dev, 1379 BMC150_ACCEL_FIFO_LENGTH, true); 1380 if (ret > 0) 1381 ack = true; 1382 } 1383 1384 if (data->ev_enable_state) { 1385 ret = bmc150_accel_handle_roc_event(indio_dev); 1386 if (ret > 0) 1387 ack = true; 1388 } 1389 1390 if (ack) { 1391 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1392 BMC150_ACCEL_INT_MODE_LATCH_INT | 1393 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1394 if (ret) 1395 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1396 1397 ret = IRQ_HANDLED; 1398 } else { 1399 ret = IRQ_NONE; 1400 } 1401 1402 mutex_unlock(&data->mutex); 1403 1404 return ret; 1405 } 1406 1407 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) 1408 { 1409 struct iio_dev *indio_dev = private; 1410 struct bmc150_accel_data *data = iio_priv(indio_dev); 1411 bool ack = false; 1412 int i; 1413 1414 data->old_timestamp = data->timestamp; 1415 data->timestamp = iio_get_time_ns(indio_dev); 1416 1417 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1418 if (data->triggers[i].enabled) { 1419 iio_trigger_poll(data->triggers[i].indio_trig); 1420 ack = true; 1421 break; 1422 } 1423 } 1424 1425 if (data->ev_enable_state || data->fifo_mode) 1426 return IRQ_WAKE_THREAD; 1427 1428 if (ack) 1429 return IRQ_HANDLED; 1430 1431 return IRQ_NONE; 1432 } 1433 1434 static const struct { 1435 int intr; 1436 const char *name; 1437 int (*setup)(struct bmc150_accel_trigger *t, bool state); 1438 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = { 1439 { 1440 .intr = 0, 1441 .name = "%s-dev%d", 1442 }, 1443 { 1444 .intr = 1, 1445 .name = "%s-any-motion-dev%d", 1446 .setup = bmc150_accel_any_motion_setup, 1447 }, 1448 }; 1449 1450 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data, 1451 int from) 1452 { 1453 int i; 1454 1455 for (i = from; i >= 0; i--) { 1456 if (data->triggers[i].indio_trig) { 1457 iio_trigger_unregister(data->triggers[i].indio_trig); 1458 data->triggers[i].indio_trig = NULL; 1459 } 1460 } 1461 } 1462 1463 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, 1464 struct bmc150_accel_data *data) 1465 { 1466 struct device *dev = regmap_get_device(data->regmap); 1467 int i, ret; 1468 1469 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1470 struct bmc150_accel_trigger *t = &data->triggers[i]; 1471 1472 t->indio_trig = devm_iio_trigger_alloc(dev, 1473 bmc150_accel_triggers[i].name, 1474 indio_dev->name, 1475 indio_dev->id); 1476 if (!t->indio_trig) { 1477 ret = -ENOMEM; 1478 break; 1479 } 1480 1481 t->indio_trig->ops = &bmc150_accel_trigger_ops; 1482 t->intr = bmc150_accel_triggers[i].intr; 1483 t->data = data; 1484 t->setup = bmc150_accel_triggers[i].setup; 1485 iio_trigger_set_drvdata(t->indio_trig, t); 1486 1487 ret = iio_trigger_register(t->indio_trig); 1488 if (ret) 1489 break; 1490 } 1491 1492 if (ret) 1493 bmc150_accel_unregister_triggers(data, i - 1); 1494 1495 return ret; 1496 } 1497 1498 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 1499 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 1500 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 1501 1502 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) 1503 { 1504 struct device *dev = regmap_get_device(data->regmap); 1505 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; 1506 int ret; 1507 1508 ret = regmap_write(data->regmap, reg, data->fifo_mode); 1509 if (ret < 0) { 1510 dev_err(dev, "Error writing reg_fifo_config1\n"); 1511 return ret; 1512 } 1513 1514 if (!data->fifo_mode) 1515 return 0; 1516 1517 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0, 1518 data->watermark); 1519 if (ret < 0) 1520 dev_err(dev, "Error writing reg_fifo_config0\n"); 1521 1522 return ret; 1523 } 1524 1525 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev) 1526 { 1527 struct bmc150_accel_data *data = iio_priv(indio_dev); 1528 1529 return bmc150_accel_set_power_state(data, true); 1530 } 1531 1532 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) 1533 { 1534 struct bmc150_accel_data *data = iio_priv(indio_dev); 1535 int ret = 0; 1536 1537 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1538 return 0; 1539 1540 mutex_lock(&data->mutex); 1541 1542 if (!data->watermark) 1543 goto out; 1544 1545 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1546 true); 1547 if (ret) 1548 goto out; 1549 1550 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; 1551 1552 ret = bmc150_accel_fifo_set_mode(data); 1553 if (ret) { 1554 data->fifo_mode = 0; 1555 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1556 false); 1557 } 1558 1559 out: 1560 mutex_unlock(&data->mutex); 1561 1562 return ret; 1563 } 1564 1565 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) 1566 { 1567 struct bmc150_accel_data *data = iio_priv(indio_dev); 1568 1569 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1570 return 0; 1571 1572 mutex_lock(&data->mutex); 1573 1574 if (!data->fifo_mode) 1575 goto out; 1576 1577 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); 1578 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); 1579 data->fifo_mode = 0; 1580 bmc150_accel_fifo_set_mode(data); 1581 1582 out: 1583 mutex_unlock(&data->mutex); 1584 1585 return 0; 1586 } 1587 1588 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev) 1589 { 1590 struct bmc150_accel_data *data = iio_priv(indio_dev); 1591 1592 return bmc150_accel_set_power_state(data, false); 1593 } 1594 1595 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { 1596 .preenable = bmc150_accel_buffer_preenable, 1597 .postenable = bmc150_accel_buffer_postenable, 1598 .predisable = bmc150_accel_buffer_predisable, 1599 .postdisable = bmc150_accel_buffer_postdisable, 1600 }; 1601 1602 static int bmc150_accel_chip_init(struct bmc150_accel_data *data) 1603 { 1604 struct device *dev = regmap_get_device(data->regmap); 1605 int ret, i; 1606 unsigned int val; 1607 1608 /* 1609 * Reset chip to get it in a known good state. A delay of 1.8ms after 1610 * reset is required according to the data sheets of supported chips. 1611 */ 1612 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET, 1613 BMC150_ACCEL_RESET_VAL); 1614 usleep_range(1800, 2500); 1615 1616 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val); 1617 if (ret < 0) { 1618 dev_err(dev, "Error: Reading chip id\n"); 1619 return ret; 1620 } 1621 1622 dev_dbg(dev, "Chip Id %x\n", val); 1623 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) { 1624 if (bmc150_accel_chip_info_tbl[i].chip_id == val) { 1625 data->chip_info = &bmc150_accel_chip_info_tbl[i]; 1626 break; 1627 } 1628 } 1629 1630 if (!data->chip_info) { 1631 dev_err(dev, "Invalid chip %x\n", val); 1632 return -ENODEV; 1633 } 1634 1635 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1636 if (ret < 0) 1637 return ret; 1638 1639 /* Set Bandwidth */ 1640 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); 1641 if (ret < 0) 1642 return ret; 1643 1644 /* Set Default Range */ 1645 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE, 1646 BMC150_ACCEL_DEF_RANGE_4G); 1647 if (ret < 0) { 1648 dev_err(dev, "Error writing reg_pmu_range\n"); 1649 return ret; 1650 } 1651 1652 data->range = BMC150_ACCEL_DEF_RANGE_4G; 1653 1654 /* Set default slope duration and thresholds */ 1655 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; 1656 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION; 1657 ret = bmc150_accel_update_slope(data); 1658 if (ret < 0) 1659 return ret; 1660 1661 /* Set default as latched interrupts */ 1662 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1663 BMC150_ACCEL_INT_MODE_LATCH_INT | 1664 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1665 if (ret < 0) { 1666 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1667 return ret; 1668 } 1669 1670 return 0; 1671 } 1672 1673 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq, 1674 const char *name, bool block_supported) 1675 { 1676 const struct attribute **fifo_attrs; 1677 struct bmc150_accel_data *data; 1678 struct iio_dev *indio_dev; 1679 int ret; 1680 1681 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1682 if (!indio_dev) 1683 return -ENOMEM; 1684 1685 data = iio_priv(indio_dev); 1686 dev_set_drvdata(dev, indio_dev); 1687 1688 data->regmap = regmap; 1689 1690 if (!bmc150_apply_acpi_orientation(dev, &data->orientation)) { 1691 ret = iio_read_mount_matrix(dev, "mount-matrix", 1692 &data->orientation); 1693 if (ret) 1694 return ret; 1695 } 1696 1697 /* 1698 * VDD is the analog and digital domain voltage supply 1699 * VDDIO is the digital I/O voltage supply 1700 */ 1701 data->regulators[0].supply = "vdd"; 1702 data->regulators[1].supply = "vddio"; 1703 ret = devm_regulator_bulk_get(dev, 1704 ARRAY_SIZE(data->regulators), 1705 data->regulators); 1706 if (ret) 1707 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1708 1709 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators), 1710 data->regulators); 1711 if (ret) { 1712 dev_err(dev, "failed to enable regulators: %d\n", ret); 1713 return ret; 1714 } 1715 /* 1716 * 2ms or 3ms power-on time according to datasheets, let's better 1717 * be safe than sorry and set this delay to 5ms. 1718 */ 1719 msleep(5); 1720 1721 ret = bmc150_accel_chip_init(data); 1722 if (ret < 0) 1723 goto err_disable_regulators; 1724 1725 mutex_init(&data->mutex); 1726 1727 indio_dev->channels = data->chip_info->channels; 1728 indio_dev->num_channels = data->chip_info->num_channels; 1729 indio_dev->name = name ? name : data->chip_info->name; 1730 indio_dev->available_scan_masks = bmc150_accel_scan_masks; 1731 indio_dev->modes = INDIO_DIRECT_MODE; 1732 indio_dev->info = &bmc150_accel_info; 1733 1734 if (block_supported) { 1735 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 1736 indio_dev->info = &bmc150_accel_info_fifo; 1737 fifo_attrs = bmc150_accel_fifo_attributes; 1738 } else { 1739 fifo_attrs = NULL; 1740 } 1741 1742 ret = iio_triggered_buffer_setup_ext(indio_dev, 1743 &iio_pollfunc_store_time, 1744 bmc150_accel_trigger_handler, 1745 &bmc150_accel_buffer_ops, 1746 fifo_attrs); 1747 if (ret < 0) { 1748 dev_err(dev, "Failed: iio triggered buffer setup\n"); 1749 goto err_disable_regulators; 1750 } 1751 1752 if (irq > 0) { 1753 ret = devm_request_threaded_irq(dev, irq, 1754 bmc150_accel_irq_handler, 1755 bmc150_accel_irq_thread_handler, 1756 IRQF_TRIGGER_RISING, 1757 BMC150_ACCEL_IRQ_NAME, 1758 indio_dev); 1759 if (ret) 1760 goto err_buffer_cleanup; 1761 1762 /* 1763 * Set latched mode interrupt. While certain interrupts are 1764 * non-latched regardless of this settings (e.g. new data) we 1765 * want to use latch mode when we can to prevent interrupt 1766 * flooding. 1767 */ 1768 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1769 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1770 if (ret < 0) { 1771 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1772 goto err_buffer_cleanup; 1773 } 1774 1775 bmc150_accel_interrupts_setup(indio_dev, data); 1776 1777 ret = bmc150_accel_triggers_setup(indio_dev, data); 1778 if (ret) 1779 goto err_buffer_cleanup; 1780 } 1781 1782 ret = pm_runtime_set_active(dev); 1783 if (ret) 1784 goto err_trigger_unregister; 1785 1786 pm_runtime_enable(dev); 1787 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS); 1788 pm_runtime_use_autosuspend(dev); 1789 1790 ret = iio_device_register(indio_dev); 1791 if (ret < 0) { 1792 dev_err(dev, "Unable to register iio device\n"); 1793 goto err_trigger_unregister; 1794 } 1795 1796 return 0; 1797 1798 err_trigger_unregister: 1799 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1800 err_buffer_cleanup: 1801 iio_triggered_buffer_cleanup(indio_dev); 1802 err_disable_regulators: 1803 regulator_bulk_disable(ARRAY_SIZE(data->regulators), 1804 data->regulators); 1805 1806 return ret; 1807 } 1808 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe); 1809 1810 struct i2c_client *bmc150_get_second_device(struct i2c_client *client) 1811 { 1812 struct bmc150_accel_data *data = i2c_get_clientdata(client); 1813 1814 if (!data) 1815 return NULL; 1816 1817 return data->second_device; 1818 } 1819 EXPORT_SYMBOL_GPL(bmc150_get_second_device); 1820 1821 void bmc150_set_second_device(struct i2c_client *client) 1822 { 1823 struct bmc150_accel_data *data = i2c_get_clientdata(client); 1824 1825 if (data) 1826 data->second_device = client; 1827 } 1828 EXPORT_SYMBOL_GPL(bmc150_set_second_device); 1829 1830 int bmc150_accel_core_remove(struct device *dev) 1831 { 1832 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1833 struct bmc150_accel_data *data = iio_priv(indio_dev); 1834 1835 iio_device_unregister(indio_dev); 1836 1837 pm_runtime_disable(dev); 1838 pm_runtime_set_suspended(dev); 1839 pm_runtime_put_noidle(dev); 1840 1841 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1842 1843 iio_triggered_buffer_cleanup(indio_dev); 1844 1845 mutex_lock(&data->mutex); 1846 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); 1847 mutex_unlock(&data->mutex); 1848 1849 regulator_bulk_disable(ARRAY_SIZE(data->regulators), 1850 data->regulators); 1851 1852 return 0; 1853 } 1854 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove); 1855 1856 #ifdef CONFIG_PM_SLEEP 1857 static int bmc150_accel_suspend(struct device *dev) 1858 { 1859 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1860 struct bmc150_accel_data *data = iio_priv(indio_dev); 1861 1862 mutex_lock(&data->mutex); 1863 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1864 mutex_unlock(&data->mutex); 1865 1866 return 0; 1867 } 1868 1869 static int bmc150_accel_resume(struct device *dev) 1870 { 1871 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1872 struct bmc150_accel_data *data = iio_priv(indio_dev); 1873 1874 mutex_lock(&data->mutex); 1875 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1876 bmc150_accel_fifo_set_mode(data); 1877 mutex_unlock(&data->mutex); 1878 1879 return 0; 1880 } 1881 #endif 1882 1883 #ifdef CONFIG_PM 1884 static int bmc150_accel_runtime_suspend(struct device *dev) 1885 { 1886 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1887 struct bmc150_accel_data *data = iio_priv(indio_dev); 1888 int ret; 1889 1890 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1891 if (ret < 0) 1892 return -EAGAIN; 1893 1894 return 0; 1895 } 1896 1897 static int bmc150_accel_runtime_resume(struct device *dev) 1898 { 1899 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1900 struct bmc150_accel_data *data = iio_priv(indio_dev); 1901 int ret; 1902 int sleep_val; 1903 1904 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1905 if (ret < 0) 1906 return ret; 1907 ret = bmc150_accel_fifo_set_mode(data); 1908 if (ret < 0) 1909 return ret; 1910 1911 sleep_val = bmc150_accel_get_startup_times(data); 1912 if (sleep_val < 20) 1913 usleep_range(sleep_val * 1000, 20000); 1914 else 1915 msleep_interruptible(sleep_val); 1916 1917 return 0; 1918 } 1919 #endif 1920 1921 const struct dev_pm_ops bmc150_accel_pm_ops = { 1922 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) 1923 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, 1924 bmc150_accel_runtime_resume, NULL) 1925 }; 1926 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops); 1927 1928 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1929 MODULE_LICENSE("GPL v2"); 1930 MODULE_DESCRIPTION("BMC150 accelerometer driver"); 1931