1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Core IIO driver for Bosch BMA400 triaxial acceleration sensor. 4 * 5 * Copyright 2019 Dan Robertson <dan@dlrobertson.com> 6 * 7 * TODO: 8 * - Support for power management 9 * - Support events and interrupts 10 * - Create channel for step count 11 * - Create channel for sensor time 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/bitops.h> 16 #include <linux/device.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 24 #include <asm/unaligned.h> 25 26 #include <linux/iio/iio.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/trigger.h> 30 #include <linux/iio/trigger_consumer.h> 31 #include <linux/iio/triggered_buffer.h> 32 33 #include "bma400.h" 34 35 /* 36 * The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may 37 * be selected with the acc_range bits of the ACC_CONFIG1 register. 38 * NB: This buffer is populated in the device init. 39 */ 40 static int bma400_scales[8]; 41 42 /* 43 * See the ACC_CONFIG1 section of the datasheet. 44 * NB: This buffer is populated in the device init. 45 */ 46 static int bma400_sample_freqs[14]; 47 48 static const int bma400_osr_range[] = { 0, 1, 3 }; 49 50 /* See the ACC_CONFIG0 section of the datasheet */ 51 enum bma400_power_mode { 52 POWER_MODE_SLEEP = 0x00, 53 POWER_MODE_LOW = 0x01, 54 POWER_MODE_NORMAL = 0x02, 55 POWER_MODE_INVALID = 0x03, 56 }; 57 58 enum bma400_scan { 59 BMA400_ACCL_X, 60 BMA400_ACCL_Y, 61 BMA400_ACCL_Z, 62 BMA400_TEMP, 63 }; 64 65 struct bma400_sample_freq { 66 int hz; 67 int uhz; 68 }; 69 70 enum bma400_activity { 71 BMA400_STILL, 72 BMA400_WALKING, 73 BMA400_RUNNING, 74 }; 75 76 struct bma400_data { 77 struct device *dev; 78 struct regmap *regmap; 79 struct regulator_bulk_data regulators[BMA400_NUM_REGULATORS]; 80 struct mutex mutex; /* data register lock */ 81 struct iio_mount_matrix orientation; 82 enum bma400_power_mode power_mode; 83 struct bma400_sample_freq sample_freq; 84 int oversampling_ratio; 85 int scale; 86 struct iio_trigger *trig; 87 int steps_enabled; 88 bool step_event_en; 89 bool activity_event_en; 90 unsigned int generic_event_en; 91 /* Correct time stamp alignment */ 92 struct { 93 __le16 buff[3]; 94 u8 temperature; 95 s64 ts __aligned(8); 96 } buffer __aligned(IIO_DMA_MINALIGN); 97 __le16 status; 98 __be16 duration; 99 }; 100 101 static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) 102 { 103 switch (reg) { 104 case BMA400_CHIP_ID_REG: 105 case BMA400_ERR_REG: 106 case BMA400_STATUS_REG: 107 case BMA400_X_AXIS_LSB_REG: 108 case BMA400_X_AXIS_MSB_REG: 109 case BMA400_Y_AXIS_LSB_REG: 110 case BMA400_Y_AXIS_MSB_REG: 111 case BMA400_Z_AXIS_LSB_REG: 112 case BMA400_Z_AXIS_MSB_REG: 113 case BMA400_SENSOR_TIME0: 114 case BMA400_SENSOR_TIME1: 115 case BMA400_SENSOR_TIME2: 116 case BMA400_EVENT_REG: 117 case BMA400_INT_STAT0_REG: 118 case BMA400_INT_STAT1_REG: 119 case BMA400_INT_STAT2_REG: 120 case BMA400_TEMP_DATA_REG: 121 case BMA400_FIFO_LENGTH0_REG: 122 case BMA400_FIFO_LENGTH1_REG: 123 case BMA400_FIFO_DATA_REG: 124 case BMA400_STEP_CNT0_REG: 125 case BMA400_STEP_CNT1_REG: 126 case BMA400_STEP_CNT3_REG: 127 case BMA400_STEP_STAT_REG: 128 return false; 129 default: 130 return true; 131 } 132 } 133 134 static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg) 135 { 136 switch (reg) { 137 case BMA400_ERR_REG: 138 case BMA400_STATUS_REG: 139 case BMA400_X_AXIS_LSB_REG: 140 case BMA400_X_AXIS_MSB_REG: 141 case BMA400_Y_AXIS_LSB_REG: 142 case BMA400_Y_AXIS_MSB_REG: 143 case BMA400_Z_AXIS_LSB_REG: 144 case BMA400_Z_AXIS_MSB_REG: 145 case BMA400_SENSOR_TIME0: 146 case BMA400_SENSOR_TIME1: 147 case BMA400_SENSOR_TIME2: 148 case BMA400_EVENT_REG: 149 case BMA400_INT_STAT0_REG: 150 case BMA400_INT_STAT1_REG: 151 case BMA400_INT_STAT2_REG: 152 case BMA400_TEMP_DATA_REG: 153 case BMA400_FIFO_LENGTH0_REG: 154 case BMA400_FIFO_LENGTH1_REG: 155 case BMA400_FIFO_DATA_REG: 156 case BMA400_STEP_CNT0_REG: 157 case BMA400_STEP_CNT1_REG: 158 case BMA400_STEP_CNT3_REG: 159 case BMA400_STEP_STAT_REG: 160 return true; 161 default: 162 return false; 163 } 164 } 165 166 const struct regmap_config bma400_regmap_config = { 167 .reg_bits = 8, 168 .val_bits = 8, 169 .max_register = BMA400_CMD_REG, 170 .cache_type = REGCACHE_RBTREE, 171 .writeable_reg = bma400_is_writable_reg, 172 .volatile_reg = bma400_is_volatile_reg, 173 }; 174 EXPORT_SYMBOL_NS(bma400_regmap_config, IIO_BMA400); 175 176 static const struct iio_mount_matrix * 177 bma400_accel_get_mount_matrix(const struct iio_dev *indio_dev, 178 const struct iio_chan_spec *chan) 179 { 180 struct bma400_data *data = iio_priv(indio_dev); 181 182 return &data->orientation; 183 } 184 185 static const struct iio_chan_spec_ext_info bma400_ext_info[] = { 186 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma400_accel_get_mount_matrix), 187 { } 188 }; 189 190 static const struct iio_event_spec bma400_step_detect_event = { 191 .type = IIO_EV_TYPE_CHANGE, 192 .dir = IIO_EV_DIR_NONE, 193 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 194 }; 195 196 static const struct iio_event_spec bma400_activity_event = { 197 .type = IIO_EV_TYPE_CHANGE, 198 .dir = IIO_EV_DIR_NONE, 199 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE), 200 }; 201 202 static const struct iio_event_spec bma400_accel_event[] = { 203 { 204 .type = IIO_EV_TYPE_MAG, 205 .dir = IIO_EV_DIR_FALLING, 206 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 207 BIT(IIO_EV_INFO_PERIOD) | 208 BIT(IIO_EV_INFO_HYSTERESIS) | 209 BIT(IIO_EV_INFO_ENABLE), 210 }, 211 { 212 .type = IIO_EV_TYPE_MAG, 213 .dir = IIO_EV_DIR_RISING, 214 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 215 BIT(IIO_EV_INFO_PERIOD) | 216 BIT(IIO_EV_INFO_HYSTERESIS) | 217 BIT(IIO_EV_INFO_ENABLE), 218 }, 219 }; 220 221 #define BMA400_ACC_CHANNEL(_index, _axis) { \ 222 .type = IIO_ACCEL, \ 223 .modified = 1, \ 224 .channel2 = IIO_MOD_##_axis, \ 225 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 226 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 227 BIT(IIO_CHAN_INFO_SCALE) | \ 228 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 229 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 230 BIT(IIO_CHAN_INFO_SCALE) | \ 231 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 232 .ext_info = bma400_ext_info, \ 233 .scan_index = _index, \ 234 .scan_type = { \ 235 .sign = 's', \ 236 .realbits = 12, \ 237 .storagebits = 16, \ 238 .endianness = IIO_LE, \ 239 }, \ 240 .event_spec = bma400_accel_event, \ 241 .num_event_specs = ARRAY_SIZE(bma400_accel_event) \ 242 } 243 244 #define BMA400_ACTIVITY_CHANNEL(_chan2) { \ 245 .type = IIO_ACTIVITY, \ 246 .modified = 1, \ 247 .channel2 = _chan2, \ 248 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 249 .scan_index = -1, /* No buffer support */ \ 250 .event_spec = &bma400_activity_event, \ 251 .num_event_specs = 1, \ 252 } 253 254 static const struct iio_chan_spec bma400_channels[] = { 255 BMA400_ACC_CHANNEL(0, X), 256 BMA400_ACC_CHANNEL(1, Y), 257 BMA400_ACC_CHANNEL(2, Z), 258 { 259 .type = IIO_TEMP, 260 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), 261 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), 262 .scan_index = 3, 263 .scan_type = { 264 .sign = 's', 265 .realbits = 8, 266 .storagebits = 8, 267 .endianness = IIO_LE, 268 }, 269 }, 270 { 271 .type = IIO_STEPS, 272 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | 273 BIT(IIO_CHAN_INFO_ENABLE), 274 .scan_index = -1, /* No buffer support */ 275 .event_spec = &bma400_step_detect_event, 276 .num_event_specs = 1, 277 }, 278 BMA400_ACTIVITY_CHANNEL(IIO_MOD_STILL), 279 BMA400_ACTIVITY_CHANNEL(IIO_MOD_WALKING), 280 BMA400_ACTIVITY_CHANNEL(IIO_MOD_RUNNING), 281 IIO_CHAN_SOFT_TIMESTAMP(4), 282 }; 283 284 static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2) 285 { 286 unsigned int raw_temp; 287 int host_temp; 288 int ret; 289 290 if (data->power_mode == POWER_MODE_SLEEP) 291 return -EBUSY; 292 293 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &raw_temp); 294 if (ret) 295 return ret; 296 297 host_temp = sign_extend32(raw_temp, 7); 298 /* 299 * The formula for the TEMP_DATA register in the datasheet 300 * is: x * 0.5 + 23 301 */ 302 *val = (host_temp >> 1) + 23; 303 *val2 = (host_temp & 0x1) * 500000; 304 return IIO_VAL_INT_PLUS_MICRO; 305 } 306 307 static int bma400_get_accel_reg(struct bma400_data *data, 308 const struct iio_chan_spec *chan, 309 int *val) 310 { 311 __le16 raw_accel; 312 int lsb_reg; 313 int ret; 314 315 if (data->power_mode == POWER_MODE_SLEEP) 316 return -EBUSY; 317 318 switch (chan->channel2) { 319 case IIO_MOD_X: 320 lsb_reg = BMA400_X_AXIS_LSB_REG; 321 break; 322 case IIO_MOD_Y: 323 lsb_reg = BMA400_Y_AXIS_LSB_REG; 324 break; 325 case IIO_MOD_Z: 326 lsb_reg = BMA400_Z_AXIS_LSB_REG; 327 break; 328 default: 329 dev_err(data->dev, "invalid axis channel modifier\n"); 330 return -EINVAL; 331 } 332 333 /* bulk read two registers, with the base being the LSB register */ 334 ret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel, 335 sizeof(raw_accel)); 336 if (ret) 337 return ret; 338 339 *val = sign_extend32(le16_to_cpu(raw_accel), 11); 340 return IIO_VAL_INT; 341 } 342 343 static void bma400_output_data_rate_from_raw(int raw, unsigned int *val, 344 unsigned int *val2) 345 { 346 *val = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw); 347 if (raw > BMA400_ACC_ODR_MIN_RAW) 348 *val2 = 0; 349 else 350 *val2 = 500000; 351 } 352 353 static int bma400_get_accel_output_data_rate(struct bma400_data *data) 354 { 355 unsigned int val; 356 unsigned int odr; 357 int ret; 358 359 switch (data->power_mode) { 360 case POWER_MODE_LOW: 361 /* 362 * Runs at a fixed rate in low-power mode. See section 4.3 363 * in the datasheet. 364 */ 365 bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW, 366 &data->sample_freq.hz, 367 &data->sample_freq.uhz); 368 return 0; 369 case POWER_MODE_NORMAL: 370 /* 371 * In normal mode the ODR can be found in the ACC_CONFIG1 372 * register. 373 */ 374 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 375 if (ret) 376 goto error; 377 378 odr = val & BMA400_ACC_ODR_MASK; 379 if (odr < BMA400_ACC_ODR_MIN_RAW || 380 odr > BMA400_ACC_ODR_MAX_RAW) { 381 ret = -EINVAL; 382 goto error; 383 } 384 385 bma400_output_data_rate_from_raw(odr, &data->sample_freq.hz, 386 &data->sample_freq.uhz); 387 return 0; 388 case POWER_MODE_SLEEP: 389 data->sample_freq.hz = 0; 390 data->sample_freq.uhz = 0; 391 return 0; 392 default: 393 ret = 0; 394 goto error; 395 } 396 error: 397 data->sample_freq.hz = -1; 398 data->sample_freq.uhz = -1; 399 return ret; 400 } 401 402 static int bma400_set_accel_output_data_rate(struct bma400_data *data, 403 int hz, int uhz) 404 { 405 unsigned int idx; 406 unsigned int odr; 407 unsigned int val; 408 int ret; 409 410 if (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) { 411 if (uhz || hz > BMA400_ACC_ODR_MAX_HZ) 412 return -EINVAL; 413 414 /* Note this works because MIN_WHOLE_HZ is odd */ 415 idx = __ffs(hz); 416 417 if (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ) 418 return -EINVAL; 419 420 idx += BMA400_ACC_ODR_MIN_RAW + 1; 421 } else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) { 422 idx = BMA400_ACC_ODR_MIN_RAW; 423 } else { 424 return -EINVAL; 425 } 426 427 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 428 if (ret) 429 return ret; 430 431 /* preserve the range and normal mode osr */ 432 odr = (~BMA400_ACC_ODR_MASK & val) | idx; 433 434 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr); 435 if (ret) 436 return ret; 437 438 bma400_output_data_rate_from_raw(idx, &data->sample_freq.hz, 439 &data->sample_freq.uhz); 440 return 0; 441 } 442 443 static int bma400_get_accel_oversampling_ratio(struct bma400_data *data) 444 { 445 unsigned int val; 446 unsigned int osr; 447 int ret; 448 449 /* 450 * The oversampling ratio is stored in a different register 451 * based on the power-mode. In normal mode the OSR is stored 452 * in ACC_CONFIG1. In low-power mode it is stored in 453 * ACC_CONFIG0. 454 */ 455 switch (data->power_mode) { 456 case POWER_MODE_LOW: 457 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val); 458 if (ret) { 459 data->oversampling_ratio = -1; 460 return ret; 461 } 462 463 osr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; 464 465 data->oversampling_ratio = osr; 466 return 0; 467 case POWER_MODE_NORMAL: 468 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 469 if (ret) { 470 data->oversampling_ratio = -1; 471 return ret; 472 } 473 474 osr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; 475 476 data->oversampling_ratio = osr; 477 return 0; 478 case POWER_MODE_SLEEP: 479 data->oversampling_ratio = 0; 480 return 0; 481 default: 482 data->oversampling_ratio = -1; 483 return -EINVAL; 484 } 485 } 486 487 static int bma400_set_accel_oversampling_ratio(struct bma400_data *data, 488 int val) 489 { 490 unsigned int acc_config; 491 int ret; 492 493 if (val & ~BMA400_TWO_BITS_MASK) 494 return -EINVAL; 495 496 /* 497 * The oversampling ratio is stored in a different register 498 * based on the power-mode. 499 */ 500 switch (data->power_mode) { 501 case POWER_MODE_LOW: 502 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, 503 &acc_config); 504 if (ret) 505 return ret; 506 507 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, 508 (acc_config & ~BMA400_LP_OSR_MASK) | 509 (val << BMA400_LP_OSR_SHIFT)); 510 if (ret) { 511 dev_err(data->dev, "Failed to write out OSR\n"); 512 return ret; 513 } 514 515 data->oversampling_ratio = val; 516 return 0; 517 case POWER_MODE_NORMAL: 518 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, 519 &acc_config); 520 if (ret) 521 return ret; 522 523 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, 524 (acc_config & ~BMA400_NP_OSR_MASK) | 525 (val << BMA400_NP_OSR_SHIFT)); 526 if (ret) { 527 dev_err(data->dev, "Failed to write out OSR\n"); 528 return ret; 529 } 530 531 data->oversampling_ratio = val; 532 return 0; 533 default: 534 return -EINVAL; 535 } 536 return ret; 537 } 538 539 static int bma400_accel_scale_to_raw(struct bma400_data *data, 540 unsigned int val) 541 { 542 int raw; 543 544 if (val == 0) 545 return -EINVAL; 546 547 /* Note this works because BMA400_SCALE_MIN is odd */ 548 raw = __ffs(val); 549 550 if (val >> raw != BMA400_SCALE_MIN) 551 return -EINVAL; 552 553 return raw; 554 } 555 556 static int bma400_get_accel_scale(struct bma400_data *data) 557 { 558 unsigned int raw_scale; 559 unsigned int val; 560 int ret; 561 562 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 563 if (ret) 564 return ret; 565 566 raw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT; 567 if (raw_scale > BMA400_TWO_BITS_MASK) 568 return -EINVAL; 569 570 data->scale = BMA400_SCALE_MIN << raw_scale; 571 572 return 0; 573 } 574 575 static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val) 576 { 577 unsigned int acc_config; 578 int raw; 579 int ret; 580 581 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &acc_config); 582 if (ret) 583 return ret; 584 585 raw = bma400_accel_scale_to_raw(data, val); 586 if (raw < 0) 587 return raw; 588 589 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, 590 (acc_config & ~BMA400_ACC_SCALE_MASK) | 591 (raw << BMA400_SCALE_SHIFT)); 592 if (ret) 593 return ret; 594 595 data->scale = val; 596 return 0; 597 } 598 599 static int bma400_get_power_mode(struct bma400_data *data) 600 { 601 unsigned int val; 602 int ret; 603 604 ret = regmap_read(data->regmap, BMA400_STATUS_REG, &val); 605 if (ret) { 606 dev_err(data->dev, "Failed to read status register\n"); 607 return ret; 608 } 609 610 data->power_mode = (val >> 1) & BMA400_TWO_BITS_MASK; 611 return 0; 612 } 613 614 static int bma400_set_power_mode(struct bma400_data *data, 615 enum bma400_power_mode mode) 616 { 617 unsigned int val; 618 int ret; 619 620 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val); 621 if (ret) 622 return ret; 623 624 if (data->power_mode == mode) 625 return 0; 626 627 if (mode == POWER_MODE_INVALID) 628 return -EINVAL; 629 630 /* Preserve the low-power oversample ratio etc */ 631 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, 632 mode | (val & ~BMA400_TWO_BITS_MASK)); 633 if (ret) { 634 dev_err(data->dev, "Failed to write to power-mode\n"); 635 return ret; 636 } 637 638 data->power_mode = mode; 639 640 /* 641 * Update our cached osr and odr based on the new 642 * power-mode. 643 */ 644 bma400_get_accel_output_data_rate(data); 645 bma400_get_accel_oversampling_ratio(data); 646 return 0; 647 } 648 649 static int bma400_enable_steps(struct bma400_data *data, int val) 650 { 651 int ret; 652 653 if (data->steps_enabled == val) 654 return 0; 655 656 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, 657 BMA400_STEP_INT_MSK, 658 FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0)); 659 if (ret) 660 return ret; 661 data->steps_enabled = val; 662 return ret; 663 } 664 665 static int bma400_get_steps_reg(struct bma400_data *data, int *val) 666 { 667 u8 *steps_raw; 668 int ret; 669 670 steps_raw = kmalloc(BMA400_STEP_RAW_LEN, GFP_KERNEL); 671 if (!steps_raw) 672 return -ENOMEM; 673 674 ret = regmap_bulk_read(data->regmap, BMA400_STEP_CNT0_REG, 675 steps_raw, BMA400_STEP_RAW_LEN); 676 if (ret) 677 return ret; 678 *val = get_unaligned_le24(steps_raw); 679 kfree(steps_raw); 680 return IIO_VAL_INT; 681 } 682 683 static void bma400_init_tables(void) 684 { 685 int raw; 686 int i; 687 688 for (i = 0; i + 1 < ARRAY_SIZE(bma400_sample_freqs); i += 2) { 689 raw = (i / 2) + 5; 690 bma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i], 691 &bma400_sample_freqs[i + 1]); 692 } 693 694 for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) { 695 raw = i / 2; 696 bma400_scales[i] = 0; 697 bma400_scales[i + 1] = BMA400_SCALE_MIN << raw; 698 } 699 } 700 701 static void bma400_regulators_disable(void *data_ptr) 702 { 703 struct bma400_data *data = data_ptr; 704 705 regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators); 706 } 707 708 static void bma400_power_disable(void *data_ptr) 709 { 710 struct bma400_data *data = data_ptr; 711 int ret; 712 713 mutex_lock(&data->mutex); 714 ret = bma400_set_power_mode(data, POWER_MODE_SLEEP); 715 mutex_unlock(&data->mutex); 716 if (ret) 717 dev_warn(data->dev, "Failed to put device into sleep mode (%pe)\n", 718 ERR_PTR(ret)); 719 } 720 721 static enum iio_modifier bma400_act_to_mod(enum bma400_activity activity) 722 { 723 switch (activity) { 724 case BMA400_STILL: 725 return IIO_MOD_STILL; 726 case BMA400_WALKING: 727 return IIO_MOD_WALKING; 728 case BMA400_RUNNING: 729 return IIO_MOD_RUNNING; 730 default: 731 return IIO_NO_MOD; 732 } 733 } 734 735 static int bma400_init(struct bma400_data *data) 736 { 737 unsigned int val; 738 int ret; 739 740 /* Try to read chip_id register. It must return 0x90. */ 741 ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val); 742 if (ret) { 743 dev_err(data->dev, "Failed to read chip id register\n"); 744 return ret; 745 } 746 747 if (val != BMA400_ID_REG_VAL) { 748 dev_err(data->dev, "Chip ID mismatch\n"); 749 return -ENODEV; 750 } 751 752 data->regulators[BMA400_VDD_REGULATOR].supply = "vdd"; 753 data->regulators[BMA400_VDDIO_REGULATOR].supply = "vddio"; 754 ret = devm_regulator_bulk_get(data->dev, 755 ARRAY_SIZE(data->regulators), 756 data->regulators); 757 if (ret) { 758 if (ret != -EPROBE_DEFER) 759 dev_err(data->dev, 760 "Failed to get regulators: %d\n", 761 ret); 762 763 return ret; 764 } 765 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators), 766 data->regulators); 767 if (ret) { 768 dev_err(data->dev, "Failed to enable regulators: %d\n", 769 ret); 770 return ret; 771 } 772 773 ret = devm_add_action_or_reset(data->dev, bma400_regulators_disable, data); 774 if (ret) 775 return ret; 776 777 ret = bma400_get_power_mode(data); 778 if (ret) { 779 dev_err(data->dev, "Failed to get the initial power-mode\n"); 780 return ret; 781 } 782 783 if (data->power_mode != POWER_MODE_NORMAL) { 784 ret = bma400_set_power_mode(data, POWER_MODE_NORMAL); 785 if (ret) { 786 dev_err(data->dev, "Failed to wake up the device\n"); 787 return ret; 788 } 789 /* 790 * TODO: The datasheet waits 1500us here in the example, but 791 * lists 2/ODR as the wakeup time. 792 */ 793 usleep_range(1500, 2000); 794 } 795 796 ret = devm_add_action_or_reset(data->dev, bma400_power_disable, data); 797 if (ret) 798 return ret; 799 800 bma400_init_tables(); 801 802 ret = bma400_get_accel_output_data_rate(data); 803 if (ret) 804 return ret; 805 806 ret = bma400_get_accel_oversampling_ratio(data); 807 if (ret) 808 return ret; 809 810 ret = bma400_get_accel_scale(data); 811 if (ret) 812 return ret; 813 814 /* Configure INT1 pin to open drain */ 815 ret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06); 816 if (ret) 817 return ret; 818 /* 819 * Once the interrupt engine is supported we might use the 820 * data_src_reg, but for now ensure this is set to the 821 * variable ODR filter selectable by the sample frequency 822 * channel. 823 */ 824 return regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00); 825 } 826 827 static int bma400_read_raw(struct iio_dev *indio_dev, 828 struct iio_chan_spec const *chan, int *val, 829 int *val2, long mask) 830 { 831 struct bma400_data *data = iio_priv(indio_dev); 832 unsigned int activity; 833 int ret; 834 835 switch (mask) { 836 case IIO_CHAN_INFO_PROCESSED: 837 switch (chan->type) { 838 case IIO_TEMP: 839 mutex_lock(&data->mutex); 840 ret = bma400_get_temp_reg(data, val, val2); 841 mutex_unlock(&data->mutex); 842 return ret; 843 case IIO_STEPS: 844 return bma400_get_steps_reg(data, val); 845 case IIO_ACTIVITY: 846 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG, 847 &activity); 848 if (ret) 849 return ret; 850 /* 851 * The device does not support confidence value levels, 852 * so we will always have 100% for current activity and 853 * 0% for the others. 854 */ 855 if (chan->channel2 == bma400_act_to_mod(activity)) 856 *val = 100; 857 else 858 *val = 0; 859 return IIO_VAL_INT; 860 default: 861 return -EINVAL; 862 } 863 case IIO_CHAN_INFO_RAW: 864 mutex_lock(&data->mutex); 865 ret = bma400_get_accel_reg(data, chan, val); 866 mutex_unlock(&data->mutex); 867 return ret; 868 case IIO_CHAN_INFO_SAMP_FREQ: 869 switch (chan->type) { 870 case IIO_ACCEL: 871 if (data->sample_freq.hz < 0) 872 return -EINVAL; 873 874 *val = data->sample_freq.hz; 875 *val2 = data->sample_freq.uhz; 876 return IIO_VAL_INT_PLUS_MICRO; 877 case IIO_TEMP: 878 /* 879 * Runs at a fixed sampling frequency. See Section 4.4 880 * of the datasheet. 881 */ 882 *val = 6; 883 *val2 = 250000; 884 return IIO_VAL_INT_PLUS_MICRO; 885 default: 886 return -EINVAL; 887 } 888 case IIO_CHAN_INFO_SCALE: 889 *val = 0; 890 *val2 = data->scale; 891 return IIO_VAL_INT_PLUS_MICRO; 892 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 893 /* 894 * TODO: We could avoid this logic and returning -EINVAL here if 895 * we set both the low-power and normal mode OSR registers when 896 * we configure the device. 897 */ 898 if (data->oversampling_ratio < 0) 899 return -EINVAL; 900 901 *val = data->oversampling_ratio; 902 return IIO_VAL_INT; 903 case IIO_CHAN_INFO_ENABLE: 904 *val = data->steps_enabled; 905 return IIO_VAL_INT; 906 default: 907 return -EINVAL; 908 } 909 } 910 911 static int bma400_read_avail(struct iio_dev *indio_dev, 912 struct iio_chan_spec const *chan, 913 const int **vals, int *type, int *length, 914 long mask) 915 { 916 switch (mask) { 917 case IIO_CHAN_INFO_SCALE: 918 *type = IIO_VAL_INT_PLUS_MICRO; 919 *vals = bma400_scales; 920 *length = ARRAY_SIZE(bma400_scales); 921 return IIO_AVAIL_LIST; 922 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 923 *type = IIO_VAL_INT; 924 *vals = bma400_osr_range; 925 *length = ARRAY_SIZE(bma400_osr_range); 926 return IIO_AVAIL_RANGE; 927 case IIO_CHAN_INFO_SAMP_FREQ: 928 *type = IIO_VAL_INT_PLUS_MICRO; 929 *vals = bma400_sample_freqs; 930 *length = ARRAY_SIZE(bma400_sample_freqs); 931 return IIO_AVAIL_LIST; 932 default: 933 return -EINVAL; 934 } 935 } 936 937 static int bma400_write_raw(struct iio_dev *indio_dev, 938 struct iio_chan_spec const *chan, int val, int val2, 939 long mask) 940 { 941 struct bma400_data *data = iio_priv(indio_dev); 942 int ret; 943 944 switch (mask) { 945 case IIO_CHAN_INFO_SAMP_FREQ: 946 /* 947 * The sample frequency is readonly for the temperature 948 * register and a fixed value in low-power mode. 949 */ 950 if (chan->type != IIO_ACCEL) 951 return -EINVAL; 952 953 mutex_lock(&data->mutex); 954 ret = bma400_set_accel_output_data_rate(data, val, val2); 955 mutex_unlock(&data->mutex); 956 return ret; 957 case IIO_CHAN_INFO_SCALE: 958 if (val != 0 || 959 val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX) 960 return -EINVAL; 961 962 mutex_lock(&data->mutex); 963 ret = bma400_set_accel_scale(data, val2); 964 mutex_unlock(&data->mutex); 965 return ret; 966 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 967 mutex_lock(&data->mutex); 968 ret = bma400_set_accel_oversampling_ratio(data, val); 969 mutex_unlock(&data->mutex); 970 return ret; 971 case IIO_CHAN_INFO_ENABLE: 972 mutex_lock(&data->mutex); 973 ret = bma400_enable_steps(data, val); 974 mutex_unlock(&data->mutex); 975 return ret; 976 default: 977 return -EINVAL; 978 } 979 } 980 981 static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev, 982 struct iio_chan_spec const *chan, 983 long mask) 984 { 985 switch (mask) { 986 case IIO_CHAN_INFO_SAMP_FREQ: 987 return IIO_VAL_INT_PLUS_MICRO; 988 case IIO_CHAN_INFO_SCALE: 989 return IIO_VAL_INT_PLUS_MICRO; 990 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 991 return IIO_VAL_INT; 992 case IIO_CHAN_INFO_ENABLE: 993 return IIO_VAL_INT; 994 default: 995 return -EINVAL; 996 } 997 } 998 999 static int bma400_read_event_config(struct iio_dev *indio_dev, 1000 const struct iio_chan_spec *chan, 1001 enum iio_event_type type, 1002 enum iio_event_direction dir) 1003 { 1004 struct bma400_data *data = iio_priv(indio_dev); 1005 1006 switch (chan->type) { 1007 case IIO_ACCEL: 1008 switch (dir) { 1009 case IIO_EV_DIR_RISING: 1010 return FIELD_GET(BMA400_INT_GEN1_MSK, 1011 data->generic_event_en); 1012 case IIO_EV_DIR_FALLING: 1013 return FIELD_GET(BMA400_INT_GEN2_MSK, 1014 data->generic_event_en); 1015 default: 1016 return -EINVAL; 1017 } 1018 case IIO_STEPS: 1019 return data->step_event_en; 1020 case IIO_ACTIVITY: 1021 return data->activity_event_en; 1022 default: 1023 return -EINVAL; 1024 } 1025 } 1026 1027 static int bma400_steps_event_enable(struct bma400_data *data, int state) 1028 { 1029 int ret; 1030 1031 ret = bma400_enable_steps(data, 1); 1032 if (ret) 1033 return ret; 1034 1035 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, 1036 BMA400_STEP_INT_MSK, 1037 FIELD_PREP(BMA400_STEP_INT_MSK, 1038 state)); 1039 if (ret) 1040 return ret; 1041 data->step_event_en = state; 1042 return 0; 1043 } 1044 1045 static int bma400_activity_event_en(struct bma400_data *data, 1046 enum iio_event_direction dir, 1047 int state) 1048 { 1049 int ret, reg, msk, value, field_value; 1050 1051 switch (dir) { 1052 case IIO_EV_DIR_RISING: 1053 reg = BMA400_GEN1INT_CONFIG0; 1054 msk = BMA400_INT_GEN1_MSK; 1055 value = 2; 1056 set_mask_bits(&field_value, BMA400_INT_GEN1_MSK, 1057 FIELD_PREP(BMA400_INT_GEN1_MSK, state)); 1058 break; 1059 case IIO_EV_DIR_FALLING: 1060 reg = BMA400_GEN2INT_CONFIG0; 1061 msk = BMA400_INT_GEN2_MSK; 1062 value = 0; 1063 set_mask_bits(&field_value, BMA400_INT_GEN2_MSK, 1064 FIELD_PREP(BMA400_INT_GEN2_MSK, state)); 1065 break; 1066 default: 1067 return -EINVAL; 1068 } 1069 1070 /* Enabling all axis for interrupt evaluation */ 1071 ret = regmap_write(data->regmap, reg, 0xF8); 1072 if (ret) 1073 return ret; 1074 1075 /* OR combination of all axis for interrupt evaluation */ 1076 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value); 1077 if (ret) 1078 return ret; 1079 1080 /* Initial value to avoid interrupts while enabling*/ 1081 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A); 1082 if (ret) 1083 return ret; 1084 1085 /* Initial duration value to avoid interrupts while enabling*/ 1086 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F); 1087 if (ret) 1088 return ret; 1089 1090 ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk, 1091 field_value); 1092 if (ret) 1093 return ret; 1094 1095 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk, 1096 field_value); 1097 if (ret) 1098 return ret; 1099 1100 set_mask_bits(&data->generic_event_en, msk, field_value); 1101 return 0; 1102 } 1103 1104 static int bma400_write_event_config(struct iio_dev *indio_dev, 1105 const struct iio_chan_spec *chan, 1106 enum iio_event_type type, 1107 enum iio_event_direction dir, int state) 1108 { 1109 struct bma400_data *data = iio_priv(indio_dev); 1110 int ret; 1111 1112 switch (chan->type) { 1113 case IIO_ACCEL: 1114 mutex_lock(&data->mutex); 1115 ret = bma400_activity_event_en(data, dir, state); 1116 mutex_unlock(&data->mutex); 1117 return ret; 1118 case IIO_STEPS: 1119 mutex_lock(&data->mutex); 1120 ret = bma400_steps_event_enable(data, state); 1121 mutex_unlock(&data->mutex); 1122 return ret; 1123 case IIO_ACTIVITY: 1124 mutex_lock(&data->mutex); 1125 if (!data->step_event_en) { 1126 ret = bma400_steps_event_enable(data, true); 1127 if (ret) { 1128 mutex_unlock(&data->mutex); 1129 return ret; 1130 } 1131 } 1132 data->activity_event_en = state; 1133 mutex_unlock(&data->mutex); 1134 return 0; 1135 default: 1136 return -EINVAL; 1137 } 1138 } 1139 1140 static int get_gen_config_reg(enum iio_event_direction dir) 1141 { 1142 switch (dir) { 1143 case IIO_EV_DIR_FALLING: 1144 return BMA400_GEN2INT_CONFIG0; 1145 case IIO_EV_DIR_RISING: 1146 return BMA400_GEN1INT_CONFIG0; 1147 default: 1148 return -EINVAL; 1149 } 1150 } 1151 1152 static int bma400_read_event_value(struct iio_dev *indio_dev, 1153 const struct iio_chan_spec *chan, 1154 enum iio_event_type type, 1155 enum iio_event_direction dir, 1156 enum iio_event_info info, 1157 int *val, int *val2) 1158 { 1159 struct bma400_data *data = iio_priv(indio_dev); 1160 int ret, reg; 1161 1162 switch (chan->type) { 1163 case IIO_ACCEL: 1164 reg = get_gen_config_reg(dir); 1165 if (reg < 0) 1166 return -EINVAL; 1167 1168 *val2 = 0; 1169 switch (info) { 1170 case IIO_EV_INFO_VALUE: 1171 ret = regmap_read(data->regmap, 1172 reg + BMA400_GEN_CONFIG2_OFF, 1173 val); 1174 if (ret) 1175 return ret; 1176 return IIO_VAL_INT; 1177 case IIO_EV_INFO_PERIOD: 1178 mutex_lock(&data->mutex); 1179 ret = regmap_bulk_read(data->regmap, 1180 reg + BMA400_GEN_CONFIG3_OFF, 1181 &data->duration, 1182 sizeof(data->duration)); 1183 if (ret) { 1184 mutex_unlock(&data->mutex); 1185 return ret; 1186 } 1187 *val = be16_to_cpu(data->duration); 1188 mutex_unlock(&data->mutex); 1189 return IIO_VAL_INT; 1190 case IIO_EV_INFO_HYSTERESIS: 1191 ret = regmap_read(data->regmap, reg, val); 1192 if (ret) 1193 return ret; 1194 *val = FIELD_GET(BMA400_GEN_HYST_MSK, *val); 1195 return IIO_VAL_INT; 1196 default: 1197 return -EINVAL; 1198 } 1199 default: 1200 return -EINVAL; 1201 } 1202 } 1203 1204 static int bma400_write_event_value(struct iio_dev *indio_dev, 1205 const struct iio_chan_spec *chan, 1206 enum iio_event_type type, 1207 enum iio_event_direction dir, 1208 enum iio_event_info info, 1209 int val, int val2) 1210 { 1211 struct bma400_data *data = iio_priv(indio_dev); 1212 int reg, ret; 1213 1214 switch (chan->type) { 1215 case IIO_ACCEL: 1216 reg = get_gen_config_reg(dir); 1217 if (reg < 0) 1218 return -EINVAL; 1219 1220 switch (info) { 1221 case IIO_EV_INFO_VALUE: 1222 if (val < 1 || val > 255) 1223 return -EINVAL; 1224 1225 return regmap_write(data->regmap, 1226 reg + BMA400_GEN_CONFIG2_OFF, 1227 val); 1228 case IIO_EV_INFO_PERIOD: 1229 if (val < 1 || val > 65535) 1230 return -EINVAL; 1231 1232 mutex_lock(&data->mutex); 1233 put_unaligned_be16(val, &data->duration); 1234 ret = regmap_bulk_write(data->regmap, 1235 reg + BMA400_GEN_CONFIG3_OFF, 1236 &data->duration, 1237 sizeof(data->duration)); 1238 mutex_unlock(&data->mutex); 1239 return ret; 1240 case IIO_EV_INFO_HYSTERESIS: 1241 if (val < 0 || val > 3) 1242 return -EINVAL; 1243 1244 return regmap_update_bits(data->regmap, reg, 1245 BMA400_GEN_HYST_MSK, 1246 FIELD_PREP(BMA400_GEN_HYST_MSK, 1247 val)); 1248 default: 1249 return -EINVAL; 1250 } 1251 default: 1252 return -EINVAL; 1253 } 1254 } 1255 1256 static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig, 1257 bool state) 1258 { 1259 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1260 struct bma400_data *data = iio_priv(indio_dev); 1261 int ret; 1262 1263 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, 1264 BMA400_INT_DRDY_MSK, 1265 FIELD_PREP(BMA400_INT_DRDY_MSK, state)); 1266 if (ret) 1267 return ret; 1268 1269 return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, 1270 BMA400_INT_DRDY_MSK, 1271 FIELD_PREP(BMA400_INT_DRDY_MSK, state)); 1272 } 1273 1274 static const unsigned long bma400_avail_scan_masks[] = { 1275 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z), 1276 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z) 1277 | BIT(BMA400_TEMP), 1278 0 1279 }; 1280 1281 static const struct iio_info bma400_info = { 1282 .read_raw = bma400_read_raw, 1283 .read_avail = bma400_read_avail, 1284 .write_raw = bma400_write_raw, 1285 .write_raw_get_fmt = bma400_write_raw_get_fmt, 1286 .read_event_config = bma400_read_event_config, 1287 .write_event_config = bma400_write_event_config, 1288 .write_event_value = bma400_write_event_value, 1289 .read_event_value = bma400_read_event_value, 1290 }; 1291 1292 static const struct iio_trigger_ops bma400_trigger_ops = { 1293 .set_trigger_state = &bma400_data_rdy_trigger_set_state, 1294 .validate_device = &iio_trigger_validate_own_device, 1295 }; 1296 1297 static irqreturn_t bma400_trigger_handler(int irq, void *p) 1298 { 1299 struct iio_poll_func *pf = p; 1300 struct iio_dev *indio_dev = pf->indio_dev; 1301 struct bma400_data *data = iio_priv(indio_dev); 1302 int ret, temp; 1303 1304 /* Lock to protect the data->buffer */ 1305 mutex_lock(&data->mutex); 1306 1307 /* bulk read six registers, with the base being the LSB register */ 1308 ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG, 1309 &data->buffer.buff, sizeof(data->buffer.buff)); 1310 if (ret) 1311 goto unlock_err; 1312 1313 if (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) { 1314 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp); 1315 if (ret) 1316 goto unlock_err; 1317 1318 data->buffer.temperature = temp; 1319 } 1320 1321 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer, 1322 iio_get_time_ns(indio_dev)); 1323 1324 mutex_unlock(&data->mutex); 1325 iio_trigger_notify_done(indio_dev->trig); 1326 return IRQ_HANDLED; 1327 1328 unlock_err: 1329 mutex_unlock(&data->mutex); 1330 return IRQ_NONE; 1331 } 1332 1333 static irqreturn_t bma400_interrupt(int irq, void *private) 1334 { 1335 struct iio_dev *indio_dev = private; 1336 struct bma400_data *data = iio_priv(indio_dev); 1337 s64 timestamp = iio_get_time_ns(indio_dev); 1338 unsigned int act, ev_dir = IIO_EV_DIR_NONE; 1339 int ret; 1340 1341 /* Lock to protect the data->status */ 1342 mutex_lock(&data->mutex); 1343 ret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG, 1344 &data->status, 1345 sizeof(data->status)); 1346 /* 1347 * if none of the bit is set in the status register then it is 1348 * spurious interrupt. 1349 */ 1350 if (ret || !data->status) 1351 goto unlock_err; 1352 1353 if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status))) 1354 ev_dir = IIO_EV_DIR_RISING; 1355 1356 if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status))) 1357 ev_dir = IIO_EV_DIR_FALLING; 1358 1359 if (ev_dir != IIO_EV_DIR_NONE) { 1360 iio_push_event(indio_dev, 1361 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1362 IIO_MOD_X_OR_Y_OR_Z, 1363 IIO_EV_TYPE_MAG, ev_dir), 1364 timestamp); 1365 } 1366 1367 if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) { 1368 iio_push_event(indio_dev, 1369 IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD, 1370 IIO_EV_TYPE_CHANGE, 1371 IIO_EV_DIR_NONE), 1372 timestamp); 1373 1374 if (data->activity_event_en) { 1375 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG, 1376 &act); 1377 if (ret) 1378 goto unlock_err; 1379 1380 iio_push_event(indio_dev, 1381 IIO_MOD_EVENT_CODE(IIO_ACTIVITY, 0, 1382 bma400_act_to_mod(act), 1383 IIO_EV_TYPE_CHANGE, 1384 IIO_EV_DIR_NONE), 1385 timestamp); 1386 } 1387 } 1388 1389 if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) { 1390 mutex_unlock(&data->mutex); 1391 iio_trigger_poll_chained(data->trig); 1392 return IRQ_HANDLED; 1393 } 1394 1395 mutex_unlock(&data->mutex); 1396 return IRQ_HANDLED; 1397 1398 unlock_err: 1399 mutex_unlock(&data->mutex); 1400 return IRQ_NONE; 1401 } 1402 1403 int bma400_probe(struct device *dev, struct regmap *regmap, int irq, 1404 const char *name) 1405 { 1406 struct iio_dev *indio_dev; 1407 struct bma400_data *data; 1408 int ret; 1409 1410 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1411 if (!indio_dev) 1412 return -ENOMEM; 1413 1414 data = iio_priv(indio_dev); 1415 data->regmap = regmap; 1416 data->dev = dev; 1417 1418 ret = bma400_init(data); 1419 if (ret) 1420 return ret; 1421 1422 ret = iio_read_mount_matrix(dev, &data->orientation); 1423 if (ret) 1424 return ret; 1425 1426 mutex_init(&data->mutex); 1427 indio_dev->name = name; 1428 indio_dev->info = &bma400_info; 1429 indio_dev->channels = bma400_channels; 1430 indio_dev->num_channels = ARRAY_SIZE(bma400_channels); 1431 indio_dev->available_scan_masks = bma400_avail_scan_masks; 1432 indio_dev->modes = INDIO_DIRECT_MODE; 1433 1434 if (irq > 0) { 1435 data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 1436 indio_dev->name, 1437 iio_device_id(indio_dev)); 1438 if (!data->trig) 1439 return -ENOMEM; 1440 1441 data->trig->ops = &bma400_trigger_ops; 1442 iio_trigger_set_drvdata(data->trig, indio_dev); 1443 1444 ret = devm_iio_trigger_register(data->dev, data->trig); 1445 if (ret) 1446 return dev_err_probe(data->dev, ret, 1447 "iio trigger register fail\n"); 1448 1449 indio_dev->trig = iio_trigger_get(data->trig); 1450 ret = devm_request_threaded_irq(dev, irq, NULL, 1451 &bma400_interrupt, 1452 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1453 indio_dev->name, indio_dev); 1454 if (ret) 1455 return dev_err_probe(data->dev, ret, 1456 "request irq %d failed\n", irq); 1457 } 1458 1459 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 1460 &bma400_trigger_handler, NULL); 1461 if (ret) 1462 return dev_err_probe(data->dev, ret, 1463 "iio triggered buffer setup failed\n"); 1464 1465 return devm_iio_device_register(dev, indio_dev); 1466 } 1467 EXPORT_SYMBOL_NS(bma400_probe, IIO_BMA400); 1468 1469 MODULE_AUTHOR("Dan Robertson <dan@dlrobertson.com>"); 1470 MODULE_DESCRIPTION("Bosch BMA400 triaxial acceleration sensor core"); 1471 MODULE_LICENSE("GPL"); 1472