1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Core IIO driver for Bosch BMA400 triaxial acceleration sensor. 4 * 5 * Copyright 2019 Dan Robertson <dan@dlrobertson.com> 6 * 7 * TODO: 8 * - Support for power management 9 * - Support events and interrupts 10 * - Create channel for step count 11 * - Create channel for sensor time 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/bitops.h> 16 #include <linux/device.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 24 #include <asm/unaligned.h> 25 26 #include <linux/iio/iio.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/sysfs.h> 30 #include <linux/iio/trigger.h> 31 #include <linux/iio/trigger_consumer.h> 32 #include <linux/iio/triggered_buffer.h> 33 34 #include "bma400.h" 35 36 /* 37 * The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may 38 * be selected with the acc_range bits of the ACC_CONFIG1 register. 39 * NB: This buffer is populated in the device init. 40 */ 41 static int bma400_scales[8]; 42 43 /* 44 * See the ACC_CONFIG1 section of the datasheet. 45 * NB: This buffer is populated in the device init. 46 */ 47 static int bma400_sample_freqs[14]; 48 49 static const int bma400_osr_range[] = { 0, 1, 3 }; 50 51 static int tap_reset_timeout[BMA400_TAP_TIM_LIST_LEN] = { 52 300000, 53 400000, 54 500000, 55 600000 56 }; 57 58 static int tap_max2min_time[BMA400_TAP_TIM_LIST_LEN] = { 59 30000, 60 45000, 61 60000, 62 90000 63 }; 64 65 static int double_tap2_min_delay[BMA400_TAP_TIM_LIST_LEN] = { 66 20000, 67 40000, 68 60000, 69 80000 70 }; 71 72 /* See the ACC_CONFIG0 section of the datasheet */ 73 enum bma400_power_mode { 74 POWER_MODE_SLEEP = 0x00, 75 POWER_MODE_LOW = 0x01, 76 POWER_MODE_NORMAL = 0x02, 77 POWER_MODE_INVALID = 0x03, 78 }; 79 80 enum bma400_scan { 81 BMA400_ACCL_X, 82 BMA400_ACCL_Y, 83 BMA400_ACCL_Z, 84 BMA400_TEMP, 85 }; 86 87 struct bma400_sample_freq { 88 int hz; 89 int uhz; 90 }; 91 92 enum bma400_activity { 93 BMA400_STILL, 94 BMA400_WALKING, 95 BMA400_RUNNING, 96 }; 97 98 struct bma400_data { 99 struct device *dev; 100 struct regmap *regmap; 101 struct regulator_bulk_data regulators[BMA400_NUM_REGULATORS]; 102 struct mutex mutex; /* data register lock */ 103 struct iio_mount_matrix orientation; 104 enum bma400_power_mode power_mode; 105 struct bma400_sample_freq sample_freq; 106 int oversampling_ratio; 107 int scale; 108 struct iio_trigger *trig; 109 int steps_enabled; 110 bool step_event_en; 111 bool activity_event_en; 112 unsigned int generic_event_en; 113 unsigned int tap_event_en_bitmask; 114 /* Correct time stamp alignment */ 115 struct { 116 __le16 buff[3]; 117 u8 temperature; 118 s64 ts __aligned(8); 119 } buffer __aligned(IIO_DMA_MINALIGN); 120 __le16 status; 121 __be16 duration; 122 }; 123 124 static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) 125 { 126 switch (reg) { 127 case BMA400_CHIP_ID_REG: 128 case BMA400_ERR_REG: 129 case BMA400_STATUS_REG: 130 case BMA400_X_AXIS_LSB_REG: 131 case BMA400_X_AXIS_MSB_REG: 132 case BMA400_Y_AXIS_LSB_REG: 133 case BMA400_Y_AXIS_MSB_REG: 134 case BMA400_Z_AXIS_LSB_REG: 135 case BMA400_Z_AXIS_MSB_REG: 136 case BMA400_SENSOR_TIME0: 137 case BMA400_SENSOR_TIME1: 138 case BMA400_SENSOR_TIME2: 139 case BMA400_EVENT_REG: 140 case BMA400_INT_STAT0_REG: 141 case BMA400_INT_STAT1_REG: 142 case BMA400_INT_STAT2_REG: 143 case BMA400_TEMP_DATA_REG: 144 case BMA400_FIFO_LENGTH0_REG: 145 case BMA400_FIFO_LENGTH1_REG: 146 case BMA400_FIFO_DATA_REG: 147 case BMA400_STEP_CNT0_REG: 148 case BMA400_STEP_CNT1_REG: 149 case BMA400_STEP_CNT3_REG: 150 case BMA400_STEP_STAT_REG: 151 return false; 152 default: 153 return true; 154 } 155 } 156 157 static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg) 158 { 159 switch (reg) { 160 case BMA400_ERR_REG: 161 case BMA400_STATUS_REG: 162 case BMA400_X_AXIS_LSB_REG: 163 case BMA400_X_AXIS_MSB_REG: 164 case BMA400_Y_AXIS_LSB_REG: 165 case BMA400_Y_AXIS_MSB_REG: 166 case BMA400_Z_AXIS_LSB_REG: 167 case BMA400_Z_AXIS_MSB_REG: 168 case BMA400_SENSOR_TIME0: 169 case BMA400_SENSOR_TIME1: 170 case BMA400_SENSOR_TIME2: 171 case BMA400_EVENT_REG: 172 case BMA400_INT_STAT0_REG: 173 case BMA400_INT_STAT1_REG: 174 case BMA400_INT_STAT2_REG: 175 case BMA400_TEMP_DATA_REG: 176 case BMA400_FIFO_LENGTH0_REG: 177 case BMA400_FIFO_LENGTH1_REG: 178 case BMA400_FIFO_DATA_REG: 179 case BMA400_STEP_CNT0_REG: 180 case BMA400_STEP_CNT1_REG: 181 case BMA400_STEP_CNT3_REG: 182 case BMA400_STEP_STAT_REG: 183 return true; 184 default: 185 return false; 186 } 187 } 188 189 const struct regmap_config bma400_regmap_config = { 190 .reg_bits = 8, 191 .val_bits = 8, 192 .max_register = BMA400_CMD_REG, 193 .cache_type = REGCACHE_RBTREE, 194 .writeable_reg = bma400_is_writable_reg, 195 .volatile_reg = bma400_is_volatile_reg, 196 }; 197 EXPORT_SYMBOL_NS(bma400_regmap_config, IIO_BMA400); 198 199 static const struct iio_mount_matrix * 200 bma400_accel_get_mount_matrix(const struct iio_dev *indio_dev, 201 const struct iio_chan_spec *chan) 202 { 203 struct bma400_data *data = iio_priv(indio_dev); 204 205 return &data->orientation; 206 } 207 208 static const struct iio_chan_spec_ext_info bma400_ext_info[] = { 209 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma400_accel_get_mount_matrix), 210 { } 211 }; 212 213 static const struct iio_event_spec bma400_step_detect_event = { 214 .type = IIO_EV_TYPE_CHANGE, 215 .dir = IIO_EV_DIR_NONE, 216 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 217 }; 218 219 static const struct iio_event_spec bma400_activity_event = { 220 .type = IIO_EV_TYPE_CHANGE, 221 .dir = IIO_EV_DIR_NONE, 222 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE), 223 }; 224 225 static const struct iio_event_spec bma400_accel_event[] = { 226 { 227 .type = IIO_EV_TYPE_MAG, 228 .dir = IIO_EV_DIR_FALLING, 229 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 230 BIT(IIO_EV_INFO_PERIOD) | 231 BIT(IIO_EV_INFO_HYSTERESIS) | 232 BIT(IIO_EV_INFO_ENABLE), 233 }, 234 { 235 .type = IIO_EV_TYPE_MAG, 236 .dir = IIO_EV_DIR_RISING, 237 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 238 BIT(IIO_EV_INFO_PERIOD) | 239 BIT(IIO_EV_INFO_HYSTERESIS) | 240 BIT(IIO_EV_INFO_ENABLE), 241 }, 242 { 243 .type = IIO_EV_TYPE_GESTURE, 244 .dir = IIO_EV_DIR_SINGLETAP, 245 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 246 BIT(IIO_EV_INFO_ENABLE) | 247 BIT(IIO_EV_INFO_RESET_TIMEOUT), 248 }, 249 { 250 .type = IIO_EV_TYPE_GESTURE, 251 .dir = IIO_EV_DIR_DOUBLETAP, 252 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 253 BIT(IIO_EV_INFO_ENABLE) | 254 BIT(IIO_EV_INFO_RESET_TIMEOUT) | 255 BIT(IIO_EV_INFO_TAP2_MIN_DELAY), 256 }, 257 }; 258 259 static int usec_to_tapreg_raw(int usec, const int *time_list) 260 { 261 int index; 262 263 for (index = 0; index < BMA400_TAP_TIM_LIST_LEN; index++) { 264 if (usec == time_list[index]) 265 return index; 266 } 267 return -EINVAL; 268 } 269 270 static ssize_t in_accel_gesture_tap_maxtomin_time_show(struct device *dev, 271 struct device_attribute *attr, 272 char *buf) 273 { 274 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 275 struct bma400_data *data = iio_priv(indio_dev); 276 int ret, reg_val, raw, vals[2]; 277 278 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, ®_val); 279 if (ret) 280 return ret; 281 282 raw = FIELD_GET(BMA400_TAP_TICSTH_MSK, reg_val); 283 vals[0] = 0; 284 vals[1] = tap_max2min_time[raw]; 285 286 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals); 287 } 288 289 static ssize_t in_accel_gesture_tap_maxtomin_time_store(struct device *dev, 290 struct device_attribute *attr, 291 const char *buf, size_t len) 292 { 293 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 294 struct bma400_data *data = iio_priv(indio_dev); 295 int ret, val_int, val_fract, raw; 296 297 ret = iio_str_to_fixpoint(buf, 100000, &val_int, &val_fract); 298 if (ret) 299 return ret; 300 301 raw = usec_to_tapreg_raw(val_fract, tap_max2min_time); 302 if (raw < 0) 303 return -EINVAL; 304 305 ret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1, 306 BMA400_TAP_TICSTH_MSK, 307 FIELD_PREP(BMA400_TAP_TICSTH_MSK, raw)); 308 if (ret) 309 return ret; 310 311 return len; 312 } 313 314 static IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_maxtomin_time, 0); 315 316 /* 317 * Tap interrupts works with 200 Hz input data rate and the time based tap 318 * controls are in the terms of data samples so the below calculation is 319 * used to convert the configuration values into seconds. 320 * e.g.: 321 * 60 data samples * 0.005 ms = 0.3 seconds. 322 * 80 data samples * 0.005 ms = 0.4 seconds. 323 */ 324 325 /* quiet configuration values in seconds */ 326 static IIO_CONST_ATTR(in_accel_gesture_tap_reset_timeout_available, 327 "0.3 0.4 0.5 0.6"); 328 329 /* tics_th configuration values in seconds */ 330 static IIO_CONST_ATTR(in_accel_gesture_tap_maxtomin_time_available, 331 "0.03 0.045 0.06 0.09"); 332 333 /* quiet_dt configuration values in seconds */ 334 static IIO_CONST_ATTR(in_accel_gesture_doubletap_tap2_min_delay_available, 335 "0.02 0.04 0.06 0.08"); 336 337 /* List of sensitivity values available to configure tap interrupts */ 338 static IIO_CONST_ATTR(in_accel_gesture_tap_value_available, "0 1 2 3 4 5 6 7"); 339 340 static struct attribute *bma400_event_attributes[] = { 341 &iio_const_attr_in_accel_gesture_tap_value_available.dev_attr.attr, 342 &iio_const_attr_in_accel_gesture_tap_reset_timeout_available.dev_attr.attr, 343 &iio_const_attr_in_accel_gesture_tap_maxtomin_time_available.dev_attr.attr, 344 &iio_const_attr_in_accel_gesture_doubletap_tap2_min_delay_available.dev_attr.attr, 345 &iio_dev_attr_in_accel_gesture_tap_maxtomin_time.dev_attr.attr, 346 NULL 347 }; 348 349 static const struct attribute_group bma400_event_attribute_group = { 350 .attrs = bma400_event_attributes, 351 }; 352 353 #define BMA400_ACC_CHANNEL(_index, _axis) { \ 354 .type = IIO_ACCEL, \ 355 .modified = 1, \ 356 .channel2 = IIO_MOD_##_axis, \ 357 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 358 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 359 BIT(IIO_CHAN_INFO_SCALE) | \ 360 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 361 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 362 BIT(IIO_CHAN_INFO_SCALE) | \ 363 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 364 .ext_info = bma400_ext_info, \ 365 .scan_index = _index, \ 366 .scan_type = { \ 367 .sign = 's', \ 368 .realbits = 12, \ 369 .storagebits = 16, \ 370 .endianness = IIO_LE, \ 371 }, \ 372 .event_spec = bma400_accel_event, \ 373 .num_event_specs = ARRAY_SIZE(bma400_accel_event) \ 374 } 375 376 #define BMA400_ACTIVITY_CHANNEL(_chan2) { \ 377 .type = IIO_ACTIVITY, \ 378 .modified = 1, \ 379 .channel2 = _chan2, \ 380 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 381 .scan_index = -1, /* No buffer support */ \ 382 .event_spec = &bma400_activity_event, \ 383 .num_event_specs = 1, \ 384 } 385 386 static const struct iio_chan_spec bma400_channels[] = { 387 BMA400_ACC_CHANNEL(0, X), 388 BMA400_ACC_CHANNEL(1, Y), 389 BMA400_ACC_CHANNEL(2, Z), 390 { 391 .type = IIO_TEMP, 392 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), 393 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), 394 .scan_index = 3, 395 .scan_type = { 396 .sign = 's', 397 .realbits = 8, 398 .storagebits = 8, 399 .endianness = IIO_LE, 400 }, 401 }, 402 { 403 .type = IIO_STEPS, 404 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | 405 BIT(IIO_CHAN_INFO_ENABLE), 406 .scan_index = -1, /* No buffer support */ 407 .event_spec = &bma400_step_detect_event, 408 .num_event_specs = 1, 409 }, 410 BMA400_ACTIVITY_CHANNEL(IIO_MOD_STILL), 411 BMA400_ACTIVITY_CHANNEL(IIO_MOD_WALKING), 412 BMA400_ACTIVITY_CHANNEL(IIO_MOD_RUNNING), 413 IIO_CHAN_SOFT_TIMESTAMP(4), 414 }; 415 416 static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2) 417 { 418 unsigned int raw_temp; 419 int host_temp; 420 int ret; 421 422 if (data->power_mode == POWER_MODE_SLEEP) 423 return -EBUSY; 424 425 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &raw_temp); 426 if (ret) 427 return ret; 428 429 host_temp = sign_extend32(raw_temp, 7); 430 /* 431 * The formula for the TEMP_DATA register in the datasheet 432 * is: x * 0.5 + 23 433 */ 434 *val = (host_temp >> 1) + 23; 435 *val2 = (host_temp & 0x1) * 500000; 436 return IIO_VAL_INT_PLUS_MICRO; 437 } 438 439 static int bma400_get_accel_reg(struct bma400_data *data, 440 const struct iio_chan_spec *chan, 441 int *val) 442 { 443 __le16 raw_accel; 444 int lsb_reg; 445 int ret; 446 447 if (data->power_mode == POWER_MODE_SLEEP) 448 return -EBUSY; 449 450 switch (chan->channel2) { 451 case IIO_MOD_X: 452 lsb_reg = BMA400_X_AXIS_LSB_REG; 453 break; 454 case IIO_MOD_Y: 455 lsb_reg = BMA400_Y_AXIS_LSB_REG; 456 break; 457 case IIO_MOD_Z: 458 lsb_reg = BMA400_Z_AXIS_LSB_REG; 459 break; 460 default: 461 dev_err(data->dev, "invalid axis channel modifier\n"); 462 return -EINVAL; 463 } 464 465 /* bulk read two registers, with the base being the LSB register */ 466 ret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel, 467 sizeof(raw_accel)); 468 if (ret) 469 return ret; 470 471 *val = sign_extend32(le16_to_cpu(raw_accel), 11); 472 return IIO_VAL_INT; 473 } 474 475 static void bma400_output_data_rate_from_raw(int raw, unsigned int *val, 476 unsigned int *val2) 477 { 478 *val = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw); 479 if (raw > BMA400_ACC_ODR_MIN_RAW) 480 *val2 = 0; 481 else 482 *val2 = 500000; 483 } 484 485 static int bma400_get_accel_output_data_rate(struct bma400_data *data) 486 { 487 unsigned int val; 488 unsigned int odr; 489 int ret; 490 491 switch (data->power_mode) { 492 case POWER_MODE_LOW: 493 /* 494 * Runs at a fixed rate in low-power mode. See section 4.3 495 * in the datasheet. 496 */ 497 bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW, 498 &data->sample_freq.hz, 499 &data->sample_freq.uhz); 500 return 0; 501 case POWER_MODE_NORMAL: 502 /* 503 * In normal mode the ODR can be found in the ACC_CONFIG1 504 * register. 505 */ 506 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 507 if (ret) 508 goto error; 509 510 odr = val & BMA400_ACC_ODR_MASK; 511 if (odr < BMA400_ACC_ODR_MIN_RAW || 512 odr > BMA400_ACC_ODR_MAX_RAW) { 513 ret = -EINVAL; 514 goto error; 515 } 516 517 bma400_output_data_rate_from_raw(odr, &data->sample_freq.hz, 518 &data->sample_freq.uhz); 519 return 0; 520 case POWER_MODE_SLEEP: 521 data->sample_freq.hz = 0; 522 data->sample_freq.uhz = 0; 523 return 0; 524 default: 525 ret = 0; 526 goto error; 527 } 528 error: 529 data->sample_freq.hz = -1; 530 data->sample_freq.uhz = -1; 531 return ret; 532 } 533 534 static int bma400_set_accel_output_data_rate(struct bma400_data *data, 535 int hz, int uhz) 536 { 537 unsigned int idx; 538 unsigned int odr; 539 unsigned int val; 540 int ret; 541 542 if (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) { 543 if (uhz || hz > BMA400_ACC_ODR_MAX_HZ) 544 return -EINVAL; 545 546 /* Note this works because MIN_WHOLE_HZ is odd */ 547 idx = __ffs(hz); 548 549 if (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ) 550 return -EINVAL; 551 552 idx += BMA400_ACC_ODR_MIN_RAW + 1; 553 } else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) { 554 idx = BMA400_ACC_ODR_MIN_RAW; 555 } else { 556 return -EINVAL; 557 } 558 559 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 560 if (ret) 561 return ret; 562 563 /* preserve the range and normal mode osr */ 564 odr = (~BMA400_ACC_ODR_MASK & val) | idx; 565 566 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr); 567 if (ret) 568 return ret; 569 570 bma400_output_data_rate_from_raw(idx, &data->sample_freq.hz, 571 &data->sample_freq.uhz); 572 return 0; 573 } 574 575 static int bma400_get_accel_oversampling_ratio(struct bma400_data *data) 576 { 577 unsigned int val; 578 unsigned int osr; 579 int ret; 580 581 /* 582 * The oversampling ratio is stored in a different register 583 * based on the power-mode. In normal mode the OSR is stored 584 * in ACC_CONFIG1. In low-power mode it is stored in 585 * ACC_CONFIG0. 586 */ 587 switch (data->power_mode) { 588 case POWER_MODE_LOW: 589 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val); 590 if (ret) { 591 data->oversampling_ratio = -1; 592 return ret; 593 } 594 595 osr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; 596 597 data->oversampling_ratio = osr; 598 return 0; 599 case POWER_MODE_NORMAL: 600 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 601 if (ret) { 602 data->oversampling_ratio = -1; 603 return ret; 604 } 605 606 osr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; 607 608 data->oversampling_ratio = osr; 609 return 0; 610 case POWER_MODE_SLEEP: 611 data->oversampling_ratio = 0; 612 return 0; 613 default: 614 data->oversampling_ratio = -1; 615 return -EINVAL; 616 } 617 } 618 619 static int bma400_set_accel_oversampling_ratio(struct bma400_data *data, 620 int val) 621 { 622 unsigned int acc_config; 623 int ret; 624 625 if (val & ~BMA400_TWO_BITS_MASK) 626 return -EINVAL; 627 628 /* 629 * The oversampling ratio is stored in a different register 630 * based on the power-mode. 631 */ 632 switch (data->power_mode) { 633 case POWER_MODE_LOW: 634 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, 635 &acc_config); 636 if (ret) 637 return ret; 638 639 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, 640 (acc_config & ~BMA400_LP_OSR_MASK) | 641 (val << BMA400_LP_OSR_SHIFT)); 642 if (ret) { 643 dev_err(data->dev, "Failed to write out OSR\n"); 644 return ret; 645 } 646 647 data->oversampling_ratio = val; 648 return 0; 649 case POWER_MODE_NORMAL: 650 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, 651 &acc_config); 652 if (ret) 653 return ret; 654 655 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, 656 (acc_config & ~BMA400_NP_OSR_MASK) | 657 (val << BMA400_NP_OSR_SHIFT)); 658 if (ret) { 659 dev_err(data->dev, "Failed to write out OSR\n"); 660 return ret; 661 } 662 663 data->oversampling_ratio = val; 664 return 0; 665 default: 666 return -EINVAL; 667 } 668 return ret; 669 } 670 671 static int bma400_accel_scale_to_raw(struct bma400_data *data, 672 unsigned int val) 673 { 674 int raw; 675 676 if (val == 0) 677 return -EINVAL; 678 679 /* Note this works because BMA400_SCALE_MIN is odd */ 680 raw = __ffs(val); 681 682 if (val >> raw != BMA400_SCALE_MIN) 683 return -EINVAL; 684 685 return raw; 686 } 687 688 static int bma400_get_accel_scale(struct bma400_data *data) 689 { 690 unsigned int raw_scale; 691 unsigned int val; 692 int ret; 693 694 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val); 695 if (ret) 696 return ret; 697 698 raw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT; 699 if (raw_scale > BMA400_TWO_BITS_MASK) 700 return -EINVAL; 701 702 data->scale = BMA400_SCALE_MIN << raw_scale; 703 704 return 0; 705 } 706 707 static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val) 708 { 709 unsigned int acc_config; 710 int raw; 711 int ret; 712 713 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &acc_config); 714 if (ret) 715 return ret; 716 717 raw = bma400_accel_scale_to_raw(data, val); 718 if (raw < 0) 719 return raw; 720 721 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, 722 (acc_config & ~BMA400_ACC_SCALE_MASK) | 723 (raw << BMA400_SCALE_SHIFT)); 724 if (ret) 725 return ret; 726 727 data->scale = val; 728 return 0; 729 } 730 731 static int bma400_get_power_mode(struct bma400_data *data) 732 { 733 unsigned int val; 734 int ret; 735 736 ret = regmap_read(data->regmap, BMA400_STATUS_REG, &val); 737 if (ret) { 738 dev_err(data->dev, "Failed to read status register\n"); 739 return ret; 740 } 741 742 data->power_mode = (val >> 1) & BMA400_TWO_BITS_MASK; 743 return 0; 744 } 745 746 static int bma400_set_power_mode(struct bma400_data *data, 747 enum bma400_power_mode mode) 748 { 749 unsigned int val; 750 int ret; 751 752 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val); 753 if (ret) 754 return ret; 755 756 if (data->power_mode == mode) 757 return 0; 758 759 if (mode == POWER_MODE_INVALID) 760 return -EINVAL; 761 762 /* Preserve the low-power oversample ratio etc */ 763 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, 764 mode | (val & ~BMA400_TWO_BITS_MASK)); 765 if (ret) { 766 dev_err(data->dev, "Failed to write to power-mode\n"); 767 return ret; 768 } 769 770 data->power_mode = mode; 771 772 /* 773 * Update our cached osr and odr based on the new 774 * power-mode. 775 */ 776 bma400_get_accel_output_data_rate(data); 777 bma400_get_accel_oversampling_ratio(data); 778 return 0; 779 } 780 781 static int bma400_enable_steps(struct bma400_data *data, int val) 782 { 783 int ret; 784 785 if (data->steps_enabled == val) 786 return 0; 787 788 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, 789 BMA400_STEP_INT_MSK, 790 FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0)); 791 if (ret) 792 return ret; 793 data->steps_enabled = val; 794 return ret; 795 } 796 797 static int bma400_get_steps_reg(struct bma400_data *data, int *val) 798 { 799 u8 *steps_raw; 800 int ret; 801 802 steps_raw = kmalloc(BMA400_STEP_RAW_LEN, GFP_KERNEL); 803 if (!steps_raw) 804 return -ENOMEM; 805 806 ret = regmap_bulk_read(data->regmap, BMA400_STEP_CNT0_REG, 807 steps_raw, BMA400_STEP_RAW_LEN); 808 if (ret) 809 return ret; 810 *val = get_unaligned_le24(steps_raw); 811 kfree(steps_raw); 812 return IIO_VAL_INT; 813 } 814 815 static void bma400_init_tables(void) 816 { 817 int raw; 818 int i; 819 820 for (i = 0; i + 1 < ARRAY_SIZE(bma400_sample_freqs); i += 2) { 821 raw = (i / 2) + 5; 822 bma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i], 823 &bma400_sample_freqs[i + 1]); 824 } 825 826 for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) { 827 raw = i / 2; 828 bma400_scales[i] = 0; 829 bma400_scales[i + 1] = BMA400_SCALE_MIN << raw; 830 } 831 } 832 833 static void bma400_regulators_disable(void *data_ptr) 834 { 835 struct bma400_data *data = data_ptr; 836 837 regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators); 838 } 839 840 static void bma400_power_disable(void *data_ptr) 841 { 842 struct bma400_data *data = data_ptr; 843 int ret; 844 845 mutex_lock(&data->mutex); 846 ret = bma400_set_power_mode(data, POWER_MODE_SLEEP); 847 mutex_unlock(&data->mutex); 848 if (ret) 849 dev_warn(data->dev, "Failed to put device into sleep mode (%pe)\n", 850 ERR_PTR(ret)); 851 } 852 853 static enum iio_modifier bma400_act_to_mod(enum bma400_activity activity) 854 { 855 switch (activity) { 856 case BMA400_STILL: 857 return IIO_MOD_STILL; 858 case BMA400_WALKING: 859 return IIO_MOD_WALKING; 860 case BMA400_RUNNING: 861 return IIO_MOD_RUNNING; 862 default: 863 return IIO_NO_MOD; 864 } 865 } 866 867 static int bma400_init(struct bma400_data *data) 868 { 869 unsigned int val; 870 int ret; 871 872 /* Try to read chip_id register. It must return 0x90. */ 873 ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val); 874 if (ret) { 875 dev_err(data->dev, "Failed to read chip id register\n"); 876 return ret; 877 } 878 879 if (val != BMA400_ID_REG_VAL) { 880 dev_err(data->dev, "Chip ID mismatch\n"); 881 return -ENODEV; 882 } 883 884 data->regulators[BMA400_VDD_REGULATOR].supply = "vdd"; 885 data->regulators[BMA400_VDDIO_REGULATOR].supply = "vddio"; 886 ret = devm_regulator_bulk_get(data->dev, 887 ARRAY_SIZE(data->regulators), 888 data->regulators); 889 if (ret) { 890 if (ret != -EPROBE_DEFER) 891 dev_err(data->dev, 892 "Failed to get regulators: %d\n", 893 ret); 894 895 return ret; 896 } 897 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators), 898 data->regulators); 899 if (ret) { 900 dev_err(data->dev, "Failed to enable regulators: %d\n", 901 ret); 902 return ret; 903 } 904 905 ret = devm_add_action_or_reset(data->dev, bma400_regulators_disable, data); 906 if (ret) 907 return ret; 908 909 ret = bma400_get_power_mode(data); 910 if (ret) { 911 dev_err(data->dev, "Failed to get the initial power-mode\n"); 912 return ret; 913 } 914 915 if (data->power_mode != POWER_MODE_NORMAL) { 916 ret = bma400_set_power_mode(data, POWER_MODE_NORMAL); 917 if (ret) { 918 dev_err(data->dev, "Failed to wake up the device\n"); 919 return ret; 920 } 921 /* 922 * TODO: The datasheet waits 1500us here in the example, but 923 * lists 2/ODR as the wakeup time. 924 */ 925 usleep_range(1500, 2000); 926 } 927 928 ret = devm_add_action_or_reset(data->dev, bma400_power_disable, data); 929 if (ret) 930 return ret; 931 932 bma400_init_tables(); 933 934 ret = bma400_get_accel_output_data_rate(data); 935 if (ret) 936 return ret; 937 938 ret = bma400_get_accel_oversampling_ratio(data); 939 if (ret) 940 return ret; 941 942 ret = bma400_get_accel_scale(data); 943 if (ret) 944 return ret; 945 946 /* Configure INT1 pin to open drain */ 947 ret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06); 948 if (ret) 949 return ret; 950 /* 951 * Once the interrupt engine is supported we might use the 952 * data_src_reg, but for now ensure this is set to the 953 * variable ODR filter selectable by the sample frequency 954 * channel. 955 */ 956 return regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00); 957 } 958 959 static int bma400_read_raw(struct iio_dev *indio_dev, 960 struct iio_chan_spec const *chan, int *val, 961 int *val2, long mask) 962 { 963 struct bma400_data *data = iio_priv(indio_dev); 964 unsigned int activity; 965 int ret; 966 967 switch (mask) { 968 case IIO_CHAN_INFO_PROCESSED: 969 switch (chan->type) { 970 case IIO_TEMP: 971 mutex_lock(&data->mutex); 972 ret = bma400_get_temp_reg(data, val, val2); 973 mutex_unlock(&data->mutex); 974 return ret; 975 case IIO_STEPS: 976 return bma400_get_steps_reg(data, val); 977 case IIO_ACTIVITY: 978 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG, 979 &activity); 980 if (ret) 981 return ret; 982 /* 983 * The device does not support confidence value levels, 984 * so we will always have 100% for current activity and 985 * 0% for the others. 986 */ 987 if (chan->channel2 == bma400_act_to_mod(activity)) 988 *val = 100; 989 else 990 *val = 0; 991 return IIO_VAL_INT; 992 default: 993 return -EINVAL; 994 } 995 case IIO_CHAN_INFO_RAW: 996 mutex_lock(&data->mutex); 997 ret = bma400_get_accel_reg(data, chan, val); 998 mutex_unlock(&data->mutex); 999 return ret; 1000 case IIO_CHAN_INFO_SAMP_FREQ: 1001 switch (chan->type) { 1002 case IIO_ACCEL: 1003 if (data->sample_freq.hz < 0) 1004 return -EINVAL; 1005 1006 *val = data->sample_freq.hz; 1007 *val2 = data->sample_freq.uhz; 1008 return IIO_VAL_INT_PLUS_MICRO; 1009 case IIO_TEMP: 1010 /* 1011 * Runs at a fixed sampling frequency. See Section 4.4 1012 * of the datasheet. 1013 */ 1014 *val = 6; 1015 *val2 = 250000; 1016 return IIO_VAL_INT_PLUS_MICRO; 1017 default: 1018 return -EINVAL; 1019 } 1020 case IIO_CHAN_INFO_SCALE: 1021 *val = 0; 1022 *val2 = data->scale; 1023 return IIO_VAL_INT_PLUS_MICRO; 1024 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1025 /* 1026 * TODO: We could avoid this logic and returning -EINVAL here if 1027 * we set both the low-power and normal mode OSR registers when 1028 * we configure the device. 1029 */ 1030 if (data->oversampling_ratio < 0) 1031 return -EINVAL; 1032 1033 *val = data->oversampling_ratio; 1034 return IIO_VAL_INT; 1035 case IIO_CHAN_INFO_ENABLE: 1036 *val = data->steps_enabled; 1037 return IIO_VAL_INT; 1038 default: 1039 return -EINVAL; 1040 } 1041 } 1042 1043 static int bma400_read_avail(struct iio_dev *indio_dev, 1044 struct iio_chan_spec const *chan, 1045 const int **vals, int *type, int *length, 1046 long mask) 1047 { 1048 switch (mask) { 1049 case IIO_CHAN_INFO_SCALE: 1050 *type = IIO_VAL_INT_PLUS_MICRO; 1051 *vals = bma400_scales; 1052 *length = ARRAY_SIZE(bma400_scales); 1053 return IIO_AVAIL_LIST; 1054 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1055 *type = IIO_VAL_INT; 1056 *vals = bma400_osr_range; 1057 *length = ARRAY_SIZE(bma400_osr_range); 1058 return IIO_AVAIL_RANGE; 1059 case IIO_CHAN_INFO_SAMP_FREQ: 1060 *type = IIO_VAL_INT_PLUS_MICRO; 1061 *vals = bma400_sample_freqs; 1062 *length = ARRAY_SIZE(bma400_sample_freqs); 1063 return IIO_AVAIL_LIST; 1064 default: 1065 return -EINVAL; 1066 } 1067 } 1068 1069 static int bma400_write_raw(struct iio_dev *indio_dev, 1070 struct iio_chan_spec const *chan, int val, int val2, 1071 long mask) 1072 { 1073 struct bma400_data *data = iio_priv(indio_dev); 1074 int ret; 1075 1076 switch (mask) { 1077 case IIO_CHAN_INFO_SAMP_FREQ: 1078 /* 1079 * The sample frequency is readonly for the temperature 1080 * register and a fixed value in low-power mode. 1081 */ 1082 if (chan->type != IIO_ACCEL) 1083 return -EINVAL; 1084 1085 mutex_lock(&data->mutex); 1086 ret = bma400_set_accel_output_data_rate(data, val, val2); 1087 mutex_unlock(&data->mutex); 1088 return ret; 1089 case IIO_CHAN_INFO_SCALE: 1090 if (val != 0 || 1091 val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX) 1092 return -EINVAL; 1093 1094 mutex_lock(&data->mutex); 1095 ret = bma400_set_accel_scale(data, val2); 1096 mutex_unlock(&data->mutex); 1097 return ret; 1098 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1099 mutex_lock(&data->mutex); 1100 ret = bma400_set_accel_oversampling_ratio(data, val); 1101 mutex_unlock(&data->mutex); 1102 return ret; 1103 case IIO_CHAN_INFO_ENABLE: 1104 mutex_lock(&data->mutex); 1105 ret = bma400_enable_steps(data, val); 1106 mutex_unlock(&data->mutex); 1107 return ret; 1108 default: 1109 return -EINVAL; 1110 } 1111 } 1112 1113 static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev, 1114 struct iio_chan_spec const *chan, 1115 long mask) 1116 { 1117 switch (mask) { 1118 case IIO_CHAN_INFO_SAMP_FREQ: 1119 return IIO_VAL_INT_PLUS_MICRO; 1120 case IIO_CHAN_INFO_SCALE: 1121 return IIO_VAL_INT_PLUS_MICRO; 1122 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1123 return IIO_VAL_INT; 1124 case IIO_CHAN_INFO_ENABLE: 1125 return IIO_VAL_INT; 1126 default: 1127 return -EINVAL; 1128 } 1129 } 1130 1131 static int bma400_read_event_config(struct iio_dev *indio_dev, 1132 const struct iio_chan_spec *chan, 1133 enum iio_event_type type, 1134 enum iio_event_direction dir) 1135 { 1136 struct bma400_data *data = iio_priv(indio_dev); 1137 1138 switch (chan->type) { 1139 case IIO_ACCEL: 1140 switch (dir) { 1141 case IIO_EV_DIR_RISING: 1142 return FIELD_GET(BMA400_INT_GEN1_MSK, 1143 data->generic_event_en); 1144 case IIO_EV_DIR_FALLING: 1145 return FIELD_GET(BMA400_INT_GEN2_MSK, 1146 data->generic_event_en); 1147 case IIO_EV_DIR_SINGLETAP: 1148 return FIELD_GET(BMA400_S_TAP_MSK, 1149 data->tap_event_en_bitmask); 1150 case IIO_EV_DIR_DOUBLETAP: 1151 return FIELD_GET(BMA400_D_TAP_MSK, 1152 data->tap_event_en_bitmask); 1153 default: 1154 return -EINVAL; 1155 } 1156 case IIO_STEPS: 1157 return data->step_event_en; 1158 case IIO_ACTIVITY: 1159 return data->activity_event_en; 1160 default: 1161 return -EINVAL; 1162 } 1163 } 1164 1165 static int bma400_steps_event_enable(struct bma400_data *data, int state) 1166 { 1167 int ret; 1168 1169 ret = bma400_enable_steps(data, 1); 1170 if (ret) 1171 return ret; 1172 1173 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, 1174 BMA400_STEP_INT_MSK, 1175 FIELD_PREP(BMA400_STEP_INT_MSK, 1176 state)); 1177 if (ret) 1178 return ret; 1179 data->step_event_en = state; 1180 return 0; 1181 } 1182 1183 static int bma400_activity_event_en(struct bma400_data *data, 1184 enum iio_event_direction dir, 1185 int state) 1186 { 1187 int ret, reg, msk, value, field_value; 1188 1189 switch (dir) { 1190 case IIO_EV_DIR_RISING: 1191 reg = BMA400_GEN1INT_CONFIG0; 1192 msk = BMA400_INT_GEN1_MSK; 1193 value = 2; 1194 set_mask_bits(&field_value, BMA400_INT_GEN1_MSK, 1195 FIELD_PREP(BMA400_INT_GEN1_MSK, state)); 1196 break; 1197 case IIO_EV_DIR_FALLING: 1198 reg = BMA400_GEN2INT_CONFIG0; 1199 msk = BMA400_INT_GEN2_MSK; 1200 value = 0; 1201 set_mask_bits(&field_value, BMA400_INT_GEN2_MSK, 1202 FIELD_PREP(BMA400_INT_GEN2_MSK, state)); 1203 break; 1204 default: 1205 return -EINVAL; 1206 } 1207 1208 /* Enabling all axis for interrupt evaluation */ 1209 ret = regmap_write(data->regmap, reg, 0xF8); 1210 if (ret) 1211 return ret; 1212 1213 /* OR combination of all axis for interrupt evaluation */ 1214 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value); 1215 if (ret) 1216 return ret; 1217 1218 /* Initial value to avoid interrupts while enabling*/ 1219 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A); 1220 if (ret) 1221 return ret; 1222 1223 /* Initial duration value to avoid interrupts while enabling*/ 1224 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F); 1225 if (ret) 1226 return ret; 1227 1228 ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk, 1229 field_value); 1230 if (ret) 1231 return ret; 1232 1233 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk, 1234 field_value); 1235 if (ret) 1236 return ret; 1237 1238 set_mask_bits(&data->generic_event_en, msk, field_value); 1239 return 0; 1240 } 1241 1242 static int bma400_tap_event_en(struct bma400_data *data, 1243 enum iio_event_direction dir, int state) 1244 { 1245 unsigned int mask, field_value; 1246 int ret; 1247 1248 /* 1249 * Tap interrupts can be configured only in normal mode. 1250 * See table in section 4.3 "Power modes - performance modes" of 1251 * datasheet v1.2. 1252 */ 1253 if (data->power_mode != POWER_MODE_NORMAL) 1254 return -EINVAL; 1255 1256 /* 1257 * Tap interrupts are operating with a data rate of 200Hz. 1258 * See section 4.7 "Tap sensing interrupt" in datasheet v1.2. 1259 */ 1260 if (data->sample_freq.hz != 200 && state) { 1261 dev_err(data->dev, "Invalid data rate for tap interrupts.\n"); 1262 return -EINVAL; 1263 } 1264 1265 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, 1266 BMA400_S_TAP_MSK, 1267 FIELD_PREP(BMA400_S_TAP_MSK, state)); 1268 if (ret) 1269 return ret; 1270 1271 switch (dir) { 1272 case IIO_EV_DIR_SINGLETAP: 1273 mask = BMA400_S_TAP_MSK; 1274 set_mask_bits(&field_value, BMA400_S_TAP_MSK, 1275 FIELD_PREP(BMA400_S_TAP_MSK, state)); 1276 break; 1277 case IIO_EV_DIR_DOUBLETAP: 1278 mask = BMA400_D_TAP_MSK; 1279 set_mask_bits(&field_value, BMA400_D_TAP_MSK, 1280 FIELD_PREP(BMA400_D_TAP_MSK, state)); 1281 break; 1282 default: 1283 return -EINVAL; 1284 } 1285 1286 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, mask, 1287 field_value); 1288 if (ret) 1289 return ret; 1290 1291 set_mask_bits(&data->tap_event_en_bitmask, mask, field_value); 1292 1293 return 0; 1294 } 1295 1296 static int bma400_disable_adv_interrupt(struct bma400_data *data) 1297 { 1298 int ret; 1299 1300 ret = regmap_write(data->regmap, BMA400_INT_CONFIG0_REG, 0); 1301 if (ret) 1302 return ret; 1303 1304 ret = regmap_write(data->regmap, BMA400_INT_CONFIG1_REG, 0); 1305 if (ret) 1306 return ret; 1307 1308 data->tap_event_en_bitmask = 0; 1309 data->generic_event_en = 0; 1310 data->step_event_en = false; 1311 data->activity_event_en = false; 1312 1313 return 0; 1314 } 1315 1316 static int bma400_write_event_config(struct iio_dev *indio_dev, 1317 const struct iio_chan_spec *chan, 1318 enum iio_event_type type, 1319 enum iio_event_direction dir, int state) 1320 { 1321 struct bma400_data *data = iio_priv(indio_dev); 1322 int ret; 1323 1324 switch (chan->type) { 1325 case IIO_ACCEL: 1326 switch (type) { 1327 case IIO_EV_TYPE_MAG: 1328 mutex_lock(&data->mutex); 1329 ret = bma400_activity_event_en(data, dir, state); 1330 mutex_unlock(&data->mutex); 1331 return ret; 1332 case IIO_EV_TYPE_GESTURE: 1333 mutex_lock(&data->mutex); 1334 ret = bma400_tap_event_en(data, dir, state); 1335 mutex_unlock(&data->mutex); 1336 return ret; 1337 default: 1338 return -EINVAL; 1339 } 1340 case IIO_STEPS: 1341 mutex_lock(&data->mutex); 1342 ret = bma400_steps_event_enable(data, state); 1343 mutex_unlock(&data->mutex); 1344 return ret; 1345 case IIO_ACTIVITY: 1346 mutex_lock(&data->mutex); 1347 if (!data->step_event_en) { 1348 ret = bma400_steps_event_enable(data, true); 1349 if (ret) { 1350 mutex_unlock(&data->mutex); 1351 return ret; 1352 } 1353 } 1354 data->activity_event_en = state; 1355 mutex_unlock(&data->mutex); 1356 return 0; 1357 default: 1358 return -EINVAL; 1359 } 1360 } 1361 1362 static int get_gen_config_reg(enum iio_event_direction dir) 1363 { 1364 switch (dir) { 1365 case IIO_EV_DIR_FALLING: 1366 return BMA400_GEN2INT_CONFIG0; 1367 case IIO_EV_DIR_RISING: 1368 return BMA400_GEN1INT_CONFIG0; 1369 default: 1370 return -EINVAL; 1371 } 1372 } 1373 1374 static int bma400_read_event_value(struct iio_dev *indio_dev, 1375 const struct iio_chan_spec *chan, 1376 enum iio_event_type type, 1377 enum iio_event_direction dir, 1378 enum iio_event_info info, 1379 int *val, int *val2) 1380 { 1381 struct bma400_data *data = iio_priv(indio_dev); 1382 int ret, reg, reg_val, raw; 1383 1384 if (chan->type != IIO_ACCEL) 1385 return -EINVAL; 1386 1387 switch (type) { 1388 case IIO_EV_TYPE_MAG: 1389 reg = get_gen_config_reg(dir); 1390 if (reg < 0) 1391 return -EINVAL; 1392 1393 *val2 = 0; 1394 switch (info) { 1395 case IIO_EV_INFO_VALUE: 1396 ret = regmap_read(data->regmap, 1397 reg + BMA400_GEN_CONFIG2_OFF, 1398 val); 1399 if (ret) 1400 return ret; 1401 return IIO_VAL_INT; 1402 case IIO_EV_INFO_PERIOD: 1403 mutex_lock(&data->mutex); 1404 ret = regmap_bulk_read(data->regmap, 1405 reg + BMA400_GEN_CONFIG3_OFF, 1406 &data->duration, 1407 sizeof(data->duration)); 1408 if (ret) { 1409 mutex_unlock(&data->mutex); 1410 return ret; 1411 } 1412 *val = be16_to_cpu(data->duration); 1413 mutex_unlock(&data->mutex); 1414 return IIO_VAL_INT; 1415 case IIO_EV_INFO_HYSTERESIS: 1416 ret = regmap_read(data->regmap, reg, val); 1417 if (ret) 1418 return ret; 1419 *val = FIELD_GET(BMA400_GEN_HYST_MSK, *val); 1420 return IIO_VAL_INT; 1421 default: 1422 return -EINVAL; 1423 } 1424 case IIO_EV_TYPE_GESTURE: 1425 switch (info) { 1426 case IIO_EV_INFO_VALUE: 1427 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG, 1428 ®_val); 1429 if (ret) 1430 return ret; 1431 1432 *val = FIELD_GET(BMA400_TAP_SEN_MSK, reg_val); 1433 return IIO_VAL_INT; 1434 case IIO_EV_INFO_RESET_TIMEOUT: 1435 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, 1436 ®_val); 1437 if (ret) 1438 return ret; 1439 1440 raw = FIELD_GET(BMA400_TAP_QUIET_MSK, reg_val); 1441 *val = 0; 1442 *val2 = tap_reset_timeout[raw]; 1443 return IIO_VAL_INT_PLUS_MICRO; 1444 case IIO_EV_INFO_TAP2_MIN_DELAY: 1445 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, 1446 ®_val); 1447 if (ret) 1448 return ret; 1449 1450 raw = FIELD_GET(BMA400_TAP_QUIETDT_MSK, reg_val); 1451 *val = 0; 1452 *val2 = double_tap2_min_delay[raw]; 1453 return IIO_VAL_INT_PLUS_MICRO; 1454 default: 1455 return -EINVAL; 1456 } 1457 default: 1458 return -EINVAL; 1459 } 1460 } 1461 1462 static int bma400_write_event_value(struct iio_dev *indio_dev, 1463 const struct iio_chan_spec *chan, 1464 enum iio_event_type type, 1465 enum iio_event_direction dir, 1466 enum iio_event_info info, 1467 int val, int val2) 1468 { 1469 struct bma400_data *data = iio_priv(indio_dev); 1470 int reg, ret, raw; 1471 1472 if (chan->type != IIO_ACCEL) 1473 return -EINVAL; 1474 1475 switch (type) { 1476 case IIO_EV_TYPE_MAG: 1477 reg = get_gen_config_reg(dir); 1478 if (reg < 0) 1479 return -EINVAL; 1480 1481 switch (info) { 1482 case IIO_EV_INFO_VALUE: 1483 if (val < 1 || val > 255) 1484 return -EINVAL; 1485 1486 return regmap_write(data->regmap, 1487 reg + BMA400_GEN_CONFIG2_OFF, 1488 val); 1489 case IIO_EV_INFO_PERIOD: 1490 if (val < 1 || val > 65535) 1491 return -EINVAL; 1492 1493 mutex_lock(&data->mutex); 1494 put_unaligned_be16(val, &data->duration); 1495 ret = regmap_bulk_write(data->regmap, 1496 reg + BMA400_GEN_CONFIG3_OFF, 1497 &data->duration, 1498 sizeof(data->duration)); 1499 mutex_unlock(&data->mutex); 1500 return ret; 1501 case IIO_EV_INFO_HYSTERESIS: 1502 if (val < 0 || val > 3) 1503 return -EINVAL; 1504 1505 return regmap_update_bits(data->regmap, reg, 1506 BMA400_GEN_HYST_MSK, 1507 FIELD_PREP(BMA400_GEN_HYST_MSK, 1508 val)); 1509 default: 1510 return -EINVAL; 1511 } 1512 case IIO_EV_TYPE_GESTURE: 1513 switch (info) { 1514 case IIO_EV_INFO_VALUE: 1515 if (val < 0 || val > 7) 1516 return -EINVAL; 1517 1518 return regmap_update_bits(data->regmap, 1519 BMA400_TAP_CONFIG, 1520 BMA400_TAP_SEN_MSK, 1521 FIELD_PREP(BMA400_TAP_SEN_MSK, 1522 val)); 1523 case IIO_EV_INFO_RESET_TIMEOUT: 1524 raw = usec_to_tapreg_raw(val2, tap_reset_timeout); 1525 if (raw < 0) 1526 return -EINVAL; 1527 1528 return regmap_update_bits(data->regmap, 1529 BMA400_TAP_CONFIG1, 1530 BMA400_TAP_QUIET_MSK, 1531 FIELD_PREP(BMA400_TAP_QUIET_MSK, 1532 raw)); 1533 case IIO_EV_INFO_TAP2_MIN_DELAY: 1534 raw = usec_to_tapreg_raw(val2, double_tap2_min_delay); 1535 if (raw < 0) 1536 return -EINVAL; 1537 1538 return regmap_update_bits(data->regmap, 1539 BMA400_TAP_CONFIG1, 1540 BMA400_TAP_QUIETDT_MSK, 1541 FIELD_PREP(BMA400_TAP_QUIETDT_MSK, 1542 raw)); 1543 default: 1544 return -EINVAL; 1545 } 1546 default: 1547 return -EINVAL; 1548 } 1549 } 1550 1551 static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig, 1552 bool state) 1553 { 1554 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1555 struct bma400_data *data = iio_priv(indio_dev); 1556 int ret; 1557 1558 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, 1559 BMA400_INT_DRDY_MSK, 1560 FIELD_PREP(BMA400_INT_DRDY_MSK, state)); 1561 if (ret) 1562 return ret; 1563 1564 return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, 1565 BMA400_INT_DRDY_MSK, 1566 FIELD_PREP(BMA400_INT_DRDY_MSK, state)); 1567 } 1568 1569 static const unsigned long bma400_avail_scan_masks[] = { 1570 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z), 1571 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z) 1572 | BIT(BMA400_TEMP), 1573 0 1574 }; 1575 1576 static const struct iio_info bma400_info = { 1577 .read_raw = bma400_read_raw, 1578 .read_avail = bma400_read_avail, 1579 .write_raw = bma400_write_raw, 1580 .write_raw_get_fmt = bma400_write_raw_get_fmt, 1581 .read_event_config = bma400_read_event_config, 1582 .write_event_config = bma400_write_event_config, 1583 .write_event_value = bma400_write_event_value, 1584 .read_event_value = bma400_read_event_value, 1585 .event_attrs = &bma400_event_attribute_group, 1586 }; 1587 1588 static const struct iio_trigger_ops bma400_trigger_ops = { 1589 .set_trigger_state = &bma400_data_rdy_trigger_set_state, 1590 .validate_device = &iio_trigger_validate_own_device, 1591 }; 1592 1593 static irqreturn_t bma400_trigger_handler(int irq, void *p) 1594 { 1595 struct iio_poll_func *pf = p; 1596 struct iio_dev *indio_dev = pf->indio_dev; 1597 struct bma400_data *data = iio_priv(indio_dev); 1598 int ret, temp; 1599 1600 /* Lock to protect the data->buffer */ 1601 mutex_lock(&data->mutex); 1602 1603 /* bulk read six registers, with the base being the LSB register */ 1604 ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG, 1605 &data->buffer.buff, sizeof(data->buffer.buff)); 1606 if (ret) 1607 goto unlock_err; 1608 1609 if (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) { 1610 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp); 1611 if (ret) 1612 goto unlock_err; 1613 1614 data->buffer.temperature = temp; 1615 } 1616 1617 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer, 1618 iio_get_time_ns(indio_dev)); 1619 1620 mutex_unlock(&data->mutex); 1621 iio_trigger_notify_done(indio_dev->trig); 1622 return IRQ_HANDLED; 1623 1624 unlock_err: 1625 mutex_unlock(&data->mutex); 1626 return IRQ_NONE; 1627 } 1628 1629 static irqreturn_t bma400_interrupt(int irq, void *private) 1630 { 1631 struct iio_dev *indio_dev = private; 1632 struct bma400_data *data = iio_priv(indio_dev); 1633 s64 timestamp = iio_get_time_ns(indio_dev); 1634 unsigned int act, ev_dir = IIO_EV_DIR_NONE; 1635 int ret; 1636 1637 /* Lock to protect the data->status */ 1638 mutex_lock(&data->mutex); 1639 ret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG, 1640 &data->status, 1641 sizeof(data->status)); 1642 /* 1643 * if none of the bit is set in the status register then it is 1644 * spurious interrupt. 1645 */ 1646 if (ret || !data->status) 1647 goto unlock_err; 1648 1649 /* 1650 * Disable all advance interrupts if interrupt engine overrun occurs. 1651 * See section 4.7 "Interrupt engine overrun" in datasheet v1.2. 1652 */ 1653 if (FIELD_GET(BMA400_INT_ENG_OVRUN_MSK, le16_to_cpu(data->status))) { 1654 bma400_disable_adv_interrupt(data); 1655 dev_err(data->dev, "Interrupt engine overrun\n"); 1656 goto unlock_err; 1657 } 1658 1659 if (FIELD_GET(BMA400_INT_S_TAP_MSK, le16_to_cpu(data->status))) 1660 iio_push_event(indio_dev, 1661 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1662 IIO_MOD_X_OR_Y_OR_Z, 1663 IIO_EV_TYPE_GESTURE, 1664 IIO_EV_DIR_SINGLETAP), 1665 timestamp); 1666 1667 if (FIELD_GET(BMA400_INT_D_TAP_MSK, le16_to_cpu(data->status))) 1668 iio_push_event(indio_dev, 1669 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1670 IIO_MOD_X_OR_Y_OR_Z, 1671 IIO_EV_TYPE_GESTURE, 1672 IIO_EV_DIR_DOUBLETAP), 1673 timestamp); 1674 1675 if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status))) 1676 ev_dir = IIO_EV_DIR_RISING; 1677 1678 if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status))) 1679 ev_dir = IIO_EV_DIR_FALLING; 1680 1681 if (ev_dir != IIO_EV_DIR_NONE) { 1682 iio_push_event(indio_dev, 1683 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1684 IIO_MOD_X_OR_Y_OR_Z, 1685 IIO_EV_TYPE_MAG, ev_dir), 1686 timestamp); 1687 } 1688 1689 if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) { 1690 iio_push_event(indio_dev, 1691 IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD, 1692 IIO_EV_TYPE_CHANGE, 1693 IIO_EV_DIR_NONE), 1694 timestamp); 1695 1696 if (data->activity_event_en) { 1697 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG, 1698 &act); 1699 if (ret) 1700 goto unlock_err; 1701 1702 iio_push_event(indio_dev, 1703 IIO_MOD_EVENT_CODE(IIO_ACTIVITY, 0, 1704 bma400_act_to_mod(act), 1705 IIO_EV_TYPE_CHANGE, 1706 IIO_EV_DIR_NONE), 1707 timestamp); 1708 } 1709 } 1710 1711 if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) { 1712 mutex_unlock(&data->mutex); 1713 iio_trigger_poll_chained(data->trig); 1714 return IRQ_HANDLED; 1715 } 1716 1717 mutex_unlock(&data->mutex); 1718 return IRQ_HANDLED; 1719 1720 unlock_err: 1721 mutex_unlock(&data->mutex); 1722 return IRQ_NONE; 1723 } 1724 1725 int bma400_probe(struct device *dev, struct regmap *regmap, int irq, 1726 const char *name) 1727 { 1728 struct iio_dev *indio_dev; 1729 struct bma400_data *data; 1730 int ret; 1731 1732 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1733 if (!indio_dev) 1734 return -ENOMEM; 1735 1736 data = iio_priv(indio_dev); 1737 data->regmap = regmap; 1738 data->dev = dev; 1739 1740 ret = bma400_init(data); 1741 if (ret) 1742 return ret; 1743 1744 ret = iio_read_mount_matrix(dev, &data->orientation); 1745 if (ret) 1746 return ret; 1747 1748 mutex_init(&data->mutex); 1749 indio_dev->name = name; 1750 indio_dev->info = &bma400_info; 1751 indio_dev->channels = bma400_channels; 1752 indio_dev->num_channels = ARRAY_SIZE(bma400_channels); 1753 indio_dev->available_scan_masks = bma400_avail_scan_masks; 1754 indio_dev->modes = INDIO_DIRECT_MODE; 1755 1756 if (irq > 0) { 1757 data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 1758 indio_dev->name, 1759 iio_device_id(indio_dev)); 1760 if (!data->trig) 1761 return -ENOMEM; 1762 1763 data->trig->ops = &bma400_trigger_ops; 1764 iio_trigger_set_drvdata(data->trig, indio_dev); 1765 1766 ret = devm_iio_trigger_register(data->dev, data->trig); 1767 if (ret) 1768 return dev_err_probe(data->dev, ret, 1769 "iio trigger register fail\n"); 1770 1771 indio_dev->trig = iio_trigger_get(data->trig); 1772 ret = devm_request_threaded_irq(dev, irq, NULL, 1773 &bma400_interrupt, 1774 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1775 indio_dev->name, indio_dev); 1776 if (ret) 1777 return dev_err_probe(data->dev, ret, 1778 "request irq %d failed\n", irq); 1779 } 1780 1781 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 1782 &bma400_trigger_handler, NULL); 1783 if (ret) 1784 return dev_err_probe(data->dev, ret, 1785 "iio triggered buffer setup failed\n"); 1786 1787 return devm_iio_device_register(dev, indio_dev); 1788 } 1789 EXPORT_SYMBOL_NS(bma400_probe, IIO_BMA400); 1790 1791 MODULE_AUTHOR("Dan Robertson <dan@dlrobertson.com>"); 1792 MODULE_AUTHOR("Jagath Jog J <jagathjog1996@gmail.com>"); 1793 MODULE_DESCRIPTION("Bosch BMA400 triaxial acceleration sensor core"); 1794 MODULE_LICENSE("GPL"); 1795