1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2021 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/iio/buffer.h> 10 #include <linux/iio/events.h> 11 #include <linux/iio/iio.h> 12 #include <linux/iio/kfifo_buf.h> 13 #include <linux/iio/sysfs.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <asm/unaligned.h> 20 21 #include "adxl367.h" 22 23 #define ADXL367_REG_DEVID 0x00 24 #define ADXL367_DEVID_AD 0xAD 25 26 #define ADXL367_REG_STATUS 0x0B 27 #define ADXL367_STATUS_INACT_MASK BIT(5) 28 #define ADXL367_STATUS_ACT_MASK BIT(4) 29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2) 30 31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0) 32 33 #define ADXL367_REG_X_DATA_H 0x0E 34 #define ADXL367_REG_Y_DATA_H 0x10 35 #define ADXL367_REG_Z_DATA_H 0x12 36 #define ADXL367_REG_TEMP_DATA_H 0x14 37 #define ADXL367_REG_EX_ADC_DATA_H 0x16 38 #define ADXL367_DATA_MASK GENMASK(15, 2) 39 40 #define ADXL367_TEMP_25C 165 41 #define ADXL367_TEMP_PER_C 54 42 43 #define ADXL367_VOLTAGE_OFFSET 8192 44 #define ADXL367_VOLTAGE_MAX_MV 1000 45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0) 46 47 #define ADXL367_REG_RESET 0x1F 48 #define ADXL367_RESET_CODE 0x52 49 50 #define ADXL367_REG_THRESH_ACT_H 0x20 51 #define ADXL367_REG_THRESH_INACT_H 0x23 52 #define ADXL367_THRESH_MAX GENMASK(12, 0) 53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6) 54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0) 55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0) 56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2) 57 58 #define ADXL367_REG_TIME_ACT 0x22 59 #define ADXL367_REG_TIME_INACT_H 0x25 60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0) 61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0) 62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8) 63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0) 64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0) 65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0) 66 67 #define ADXL367_REG_ACT_INACT_CTL 0x27 68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0) 69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4) 70 71 #define ADXL367_REG_FIFO_CTL 0x28 72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3) 73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0) 74 75 #define ADXL367_REG_FIFO_SAMPLES 0x29 76 #define ADXL367_FIFO_SIZE 512 77 #define ADXL367_FIFO_MAX_WATERMARK 511 78 79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8) 80 #define ADXL367_SAMPLES_H_MASK BIT(2) 81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0) 82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0) 83 84 #define ADXL367_REG_INT1_MAP 0x2A 85 #define ADXL367_INT_INACT_MASK BIT(5) 86 #define ADXL367_INT_ACT_MASK BIT(4) 87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2) 88 89 #define ADXL367_REG_FILTER_CTL 0x2C 90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6) 91 #define ADXL367_2G_RANGE_1G 4095 92 #define ADXL367_2G_RANGE_100MG 409 93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0) 94 95 #define ADXL367_REG_POWER_CTL 0x2D 96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0) 97 98 #define ADXL367_REG_ADC_CTL 0x3C 99 #define ADXL367_REG_TEMP_CTL 0x3D 100 #define ADXL367_ADC_EN_MASK BIT(0) 101 102 enum adxl367_range { 103 ADXL367_2G_RANGE, 104 ADXL367_4G_RANGE, 105 ADXL367_8G_RANGE, 106 }; 107 108 enum adxl367_fifo_mode { 109 ADXL367_FIFO_MODE_DISABLED = 0b00, 110 ADXL367_FIFO_MODE_STREAM = 0b10, 111 }; 112 113 enum adxl367_fifo_format { 114 ADXL367_FIFO_FORMAT_XYZ, 115 ADXL367_FIFO_FORMAT_X, 116 ADXL367_FIFO_FORMAT_Y, 117 ADXL367_FIFO_FORMAT_Z, 118 ADXL367_FIFO_FORMAT_XYZT, 119 ADXL367_FIFO_FORMAT_XT, 120 ADXL367_FIFO_FORMAT_YT, 121 ADXL367_FIFO_FORMAT_ZT, 122 ADXL367_FIFO_FORMAT_XYZA, 123 ADXL367_FIFO_FORMAT_XA, 124 ADXL367_FIFO_FORMAT_YA, 125 ADXL367_FIFO_FORMAT_ZA, 126 }; 127 128 enum adxl367_op_mode { 129 ADXL367_OP_STANDBY = 0b00, 130 ADXL367_OP_MEASURE = 0b10, 131 }; 132 133 enum adxl367_act_proc_mode { 134 ADXL367_LOOPED = 0b11, 135 }; 136 137 enum adxl367_act_en_mode { 138 ADXL367_ACT_DISABLED = 0b00, 139 ADCL367_ACT_REF_ENABLED = 0b11, 140 }; 141 142 enum adxl367_activity_type { 143 ADXL367_ACTIVITY, 144 ADXL367_INACTIVITY, 145 }; 146 147 enum adxl367_odr { 148 ADXL367_ODR_12P5HZ, 149 ADXL367_ODR_25HZ, 150 ADXL367_ODR_50HZ, 151 ADXL367_ODR_100HZ, 152 ADXL367_ODR_200HZ, 153 ADXL367_ODR_400HZ, 154 }; 155 156 struct adxl367_state { 157 const struct adxl367_ops *ops; 158 void *context; 159 160 struct device *dev; 161 struct regmap *regmap; 162 163 struct regulator_bulk_data regulators[2]; 164 165 /* 166 * Synchronize access to members of driver state, and ensure atomicity 167 * of consecutive regmap operations. 168 */ 169 struct mutex lock; 170 171 enum adxl367_odr odr; 172 enum adxl367_range range; 173 174 unsigned int act_threshold; 175 unsigned int act_time_ms; 176 unsigned int inact_threshold; 177 unsigned int inact_time_ms; 178 179 unsigned int fifo_set_size; 180 unsigned int fifo_watermark; 181 182 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); 183 __be16 sample_buf; 184 u8 act_threshold_buf[2]; 185 u8 inact_time_buf[2]; 186 u8 status_buf[3]; 187 }; 188 189 static const unsigned int adxl367_threshold_h_reg_tbl[] = { 190 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H, 191 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H, 192 }; 193 194 static const unsigned int adxl367_act_en_shift_tbl[] = { 195 [ADXL367_ACTIVITY] = 0, 196 [ADXL367_INACTIVITY] = 2, 197 }; 198 199 static const unsigned int adxl367_act_int_mask_tbl[] = { 200 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK, 201 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK, 202 }; 203 204 static const int adxl367_samp_freq_tbl[][2] = { 205 [ADXL367_ODR_12P5HZ] = {12, 500000}, 206 [ADXL367_ODR_25HZ] = {25, 0}, 207 [ADXL367_ODR_50HZ] = {50, 0}, 208 [ADXL367_ODR_100HZ] = {100, 0}, 209 [ADXL367_ODR_200HZ] = {200, 0}, 210 [ADXL367_ODR_400HZ] = {400, 0}, 211 }; 212 213 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */ 214 static const int adxl367_range_scale_tbl[][2] = { 215 [ADXL367_2G_RANGE] = {0, 2394347}, 216 [ADXL367_4G_RANGE] = {0, 4788695}, 217 [ADXL367_8G_RANGE] = {0, 9577391}, 218 }; 219 220 static const int adxl367_range_scale_factor_tbl[] = { 221 [ADXL367_2G_RANGE] = 1, 222 [ADXL367_4G_RANGE] = 2, 223 [ADXL367_8G_RANGE] = 4, 224 }; 225 226 enum { 227 ADXL367_X_CHANNEL_INDEX, 228 ADXL367_Y_CHANNEL_INDEX, 229 ADXL367_Z_CHANNEL_INDEX, 230 ADXL367_TEMP_CHANNEL_INDEX, 231 ADXL367_EX_ADC_CHANNEL_INDEX 232 }; 233 234 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX) 235 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX) 236 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX) 237 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX) 238 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX) 239 240 static const enum adxl367_fifo_format adxl367_fifo_formats[] = { 241 ADXL367_FIFO_FORMAT_X, 242 ADXL367_FIFO_FORMAT_Y, 243 ADXL367_FIFO_FORMAT_Z, 244 ADXL367_FIFO_FORMAT_XT, 245 ADXL367_FIFO_FORMAT_YT, 246 ADXL367_FIFO_FORMAT_ZT, 247 ADXL367_FIFO_FORMAT_XA, 248 ADXL367_FIFO_FORMAT_YA, 249 ADXL367_FIFO_FORMAT_ZA, 250 ADXL367_FIFO_FORMAT_XYZ, 251 ADXL367_FIFO_FORMAT_XYZT, 252 ADXL367_FIFO_FORMAT_XYZA, 253 }; 254 255 static const unsigned long adxl367_channel_masks[] = { 256 ADXL367_X_CHANNEL_MASK, 257 ADXL367_Y_CHANNEL_MASK, 258 ADXL367_Z_CHANNEL_MASK, 259 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 260 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 261 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 262 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 263 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 264 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 265 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK, 266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK | 267 ADXL367_TEMP_CHANNEL_MASK, 268 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK | 269 ADXL367_EX_ADC_CHANNEL_MASK, 270 0, 271 }; 272 273 static int adxl367_set_measure_en(struct adxl367_state *st, bool en) 274 { 275 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE 276 : ADXL367_OP_STANDBY; 277 int ret; 278 279 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL, 280 ADXL367_POWER_CTL_MODE_MASK, 281 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK, 282 op_mode)); 283 if (ret) 284 return ret; 285 286 /* 287 * Wait for acceleration output to settle after entering 288 * measure mode. 289 */ 290 if (en) 291 msleep(100); 292 293 return 0; 294 } 295 296 static void adxl367_scale_act_thresholds(struct adxl367_state *st, 297 enum adxl367_range old_range, 298 enum adxl367_range new_range) 299 { 300 st->act_threshold = st->act_threshold 301 * adxl367_range_scale_factor_tbl[old_range] 302 / adxl367_range_scale_factor_tbl[new_range]; 303 st->inact_threshold = st->inact_threshold 304 * adxl367_range_scale_factor_tbl[old_range] 305 / adxl367_range_scale_factor_tbl[new_range]; 306 } 307 308 static int _adxl367_set_act_threshold(struct adxl367_state *st, 309 enum adxl367_activity_type act, 310 unsigned int threshold) 311 { 312 u8 reg = adxl367_threshold_h_reg_tbl[act]; 313 int ret; 314 315 if (threshold > ADXL367_THRESH_MAX) 316 return -EINVAL; 317 318 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK, 319 FIELD_GET(ADXL367_THRESH_VAL_H_MASK, 320 threshold)); 321 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK, 322 FIELD_GET(ADXL367_THRESH_VAL_L_MASK, 323 threshold)); 324 325 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf, 326 sizeof(st->act_threshold_buf)); 327 if (ret) 328 return ret; 329 330 if (act == ADXL367_ACTIVITY) 331 st->act_threshold = threshold; 332 else 333 st->inact_threshold = threshold; 334 335 return 0; 336 } 337 338 static int adxl367_set_act_threshold(struct adxl367_state *st, 339 enum adxl367_activity_type act, 340 unsigned int threshold) 341 { 342 int ret; 343 344 mutex_lock(&st->lock); 345 346 ret = adxl367_set_measure_en(st, false); 347 if (ret) 348 goto out; 349 350 ret = _adxl367_set_act_threshold(st, act, threshold); 351 if (ret) 352 goto out; 353 354 ret = adxl367_set_measure_en(st, true); 355 356 out: 357 mutex_unlock(&st->lock); 358 359 return ret; 360 } 361 362 static int adxl367_set_act_proc_mode(struct adxl367_state *st, 363 enum adxl367_act_proc_mode mode) 364 { 365 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL, 366 ADXL367_ACT_LINKLOOP_MASK, 367 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK, 368 mode)); 369 } 370 371 static int adxl367_set_act_interrupt_en(struct adxl367_state *st, 372 enum adxl367_activity_type act, 373 bool en) 374 { 375 unsigned int mask = adxl367_act_int_mask_tbl[act]; 376 377 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, 378 mask, en ? mask : 0); 379 } 380 381 static int adxl367_get_act_interrupt_en(struct adxl367_state *st, 382 enum adxl367_activity_type act, 383 bool *en) 384 { 385 unsigned int mask = adxl367_act_int_mask_tbl[act]; 386 unsigned int val; 387 int ret; 388 389 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val); 390 if (ret) 391 return ret; 392 393 *en = !!(val & mask); 394 395 return 0; 396 } 397 398 static int adxl367_set_act_en(struct adxl367_state *st, 399 enum adxl367_activity_type act, 400 enum adxl367_act_en_mode en) 401 { 402 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act]; 403 404 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL, 405 ADXL367_ACT_EN_MASK << ctl_shift, 406 en << ctl_shift); 407 } 408 409 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st, 410 bool en) 411 { 412 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, 413 ADXL367_INT_FIFO_WATERMARK_MASK, 414 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0); 415 } 416 417 static int adxl367_get_fifo_mode(struct adxl367_state *st, 418 enum adxl367_fifo_mode *fifo_mode) 419 { 420 unsigned int val; 421 int ret; 422 423 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val); 424 if (ret) 425 return ret; 426 427 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val); 428 429 return 0; 430 } 431 432 static int adxl367_set_fifo_mode(struct adxl367_state *st, 433 enum adxl367_fifo_mode fifo_mode) 434 { 435 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 436 ADXL367_FIFO_CTL_MODE_MASK, 437 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK, 438 fifo_mode)); 439 } 440 441 static int adxl367_set_fifo_format(struct adxl367_state *st, 442 enum adxl367_fifo_format fifo_format) 443 { 444 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 445 ADXL367_FIFO_CTL_FORMAT_MASK, 446 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK, 447 fifo_format)); 448 } 449 450 static int adxl367_set_fifo_watermark(struct adxl367_state *st, 451 unsigned int fifo_watermark) 452 { 453 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size; 454 unsigned int fifo_samples_h, fifo_samples_l; 455 int ret; 456 457 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK) 458 fifo_samples = ADXL367_FIFO_MAX_WATERMARK; 459 460 fifo_samples /= st->fifo_set_size; 461 462 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK, 463 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK, 464 fifo_samples)); 465 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK, 466 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK, 467 fifo_samples)); 468 469 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 470 ADXL367_SAMPLES_H_MASK, fifo_samples_h); 471 if (ret) 472 return ret; 473 474 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES, 475 ADXL367_SAMPLES_L_MASK, fifo_samples_l); 476 if (ret) 477 return ret; 478 479 st->fifo_watermark = fifo_watermark; 480 481 return 0; 482 } 483 484 static int adxl367_set_range(struct iio_dev *indio_dev, 485 enum adxl367_range range) 486 { 487 struct adxl367_state *st = iio_priv(indio_dev); 488 int ret; 489 490 ret = iio_device_claim_direct_mode(indio_dev); 491 if (ret) 492 return ret; 493 494 mutex_lock(&st->lock); 495 496 ret = adxl367_set_measure_en(st, false); 497 if (ret) 498 goto out; 499 500 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL, 501 ADXL367_FILTER_CTL_RANGE_MASK, 502 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK, 503 range)); 504 if (ret) 505 goto out; 506 507 adxl367_scale_act_thresholds(st, st->range, range); 508 509 /* Activity thresholds depend on range */ 510 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY, 511 st->act_threshold); 512 if (ret) 513 goto out; 514 515 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY, 516 st->inact_threshold); 517 if (ret) 518 goto out; 519 520 ret = adxl367_set_measure_en(st, true); 521 if (ret) 522 goto out; 523 524 st->range = range; 525 526 out: 527 mutex_unlock(&st->lock); 528 529 iio_device_release_direct_mode(indio_dev); 530 531 return ret; 532 } 533 534 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms) 535 { 536 int freq_hz = adxl367_samp_freq_tbl[st->odr][0]; 537 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1]; 538 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */ 539 int freq_dhz = freq_hz * 10 + freq_microhz / 100000; 540 541 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000); 542 } 543 544 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms) 545 { 546 unsigned int val = adxl367_time_ms_to_samples(st, ms); 547 int ret; 548 549 if (val > ADXL367_TIME_ACT_MAX) 550 val = ADXL367_TIME_ACT_MAX; 551 552 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val); 553 if (ret) 554 return ret; 555 556 st->act_time_ms = ms; 557 558 return 0; 559 } 560 561 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms) 562 { 563 unsigned int val = adxl367_time_ms_to_samples(st, ms); 564 int ret; 565 566 if (val > ADXL367_TIME_INACT_MAX) 567 val = ADXL367_TIME_INACT_MAX; 568 569 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK, 570 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK, 571 val)); 572 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK, 573 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK, 574 val)); 575 576 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H, 577 st->inact_time_buf, sizeof(st->inact_time_buf)); 578 if (ret) 579 return ret; 580 581 st->inact_time_ms = ms; 582 583 return 0; 584 } 585 586 static int adxl367_set_act_time_ms(struct adxl367_state *st, 587 enum adxl367_activity_type act, 588 unsigned int ms) 589 { 590 int ret; 591 592 mutex_lock(&st->lock); 593 594 ret = adxl367_set_measure_en(st, false); 595 if (ret) 596 goto out; 597 598 if (act == ADXL367_ACTIVITY) 599 ret = _adxl367_set_act_time_ms(st, ms); 600 else 601 ret = _adxl367_set_inact_time_ms(st, ms); 602 603 if (ret) 604 goto out; 605 606 ret = adxl367_set_measure_en(st, true); 607 608 out: 609 mutex_unlock(&st->lock); 610 611 return ret; 612 } 613 614 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr) 615 { 616 int ret; 617 618 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL, 619 ADXL367_FILTER_CTL_ODR_MASK, 620 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK, 621 odr)); 622 if (ret) 623 return ret; 624 625 /* Activity timers depend on ODR */ 626 ret = _adxl367_set_act_time_ms(st, st->act_time_ms); 627 if (ret) 628 return ret; 629 630 ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms); 631 if (ret) 632 return ret; 633 634 st->odr = odr; 635 636 return 0; 637 } 638 639 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr) 640 { 641 struct adxl367_state *st = iio_priv(indio_dev); 642 int ret; 643 644 ret = iio_device_claim_direct_mode(indio_dev); 645 if (ret) 646 return ret; 647 648 mutex_lock(&st->lock); 649 650 ret = adxl367_set_measure_en(st, false); 651 if (ret) 652 goto out; 653 654 ret = _adxl367_set_odr(st, odr); 655 if (ret) 656 goto out; 657 658 ret = adxl367_set_measure_en(st, true); 659 660 out: 661 mutex_unlock(&st->lock); 662 663 iio_device_release_direct_mode(indio_dev); 664 665 return ret; 666 } 667 668 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg, 669 bool en) 670 { 671 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK, 672 en ? ADXL367_ADC_EN_MASK : 0); 673 } 674 675 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st, 676 unsigned int reg, bool en) 677 { 678 int ret; 679 680 switch (reg) { 681 case ADXL367_REG_TEMP_DATA_H: 682 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en); 683 break; 684 case ADXL367_REG_EX_ADC_DATA_H: 685 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en); 686 break; 687 default: 688 return 0; 689 } 690 691 if (ret) 692 return ret; 693 694 if (en) 695 msleep(100); 696 697 return 0; 698 } 699 700 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st, 701 const unsigned long *active_scan_mask, 702 bool en) 703 { 704 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK) 705 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en); 706 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK) 707 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en); 708 709 return 0; 710 } 711 712 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2, 713 enum adxl367_odr *odr) 714 { 715 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl); 716 int i; 717 718 for (i = 0; i < size; i++) 719 if (val == adxl367_samp_freq_tbl[i][0] && 720 val2 == adxl367_samp_freq_tbl[i][1]) 721 break; 722 723 if (i == size) 724 return -EINVAL; 725 726 *odr = i; 727 728 return 0; 729 } 730 731 static int adxl367_find_range(struct adxl367_state *st, int val, int val2, 732 enum adxl367_range *range) 733 { 734 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl); 735 int i; 736 737 for (i = 0; i < size; i++) 738 if (val == adxl367_range_scale_tbl[i][0] && 739 val2 == adxl367_range_scale_tbl[i][1]) 740 break; 741 742 if (i == size) 743 return -EINVAL; 744 745 *range = i; 746 747 return 0; 748 } 749 750 static int adxl367_read_sample(struct iio_dev *indio_dev, 751 struct iio_chan_spec const *chan, 752 int *val) 753 { 754 struct adxl367_state *st = iio_priv(indio_dev); 755 u16 sample; 756 int ret; 757 758 ret = iio_device_claim_direct_mode(indio_dev); 759 if (ret) 760 return ret; 761 762 mutex_lock(&st->lock); 763 764 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true); 765 if (ret) 766 goto out; 767 768 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf, 769 sizeof(st->sample_buf)); 770 if (ret) 771 goto out; 772 773 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf)); 774 *val = sign_extend32(sample, chan->scan_type.realbits - 1); 775 776 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false); 777 778 out: 779 mutex_unlock(&st->lock); 780 781 iio_device_release_direct_mode(indio_dev); 782 783 return ret ?: IIO_VAL_INT; 784 } 785 786 static int adxl367_get_status(struct adxl367_state *st, u8 *status, 787 u16 *fifo_entries) 788 { 789 int ret; 790 791 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */ 792 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS, 793 st->status_buf, sizeof(st->status_buf)); 794 if (ret) 795 return ret; 796 797 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK; 798 799 *status = st->status_buf[0]; 800 *fifo_entries = get_unaligned_le16(&st->status_buf[1]); 801 802 return 0; 803 } 804 805 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status) 806 { 807 unsigned int ev_dir; 808 809 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status)) 810 ev_dir = IIO_EV_DIR_RISING; 811 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status)) 812 ev_dir = IIO_EV_DIR_FALLING; 813 else 814 return false; 815 816 iio_push_event(indio_dev, 817 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, 818 IIO_EV_TYPE_THRESH, ev_dir), 819 iio_get_time_ns(indio_dev)); 820 821 return true; 822 } 823 824 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status, 825 u16 fifo_entries) 826 { 827 struct adxl367_state *st = iio_priv(indio_dev); 828 int ret; 829 int i; 830 831 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status)) 832 return false; 833 834 fifo_entries -= fifo_entries % st->fifo_set_size; 835 836 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries); 837 if (ret) { 838 dev_err(st->dev, "Failed to read FIFO: %d\n", ret); 839 return true; 840 } 841 842 for (i = 0; i < fifo_entries; i += st->fifo_set_size) 843 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); 844 845 return true; 846 } 847 848 static irqreturn_t adxl367_irq_handler(int irq, void *private) 849 { 850 struct iio_dev *indio_dev = private; 851 struct adxl367_state *st = iio_priv(indio_dev); 852 u16 fifo_entries; 853 bool handled; 854 u8 status; 855 int ret; 856 857 ret = adxl367_get_status(st, &status, &fifo_entries); 858 if (ret) 859 return IRQ_NONE; 860 861 handled = adxl367_push_event(indio_dev, status); 862 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries); 863 864 return handled ? IRQ_HANDLED : IRQ_NONE; 865 } 866 867 static int adxl367_reg_access(struct iio_dev *indio_dev, 868 unsigned int reg, 869 unsigned int writeval, 870 unsigned int *readval) 871 { 872 struct adxl367_state *st = iio_priv(indio_dev); 873 874 if (readval) 875 return regmap_read(st->regmap, reg, readval); 876 else 877 return regmap_write(st->regmap, reg, writeval); 878 } 879 880 static int adxl367_read_raw(struct iio_dev *indio_dev, 881 struct iio_chan_spec const *chan, 882 int *val, int *val2, long info) 883 { 884 struct adxl367_state *st = iio_priv(indio_dev); 885 886 switch (info) { 887 case IIO_CHAN_INFO_RAW: 888 return adxl367_read_sample(indio_dev, chan, val); 889 case IIO_CHAN_INFO_SCALE: 890 switch (chan->type) { 891 case IIO_ACCEL: 892 mutex_lock(&st->lock); 893 *val = adxl367_range_scale_tbl[st->range][0]; 894 *val2 = adxl367_range_scale_tbl[st->range][1]; 895 mutex_unlock(&st->lock); 896 return IIO_VAL_INT_PLUS_NANO; 897 case IIO_TEMP: 898 *val = 1000; 899 *val2 = ADXL367_TEMP_PER_C; 900 return IIO_VAL_FRACTIONAL; 901 case IIO_VOLTAGE: 902 *val = ADXL367_VOLTAGE_MAX_MV; 903 *val2 = ADXL367_VOLTAGE_MAX_RAW; 904 return IIO_VAL_FRACTIONAL; 905 default: 906 return -EINVAL; 907 } 908 case IIO_CHAN_INFO_OFFSET: 909 switch (chan->type) { 910 case IIO_TEMP: 911 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C; 912 return IIO_VAL_INT; 913 case IIO_VOLTAGE: 914 *val = ADXL367_VOLTAGE_OFFSET; 915 return IIO_VAL_INT; 916 default: 917 return -EINVAL; 918 } 919 case IIO_CHAN_INFO_SAMP_FREQ: 920 mutex_lock(&st->lock); 921 *val = adxl367_samp_freq_tbl[st->odr][0]; 922 *val2 = adxl367_samp_freq_tbl[st->odr][1]; 923 mutex_unlock(&st->lock); 924 return IIO_VAL_INT_PLUS_MICRO; 925 default: 926 return -EINVAL; 927 } 928 } 929 930 static int adxl367_write_raw(struct iio_dev *indio_dev, 931 struct iio_chan_spec const *chan, 932 int val, int val2, long info) 933 { 934 struct adxl367_state *st = iio_priv(indio_dev); 935 int ret; 936 937 switch (info) { 938 case IIO_CHAN_INFO_SAMP_FREQ: { 939 enum adxl367_odr odr; 940 941 ret = adxl367_find_odr(st, val, val2, &odr); 942 if (ret) 943 return ret; 944 945 return adxl367_set_odr(indio_dev, odr); 946 } 947 case IIO_CHAN_INFO_SCALE: { 948 enum adxl367_range range; 949 950 ret = adxl367_find_range(st, val, val2, &range); 951 if (ret) 952 return ret; 953 954 return adxl367_set_range(indio_dev, range); 955 } 956 default: 957 return -EINVAL; 958 } 959 } 960 961 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev, 962 struct iio_chan_spec const *chan, 963 long info) 964 { 965 switch (info) { 966 case IIO_CHAN_INFO_SCALE: 967 if (chan->type != IIO_ACCEL) 968 return -EINVAL; 969 970 return IIO_VAL_INT_PLUS_NANO; 971 default: 972 return IIO_VAL_INT_PLUS_MICRO; 973 } 974 } 975 976 static int adxl367_read_avail(struct iio_dev *indio_dev, 977 struct iio_chan_spec const *chan, 978 const int **vals, int *type, int *length, 979 long info) 980 { 981 switch (info) { 982 case IIO_CHAN_INFO_SCALE: 983 if (chan->type != IIO_ACCEL) 984 return -EINVAL; 985 986 *vals = (int *)adxl367_range_scale_tbl; 987 *type = IIO_VAL_INT_PLUS_NANO; 988 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2; 989 return IIO_AVAIL_LIST; 990 case IIO_CHAN_INFO_SAMP_FREQ: 991 *vals = (int *)adxl367_samp_freq_tbl; 992 *type = IIO_VAL_INT_PLUS_MICRO; 993 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2; 994 return IIO_AVAIL_LIST; 995 default: 996 return -EINVAL; 997 } 998 } 999 1000 static int adxl367_read_event_value(struct iio_dev *indio_dev, 1001 const struct iio_chan_spec *chan, 1002 enum iio_event_type type, 1003 enum iio_event_direction dir, 1004 enum iio_event_info info, 1005 int *val, int *val2) 1006 { 1007 struct adxl367_state *st = iio_priv(indio_dev); 1008 1009 switch (info) { 1010 case IIO_EV_INFO_VALUE: { 1011 switch (dir) { 1012 case IIO_EV_DIR_RISING: 1013 mutex_lock(&st->lock); 1014 *val = st->act_threshold; 1015 mutex_unlock(&st->lock); 1016 return IIO_VAL_INT; 1017 case IIO_EV_DIR_FALLING: 1018 mutex_lock(&st->lock); 1019 *val = st->inact_threshold; 1020 mutex_unlock(&st->lock); 1021 return IIO_VAL_INT; 1022 default: 1023 return -EINVAL; 1024 } 1025 } 1026 case IIO_EV_INFO_PERIOD: 1027 switch (dir) { 1028 case IIO_EV_DIR_RISING: 1029 mutex_lock(&st->lock); 1030 *val = st->act_time_ms; 1031 mutex_unlock(&st->lock); 1032 *val2 = 1000; 1033 return IIO_VAL_FRACTIONAL; 1034 case IIO_EV_DIR_FALLING: 1035 mutex_lock(&st->lock); 1036 *val = st->inact_time_ms; 1037 mutex_unlock(&st->lock); 1038 *val2 = 1000; 1039 return IIO_VAL_FRACTIONAL; 1040 default: 1041 return -EINVAL; 1042 } 1043 default: 1044 return -EINVAL; 1045 } 1046 } 1047 1048 static int adxl367_write_event_value(struct iio_dev *indio_dev, 1049 const struct iio_chan_spec *chan, 1050 enum iio_event_type type, 1051 enum iio_event_direction dir, 1052 enum iio_event_info info, 1053 int val, int val2) 1054 { 1055 struct adxl367_state *st = iio_priv(indio_dev); 1056 1057 switch (info) { 1058 case IIO_EV_INFO_VALUE: 1059 if (val < 0) 1060 return -EINVAL; 1061 1062 switch (dir) { 1063 case IIO_EV_DIR_RISING: 1064 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val); 1065 case IIO_EV_DIR_FALLING: 1066 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val); 1067 default: 1068 return -EINVAL; 1069 } 1070 case IIO_EV_INFO_PERIOD: 1071 if (val < 0) 1072 return -EINVAL; 1073 1074 val = val * 1000 + DIV_ROUND_UP(val2, 1000); 1075 switch (dir) { 1076 case IIO_EV_DIR_RISING: 1077 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val); 1078 case IIO_EV_DIR_FALLING: 1079 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val); 1080 default: 1081 return -EINVAL; 1082 } 1083 default: 1084 return -EINVAL; 1085 } 1086 } 1087 1088 static int adxl367_read_event_config(struct iio_dev *indio_dev, 1089 const struct iio_chan_spec *chan, 1090 enum iio_event_type type, 1091 enum iio_event_direction dir) 1092 { 1093 struct adxl367_state *st = iio_priv(indio_dev); 1094 bool en; 1095 int ret; 1096 1097 switch (dir) { 1098 case IIO_EV_DIR_RISING: 1099 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en); 1100 return ret ?: en; 1101 case IIO_EV_DIR_FALLING: 1102 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en); 1103 return ret ?: en; 1104 default: 1105 return -EINVAL; 1106 } 1107 } 1108 1109 static int adxl367_write_event_config(struct iio_dev *indio_dev, 1110 const struct iio_chan_spec *chan, 1111 enum iio_event_type type, 1112 enum iio_event_direction dir, 1113 int state) 1114 { 1115 struct adxl367_state *st = iio_priv(indio_dev); 1116 enum adxl367_activity_type act; 1117 int ret; 1118 1119 switch (dir) { 1120 case IIO_EV_DIR_RISING: 1121 act = ADXL367_ACTIVITY; 1122 break; 1123 case IIO_EV_DIR_FALLING: 1124 act = ADXL367_INACTIVITY; 1125 break; 1126 default: 1127 return -EINVAL; 1128 } 1129 1130 ret = iio_device_claim_direct_mode(indio_dev); 1131 if (ret) 1132 return ret; 1133 1134 mutex_lock(&st->lock); 1135 1136 ret = adxl367_set_measure_en(st, false); 1137 if (ret) 1138 goto out; 1139 1140 ret = adxl367_set_act_interrupt_en(st, act, state); 1141 if (ret) 1142 goto out; 1143 1144 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED 1145 : ADXL367_ACT_DISABLED); 1146 if (ret) 1147 goto out; 1148 1149 ret = adxl367_set_measure_en(st, true); 1150 1151 out: 1152 mutex_unlock(&st->lock); 1153 1154 iio_device_release_direct_mode(indio_dev); 1155 1156 return ret; 1157 } 1158 1159 static ssize_t adxl367_get_fifo_enabled(struct device *dev, 1160 struct device_attribute *attr, 1161 char *buf) 1162 { 1163 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev)); 1164 enum adxl367_fifo_mode fifo_mode; 1165 int ret; 1166 1167 ret = adxl367_get_fifo_mode(st, &fifo_mode); 1168 if (ret) 1169 return ret; 1170 1171 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED); 1172 } 1173 1174 static ssize_t adxl367_get_fifo_watermark(struct device *dev, 1175 struct device_attribute *attr, 1176 char *buf) 1177 { 1178 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev)); 1179 unsigned int fifo_watermark; 1180 1181 mutex_lock(&st->lock); 1182 fifo_watermark = st->fifo_watermark; 1183 mutex_unlock(&st->lock); 1184 1185 return sysfs_emit(buf, "%d\n", fifo_watermark); 1186 } 1187 1188 static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 1189 static IIO_CONST_ATTR(hwfifo_watermark_max, 1190 __stringify(ADXL367_FIFO_MAX_WATERMARK)); 1191 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1192 adxl367_get_fifo_watermark, NULL, 0); 1193 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1194 adxl367_get_fifo_enabled, NULL, 0); 1195 1196 static const struct attribute *adxl367_fifo_attributes[] = { 1197 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 1198 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 1199 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 1200 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 1201 NULL, 1202 }; 1203 1204 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1205 { 1206 struct adxl367_state *st = iio_priv(indio_dev); 1207 int ret; 1208 1209 if (val > ADXL367_FIFO_MAX_WATERMARK) 1210 return -EINVAL; 1211 1212 mutex_lock(&st->lock); 1213 1214 ret = adxl367_set_measure_en(st, false); 1215 if (ret) 1216 goto out; 1217 1218 ret = adxl367_set_fifo_watermark(st, val); 1219 if (ret) 1220 goto out; 1221 1222 ret = adxl367_set_measure_en(st, true); 1223 1224 out: 1225 mutex_unlock(&st->lock); 1226 1227 return ret; 1228 } 1229 1230 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask, 1231 enum adxl367_fifo_format *fifo_format) 1232 { 1233 size_t size = ARRAY_SIZE(adxl367_fifo_formats); 1234 int i; 1235 1236 for (i = 0; i < size; i++) 1237 if (*scan_mask == adxl367_channel_masks[i]) 1238 break; 1239 1240 if (i == size) 1241 return false; 1242 1243 *fifo_format = adxl367_fifo_formats[i]; 1244 1245 return true; 1246 } 1247 1248 static int adxl367_update_scan_mode(struct iio_dev *indio_dev, 1249 const unsigned long *active_scan_mask) 1250 { 1251 struct adxl367_state *st = iio_priv(indio_dev); 1252 enum adxl367_fifo_format fifo_format; 1253 int ret; 1254 1255 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format)) 1256 return -EINVAL; 1257 1258 mutex_lock(&st->lock); 1259 1260 ret = adxl367_set_measure_en(st, false); 1261 if (ret) 1262 goto out; 1263 1264 ret = adxl367_set_fifo_format(st, fifo_format); 1265 if (ret) 1266 goto out; 1267 1268 ret = adxl367_set_measure_en(st, true); 1269 if (ret) 1270 goto out; 1271 1272 st->fifo_set_size = bitmap_weight(active_scan_mask, 1273 indio_dev->masklength); 1274 1275 out: 1276 mutex_unlock(&st->lock); 1277 1278 return ret; 1279 } 1280 1281 static int adxl367_buffer_postenable(struct iio_dev *indio_dev) 1282 { 1283 struct adxl367_state *st = iio_priv(indio_dev); 1284 int ret; 1285 1286 mutex_lock(&st->lock); 1287 1288 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask, 1289 true); 1290 if (ret) 1291 goto out; 1292 1293 ret = adxl367_set_measure_en(st, false); 1294 if (ret) 1295 goto out; 1296 1297 ret = adxl367_set_fifo_watermark_interrupt_en(st, true); 1298 if (ret) 1299 goto out; 1300 1301 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM); 1302 if (ret) 1303 goto out; 1304 1305 ret = adxl367_set_measure_en(st, true); 1306 1307 out: 1308 mutex_unlock(&st->lock); 1309 1310 return ret; 1311 } 1312 1313 static int adxl367_buffer_predisable(struct iio_dev *indio_dev) 1314 { 1315 struct adxl367_state *st = iio_priv(indio_dev); 1316 int ret; 1317 1318 mutex_lock(&st->lock); 1319 1320 ret = adxl367_set_measure_en(st, false); 1321 if (ret) 1322 goto out; 1323 1324 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED); 1325 if (ret) 1326 goto out; 1327 1328 ret = adxl367_set_fifo_watermark_interrupt_en(st, false); 1329 if (ret) 1330 goto out; 1331 1332 ret = adxl367_set_measure_en(st, true); 1333 if (ret) 1334 goto out; 1335 1336 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask, 1337 false); 1338 1339 out: 1340 mutex_unlock(&st->lock); 1341 1342 return ret; 1343 } 1344 1345 static const struct iio_buffer_setup_ops adxl367_buffer_ops = { 1346 .postenable = adxl367_buffer_postenable, 1347 .predisable = adxl367_buffer_predisable, 1348 }; 1349 1350 static const struct iio_info adxl367_info = { 1351 .read_raw = adxl367_read_raw, 1352 .write_raw = adxl367_write_raw, 1353 .write_raw_get_fmt = adxl367_write_raw_get_fmt, 1354 .read_avail = adxl367_read_avail, 1355 .read_event_config = adxl367_read_event_config, 1356 .write_event_config = adxl367_write_event_config, 1357 .read_event_value = adxl367_read_event_value, 1358 .write_event_value = adxl367_write_event_value, 1359 .debugfs_reg_access = adxl367_reg_access, 1360 .hwfifo_set_watermark = adxl367_set_watermark, 1361 .update_scan_mode = adxl367_update_scan_mode, 1362 }; 1363 1364 static const struct iio_event_spec adxl367_events[] = { 1365 { 1366 .type = IIO_EV_TYPE_MAG_REFERENCED, 1367 .dir = IIO_EV_DIR_RISING, 1368 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 1369 BIT(IIO_EV_INFO_PERIOD) | 1370 BIT(IIO_EV_INFO_VALUE), 1371 }, 1372 { 1373 .type = IIO_EV_TYPE_MAG_REFERENCED, 1374 .dir = IIO_EV_DIR_FALLING, 1375 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 1376 BIT(IIO_EV_INFO_PERIOD) | 1377 BIT(IIO_EV_INFO_VALUE), 1378 }, 1379 }; 1380 1381 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \ 1382 .type = IIO_ACCEL, \ 1383 .address = (reg), \ 1384 .modified = 1, \ 1385 .channel2 = IIO_MOD_##axis, \ 1386 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 1387 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 1388 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 1389 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1390 .info_mask_shared_by_all_available = \ 1391 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1392 .event_spec = adxl367_events, \ 1393 .num_event_specs = ARRAY_SIZE(adxl367_events), \ 1394 .scan_index = (index), \ 1395 .scan_type = { \ 1396 .sign = 's', \ 1397 .realbits = 14, \ 1398 .storagebits = 16, \ 1399 .endianness = IIO_BE, \ 1400 }, \ 1401 } 1402 1403 #define ADXL367_CHANNEL(index, reg, _type) { \ 1404 .type = (_type), \ 1405 .address = (reg), \ 1406 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1407 BIT(IIO_CHAN_INFO_OFFSET) | \ 1408 BIT(IIO_CHAN_INFO_SCALE), \ 1409 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1410 .scan_index = (index), \ 1411 .scan_type = { \ 1412 .sign = 's', \ 1413 .realbits = 14, \ 1414 .storagebits = 16, \ 1415 .endianness = IIO_BE, \ 1416 }, \ 1417 } 1418 1419 static const struct iio_chan_spec adxl367_channels[] = { 1420 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X), 1421 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y), 1422 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z), 1423 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H, 1424 IIO_TEMP), 1425 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H, 1426 IIO_VOLTAGE), 1427 }; 1428 1429 static int adxl367_verify_devid(struct adxl367_state *st) 1430 { 1431 unsigned int val; 1432 int ret; 1433 1434 ret = regmap_read_poll_timeout(st->regmap, ADXL367_REG_DEVID, val, 1435 val == ADXL367_DEVID_AD, 1000, 10000); 1436 if (ret) 1437 return dev_err_probe(st->dev, -ENODEV, 1438 "Invalid dev id 0x%02X, expected 0x%02X\n", 1439 val, ADXL367_DEVID_AD); 1440 1441 return 0; 1442 } 1443 1444 static int adxl367_setup(struct adxl367_state *st) 1445 { 1446 int ret; 1447 1448 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY, 1449 ADXL367_2G_RANGE_1G); 1450 if (ret) 1451 return ret; 1452 1453 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY, 1454 ADXL367_2G_RANGE_100MG); 1455 if (ret) 1456 return ret; 1457 1458 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED); 1459 if (ret) 1460 return ret; 1461 1462 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ); 1463 if (ret) 1464 return ret; 1465 1466 ret = _adxl367_set_act_time_ms(st, 10); 1467 if (ret) 1468 return ret; 1469 1470 ret = _adxl367_set_inact_time_ms(st, 10000); 1471 if (ret) 1472 return ret; 1473 1474 return adxl367_set_measure_en(st, true); 1475 } 1476 1477 static void adxl367_disable_regulators(void *data) 1478 { 1479 struct adxl367_state *st = data; 1480 1481 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1482 } 1483 1484 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops, 1485 void *context, struct regmap *regmap, int irq) 1486 { 1487 struct iio_dev *indio_dev; 1488 struct adxl367_state *st; 1489 int ret; 1490 1491 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1492 if (!indio_dev) 1493 return -ENOMEM; 1494 1495 st = iio_priv(indio_dev); 1496 st->dev = dev; 1497 st->regmap = regmap; 1498 st->context = context; 1499 st->ops = ops; 1500 1501 mutex_init(&st->lock); 1502 1503 indio_dev->channels = adxl367_channels; 1504 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels); 1505 indio_dev->available_scan_masks = adxl367_channel_masks; 1506 indio_dev->name = "adxl367"; 1507 indio_dev->info = &adxl367_info; 1508 indio_dev->modes = INDIO_DIRECT_MODE; 1509 1510 st->regulators[0].supply = "vdd"; 1511 st->regulators[1].supply = "vddio"; 1512 1513 ret = devm_regulator_bulk_get(st->dev, ARRAY_SIZE(st->regulators), 1514 st->regulators); 1515 if (ret) 1516 return dev_err_probe(st->dev, ret, 1517 "Failed to get regulators\n"); 1518 1519 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1520 if (ret) 1521 return dev_err_probe(st->dev, ret, 1522 "Failed to enable regulators\n"); 1523 1524 ret = devm_add_action_or_reset(st->dev, adxl367_disable_regulators, st); 1525 if (ret) 1526 return dev_err_probe(st->dev, ret, 1527 "Failed to add regulators disable action\n"); 1528 1529 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE); 1530 if (ret) 1531 return ret; 1532 1533 ret = adxl367_verify_devid(st); 1534 if (ret) 1535 return ret; 1536 1537 ret = adxl367_setup(st); 1538 if (ret) 1539 return ret; 1540 1541 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev, 1542 &adxl367_buffer_ops, 1543 adxl367_fifo_attributes); 1544 if (ret) 1545 return ret; 1546 1547 ret = devm_request_threaded_irq(st->dev, irq, NULL, 1548 adxl367_irq_handler, IRQF_ONESHOT, 1549 indio_dev->name, indio_dev); 1550 if (ret) 1551 return dev_err_probe(st->dev, ret, "Failed to request irq\n"); 1552 1553 return devm_iio_device_register(dev, indio_dev); 1554 } 1555 EXPORT_SYMBOL_NS_GPL(adxl367_probe, IIO_ADXL367); 1556 1557 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 1558 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver"); 1559 MODULE_LICENSE("GPL"); 1560