1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2021 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/iio/buffer.h> 10 #include <linux/iio/events.h> 11 #include <linux/iio/iio.h> 12 #include <linux/iio/kfifo_buf.h> 13 #include <linux/iio/sysfs.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <asm/unaligned.h> 20 21 #include "adxl367.h" 22 23 #define ADXL367_REG_DEVID 0x00 24 #define ADXL367_DEVID_AD 0xAD 25 26 #define ADXL367_REG_STATUS 0x0B 27 #define ADXL367_STATUS_INACT_MASK BIT(5) 28 #define ADXL367_STATUS_ACT_MASK BIT(4) 29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2) 30 31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0) 32 33 #define ADXL367_REG_X_DATA_H 0x0E 34 #define ADXL367_REG_Y_DATA_H 0x10 35 #define ADXL367_REG_Z_DATA_H 0x12 36 #define ADXL367_REG_TEMP_DATA_H 0x14 37 #define ADXL367_REG_EX_ADC_DATA_H 0x16 38 #define ADXL367_DATA_MASK GENMASK(15, 2) 39 40 #define ADXL367_TEMP_25C 165 41 #define ADXL367_TEMP_PER_C 54 42 43 #define ADXL367_VOLTAGE_OFFSET 8192 44 #define ADXL367_VOLTAGE_MAX_MV 1000 45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0) 46 47 #define ADXL367_REG_RESET 0x1F 48 #define ADXL367_RESET_CODE 0x52 49 50 #define ADXL367_REG_THRESH_ACT_H 0x20 51 #define ADXL367_REG_THRESH_INACT_H 0x23 52 #define ADXL367_THRESH_MAX GENMASK(12, 0) 53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6) 54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0) 55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0) 56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2) 57 58 #define ADXL367_REG_TIME_ACT 0x22 59 #define ADXL367_REG_TIME_INACT_H 0x25 60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0) 61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0) 62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8) 63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0) 64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0) 65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0) 66 67 #define ADXL367_REG_ACT_INACT_CTL 0x27 68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0) 69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4) 70 71 #define ADXL367_REG_FIFO_CTL 0x28 72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3) 73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0) 74 75 #define ADXL367_REG_FIFO_SAMPLES 0x29 76 #define ADXL367_FIFO_SIZE 512 77 #define ADXL367_FIFO_MAX_WATERMARK 511 78 79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8) 80 #define ADXL367_SAMPLES_H_MASK BIT(2) 81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0) 82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0) 83 84 #define ADXL367_REG_INT1_MAP 0x2A 85 #define ADXL367_INT_INACT_MASK BIT(5) 86 #define ADXL367_INT_ACT_MASK BIT(4) 87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2) 88 89 #define ADXL367_REG_FILTER_CTL 0x2C 90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6) 91 #define ADXL367_2G_RANGE_1G 4095 92 #define ADXL367_2G_RANGE_100MG 409 93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0) 94 95 #define ADXL367_REG_POWER_CTL 0x2D 96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0) 97 98 #define ADXL367_REG_ADC_CTL 0x3C 99 #define ADXL367_REG_TEMP_CTL 0x3D 100 #define ADXL367_ADC_EN_MASK BIT(0) 101 102 enum adxl367_range { 103 ADXL367_2G_RANGE, 104 ADXL367_4G_RANGE, 105 ADXL367_8G_RANGE, 106 }; 107 108 enum adxl367_fifo_mode { 109 ADXL367_FIFO_MODE_DISABLED = 0b00, 110 ADXL367_FIFO_MODE_STREAM = 0b10, 111 }; 112 113 enum adxl367_fifo_format { 114 ADXL367_FIFO_FORMAT_XYZ, 115 ADXL367_FIFO_FORMAT_X, 116 ADXL367_FIFO_FORMAT_Y, 117 ADXL367_FIFO_FORMAT_Z, 118 ADXL367_FIFO_FORMAT_XYZT, 119 ADXL367_FIFO_FORMAT_XT, 120 ADXL367_FIFO_FORMAT_YT, 121 ADXL367_FIFO_FORMAT_ZT, 122 ADXL367_FIFO_FORMAT_XYZA, 123 ADXL367_FIFO_FORMAT_XA, 124 ADXL367_FIFO_FORMAT_YA, 125 ADXL367_FIFO_FORMAT_ZA, 126 }; 127 128 enum adxl367_op_mode { 129 ADXL367_OP_STANDBY = 0b00, 130 ADXL367_OP_MEASURE = 0b10, 131 }; 132 133 enum adxl367_act_proc_mode { 134 ADXL367_LOOPED = 0b11, 135 }; 136 137 enum adxl367_act_en_mode { 138 ADXL367_ACT_DISABLED = 0b00, 139 ADCL367_ACT_REF_ENABLED = 0b11, 140 }; 141 142 enum adxl367_activity_type { 143 ADXL367_ACTIVITY, 144 ADXL367_INACTIVITY, 145 }; 146 147 enum adxl367_odr { 148 ADXL367_ODR_12P5HZ, 149 ADXL367_ODR_25HZ, 150 ADXL367_ODR_50HZ, 151 ADXL367_ODR_100HZ, 152 ADXL367_ODR_200HZ, 153 ADXL367_ODR_400HZ, 154 }; 155 156 struct adxl367_state { 157 const struct adxl367_ops *ops; 158 void *context; 159 160 struct device *dev; 161 struct regmap *regmap; 162 163 struct regulator_bulk_data regulators[2]; 164 165 /* 166 * Synchronize access to members of driver state, and ensure atomicity 167 * of consecutive regmap operations. 168 */ 169 struct mutex lock; 170 171 enum adxl367_odr odr; 172 enum adxl367_range range; 173 174 unsigned int act_threshold; 175 unsigned int act_time_ms; 176 unsigned int inact_threshold; 177 unsigned int inact_time_ms; 178 179 unsigned int fifo_set_size; 180 unsigned int fifo_watermark; 181 182 __be16 fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned; 183 __be16 sample_buf; 184 u8 act_threshold_buf[2]; 185 u8 inact_time_buf[2]; 186 u8 status_buf[3]; 187 }; 188 189 static const unsigned int adxl367_threshold_h_reg_tbl[] = { 190 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H, 191 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H, 192 }; 193 194 static const unsigned int adxl367_act_en_shift_tbl[] = { 195 [ADXL367_ACTIVITY] = 0, 196 [ADXL367_INACTIVITY] = 2, 197 }; 198 199 static const unsigned int adxl367_act_int_mask_tbl[] = { 200 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK, 201 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK, 202 }; 203 204 static const int adxl367_samp_freq_tbl[][2] = { 205 [ADXL367_ODR_12P5HZ] = {12, 500000}, 206 [ADXL367_ODR_25HZ] = {25, 0}, 207 [ADXL367_ODR_50HZ] = {50, 0}, 208 [ADXL367_ODR_100HZ] = {100, 0}, 209 [ADXL367_ODR_200HZ] = {200, 0}, 210 [ADXL367_ODR_400HZ] = {400, 0}, 211 }; 212 213 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */ 214 static const int adxl367_range_scale_tbl[][2] = { 215 [ADXL367_2G_RANGE] = {0, 2394347}, 216 [ADXL367_4G_RANGE] = {0, 4788695}, 217 [ADXL367_8G_RANGE] = {0, 9577391}, 218 }; 219 220 static const int adxl367_range_scale_factor_tbl[] = { 221 [ADXL367_2G_RANGE] = 1, 222 [ADXL367_4G_RANGE] = 2, 223 [ADXL367_8G_RANGE] = 4, 224 }; 225 226 enum { 227 ADXL367_X_CHANNEL_INDEX, 228 ADXL367_Y_CHANNEL_INDEX, 229 ADXL367_Z_CHANNEL_INDEX, 230 ADXL367_TEMP_CHANNEL_INDEX, 231 ADXL367_EX_ADC_CHANNEL_INDEX 232 }; 233 234 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX) 235 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX) 236 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX) 237 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX) 238 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX) 239 240 static const enum adxl367_fifo_format adxl367_fifo_formats[] = { 241 ADXL367_FIFO_FORMAT_X, 242 ADXL367_FIFO_FORMAT_Y, 243 ADXL367_FIFO_FORMAT_Z, 244 ADXL367_FIFO_FORMAT_XT, 245 ADXL367_FIFO_FORMAT_YT, 246 ADXL367_FIFO_FORMAT_ZT, 247 ADXL367_FIFO_FORMAT_XA, 248 ADXL367_FIFO_FORMAT_YA, 249 ADXL367_FIFO_FORMAT_ZA, 250 ADXL367_FIFO_FORMAT_XYZ, 251 ADXL367_FIFO_FORMAT_XYZT, 252 ADXL367_FIFO_FORMAT_XYZA, 253 }; 254 255 static const unsigned long adxl367_channel_masks[] = { 256 ADXL367_X_CHANNEL_MASK, 257 ADXL367_Y_CHANNEL_MASK, 258 ADXL367_Z_CHANNEL_MASK, 259 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 260 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 261 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK, 262 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 263 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 264 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK, 265 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK, 266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK | 267 ADXL367_TEMP_CHANNEL_MASK, 268 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK | 269 ADXL367_EX_ADC_CHANNEL_MASK, 270 0, 271 }; 272 273 static int adxl367_set_measure_en(struct adxl367_state *st, bool en) 274 { 275 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE 276 : ADXL367_OP_STANDBY; 277 int ret; 278 279 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL, 280 ADXL367_POWER_CTL_MODE_MASK, 281 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK, 282 op_mode)); 283 if (ret) 284 return ret; 285 286 /* 287 * Wait for acceleration output to settle after entering 288 * measure mode. 289 */ 290 if (en) 291 msleep(100); 292 293 return 0; 294 } 295 296 static void adxl367_scale_act_thresholds(struct adxl367_state *st, 297 enum adxl367_range old_range, 298 enum adxl367_range new_range) 299 { 300 st->act_threshold = st->act_threshold 301 * adxl367_range_scale_factor_tbl[old_range] 302 / adxl367_range_scale_factor_tbl[new_range]; 303 st->inact_threshold = st->inact_threshold 304 * adxl367_range_scale_factor_tbl[old_range] 305 / adxl367_range_scale_factor_tbl[new_range]; 306 } 307 308 static int _adxl367_set_act_threshold(struct adxl367_state *st, 309 enum adxl367_activity_type act, 310 unsigned int threshold) 311 { 312 u8 reg = adxl367_threshold_h_reg_tbl[act]; 313 int ret; 314 315 if (threshold > ADXL367_THRESH_MAX) 316 return -EINVAL; 317 318 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK, 319 FIELD_GET(ADXL367_THRESH_VAL_H_MASK, 320 threshold)); 321 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK, 322 FIELD_GET(ADXL367_THRESH_VAL_L_MASK, 323 threshold)); 324 325 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf, 326 sizeof(st->act_threshold_buf)); 327 if (ret) 328 return ret; 329 330 if (act == ADXL367_ACTIVITY) 331 st->act_threshold = threshold; 332 else 333 st->inact_threshold = threshold; 334 335 return 0; 336 } 337 338 static int adxl367_set_act_threshold(struct adxl367_state *st, 339 enum adxl367_activity_type act, 340 unsigned int threshold) 341 { 342 int ret; 343 344 mutex_lock(&st->lock); 345 346 ret = adxl367_set_measure_en(st, false); 347 if (ret) 348 goto out; 349 350 ret = _adxl367_set_act_threshold(st, act, threshold); 351 if (ret) 352 goto out; 353 354 ret = adxl367_set_measure_en(st, true); 355 356 out: 357 mutex_unlock(&st->lock); 358 359 return ret; 360 } 361 362 static int adxl367_set_act_proc_mode(struct adxl367_state *st, 363 enum adxl367_act_proc_mode mode) 364 { 365 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL, 366 ADXL367_ACT_LINKLOOP_MASK, 367 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK, 368 mode)); 369 } 370 371 static int adxl367_set_act_interrupt_en(struct adxl367_state *st, 372 enum adxl367_activity_type act, 373 bool en) 374 { 375 unsigned int mask = adxl367_act_int_mask_tbl[act]; 376 377 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, 378 mask, en ? mask : 0); 379 } 380 381 static int adxl367_get_act_interrupt_en(struct adxl367_state *st, 382 enum adxl367_activity_type act, 383 bool *en) 384 { 385 unsigned int mask = adxl367_act_int_mask_tbl[act]; 386 unsigned int val; 387 int ret; 388 389 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val); 390 if (ret) 391 return ret; 392 393 *en = !!(val & mask); 394 395 return 0; 396 } 397 398 static int adxl367_set_act_en(struct adxl367_state *st, 399 enum adxl367_activity_type act, 400 enum adxl367_act_en_mode en) 401 { 402 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act]; 403 404 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL, 405 ADXL367_ACT_EN_MASK << ctl_shift, 406 en << ctl_shift); 407 } 408 409 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st, 410 bool en) 411 { 412 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP, 413 ADXL367_INT_FIFO_WATERMARK_MASK, 414 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0); 415 } 416 417 static int adxl367_get_fifo_mode(struct adxl367_state *st, 418 enum adxl367_fifo_mode *fifo_mode) 419 { 420 unsigned int val; 421 int ret; 422 423 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val); 424 if (ret) 425 return ret; 426 427 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val); 428 429 return 0; 430 } 431 432 static int adxl367_set_fifo_mode(struct adxl367_state *st, 433 enum adxl367_fifo_mode fifo_mode) 434 { 435 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 436 ADXL367_FIFO_CTL_MODE_MASK, 437 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK, 438 fifo_mode)); 439 } 440 441 static int adxl367_set_fifo_format(struct adxl367_state *st, 442 enum adxl367_fifo_format fifo_format) 443 { 444 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 445 ADXL367_FIFO_CTL_FORMAT_MASK, 446 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK, 447 fifo_format)); 448 } 449 450 static int adxl367_set_fifo_samples(struct adxl367_state *st, 451 unsigned int fifo_watermark, 452 unsigned int fifo_set_size) 453 { 454 unsigned int fifo_samples = fifo_watermark * fifo_set_size; 455 unsigned int fifo_samples_h, fifo_samples_l; 456 int ret; 457 458 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK) 459 fifo_samples = ADXL367_FIFO_MAX_WATERMARK; 460 461 if (fifo_set_size == 0) 462 return 0; 463 464 fifo_samples /= fifo_set_size; 465 466 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK, 467 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK, 468 fifo_samples)); 469 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK, 470 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK, 471 fifo_samples)); 472 473 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL, 474 ADXL367_SAMPLES_H_MASK, fifo_samples_h); 475 if (ret) 476 return ret; 477 478 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES, 479 ADXL367_SAMPLES_L_MASK, fifo_samples_l); 480 } 481 482 static int adxl367_set_fifo_set_size(struct adxl367_state *st, 483 unsigned int fifo_set_size) 484 { 485 int ret; 486 487 ret = adxl367_set_fifo_samples(st, st->fifo_watermark, fifo_set_size); 488 if (ret) 489 return ret; 490 491 st->fifo_set_size = fifo_set_size; 492 493 return 0; 494 } 495 496 static int adxl367_set_fifo_watermark(struct adxl367_state *st, 497 unsigned int fifo_watermark) 498 { 499 int ret; 500 501 ret = adxl367_set_fifo_samples(st, fifo_watermark, st->fifo_set_size); 502 if (ret) 503 return ret; 504 505 st->fifo_watermark = fifo_watermark; 506 507 return 0; 508 } 509 510 static int adxl367_set_range(struct iio_dev *indio_dev, 511 enum adxl367_range range) 512 { 513 struct adxl367_state *st = iio_priv(indio_dev); 514 int ret; 515 516 ret = iio_device_claim_direct_mode(indio_dev); 517 if (ret) 518 return ret; 519 520 mutex_lock(&st->lock); 521 522 ret = adxl367_set_measure_en(st, false); 523 if (ret) 524 goto out; 525 526 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL, 527 ADXL367_FILTER_CTL_RANGE_MASK, 528 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK, 529 range)); 530 if (ret) 531 goto out; 532 533 adxl367_scale_act_thresholds(st, st->range, range); 534 535 /* Activity thresholds depend on range */ 536 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY, 537 st->act_threshold); 538 if (ret) 539 goto out; 540 541 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY, 542 st->inact_threshold); 543 if (ret) 544 goto out; 545 546 ret = adxl367_set_measure_en(st, true); 547 if (ret) 548 goto out; 549 550 st->range = range; 551 552 out: 553 mutex_unlock(&st->lock); 554 555 iio_device_release_direct_mode(indio_dev); 556 557 return ret; 558 } 559 560 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms) 561 { 562 int freq_hz = adxl367_samp_freq_tbl[st->odr][0]; 563 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1]; 564 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */ 565 int freq_dhz = freq_hz * 10 + freq_microhz / 100000; 566 567 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000); 568 } 569 570 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms) 571 { 572 unsigned int val = adxl367_time_ms_to_samples(st, ms); 573 int ret; 574 575 if (val > ADXL367_TIME_ACT_MAX) 576 val = ADXL367_TIME_ACT_MAX; 577 578 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val); 579 if (ret) 580 return ret; 581 582 st->act_time_ms = ms; 583 584 return 0; 585 } 586 587 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms) 588 { 589 unsigned int val = adxl367_time_ms_to_samples(st, ms); 590 int ret; 591 592 if (val > ADXL367_TIME_INACT_MAX) 593 val = ADXL367_TIME_INACT_MAX; 594 595 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK, 596 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK, 597 val)); 598 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK, 599 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK, 600 val)); 601 602 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H, 603 st->inact_time_buf, sizeof(st->inact_time_buf)); 604 if (ret) 605 return ret; 606 607 st->inact_time_ms = ms; 608 609 return 0; 610 } 611 612 static int adxl367_set_act_time_ms(struct adxl367_state *st, 613 enum adxl367_activity_type act, 614 unsigned int ms) 615 { 616 int ret; 617 618 mutex_lock(&st->lock); 619 620 ret = adxl367_set_measure_en(st, false); 621 if (ret) 622 goto out; 623 624 if (act == ADXL367_ACTIVITY) 625 ret = _adxl367_set_act_time_ms(st, ms); 626 else 627 ret = _adxl367_set_inact_time_ms(st, ms); 628 629 if (ret) 630 goto out; 631 632 ret = adxl367_set_measure_en(st, true); 633 634 out: 635 mutex_unlock(&st->lock); 636 637 return ret; 638 } 639 640 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr) 641 { 642 int ret; 643 644 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL, 645 ADXL367_FILTER_CTL_ODR_MASK, 646 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK, 647 odr)); 648 if (ret) 649 return ret; 650 651 /* Activity timers depend on ODR */ 652 ret = _adxl367_set_act_time_ms(st, st->act_time_ms); 653 if (ret) 654 return ret; 655 656 ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms); 657 if (ret) 658 return ret; 659 660 st->odr = odr; 661 662 return 0; 663 } 664 665 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr) 666 { 667 struct adxl367_state *st = iio_priv(indio_dev); 668 int ret; 669 670 ret = iio_device_claim_direct_mode(indio_dev); 671 if (ret) 672 return ret; 673 674 mutex_lock(&st->lock); 675 676 ret = adxl367_set_measure_en(st, false); 677 if (ret) 678 goto out; 679 680 ret = _adxl367_set_odr(st, odr); 681 if (ret) 682 goto out; 683 684 ret = adxl367_set_measure_en(st, true); 685 686 out: 687 mutex_unlock(&st->lock); 688 689 iio_device_release_direct_mode(indio_dev); 690 691 return ret; 692 } 693 694 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg, 695 bool en) 696 { 697 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK, 698 en ? ADXL367_ADC_EN_MASK : 0); 699 } 700 701 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st, 702 unsigned int reg, bool en) 703 { 704 int ret; 705 706 switch (reg) { 707 case ADXL367_REG_TEMP_DATA_H: 708 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en); 709 break; 710 case ADXL367_REG_EX_ADC_DATA_H: 711 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en); 712 break; 713 default: 714 return 0; 715 } 716 717 if (ret) 718 return ret; 719 720 if (en) 721 msleep(100); 722 723 return 0; 724 } 725 726 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st, 727 const unsigned long *active_scan_mask, 728 bool en) 729 { 730 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK) 731 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en); 732 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK) 733 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en); 734 735 return 0; 736 } 737 738 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2, 739 enum adxl367_odr *odr) 740 { 741 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl); 742 int i; 743 744 for (i = 0; i < size; i++) 745 if (val == adxl367_samp_freq_tbl[i][0] && 746 val2 == adxl367_samp_freq_tbl[i][1]) 747 break; 748 749 if (i == size) 750 return -EINVAL; 751 752 *odr = i; 753 754 return 0; 755 } 756 757 static int adxl367_find_range(struct adxl367_state *st, int val, int val2, 758 enum adxl367_range *range) 759 { 760 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl); 761 int i; 762 763 for (i = 0; i < size; i++) 764 if (val == adxl367_range_scale_tbl[i][0] && 765 val2 == adxl367_range_scale_tbl[i][1]) 766 break; 767 768 if (i == size) 769 return -EINVAL; 770 771 *range = i; 772 773 return 0; 774 } 775 776 static int adxl367_read_sample(struct iio_dev *indio_dev, 777 struct iio_chan_spec const *chan, 778 int *val) 779 { 780 struct adxl367_state *st = iio_priv(indio_dev); 781 u16 sample; 782 int ret; 783 784 ret = iio_device_claim_direct_mode(indio_dev); 785 if (ret) 786 return ret; 787 788 mutex_lock(&st->lock); 789 790 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true); 791 if (ret) 792 goto out; 793 794 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf, 795 sizeof(st->sample_buf)); 796 if (ret) 797 goto out; 798 799 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf)); 800 *val = sign_extend32(sample, chan->scan_type.realbits - 1); 801 802 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false); 803 804 out: 805 mutex_unlock(&st->lock); 806 807 iio_device_release_direct_mode(indio_dev); 808 809 return ret ?: IIO_VAL_INT; 810 } 811 812 static int adxl367_get_status(struct adxl367_state *st, u8 *status, 813 u16 *fifo_entries) 814 { 815 int ret; 816 817 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */ 818 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS, 819 st->status_buf, sizeof(st->status_buf)); 820 if (ret) 821 return ret; 822 823 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK; 824 825 *status = st->status_buf[0]; 826 *fifo_entries = get_unaligned_le16(&st->status_buf[1]); 827 828 return 0; 829 } 830 831 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status) 832 { 833 unsigned int ev_dir; 834 835 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status)) 836 ev_dir = IIO_EV_DIR_RISING; 837 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status)) 838 ev_dir = IIO_EV_DIR_FALLING; 839 else 840 return false; 841 842 iio_push_event(indio_dev, 843 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, 844 IIO_EV_TYPE_THRESH, ev_dir), 845 iio_get_time_ns(indio_dev)); 846 847 return true; 848 } 849 850 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status, 851 u16 fifo_entries) 852 { 853 struct adxl367_state *st = iio_priv(indio_dev); 854 int ret; 855 int i; 856 857 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status)) 858 return false; 859 860 fifo_entries -= fifo_entries % st->fifo_set_size; 861 862 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries); 863 if (ret) { 864 dev_err(st->dev, "Failed to read FIFO: %d\n", ret); 865 return true; 866 } 867 868 for (i = 0; i < fifo_entries; i += st->fifo_set_size) 869 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); 870 871 return true; 872 } 873 874 static irqreturn_t adxl367_irq_handler(int irq, void *private) 875 { 876 struct iio_dev *indio_dev = private; 877 struct adxl367_state *st = iio_priv(indio_dev); 878 u16 fifo_entries; 879 bool handled; 880 u8 status; 881 int ret; 882 883 ret = adxl367_get_status(st, &status, &fifo_entries); 884 if (ret) 885 return IRQ_NONE; 886 887 handled = adxl367_push_event(indio_dev, status); 888 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries); 889 890 return handled ? IRQ_HANDLED : IRQ_NONE; 891 } 892 893 static int adxl367_reg_access(struct iio_dev *indio_dev, 894 unsigned int reg, 895 unsigned int writeval, 896 unsigned int *readval) 897 { 898 struct adxl367_state *st = iio_priv(indio_dev); 899 900 if (readval) 901 return regmap_read(st->regmap, reg, readval); 902 else 903 return regmap_write(st->regmap, reg, writeval); 904 } 905 906 static int adxl367_read_raw(struct iio_dev *indio_dev, 907 struct iio_chan_spec const *chan, 908 int *val, int *val2, long info) 909 { 910 struct adxl367_state *st = iio_priv(indio_dev); 911 912 switch (info) { 913 case IIO_CHAN_INFO_RAW: 914 return adxl367_read_sample(indio_dev, chan, val); 915 case IIO_CHAN_INFO_SCALE: 916 switch (chan->type) { 917 case IIO_ACCEL: 918 mutex_lock(&st->lock); 919 *val = adxl367_range_scale_tbl[st->range][0]; 920 *val2 = adxl367_range_scale_tbl[st->range][1]; 921 mutex_unlock(&st->lock); 922 return IIO_VAL_INT_PLUS_NANO; 923 case IIO_TEMP: 924 *val = 1000; 925 *val2 = ADXL367_TEMP_PER_C; 926 return IIO_VAL_FRACTIONAL; 927 case IIO_VOLTAGE: 928 *val = ADXL367_VOLTAGE_MAX_MV; 929 *val2 = ADXL367_VOLTAGE_MAX_RAW; 930 return IIO_VAL_FRACTIONAL; 931 default: 932 return -EINVAL; 933 } 934 case IIO_CHAN_INFO_OFFSET: 935 switch (chan->type) { 936 case IIO_TEMP: 937 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C; 938 return IIO_VAL_INT; 939 case IIO_VOLTAGE: 940 *val = ADXL367_VOLTAGE_OFFSET; 941 return IIO_VAL_INT; 942 default: 943 return -EINVAL; 944 } 945 case IIO_CHAN_INFO_SAMP_FREQ: 946 mutex_lock(&st->lock); 947 *val = adxl367_samp_freq_tbl[st->odr][0]; 948 *val2 = adxl367_samp_freq_tbl[st->odr][1]; 949 mutex_unlock(&st->lock); 950 return IIO_VAL_INT_PLUS_MICRO; 951 default: 952 return -EINVAL; 953 } 954 } 955 956 static int adxl367_write_raw(struct iio_dev *indio_dev, 957 struct iio_chan_spec const *chan, 958 int val, int val2, long info) 959 { 960 struct adxl367_state *st = iio_priv(indio_dev); 961 int ret; 962 963 switch (info) { 964 case IIO_CHAN_INFO_SAMP_FREQ: { 965 enum adxl367_odr odr; 966 967 ret = adxl367_find_odr(st, val, val2, &odr); 968 if (ret) 969 return ret; 970 971 return adxl367_set_odr(indio_dev, odr); 972 } 973 case IIO_CHAN_INFO_SCALE: { 974 enum adxl367_range range; 975 976 ret = adxl367_find_range(st, val, val2, &range); 977 if (ret) 978 return ret; 979 980 return adxl367_set_range(indio_dev, range); 981 } 982 default: 983 return -EINVAL; 984 } 985 } 986 987 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev, 988 struct iio_chan_spec const *chan, 989 long info) 990 { 991 switch (info) { 992 case IIO_CHAN_INFO_SCALE: 993 if (chan->type != IIO_ACCEL) 994 return -EINVAL; 995 996 return IIO_VAL_INT_PLUS_NANO; 997 default: 998 return IIO_VAL_INT_PLUS_MICRO; 999 } 1000 } 1001 1002 static int adxl367_read_avail(struct iio_dev *indio_dev, 1003 struct iio_chan_spec const *chan, 1004 const int **vals, int *type, int *length, 1005 long info) 1006 { 1007 switch (info) { 1008 case IIO_CHAN_INFO_SCALE: 1009 if (chan->type != IIO_ACCEL) 1010 return -EINVAL; 1011 1012 *vals = (int *)adxl367_range_scale_tbl; 1013 *type = IIO_VAL_INT_PLUS_NANO; 1014 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2; 1015 return IIO_AVAIL_LIST; 1016 case IIO_CHAN_INFO_SAMP_FREQ: 1017 *vals = (int *)adxl367_samp_freq_tbl; 1018 *type = IIO_VAL_INT_PLUS_MICRO; 1019 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2; 1020 return IIO_AVAIL_LIST; 1021 default: 1022 return -EINVAL; 1023 } 1024 } 1025 1026 static int adxl367_read_event_value(struct iio_dev *indio_dev, 1027 const struct iio_chan_spec *chan, 1028 enum iio_event_type type, 1029 enum iio_event_direction dir, 1030 enum iio_event_info info, 1031 int *val, int *val2) 1032 { 1033 struct adxl367_state *st = iio_priv(indio_dev); 1034 1035 switch (info) { 1036 case IIO_EV_INFO_VALUE: { 1037 switch (dir) { 1038 case IIO_EV_DIR_RISING: 1039 mutex_lock(&st->lock); 1040 *val = st->act_threshold; 1041 mutex_unlock(&st->lock); 1042 return IIO_VAL_INT; 1043 case IIO_EV_DIR_FALLING: 1044 mutex_lock(&st->lock); 1045 *val = st->inact_threshold; 1046 mutex_unlock(&st->lock); 1047 return IIO_VAL_INT; 1048 default: 1049 return -EINVAL; 1050 } 1051 } 1052 case IIO_EV_INFO_PERIOD: 1053 switch (dir) { 1054 case IIO_EV_DIR_RISING: 1055 mutex_lock(&st->lock); 1056 *val = st->act_time_ms; 1057 mutex_unlock(&st->lock); 1058 *val2 = 1000; 1059 return IIO_VAL_FRACTIONAL; 1060 case IIO_EV_DIR_FALLING: 1061 mutex_lock(&st->lock); 1062 *val = st->inact_time_ms; 1063 mutex_unlock(&st->lock); 1064 *val2 = 1000; 1065 return IIO_VAL_FRACTIONAL; 1066 default: 1067 return -EINVAL; 1068 } 1069 default: 1070 return -EINVAL; 1071 } 1072 } 1073 1074 static int adxl367_write_event_value(struct iio_dev *indio_dev, 1075 const struct iio_chan_spec *chan, 1076 enum iio_event_type type, 1077 enum iio_event_direction dir, 1078 enum iio_event_info info, 1079 int val, int val2) 1080 { 1081 struct adxl367_state *st = iio_priv(indio_dev); 1082 1083 switch (info) { 1084 case IIO_EV_INFO_VALUE: 1085 if (val < 0) 1086 return -EINVAL; 1087 1088 switch (dir) { 1089 case IIO_EV_DIR_RISING: 1090 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val); 1091 case IIO_EV_DIR_FALLING: 1092 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val); 1093 default: 1094 return -EINVAL; 1095 } 1096 case IIO_EV_INFO_PERIOD: 1097 if (val < 0) 1098 return -EINVAL; 1099 1100 val = val * 1000 + DIV_ROUND_UP(val2, 1000); 1101 switch (dir) { 1102 case IIO_EV_DIR_RISING: 1103 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val); 1104 case IIO_EV_DIR_FALLING: 1105 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val); 1106 default: 1107 return -EINVAL; 1108 } 1109 default: 1110 return -EINVAL; 1111 } 1112 } 1113 1114 static int adxl367_read_event_config(struct iio_dev *indio_dev, 1115 const struct iio_chan_spec *chan, 1116 enum iio_event_type type, 1117 enum iio_event_direction dir) 1118 { 1119 struct adxl367_state *st = iio_priv(indio_dev); 1120 bool en; 1121 int ret; 1122 1123 switch (dir) { 1124 case IIO_EV_DIR_RISING: 1125 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en); 1126 return ret ?: en; 1127 case IIO_EV_DIR_FALLING: 1128 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en); 1129 return ret ?: en; 1130 default: 1131 return -EINVAL; 1132 } 1133 } 1134 1135 static int adxl367_write_event_config(struct iio_dev *indio_dev, 1136 const struct iio_chan_spec *chan, 1137 enum iio_event_type type, 1138 enum iio_event_direction dir, 1139 int state) 1140 { 1141 struct adxl367_state *st = iio_priv(indio_dev); 1142 enum adxl367_activity_type act; 1143 int ret; 1144 1145 switch (dir) { 1146 case IIO_EV_DIR_RISING: 1147 act = ADXL367_ACTIVITY; 1148 break; 1149 case IIO_EV_DIR_FALLING: 1150 act = ADXL367_INACTIVITY; 1151 break; 1152 default: 1153 return -EINVAL; 1154 } 1155 1156 ret = iio_device_claim_direct_mode(indio_dev); 1157 if (ret) 1158 return ret; 1159 1160 mutex_lock(&st->lock); 1161 1162 ret = adxl367_set_measure_en(st, false); 1163 if (ret) 1164 goto out; 1165 1166 ret = adxl367_set_act_interrupt_en(st, act, state); 1167 if (ret) 1168 goto out; 1169 1170 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED 1171 : ADXL367_ACT_DISABLED); 1172 if (ret) 1173 goto out; 1174 1175 ret = adxl367_set_measure_en(st, true); 1176 1177 out: 1178 mutex_unlock(&st->lock); 1179 1180 iio_device_release_direct_mode(indio_dev); 1181 1182 return ret; 1183 } 1184 1185 static ssize_t adxl367_get_fifo_enabled(struct device *dev, 1186 struct device_attribute *attr, 1187 char *buf) 1188 { 1189 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev)); 1190 enum adxl367_fifo_mode fifo_mode; 1191 int ret; 1192 1193 ret = adxl367_get_fifo_mode(st, &fifo_mode); 1194 if (ret) 1195 return ret; 1196 1197 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED); 1198 } 1199 1200 static ssize_t adxl367_get_fifo_watermark(struct device *dev, 1201 struct device_attribute *attr, 1202 char *buf) 1203 { 1204 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev)); 1205 unsigned int fifo_watermark; 1206 1207 mutex_lock(&st->lock); 1208 fifo_watermark = st->fifo_watermark; 1209 mutex_unlock(&st->lock); 1210 1211 return sysfs_emit(buf, "%d\n", fifo_watermark); 1212 } 1213 1214 static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 1215 static IIO_CONST_ATTR(hwfifo_watermark_max, 1216 __stringify(ADXL367_FIFO_MAX_WATERMARK)); 1217 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1218 adxl367_get_fifo_watermark, NULL, 0); 1219 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1220 adxl367_get_fifo_enabled, NULL, 0); 1221 1222 static const struct attribute *adxl367_fifo_attributes[] = { 1223 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 1224 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 1225 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 1226 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 1227 NULL, 1228 }; 1229 1230 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1231 { 1232 struct adxl367_state *st = iio_priv(indio_dev); 1233 int ret; 1234 1235 if (val > ADXL367_FIFO_MAX_WATERMARK) 1236 return -EINVAL; 1237 1238 mutex_lock(&st->lock); 1239 1240 ret = adxl367_set_measure_en(st, false); 1241 if (ret) 1242 goto out; 1243 1244 ret = adxl367_set_fifo_watermark(st, val); 1245 if (ret) 1246 goto out; 1247 1248 ret = adxl367_set_measure_en(st, true); 1249 1250 out: 1251 mutex_unlock(&st->lock); 1252 1253 return ret; 1254 } 1255 1256 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask, 1257 enum adxl367_fifo_format *fifo_format) 1258 { 1259 size_t size = ARRAY_SIZE(adxl367_fifo_formats); 1260 int i; 1261 1262 for (i = 0; i < size; i++) 1263 if (*scan_mask == adxl367_channel_masks[i]) 1264 break; 1265 1266 if (i == size) 1267 return false; 1268 1269 *fifo_format = adxl367_fifo_formats[i]; 1270 1271 return true; 1272 } 1273 1274 static int adxl367_update_scan_mode(struct iio_dev *indio_dev, 1275 const unsigned long *active_scan_mask) 1276 { 1277 struct adxl367_state *st = iio_priv(indio_dev); 1278 enum adxl367_fifo_format fifo_format; 1279 unsigned int fifo_set_size; 1280 int ret; 1281 1282 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format)) 1283 return -EINVAL; 1284 1285 fifo_set_size = bitmap_weight(active_scan_mask, indio_dev->masklength); 1286 1287 mutex_lock(&st->lock); 1288 1289 ret = adxl367_set_measure_en(st, false); 1290 if (ret) 1291 goto out; 1292 1293 ret = adxl367_set_fifo_format(st, fifo_format); 1294 if (ret) 1295 goto out; 1296 1297 ret = adxl367_set_fifo_set_size(st, fifo_set_size); 1298 if (ret) 1299 goto out; 1300 1301 ret = adxl367_set_measure_en(st, true); 1302 1303 out: 1304 mutex_unlock(&st->lock); 1305 1306 return ret; 1307 } 1308 1309 static int adxl367_buffer_postenable(struct iio_dev *indio_dev) 1310 { 1311 struct adxl367_state *st = iio_priv(indio_dev); 1312 int ret; 1313 1314 mutex_lock(&st->lock); 1315 1316 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask, 1317 true); 1318 if (ret) 1319 goto out; 1320 1321 ret = adxl367_set_measure_en(st, false); 1322 if (ret) 1323 goto out; 1324 1325 ret = adxl367_set_fifo_watermark_interrupt_en(st, true); 1326 if (ret) 1327 goto out; 1328 1329 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM); 1330 if (ret) 1331 goto out; 1332 1333 ret = adxl367_set_measure_en(st, true); 1334 1335 out: 1336 mutex_unlock(&st->lock); 1337 1338 return ret; 1339 } 1340 1341 static int adxl367_buffer_predisable(struct iio_dev *indio_dev) 1342 { 1343 struct adxl367_state *st = iio_priv(indio_dev); 1344 int ret; 1345 1346 mutex_lock(&st->lock); 1347 1348 ret = adxl367_set_measure_en(st, false); 1349 if (ret) 1350 goto out; 1351 1352 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED); 1353 if (ret) 1354 goto out; 1355 1356 ret = adxl367_set_fifo_watermark_interrupt_en(st, false); 1357 if (ret) 1358 goto out; 1359 1360 ret = adxl367_set_measure_en(st, true); 1361 if (ret) 1362 goto out; 1363 1364 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask, 1365 false); 1366 1367 out: 1368 mutex_unlock(&st->lock); 1369 1370 return ret; 1371 } 1372 1373 static const struct iio_buffer_setup_ops adxl367_buffer_ops = { 1374 .postenable = adxl367_buffer_postenable, 1375 .predisable = adxl367_buffer_predisable, 1376 }; 1377 1378 static const struct iio_info adxl367_info = { 1379 .read_raw = adxl367_read_raw, 1380 .write_raw = adxl367_write_raw, 1381 .write_raw_get_fmt = adxl367_write_raw_get_fmt, 1382 .read_avail = adxl367_read_avail, 1383 .read_event_config = adxl367_read_event_config, 1384 .write_event_config = adxl367_write_event_config, 1385 .read_event_value = adxl367_read_event_value, 1386 .write_event_value = adxl367_write_event_value, 1387 .debugfs_reg_access = adxl367_reg_access, 1388 .hwfifo_set_watermark = adxl367_set_watermark, 1389 .update_scan_mode = adxl367_update_scan_mode, 1390 }; 1391 1392 static const struct iio_event_spec adxl367_events[] = { 1393 { 1394 .type = IIO_EV_TYPE_MAG_REFERENCED, 1395 .dir = IIO_EV_DIR_RISING, 1396 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 1397 BIT(IIO_EV_INFO_PERIOD) | 1398 BIT(IIO_EV_INFO_VALUE), 1399 }, 1400 { 1401 .type = IIO_EV_TYPE_MAG_REFERENCED, 1402 .dir = IIO_EV_DIR_FALLING, 1403 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 1404 BIT(IIO_EV_INFO_PERIOD) | 1405 BIT(IIO_EV_INFO_VALUE), 1406 }, 1407 }; 1408 1409 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \ 1410 .type = IIO_ACCEL, \ 1411 .address = (reg), \ 1412 .modified = 1, \ 1413 .channel2 = IIO_MOD_##axis, \ 1414 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 1415 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 1416 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 1417 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1418 .info_mask_shared_by_all_available = \ 1419 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1420 .event_spec = adxl367_events, \ 1421 .num_event_specs = ARRAY_SIZE(adxl367_events), \ 1422 .scan_index = (index), \ 1423 .scan_type = { \ 1424 .sign = 's', \ 1425 .realbits = 14, \ 1426 .storagebits = 16, \ 1427 .endianness = IIO_BE, \ 1428 }, \ 1429 } 1430 1431 #define ADXL367_CHANNEL(index, reg, _type) { \ 1432 .type = (_type), \ 1433 .address = (reg), \ 1434 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1435 BIT(IIO_CHAN_INFO_OFFSET) | \ 1436 BIT(IIO_CHAN_INFO_SCALE), \ 1437 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1438 .scan_index = (index), \ 1439 .scan_type = { \ 1440 .sign = 's', \ 1441 .realbits = 14, \ 1442 .storagebits = 16, \ 1443 .endianness = IIO_BE, \ 1444 }, \ 1445 } 1446 1447 static const struct iio_chan_spec adxl367_channels[] = { 1448 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X), 1449 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y), 1450 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z), 1451 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H, 1452 IIO_TEMP), 1453 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H, 1454 IIO_VOLTAGE), 1455 }; 1456 1457 static int adxl367_verify_devid(struct adxl367_state *st) 1458 { 1459 unsigned int val; 1460 int ret; 1461 1462 ret = regmap_read_poll_timeout(st->regmap, ADXL367_REG_DEVID, val, 1463 val == ADXL367_DEVID_AD, 1000, 10000); 1464 if (ret) 1465 return dev_err_probe(st->dev, -ENODEV, 1466 "Invalid dev id 0x%02X, expected 0x%02X\n", 1467 val, ADXL367_DEVID_AD); 1468 1469 return 0; 1470 } 1471 1472 static int adxl367_setup(struct adxl367_state *st) 1473 { 1474 int ret; 1475 1476 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY, 1477 ADXL367_2G_RANGE_1G); 1478 if (ret) 1479 return ret; 1480 1481 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY, 1482 ADXL367_2G_RANGE_100MG); 1483 if (ret) 1484 return ret; 1485 1486 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED); 1487 if (ret) 1488 return ret; 1489 1490 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ); 1491 if (ret) 1492 return ret; 1493 1494 ret = _adxl367_set_act_time_ms(st, 10); 1495 if (ret) 1496 return ret; 1497 1498 ret = _adxl367_set_inact_time_ms(st, 10000); 1499 if (ret) 1500 return ret; 1501 1502 return adxl367_set_measure_en(st, true); 1503 } 1504 1505 static void adxl367_disable_regulators(void *data) 1506 { 1507 struct adxl367_state *st = data; 1508 1509 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1510 } 1511 1512 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops, 1513 void *context, struct regmap *regmap, int irq) 1514 { 1515 struct iio_dev *indio_dev; 1516 struct adxl367_state *st; 1517 int ret; 1518 1519 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1520 if (!indio_dev) 1521 return -ENOMEM; 1522 1523 st = iio_priv(indio_dev); 1524 st->dev = dev; 1525 st->regmap = regmap; 1526 st->context = context; 1527 st->ops = ops; 1528 1529 mutex_init(&st->lock); 1530 1531 indio_dev->channels = adxl367_channels; 1532 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels); 1533 indio_dev->available_scan_masks = adxl367_channel_masks; 1534 indio_dev->name = "adxl367"; 1535 indio_dev->info = &adxl367_info; 1536 indio_dev->modes = INDIO_DIRECT_MODE; 1537 1538 st->regulators[0].supply = "vdd"; 1539 st->regulators[1].supply = "vddio"; 1540 1541 ret = devm_regulator_bulk_get(st->dev, ARRAY_SIZE(st->regulators), 1542 st->regulators); 1543 if (ret) 1544 return dev_err_probe(st->dev, ret, 1545 "Failed to get regulators\n"); 1546 1547 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1548 if (ret) 1549 return dev_err_probe(st->dev, ret, 1550 "Failed to enable regulators\n"); 1551 1552 ret = devm_add_action_or_reset(st->dev, adxl367_disable_regulators, st); 1553 if (ret) 1554 return dev_err_probe(st->dev, ret, 1555 "Failed to add regulators disable action\n"); 1556 1557 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE); 1558 if (ret) 1559 return ret; 1560 1561 ret = adxl367_verify_devid(st); 1562 if (ret) 1563 return ret; 1564 1565 ret = adxl367_setup(st); 1566 if (ret) 1567 return ret; 1568 1569 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev, 1570 &adxl367_buffer_ops, 1571 adxl367_fifo_attributes); 1572 if (ret) 1573 return ret; 1574 1575 ret = devm_request_threaded_irq(st->dev, irq, NULL, 1576 adxl367_irq_handler, IRQF_ONESHOT, 1577 indio_dev->name, indio_dev); 1578 if (ret) 1579 return dev_err_probe(st->dev, ret, "Failed to request irq\n"); 1580 1581 return devm_iio_device_register(dev, indio_dev); 1582 } 1583 EXPORT_SYMBOL_NS_GPL(adxl367_probe, IIO_ADXL367); 1584 1585 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 1586 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver"); 1587 MODULE_LICENSE("GPL"); 1588