1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Silvaco dual-role I3C master driver 4 * 5 * Copyright (C) 2020 Silvaco 6 * Author: Miquel RAYNAL <miquel.raynal@bootlin.com> 7 * Based on a work from: Conor Culhane <conor.culhane@silvaco.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/errno.h> 14 #include <linux/i3c/master.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 24 /* Master Mode Registers */ 25 #define SVC_I3C_MCONFIG 0x000 26 #define SVC_I3C_MCONFIG_MASTER_EN BIT(0) 27 #define SVC_I3C_MCONFIG_DISTO(x) FIELD_PREP(BIT(3), (x)) 28 #define SVC_I3C_MCONFIG_HKEEP(x) FIELD_PREP(GENMASK(5, 4), (x)) 29 #define SVC_I3C_MCONFIG_ODSTOP(x) FIELD_PREP(BIT(6), (x)) 30 #define SVC_I3C_MCONFIG_PPBAUD(x) FIELD_PREP(GENMASK(11, 8), (x)) 31 #define SVC_I3C_MCONFIG_PPLOW(x) FIELD_PREP(GENMASK(15, 12), (x)) 32 #define SVC_I3C_MCONFIG_ODBAUD(x) FIELD_PREP(GENMASK(23, 16), (x)) 33 #define SVC_I3C_MCONFIG_ODHPP(x) FIELD_PREP(BIT(24), (x)) 34 #define SVC_I3C_MCONFIG_SKEW(x) FIELD_PREP(GENMASK(27, 25), (x)) 35 #define SVC_I3C_MCONFIG_I2CBAUD(x) FIELD_PREP(GENMASK(31, 28), (x)) 36 37 #define SVC_I3C_MCTRL 0x084 38 #define SVC_I3C_MCTRL_REQUEST_MASK GENMASK(2, 0) 39 #define SVC_I3C_MCTRL_REQUEST_NONE 0 40 #define SVC_I3C_MCTRL_REQUEST_START_ADDR 1 41 #define SVC_I3C_MCTRL_REQUEST_STOP 2 42 #define SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK 3 43 #define SVC_I3C_MCTRL_REQUEST_PROC_DAA 4 44 #define SVC_I3C_MCTRL_REQUEST_AUTO_IBI 7 45 #define SVC_I3C_MCTRL_TYPE_I3C 0 46 #define SVC_I3C_MCTRL_TYPE_I2C BIT(4) 47 #define SVC_I3C_MCTRL_IBIRESP_AUTO 0 48 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE 0 49 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE BIT(7) 50 #define SVC_I3C_MCTRL_IBIRESP_NACK BIT(6) 51 #define SVC_I3C_MCTRL_IBIRESP_MANUAL GENMASK(7, 6) 52 #define SVC_I3C_MCTRL_DIR(x) FIELD_PREP(BIT(8), (x)) 53 #define SVC_I3C_MCTRL_DIR_WRITE 0 54 #define SVC_I3C_MCTRL_DIR_READ 1 55 #define SVC_I3C_MCTRL_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x)) 56 #define SVC_I3C_MCTRL_RDTERM(x) FIELD_PREP(GENMASK(23, 16), (x)) 57 58 #define SVC_I3C_MSTATUS 0x088 59 #define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x)) 60 #define SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) == 5) 61 #define SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) == 0) 62 #define SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x)) 63 #define SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x)) 64 #define SVC_I3C_MSTATUS_IBITYPE(x) FIELD_GET(GENMASK(7, 6), (x)) 65 #define SVC_I3C_MSTATUS_IBITYPE_IBI 1 66 #define SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST 2 67 #define SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN 3 68 #define SVC_I3C_MINT_SLVSTART BIT(8) 69 #define SVC_I3C_MINT_MCTRLDONE BIT(9) 70 #define SVC_I3C_MINT_COMPLETE BIT(10) 71 #define SVC_I3C_MINT_RXPEND BIT(11) 72 #define SVC_I3C_MINT_TXNOTFULL BIT(12) 73 #define SVC_I3C_MINT_IBIWON BIT(13) 74 #define SVC_I3C_MINT_ERRWARN BIT(15) 75 #define SVC_I3C_MSTATUS_SLVSTART(x) FIELD_GET(SVC_I3C_MINT_SLVSTART, (x)) 76 #define SVC_I3C_MSTATUS_MCTRLDONE(x) FIELD_GET(SVC_I3C_MINT_MCTRLDONE, (x)) 77 #define SVC_I3C_MSTATUS_COMPLETE(x) FIELD_GET(SVC_I3C_MINT_COMPLETE, (x)) 78 #define SVC_I3C_MSTATUS_RXPEND(x) FIELD_GET(SVC_I3C_MINT_RXPEND, (x)) 79 #define SVC_I3C_MSTATUS_TXNOTFULL(x) FIELD_GET(SVC_I3C_MINT_TXNOTFULL, (x)) 80 #define SVC_I3C_MSTATUS_IBIWON(x) FIELD_GET(SVC_I3C_MINT_IBIWON, (x)) 81 #define SVC_I3C_MSTATUS_ERRWARN(x) FIELD_GET(SVC_I3C_MINT_ERRWARN, (x)) 82 #define SVC_I3C_MSTATUS_IBIADDR(x) FIELD_GET(GENMASK(30, 24), (x)) 83 84 #define SVC_I3C_IBIRULES 0x08C 85 #define SVC_I3C_IBIRULES_ADDR(slot, addr) FIELD_PREP(GENMASK(29, 0), \ 86 ((addr) & 0x3F) << ((slot) * 6)) 87 #define SVC_I3C_IBIRULES_ADDRS 5 88 #define SVC_I3C_IBIRULES_MSB0 BIT(30) 89 #define SVC_I3C_IBIRULES_NOBYTE BIT(31) 90 #define SVC_I3C_IBIRULES_MANDBYTE 0 91 #define SVC_I3C_MINTSET 0x090 92 #define SVC_I3C_MINTCLR 0x094 93 #define SVC_I3C_MINTMASKED 0x098 94 #define SVC_I3C_MERRWARN 0x09C 95 #define SVC_I3C_MERRWARN_NACK BIT(2) 96 #define SVC_I3C_MERRWARN_TIMEOUT BIT(20) 97 #define SVC_I3C_MDMACTRL 0x0A0 98 #define SVC_I3C_MDATACTRL 0x0AC 99 #define SVC_I3C_MDATACTRL_FLUSHTB BIT(0) 100 #define SVC_I3C_MDATACTRL_FLUSHRB BIT(1) 101 #define SVC_I3C_MDATACTRL_UNLOCK_TRIG BIT(3) 102 #define SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4) 103 #define SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY 0 104 #define SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x)) 105 #define SVC_I3C_MDATACTRL_TXFULL BIT(30) 106 #define SVC_I3C_MDATACTRL_RXEMPTY BIT(31) 107 108 #define SVC_I3C_MWDATAB 0x0B0 109 #define SVC_I3C_MWDATAB_END BIT(8) 110 111 #define SVC_I3C_MWDATABE 0x0B4 112 #define SVC_I3C_MWDATAH 0x0B8 113 #define SVC_I3C_MWDATAHE 0x0BC 114 #define SVC_I3C_MRDATAB 0x0C0 115 #define SVC_I3C_MRDATAH 0x0C8 116 #define SVC_I3C_MWMSG_SDR 0x0D0 117 #define SVC_I3C_MRMSG_SDR 0x0D4 118 #define SVC_I3C_MWMSG_DDR 0x0D8 119 #define SVC_I3C_MRMSG_DDR 0x0DC 120 121 #define SVC_I3C_MDYNADDR 0x0E4 122 #define SVC_MDYNADDR_VALID BIT(0) 123 #define SVC_MDYNADDR_ADDR(x) FIELD_PREP(GENMASK(7, 1), (x)) 124 125 #define SVC_I3C_MAX_DEVS 32 126 #define SVC_I3C_PM_TIMEOUT_MS 1000 127 128 /* This parameter depends on the implementation and may be tuned */ 129 #define SVC_I3C_FIFO_SIZE 16 130 131 struct svc_i3c_cmd { 132 u8 addr; 133 bool rnw; 134 u8 *in; 135 const void *out; 136 unsigned int len; 137 unsigned int actual_len; 138 struct i3c_priv_xfer *xfer; 139 bool continued; 140 }; 141 142 struct svc_i3c_xfer { 143 struct list_head node; 144 struct completion comp; 145 int ret; 146 unsigned int type; 147 unsigned int ncmds; 148 struct svc_i3c_cmd cmds[]; 149 }; 150 151 struct svc_i3c_regs_save { 152 u32 mconfig; 153 u32 mdynaddr; 154 }; 155 156 /** 157 * struct svc_i3c_master - Silvaco I3C Master structure 158 * @base: I3C master controller 159 * @dev: Corresponding device 160 * @regs: Memory mapping 161 * @saved_regs: Volatile values for PM operations 162 * @free_slots: Bit array of available slots 163 * @addrs: Array containing the dynamic addresses of each attached device 164 * @descs: Array of descriptors, one per attached device 165 * @hj_work: Hot-join work 166 * @ibi_work: IBI work 167 * @irq: Main interrupt 168 * @pclk: System clock 169 * @fclk: Fast clock (bus) 170 * @sclk: Slow clock (other events) 171 * @xferqueue: Transfer queue structure 172 * @xferqueue.list: List member 173 * @xferqueue.cur: Current ongoing transfer 174 * @xferqueue.lock: Queue lock 175 * @ibi: IBI structure 176 * @ibi.num_slots: Number of slots available in @ibi.slots 177 * @ibi.slots: Available IBI slots 178 * @ibi.tbq_slot: To be queued IBI slot 179 * @ibi.lock: IBI lock 180 * @lock: Transfer lock, protect between IBI work thread and callbacks from master 181 */ 182 struct svc_i3c_master { 183 struct i3c_master_controller base; 184 struct device *dev; 185 void __iomem *regs; 186 struct svc_i3c_regs_save saved_regs; 187 u32 free_slots; 188 u8 addrs[SVC_I3C_MAX_DEVS]; 189 struct i3c_dev_desc *descs[SVC_I3C_MAX_DEVS]; 190 struct work_struct hj_work; 191 struct work_struct ibi_work; 192 int irq; 193 struct clk *pclk; 194 struct clk *fclk; 195 struct clk *sclk; 196 struct { 197 struct list_head list; 198 struct svc_i3c_xfer *cur; 199 /* Prevent races between transfers */ 200 spinlock_t lock; 201 } xferqueue; 202 struct { 203 unsigned int num_slots; 204 struct i3c_dev_desc **slots; 205 struct i3c_ibi_slot *tbq_slot; 206 /* Prevent races within IBI handlers */ 207 spinlock_t lock; 208 } ibi; 209 struct mutex lock; 210 }; 211 212 /** 213 * struct svc_i3c_i2c_dev_data - Device specific data 214 * @index: Index in the master tables corresponding to this device 215 * @ibi: IBI slot index in the master structure 216 * @ibi_pool: IBI pool associated to this device 217 */ 218 struct svc_i3c_i2c_dev_data { 219 u8 index; 220 int ibi; 221 struct i3c_generic_ibi_pool *ibi_pool; 222 }; 223 224 static bool svc_i3c_master_error(struct svc_i3c_master *master) 225 { 226 u32 mstatus, merrwarn; 227 228 mstatus = readl(master->regs + SVC_I3C_MSTATUS); 229 if (SVC_I3C_MSTATUS_ERRWARN(mstatus)) { 230 merrwarn = readl(master->regs + SVC_I3C_MERRWARN); 231 writel(merrwarn, master->regs + SVC_I3C_MERRWARN); 232 233 /* Ignore timeout error */ 234 if (merrwarn & SVC_I3C_MERRWARN_TIMEOUT) { 235 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n", 236 mstatus, merrwarn); 237 return false; 238 } 239 240 dev_err(master->dev, 241 "Error condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n", 242 mstatus, merrwarn); 243 244 return true; 245 } 246 247 return false; 248 } 249 250 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask) 251 { 252 writel(mask, master->regs + SVC_I3C_MINTSET); 253 } 254 255 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master) 256 { 257 u32 mask = readl(master->regs + SVC_I3C_MINTSET); 258 259 writel(mask, master->regs + SVC_I3C_MINTCLR); 260 } 261 262 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master) 263 { 264 /* Clear pending warnings */ 265 writel(readl(master->regs + SVC_I3C_MERRWARN), 266 master->regs + SVC_I3C_MERRWARN); 267 } 268 269 static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master) 270 { 271 /* Flush FIFOs */ 272 writel(SVC_I3C_MDATACTRL_FLUSHTB | SVC_I3C_MDATACTRL_FLUSHRB, 273 master->regs + SVC_I3C_MDATACTRL); 274 } 275 276 static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master) 277 { 278 u32 reg; 279 280 /* Set RX and TX tigger levels, flush FIFOs */ 281 reg = SVC_I3C_MDATACTRL_FLUSHTB | 282 SVC_I3C_MDATACTRL_FLUSHRB | 283 SVC_I3C_MDATACTRL_UNLOCK_TRIG | 284 SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL | 285 SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY; 286 writel(reg, master->regs + SVC_I3C_MDATACTRL); 287 } 288 289 static void svc_i3c_master_reset(struct svc_i3c_master *master) 290 { 291 svc_i3c_master_clear_merrwarn(master); 292 svc_i3c_master_reset_fifo_trigger(master); 293 svc_i3c_master_disable_interrupts(master); 294 } 295 296 static inline struct svc_i3c_master * 297 to_svc_i3c_master(struct i3c_master_controller *master) 298 { 299 return container_of(master, struct svc_i3c_master, base); 300 } 301 302 static void svc_i3c_master_hj_work(struct work_struct *work) 303 { 304 struct svc_i3c_master *master; 305 306 master = container_of(work, struct svc_i3c_master, hj_work); 307 i3c_master_do_daa(&master->base); 308 } 309 310 static struct i3c_dev_desc * 311 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master, 312 unsigned int ibiaddr) 313 { 314 int i; 315 316 for (i = 0; i < SVC_I3C_MAX_DEVS; i++) 317 if (master->addrs[i] == ibiaddr) 318 break; 319 320 if (i == SVC_I3C_MAX_DEVS) 321 return NULL; 322 323 return master->descs[i]; 324 } 325 326 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master) 327 { 328 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL); 329 330 /* 331 * This delay is necessary after the emission of a stop, otherwise eg. 332 * repeating IBIs do not get detected. There is a note in the manual 333 * about it, stating that the stop condition might not be settled 334 * correctly if a start condition follows too rapidly. 335 */ 336 udelay(1); 337 } 338 339 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master, 340 struct i3c_dev_desc *dev) 341 { 342 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 343 struct i3c_ibi_slot *slot; 344 unsigned int count; 345 u32 mdatactrl; 346 int ret, val; 347 u8 *buf; 348 349 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 350 if (!slot) 351 return -ENOSPC; 352 353 slot->len = 0; 354 buf = slot->data; 355 356 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, 357 SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000); 358 if (ret) { 359 dev_err(master->dev, "Timeout when polling for COMPLETE\n"); 360 return ret; 361 } 362 363 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) && 364 slot->len < SVC_I3C_FIFO_SIZE) { 365 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL); 366 count = SVC_I3C_MDATACTRL_RXCOUNT(mdatactrl); 367 readsl(master->regs + SVC_I3C_MRDATAB, buf, count); 368 slot->len += count; 369 buf += count; 370 } 371 372 master->ibi.tbq_slot = slot; 373 374 return 0; 375 } 376 377 static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master, 378 bool mandatory_byte) 379 { 380 unsigned int ibi_ack_nack; 381 382 ibi_ack_nack = SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK; 383 if (mandatory_byte) 384 ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE; 385 else 386 ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE; 387 388 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL); 389 } 390 391 static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master) 392 { 393 writel(SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK | 394 SVC_I3C_MCTRL_IBIRESP_NACK, 395 master->regs + SVC_I3C_MCTRL); 396 } 397 398 static void svc_i3c_master_ibi_work(struct work_struct *work) 399 { 400 struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work); 401 struct svc_i3c_i2c_dev_data *data; 402 unsigned int ibitype, ibiaddr; 403 struct i3c_dev_desc *dev; 404 u32 status, val; 405 int ret; 406 407 mutex_lock(&master->lock); 408 /* Acknowledge the incoming interrupt with the AUTOIBI mechanism */ 409 writel(SVC_I3C_MCTRL_REQUEST_AUTO_IBI | 410 SVC_I3C_MCTRL_IBIRESP_AUTO, 411 master->regs + SVC_I3C_MCTRL); 412 413 /* Wait for IBIWON, should take approximately 100us */ 414 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, 415 SVC_I3C_MSTATUS_IBIWON(val), 0, 1000); 416 if (ret) { 417 dev_err(master->dev, "Timeout when polling for IBIWON\n"); 418 svc_i3c_master_emit_stop(master); 419 goto reenable_ibis; 420 } 421 422 /* Clear the interrupt status */ 423 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 424 425 status = readl(master->regs + SVC_I3C_MSTATUS); 426 ibitype = SVC_I3C_MSTATUS_IBITYPE(status); 427 ibiaddr = SVC_I3C_MSTATUS_IBIADDR(status); 428 429 /* Handle the critical responses to IBI's */ 430 switch (ibitype) { 431 case SVC_I3C_MSTATUS_IBITYPE_IBI: 432 dev = svc_i3c_master_dev_from_addr(master, ibiaddr); 433 if (!dev) 434 svc_i3c_master_nack_ibi(master); 435 else 436 svc_i3c_master_handle_ibi(master, dev); 437 break; 438 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: 439 svc_i3c_master_ack_ibi(master, false); 440 break; 441 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: 442 svc_i3c_master_nack_ibi(master); 443 break; 444 default: 445 break; 446 } 447 448 /* 449 * If an error happened, we probably got interrupted and the exchange 450 * timedout. In this case we just drop everything, emit a stop and wait 451 * for the slave to interrupt again. 452 */ 453 if (svc_i3c_master_error(master)) { 454 if (master->ibi.tbq_slot) { 455 data = i3c_dev_get_master_data(dev); 456 i3c_generic_ibi_recycle_slot(data->ibi_pool, 457 master->ibi.tbq_slot); 458 master->ibi.tbq_slot = NULL; 459 } 460 461 svc_i3c_master_emit_stop(master); 462 463 goto reenable_ibis; 464 } 465 466 /* Handle the non critical tasks */ 467 switch (ibitype) { 468 case SVC_I3C_MSTATUS_IBITYPE_IBI: 469 if (dev) { 470 i3c_master_queue_ibi(dev, master->ibi.tbq_slot); 471 master->ibi.tbq_slot = NULL; 472 } 473 svc_i3c_master_emit_stop(master); 474 break; 475 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: 476 queue_work(master->base.wq, &master->hj_work); 477 break; 478 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: 479 default: 480 break; 481 } 482 483 reenable_ibis: 484 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); 485 mutex_unlock(&master->lock); 486 } 487 488 static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id) 489 { 490 struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id; 491 u32 active = readl(master->regs + SVC_I3C_MSTATUS); 492 493 if (!SVC_I3C_MSTATUS_SLVSTART(active)) 494 return IRQ_NONE; 495 496 /* Clear the interrupt status */ 497 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); 498 499 svc_i3c_master_disable_interrupts(master); 500 501 /* Handle the interrupt in a non atomic context */ 502 queue_work(master->base.wq, &master->ibi_work); 503 504 return IRQ_HANDLED; 505 } 506 507 static int svc_i3c_master_bus_init(struct i3c_master_controller *m) 508 { 509 struct svc_i3c_master *master = to_svc_i3c_master(m); 510 struct i3c_bus *bus = i3c_master_get_bus(m); 511 struct i3c_device_info info = {}; 512 unsigned long fclk_rate, fclk_period_ns; 513 unsigned int high_period_ns, od_low_period_ns; 514 u32 ppbaud, pplow, odhpp, odbaud, odstop, i2cbaud, reg; 515 int ret; 516 517 ret = pm_runtime_resume_and_get(master->dev); 518 if (ret < 0) { 519 dev_err(master->dev, 520 "<%s> cannot resume i3c bus master, err: %d\n", 521 __func__, ret); 522 return ret; 523 } 524 525 /* Timings derivation */ 526 fclk_rate = clk_get_rate(master->fclk); 527 if (!fclk_rate) { 528 ret = -EINVAL; 529 goto rpm_out; 530 } 531 532 fclk_period_ns = DIV_ROUND_UP(1000000000, fclk_rate); 533 534 /* 535 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period. 536 * Simplest configuration is using a 50% duty-cycle of 40ns. 537 */ 538 ppbaud = DIV_ROUND_UP(40, fclk_period_ns) - 1; 539 pplow = 0; 540 541 /* 542 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a 543 * duty-cycle tuned so that high levels are filetered out by 544 * the 50ns filter (target being 40ns). 545 */ 546 odhpp = 1; 547 high_period_ns = (ppbaud + 1) * fclk_period_ns; 548 odbaud = DIV_ROUND_UP(240 - high_period_ns, high_period_ns) - 1; 549 od_low_period_ns = (odbaud + 1) * high_period_ns; 550 551 switch (bus->mode) { 552 case I3C_BUS_MODE_PURE: 553 i2cbaud = 0; 554 odstop = 0; 555 break; 556 case I3C_BUS_MODE_MIXED_FAST: 557 case I3C_BUS_MODE_MIXED_LIMITED: 558 /* 559 * Using I2C Fm+ mode, target is 1MHz/1000ns, the difference 560 * between the high and low period does not really matter. 561 */ 562 i2cbaud = DIV_ROUND_UP(1000, od_low_period_ns) - 2; 563 odstop = 1; 564 break; 565 case I3C_BUS_MODE_MIXED_SLOW: 566 /* 567 * Using I2C Fm mode, target is 0.4MHz/2500ns, with the same 568 * constraints as the FM+ mode. 569 */ 570 i2cbaud = DIV_ROUND_UP(2500, od_low_period_ns) - 2; 571 odstop = 1; 572 break; 573 default: 574 goto rpm_out; 575 } 576 577 reg = SVC_I3C_MCONFIG_MASTER_EN | 578 SVC_I3C_MCONFIG_DISTO(0) | 579 SVC_I3C_MCONFIG_HKEEP(0) | 580 SVC_I3C_MCONFIG_ODSTOP(odstop) | 581 SVC_I3C_MCONFIG_PPBAUD(ppbaud) | 582 SVC_I3C_MCONFIG_PPLOW(pplow) | 583 SVC_I3C_MCONFIG_ODBAUD(odbaud) | 584 SVC_I3C_MCONFIG_ODHPP(odhpp) | 585 SVC_I3C_MCONFIG_SKEW(0) | 586 SVC_I3C_MCONFIG_I2CBAUD(i2cbaud); 587 writel(reg, master->regs + SVC_I3C_MCONFIG); 588 589 /* Master core's registration */ 590 ret = i3c_master_get_free_addr(m, 0); 591 if (ret < 0) 592 goto rpm_out; 593 594 info.dyn_addr = ret; 595 596 writel(SVC_MDYNADDR_VALID | SVC_MDYNADDR_ADDR(info.dyn_addr), 597 master->regs + SVC_I3C_MDYNADDR); 598 599 ret = i3c_master_set_info(&master->base, &info); 600 if (ret) 601 goto rpm_out; 602 603 rpm_out: 604 pm_runtime_mark_last_busy(master->dev); 605 pm_runtime_put_autosuspend(master->dev); 606 607 return ret; 608 } 609 610 static void svc_i3c_master_bus_cleanup(struct i3c_master_controller *m) 611 { 612 struct svc_i3c_master *master = to_svc_i3c_master(m); 613 int ret; 614 615 ret = pm_runtime_resume_and_get(master->dev); 616 if (ret < 0) { 617 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 618 return; 619 } 620 621 svc_i3c_master_disable_interrupts(master); 622 623 /* Disable master */ 624 writel(0, master->regs + SVC_I3C_MCONFIG); 625 626 pm_runtime_mark_last_busy(master->dev); 627 pm_runtime_put_autosuspend(master->dev); 628 } 629 630 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master) 631 { 632 unsigned int slot; 633 634 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0))) 635 return -ENOSPC; 636 637 slot = ffs(master->free_slots) - 1; 638 639 master->free_slots &= ~BIT(slot); 640 641 return slot; 642 } 643 644 static void svc_i3c_master_release_slot(struct svc_i3c_master *master, 645 unsigned int slot) 646 { 647 master->free_slots |= BIT(slot); 648 } 649 650 static int svc_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 651 { 652 struct i3c_master_controller *m = i3c_dev_get_master(dev); 653 struct svc_i3c_master *master = to_svc_i3c_master(m); 654 struct svc_i3c_i2c_dev_data *data; 655 int slot; 656 657 slot = svc_i3c_master_reserve_slot(master); 658 if (slot < 0) 659 return slot; 660 661 data = kzalloc(sizeof(*data), GFP_KERNEL); 662 if (!data) { 663 svc_i3c_master_release_slot(master, slot); 664 return -ENOMEM; 665 } 666 667 data->ibi = -1; 668 data->index = slot; 669 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr : 670 dev->info.static_addr; 671 master->descs[slot] = dev; 672 673 i3c_dev_set_master_data(dev, data); 674 675 return 0; 676 } 677 678 static int svc_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, 679 u8 old_dyn_addr) 680 { 681 struct i3c_master_controller *m = i3c_dev_get_master(dev); 682 struct svc_i3c_master *master = to_svc_i3c_master(m); 683 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 684 685 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : 686 dev->info.static_addr; 687 688 return 0; 689 } 690 691 static void svc_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 692 { 693 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 694 struct i3c_master_controller *m = i3c_dev_get_master(dev); 695 struct svc_i3c_master *master = to_svc_i3c_master(m); 696 697 master->addrs[data->index] = 0; 698 svc_i3c_master_release_slot(master, data->index); 699 700 kfree(data); 701 } 702 703 static int svc_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 704 { 705 struct i3c_master_controller *m = i2c_dev_get_master(dev); 706 struct svc_i3c_master *master = to_svc_i3c_master(m); 707 struct svc_i3c_i2c_dev_data *data; 708 int slot; 709 710 slot = svc_i3c_master_reserve_slot(master); 711 if (slot < 0) 712 return slot; 713 714 data = kzalloc(sizeof(*data), GFP_KERNEL); 715 if (!data) { 716 svc_i3c_master_release_slot(master, slot); 717 return -ENOMEM; 718 } 719 720 data->index = slot; 721 master->addrs[slot] = dev->addr; 722 723 i2c_dev_set_master_data(dev, data); 724 725 return 0; 726 } 727 728 static void svc_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 729 { 730 struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 731 struct i3c_master_controller *m = i2c_dev_get_master(dev); 732 struct svc_i3c_master *master = to_svc_i3c_master(m); 733 734 svc_i3c_master_release_slot(master, data->index); 735 736 kfree(data); 737 } 738 739 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst, 740 unsigned int len) 741 { 742 int ret, i; 743 u32 reg; 744 745 for (i = 0; i < len; i++) { 746 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 747 reg, 748 SVC_I3C_MSTATUS_RXPEND(reg), 749 0, 1000); 750 if (ret) 751 return ret; 752 753 dst[i] = readl(master->regs + SVC_I3C_MRDATAB); 754 } 755 756 return 0; 757 } 758 759 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master, 760 u8 *addrs, unsigned int *count) 761 { 762 u64 prov_id[SVC_I3C_MAX_DEVS] = {}, nacking_prov_id = 0; 763 unsigned int dev_nb = 0, last_addr = 0; 764 u32 reg; 765 int ret, i; 766 767 while (true) { 768 /* Enter/proceed with DAA */ 769 writel(SVC_I3C_MCTRL_REQUEST_PROC_DAA | 770 SVC_I3C_MCTRL_TYPE_I3C | 771 SVC_I3C_MCTRL_IBIRESP_NACK | 772 SVC_I3C_MCTRL_DIR(SVC_I3C_MCTRL_DIR_WRITE), 773 master->regs + SVC_I3C_MCTRL); 774 775 /* 776 * Either one slave will send its ID, or the assignment process 777 * is done. 778 */ 779 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 780 reg, 781 SVC_I3C_MSTATUS_RXPEND(reg) | 782 SVC_I3C_MSTATUS_MCTRLDONE(reg), 783 1, 1000); 784 if (ret) 785 return ret; 786 787 if (SVC_I3C_MSTATUS_RXPEND(reg)) { 788 u8 data[6]; 789 790 /* 791 * We only care about the 48-bit provisional ID yet to 792 * be sure a device does not nack an address twice. 793 * Otherwise, we would just need to flush the RX FIFO. 794 */ 795 ret = svc_i3c_master_readb(master, data, 6); 796 if (ret) 797 return ret; 798 799 for (i = 0; i < 6; i++) 800 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i)); 801 802 /* We do not care about the BCR and DCR yet */ 803 ret = svc_i3c_master_readb(master, data, 2); 804 if (ret) 805 return ret; 806 } else if (SVC_I3C_MSTATUS_MCTRLDONE(reg)) { 807 if (SVC_I3C_MSTATUS_STATE_IDLE(reg) && 808 SVC_I3C_MSTATUS_COMPLETE(reg)) { 809 /* 810 * All devices received and acked they dynamic 811 * address, this is the natural end of the DAA 812 * procedure. 813 */ 814 break; 815 } else if (SVC_I3C_MSTATUS_NACKED(reg)) { 816 /* No I3C devices attached */ 817 if (dev_nb == 0) 818 break; 819 820 /* 821 * A slave device nacked the address, this is 822 * allowed only once, DAA will be stopped and 823 * then resumed. The same device is supposed to 824 * answer again immediately and shall ack the 825 * address this time. 826 */ 827 if (prov_id[dev_nb] == nacking_prov_id) 828 return -EIO; 829 830 dev_nb--; 831 nacking_prov_id = prov_id[dev_nb]; 832 svc_i3c_master_emit_stop(master); 833 834 continue; 835 } else { 836 return -EIO; 837 } 838 } 839 840 /* Wait for the slave to be ready to receive its address */ 841 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, 842 reg, 843 SVC_I3C_MSTATUS_MCTRLDONE(reg) && 844 SVC_I3C_MSTATUS_STATE_DAA(reg) && 845 SVC_I3C_MSTATUS_BETWEEN(reg), 846 0, 1000); 847 if (ret) 848 return ret; 849 850 /* Give the slave device a suitable dynamic address */ 851 ret = i3c_master_get_free_addr(&master->base, last_addr + 1); 852 if (ret < 0) 853 return ret; 854 855 addrs[dev_nb] = ret; 856 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n", 857 dev_nb, addrs[dev_nb]); 858 859 writel(addrs[dev_nb], master->regs + SVC_I3C_MWDATAB); 860 last_addr = addrs[dev_nb++]; 861 } 862 863 *count = dev_nb; 864 865 return 0; 866 } 867 868 static int svc_i3c_update_ibirules(struct svc_i3c_master *master) 869 { 870 struct i3c_dev_desc *dev; 871 u32 reg_mbyte = 0, reg_nobyte = SVC_I3C_IBIRULES_NOBYTE; 872 unsigned int mbyte_addr_ok = 0, mbyte_addr_ko = 0, nobyte_addr_ok = 0, 873 nobyte_addr_ko = 0; 874 bool list_mbyte = false, list_nobyte = false; 875 876 /* Create the IBIRULES register for both cases */ 877 i3c_bus_for_each_i3cdev(&master->base.bus, dev) { 878 if (I3C_BCR_DEVICE_ROLE(dev->info.bcr) == I3C_BCR_I3C_MASTER) 879 continue; 880 881 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) { 882 reg_mbyte |= SVC_I3C_IBIRULES_ADDR(mbyte_addr_ok, 883 dev->info.dyn_addr); 884 885 /* IBI rules cannot be applied to devices with MSb=1 */ 886 if (dev->info.dyn_addr & BIT(7)) 887 mbyte_addr_ko++; 888 else 889 mbyte_addr_ok++; 890 } else { 891 reg_nobyte |= SVC_I3C_IBIRULES_ADDR(nobyte_addr_ok, 892 dev->info.dyn_addr); 893 894 /* IBI rules cannot be applied to devices with MSb=1 */ 895 if (dev->info.dyn_addr & BIT(7)) 896 nobyte_addr_ko++; 897 else 898 nobyte_addr_ok++; 899 } 900 } 901 902 /* Device list cannot be handled by hardware */ 903 if (!mbyte_addr_ko && mbyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS) 904 list_mbyte = true; 905 906 if (!nobyte_addr_ko && nobyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS) 907 list_nobyte = true; 908 909 /* No list can be properly handled, return an error */ 910 if (!list_mbyte && !list_nobyte) 911 return -ERANGE; 912 913 /* Pick the first list that can be handled by hardware, randomly */ 914 if (list_mbyte) 915 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES); 916 else 917 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES); 918 919 return 0; 920 } 921 922 static int svc_i3c_master_do_daa(struct i3c_master_controller *m) 923 { 924 struct svc_i3c_master *master = to_svc_i3c_master(m); 925 u8 addrs[SVC_I3C_MAX_DEVS]; 926 unsigned long flags; 927 unsigned int dev_nb; 928 int ret, i; 929 930 ret = pm_runtime_resume_and_get(master->dev); 931 if (ret < 0) { 932 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 933 return ret; 934 } 935 936 spin_lock_irqsave(&master->xferqueue.lock, flags); 937 ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb); 938 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 939 if (ret) { 940 svc_i3c_master_emit_stop(master); 941 svc_i3c_master_clear_merrwarn(master); 942 goto rpm_out; 943 } 944 945 /* Register all devices who participated to the core */ 946 for (i = 0; i < dev_nb; i++) { 947 ret = i3c_master_add_i3c_dev_locked(m, addrs[i]); 948 if (ret) 949 goto rpm_out; 950 } 951 952 /* Configure IBI auto-rules */ 953 ret = svc_i3c_update_ibirules(master); 954 if (ret) 955 dev_err(master->dev, "Cannot handle such a list of devices"); 956 957 rpm_out: 958 pm_runtime_mark_last_busy(master->dev); 959 pm_runtime_put_autosuspend(master->dev); 960 961 return ret; 962 } 963 964 static int svc_i3c_master_read(struct svc_i3c_master *master, 965 u8 *in, unsigned int len) 966 { 967 int offset = 0, i; 968 u32 mdctrl, mstatus; 969 bool completed = false; 970 unsigned int count; 971 unsigned long start = jiffies; 972 973 while (!completed) { 974 mstatus = readl(master->regs + SVC_I3C_MSTATUS); 975 if (SVC_I3C_MSTATUS_COMPLETE(mstatus) != 0) 976 completed = true; 977 978 if (time_after(jiffies, start + msecs_to_jiffies(1000))) { 979 dev_dbg(master->dev, "I3C read timeout\n"); 980 return -ETIMEDOUT; 981 } 982 983 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL); 984 count = SVC_I3C_MDATACTRL_RXCOUNT(mdctrl); 985 if (offset + count > len) { 986 dev_err(master->dev, "I3C receive length too long!\n"); 987 return -EINVAL; 988 } 989 for (i = 0; i < count; i++) 990 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB); 991 992 offset += count; 993 } 994 995 return offset; 996 } 997 998 static int svc_i3c_master_write(struct svc_i3c_master *master, 999 const u8 *out, unsigned int len) 1000 { 1001 int offset = 0, ret; 1002 u32 mdctrl; 1003 1004 while (offset < len) { 1005 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL, 1006 mdctrl, 1007 !(mdctrl & SVC_I3C_MDATACTRL_TXFULL), 1008 0, 1000); 1009 if (ret) 1010 return ret; 1011 1012 /* 1013 * The last byte to be sent over the bus must either have the 1014 * "end" bit set or be written in MWDATABE. 1015 */ 1016 if (likely(offset < (len - 1))) 1017 writel(out[offset++], master->regs + SVC_I3C_MWDATAB); 1018 else 1019 writel(out[offset++], master->regs + SVC_I3C_MWDATABE); 1020 } 1021 1022 return 0; 1023 } 1024 1025 static int svc_i3c_master_xfer(struct svc_i3c_master *master, 1026 bool rnw, unsigned int xfer_type, u8 addr, 1027 u8 *in, const u8 *out, unsigned int xfer_len, 1028 unsigned int *actual_len, bool continued) 1029 { 1030 u32 reg; 1031 int ret; 1032 1033 /* clean SVC_I3C_MINT_IBIWON w1c bits */ 1034 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 1035 1036 writel(SVC_I3C_MCTRL_REQUEST_START_ADDR | 1037 xfer_type | 1038 SVC_I3C_MCTRL_IBIRESP_NACK | 1039 SVC_I3C_MCTRL_DIR(rnw) | 1040 SVC_I3C_MCTRL_ADDR(addr) | 1041 SVC_I3C_MCTRL_RDTERM(*actual_len), 1042 master->regs + SVC_I3C_MCTRL); 1043 1044 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1045 SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000); 1046 if (ret) 1047 goto emit_stop; 1048 1049 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) { 1050 ret = -ENXIO; 1051 *actual_len = 0; 1052 goto emit_stop; 1053 } 1054 1055 /* 1056 * According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a Frame 1057 * with I3C Target Address. 1058 * 1059 * The I3C Controller normally should start a Frame, the Address may be arbitrated, and so 1060 * the Controller shall monitor to see whether an In-Band Interrupt request, a Controller 1061 * Role Request (i.e., Secondary Controller requests to become the Active Controller), or 1062 * a Hot-Join Request has been made. 1063 * 1064 * If missed IBIWON check, the wrong data will be return. When IBIWON happen, return failure 1065 * and yield the above events handler. 1066 */ 1067 if (SVC_I3C_MSTATUS_IBIWON(reg)) { 1068 ret = -EAGAIN; 1069 *actual_len = 0; 1070 goto emit_stop; 1071 } 1072 1073 if (rnw) 1074 ret = svc_i3c_master_read(master, in, xfer_len); 1075 else 1076 ret = svc_i3c_master_write(master, out, xfer_len); 1077 if (ret < 0) 1078 goto emit_stop; 1079 1080 if (rnw) 1081 *actual_len = ret; 1082 1083 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1084 SVC_I3C_MSTATUS_COMPLETE(reg), 0, 1000); 1085 if (ret) 1086 goto emit_stop; 1087 1088 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS); 1089 1090 if (!continued) { 1091 svc_i3c_master_emit_stop(master); 1092 1093 /* Wait idle if stop is sent. */ 1094 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, 1095 SVC_I3C_MSTATUS_STATE_IDLE(reg), 0, 1000); 1096 } 1097 1098 return 0; 1099 1100 emit_stop: 1101 svc_i3c_master_emit_stop(master); 1102 svc_i3c_master_clear_merrwarn(master); 1103 1104 return ret; 1105 } 1106 1107 static struct svc_i3c_xfer * 1108 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds) 1109 { 1110 struct svc_i3c_xfer *xfer; 1111 1112 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL); 1113 if (!xfer) 1114 return NULL; 1115 1116 INIT_LIST_HEAD(&xfer->node); 1117 xfer->ncmds = ncmds; 1118 xfer->ret = -ETIMEDOUT; 1119 1120 return xfer; 1121 } 1122 1123 static void svc_i3c_master_free_xfer(struct svc_i3c_xfer *xfer) 1124 { 1125 kfree(xfer); 1126 } 1127 1128 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master, 1129 struct svc_i3c_xfer *xfer) 1130 { 1131 if (master->xferqueue.cur == xfer) 1132 master->xferqueue.cur = NULL; 1133 else 1134 list_del_init(&xfer->node); 1135 } 1136 1137 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master, 1138 struct svc_i3c_xfer *xfer) 1139 { 1140 unsigned long flags; 1141 1142 spin_lock_irqsave(&master->xferqueue.lock, flags); 1143 svc_i3c_master_dequeue_xfer_locked(master, xfer); 1144 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 1145 } 1146 1147 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master) 1148 { 1149 struct svc_i3c_xfer *xfer = master->xferqueue.cur; 1150 int ret, i; 1151 1152 if (!xfer) 1153 return; 1154 1155 svc_i3c_master_clear_merrwarn(master); 1156 svc_i3c_master_flush_fifo(master); 1157 1158 for (i = 0; i < xfer->ncmds; i++) { 1159 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1160 1161 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type, 1162 cmd->addr, cmd->in, cmd->out, 1163 cmd->len, &cmd->actual_len, 1164 cmd->continued); 1165 /* cmd->xfer is NULL if I2C or CCC transfer */ 1166 if (cmd->xfer) 1167 cmd->xfer->actual_len = cmd->actual_len; 1168 1169 if (ret) 1170 break; 1171 } 1172 1173 xfer->ret = ret; 1174 complete(&xfer->comp); 1175 1176 if (ret < 0) 1177 svc_i3c_master_dequeue_xfer_locked(master, xfer); 1178 1179 xfer = list_first_entry_or_null(&master->xferqueue.list, 1180 struct svc_i3c_xfer, 1181 node); 1182 if (xfer) 1183 list_del_init(&xfer->node); 1184 1185 master->xferqueue.cur = xfer; 1186 svc_i3c_master_start_xfer_locked(master); 1187 } 1188 1189 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master, 1190 struct svc_i3c_xfer *xfer) 1191 { 1192 unsigned long flags; 1193 int ret; 1194 1195 ret = pm_runtime_resume_and_get(master->dev); 1196 if (ret < 0) { 1197 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 1198 return; 1199 } 1200 1201 init_completion(&xfer->comp); 1202 spin_lock_irqsave(&master->xferqueue.lock, flags); 1203 if (master->xferqueue.cur) { 1204 list_add_tail(&xfer->node, &master->xferqueue.list); 1205 } else { 1206 master->xferqueue.cur = xfer; 1207 svc_i3c_master_start_xfer_locked(master); 1208 } 1209 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 1210 1211 pm_runtime_mark_last_busy(master->dev); 1212 pm_runtime_put_autosuspend(master->dev); 1213 } 1214 1215 static bool 1216 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master, 1217 const struct i3c_ccc_cmd *cmd) 1218 { 1219 /* No software support for CCC commands targeting more than one slave */ 1220 return (cmd->ndests == 1); 1221 } 1222 1223 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master, 1224 struct i3c_ccc_cmd *ccc) 1225 { 1226 unsigned int xfer_len = ccc->dests[0].payload.len + 1; 1227 struct svc_i3c_xfer *xfer; 1228 struct svc_i3c_cmd *cmd; 1229 u8 *buf; 1230 int ret; 1231 1232 xfer = svc_i3c_master_alloc_xfer(master, 1); 1233 if (!xfer) 1234 return -ENOMEM; 1235 1236 buf = kmalloc(xfer_len, GFP_KERNEL); 1237 if (!buf) { 1238 svc_i3c_master_free_xfer(xfer); 1239 return -ENOMEM; 1240 } 1241 1242 buf[0] = ccc->id; 1243 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); 1244 1245 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; 1246 1247 cmd = &xfer->cmds[0]; 1248 cmd->addr = ccc->dests[0].addr; 1249 cmd->rnw = ccc->rnw; 1250 cmd->in = NULL; 1251 cmd->out = buf; 1252 cmd->len = xfer_len; 1253 cmd->actual_len = 0; 1254 cmd->continued = false; 1255 1256 mutex_lock(&master->lock); 1257 svc_i3c_master_enqueue_xfer(master, xfer); 1258 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1259 svc_i3c_master_dequeue_xfer(master, xfer); 1260 mutex_unlock(&master->lock); 1261 1262 ret = xfer->ret; 1263 kfree(buf); 1264 svc_i3c_master_free_xfer(xfer); 1265 1266 return ret; 1267 } 1268 1269 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master, 1270 struct i3c_ccc_cmd *ccc) 1271 { 1272 unsigned int xfer_len = ccc->dests[0].payload.len; 1273 unsigned int actual_len = ccc->rnw ? xfer_len : 0; 1274 struct svc_i3c_xfer *xfer; 1275 struct svc_i3c_cmd *cmd; 1276 int ret; 1277 1278 xfer = svc_i3c_master_alloc_xfer(master, 2); 1279 if (!xfer) 1280 return -ENOMEM; 1281 1282 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; 1283 1284 /* Broadcasted message */ 1285 cmd = &xfer->cmds[0]; 1286 cmd->addr = I3C_BROADCAST_ADDR; 1287 cmd->rnw = 0; 1288 cmd->in = NULL; 1289 cmd->out = &ccc->id; 1290 cmd->len = 1; 1291 cmd->actual_len = 0; 1292 cmd->continued = true; 1293 1294 /* Directed message */ 1295 cmd = &xfer->cmds[1]; 1296 cmd->addr = ccc->dests[0].addr; 1297 cmd->rnw = ccc->rnw; 1298 cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL; 1299 cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data, 1300 cmd->len = xfer_len; 1301 cmd->actual_len = actual_len; 1302 cmd->continued = false; 1303 1304 mutex_lock(&master->lock); 1305 svc_i3c_master_enqueue_xfer(master, xfer); 1306 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1307 svc_i3c_master_dequeue_xfer(master, xfer); 1308 mutex_unlock(&master->lock); 1309 1310 if (cmd->actual_len != xfer_len) 1311 ccc->dests[0].payload.len = cmd->actual_len; 1312 1313 ret = xfer->ret; 1314 svc_i3c_master_free_xfer(xfer); 1315 1316 return ret; 1317 } 1318 1319 static int svc_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 1320 struct i3c_ccc_cmd *cmd) 1321 { 1322 struct svc_i3c_master *master = to_svc_i3c_master(m); 1323 bool broadcast = cmd->id < 0x80; 1324 int ret; 1325 1326 if (broadcast) 1327 ret = svc_i3c_master_send_bdcast_ccc_cmd(master, cmd); 1328 else 1329 ret = svc_i3c_master_send_direct_ccc_cmd(master, cmd); 1330 1331 if (ret) 1332 cmd->err = I3C_ERROR_M2; 1333 1334 return ret; 1335 } 1336 1337 static int svc_i3c_master_priv_xfers(struct i3c_dev_desc *dev, 1338 struct i3c_priv_xfer *xfers, 1339 int nxfers) 1340 { 1341 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1342 struct svc_i3c_master *master = to_svc_i3c_master(m); 1343 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1344 struct svc_i3c_xfer *xfer; 1345 int ret, i; 1346 1347 xfer = svc_i3c_master_alloc_xfer(master, nxfers); 1348 if (!xfer) 1349 return -ENOMEM; 1350 1351 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; 1352 1353 for (i = 0; i < nxfers; i++) { 1354 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1355 1356 cmd->xfer = &xfers[i]; 1357 cmd->addr = master->addrs[data->index]; 1358 cmd->rnw = xfers[i].rnw; 1359 cmd->in = xfers[i].rnw ? xfers[i].data.in : NULL; 1360 cmd->out = xfers[i].rnw ? NULL : xfers[i].data.out; 1361 cmd->len = xfers[i].len; 1362 cmd->actual_len = xfers[i].rnw ? xfers[i].len : 0; 1363 cmd->continued = (i + 1) < nxfers; 1364 } 1365 1366 mutex_lock(&master->lock); 1367 svc_i3c_master_enqueue_xfer(master, xfer); 1368 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1369 svc_i3c_master_dequeue_xfer(master, xfer); 1370 mutex_unlock(&master->lock); 1371 1372 ret = xfer->ret; 1373 svc_i3c_master_free_xfer(xfer); 1374 1375 return ret; 1376 } 1377 1378 static int svc_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 1379 const struct i2c_msg *xfers, 1380 int nxfers) 1381 { 1382 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1383 struct svc_i3c_master *master = to_svc_i3c_master(m); 1384 struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1385 struct svc_i3c_xfer *xfer; 1386 int ret, i; 1387 1388 xfer = svc_i3c_master_alloc_xfer(master, nxfers); 1389 if (!xfer) 1390 return -ENOMEM; 1391 1392 xfer->type = SVC_I3C_MCTRL_TYPE_I2C; 1393 1394 for (i = 0; i < nxfers; i++) { 1395 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; 1396 1397 cmd->addr = master->addrs[data->index]; 1398 cmd->rnw = xfers[i].flags & I2C_M_RD; 1399 cmd->in = cmd->rnw ? xfers[i].buf : NULL; 1400 cmd->out = cmd->rnw ? NULL : xfers[i].buf; 1401 cmd->len = xfers[i].len; 1402 cmd->actual_len = cmd->rnw ? xfers[i].len : 0; 1403 cmd->continued = (i + 1 < nxfers); 1404 } 1405 1406 mutex_lock(&master->lock); 1407 svc_i3c_master_enqueue_xfer(master, xfer); 1408 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 1409 svc_i3c_master_dequeue_xfer(master, xfer); 1410 mutex_unlock(&master->lock); 1411 1412 ret = xfer->ret; 1413 svc_i3c_master_free_xfer(xfer); 1414 1415 return ret; 1416 } 1417 1418 static int svc_i3c_master_request_ibi(struct i3c_dev_desc *dev, 1419 const struct i3c_ibi_setup *req) 1420 { 1421 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1422 struct svc_i3c_master *master = to_svc_i3c_master(m); 1423 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1424 unsigned long flags; 1425 unsigned int i; 1426 1427 if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) { 1428 dev_err(master->dev, "IBI max payload %d should be < %d\n", 1429 dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE); 1430 return -ERANGE; 1431 } 1432 1433 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 1434 if (IS_ERR(data->ibi_pool)) 1435 return PTR_ERR(data->ibi_pool); 1436 1437 spin_lock_irqsave(&master->ibi.lock, flags); 1438 for (i = 0; i < master->ibi.num_slots; i++) { 1439 if (!master->ibi.slots[i]) { 1440 data->ibi = i; 1441 master->ibi.slots[i] = dev; 1442 break; 1443 } 1444 } 1445 spin_unlock_irqrestore(&master->ibi.lock, flags); 1446 1447 if (i < master->ibi.num_slots) 1448 return 0; 1449 1450 i3c_generic_ibi_free_pool(data->ibi_pool); 1451 data->ibi_pool = NULL; 1452 1453 return -ENOSPC; 1454 } 1455 1456 static void svc_i3c_master_free_ibi(struct i3c_dev_desc *dev) 1457 { 1458 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1459 struct svc_i3c_master *master = to_svc_i3c_master(m); 1460 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1461 unsigned long flags; 1462 1463 spin_lock_irqsave(&master->ibi.lock, flags); 1464 master->ibi.slots[data->ibi] = NULL; 1465 data->ibi = -1; 1466 spin_unlock_irqrestore(&master->ibi.lock, flags); 1467 1468 i3c_generic_ibi_free_pool(data->ibi_pool); 1469 } 1470 1471 static int svc_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 1472 { 1473 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1474 struct svc_i3c_master *master = to_svc_i3c_master(m); 1475 int ret; 1476 1477 ret = pm_runtime_resume_and_get(master->dev); 1478 if (ret < 0) { 1479 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); 1480 return ret; 1481 } 1482 1483 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); 1484 1485 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1486 } 1487 1488 static int svc_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 1489 { 1490 struct i3c_master_controller *m = i3c_dev_get_master(dev); 1491 struct svc_i3c_master *master = to_svc_i3c_master(m); 1492 int ret; 1493 1494 svc_i3c_master_disable_interrupts(master); 1495 1496 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 1497 1498 pm_runtime_mark_last_busy(master->dev); 1499 pm_runtime_put_autosuspend(master->dev); 1500 1501 return ret; 1502 } 1503 1504 static void svc_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 1505 struct i3c_ibi_slot *slot) 1506 { 1507 struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 1508 1509 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 1510 } 1511 1512 static const struct i3c_master_controller_ops svc_i3c_master_ops = { 1513 .bus_init = svc_i3c_master_bus_init, 1514 .bus_cleanup = svc_i3c_master_bus_cleanup, 1515 .attach_i3c_dev = svc_i3c_master_attach_i3c_dev, 1516 .detach_i3c_dev = svc_i3c_master_detach_i3c_dev, 1517 .reattach_i3c_dev = svc_i3c_master_reattach_i3c_dev, 1518 .attach_i2c_dev = svc_i3c_master_attach_i2c_dev, 1519 .detach_i2c_dev = svc_i3c_master_detach_i2c_dev, 1520 .do_daa = svc_i3c_master_do_daa, 1521 .supports_ccc_cmd = svc_i3c_master_supports_ccc_cmd, 1522 .send_ccc_cmd = svc_i3c_master_send_ccc_cmd, 1523 .priv_xfers = svc_i3c_master_priv_xfers, 1524 .i2c_xfers = svc_i3c_master_i2c_xfers, 1525 .request_ibi = svc_i3c_master_request_ibi, 1526 .free_ibi = svc_i3c_master_free_ibi, 1527 .recycle_ibi_slot = svc_i3c_master_recycle_ibi_slot, 1528 .enable_ibi = svc_i3c_master_enable_ibi, 1529 .disable_ibi = svc_i3c_master_disable_ibi, 1530 }; 1531 1532 static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master) 1533 { 1534 int ret = 0; 1535 1536 ret = clk_prepare_enable(master->pclk); 1537 if (ret) 1538 return ret; 1539 1540 ret = clk_prepare_enable(master->fclk); 1541 if (ret) { 1542 clk_disable_unprepare(master->pclk); 1543 return ret; 1544 } 1545 1546 ret = clk_prepare_enable(master->sclk); 1547 if (ret) { 1548 clk_disable_unprepare(master->pclk); 1549 clk_disable_unprepare(master->fclk); 1550 return ret; 1551 } 1552 1553 return 0; 1554 } 1555 1556 static void svc_i3c_master_unprepare_clks(struct svc_i3c_master *master) 1557 { 1558 clk_disable_unprepare(master->pclk); 1559 clk_disable_unprepare(master->fclk); 1560 clk_disable_unprepare(master->sclk); 1561 } 1562 1563 static int svc_i3c_master_probe(struct platform_device *pdev) 1564 { 1565 struct device *dev = &pdev->dev; 1566 struct svc_i3c_master *master; 1567 int ret; 1568 1569 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); 1570 if (!master) 1571 return -ENOMEM; 1572 1573 master->regs = devm_platform_ioremap_resource(pdev, 0); 1574 if (IS_ERR(master->regs)) 1575 return PTR_ERR(master->regs); 1576 1577 master->pclk = devm_clk_get(dev, "pclk"); 1578 if (IS_ERR(master->pclk)) 1579 return PTR_ERR(master->pclk); 1580 1581 master->fclk = devm_clk_get(dev, "fast_clk"); 1582 if (IS_ERR(master->fclk)) 1583 return PTR_ERR(master->fclk); 1584 1585 master->sclk = devm_clk_get(dev, "slow_clk"); 1586 if (IS_ERR(master->sclk)) 1587 return PTR_ERR(master->sclk); 1588 1589 master->irq = platform_get_irq(pdev, 0); 1590 if (master->irq < 0) 1591 return master->irq; 1592 1593 master->dev = dev; 1594 1595 ret = svc_i3c_master_prepare_clks(master); 1596 if (ret) 1597 return ret; 1598 1599 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work); 1600 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work); 1601 mutex_init(&master->lock); 1602 1603 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler, 1604 IRQF_NO_SUSPEND, "svc-i3c-irq", master); 1605 if (ret) 1606 goto err_disable_clks; 1607 1608 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0); 1609 1610 spin_lock_init(&master->xferqueue.lock); 1611 INIT_LIST_HEAD(&master->xferqueue.list); 1612 1613 spin_lock_init(&master->ibi.lock); 1614 master->ibi.num_slots = SVC_I3C_MAX_DEVS; 1615 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, 1616 sizeof(*master->ibi.slots), 1617 GFP_KERNEL); 1618 if (!master->ibi.slots) { 1619 ret = -ENOMEM; 1620 goto err_disable_clks; 1621 } 1622 1623 platform_set_drvdata(pdev, master); 1624 1625 pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS); 1626 pm_runtime_use_autosuspend(&pdev->dev); 1627 pm_runtime_get_noresume(&pdev->dev); 1628 pm_runtime_set_active(&pdev->dev); 1629 pm_runtime_enable(&pdev->dev); 1630 1631 svc_i3c_master_reset(master); 1632 1633 /* Register the master */ 1634 ret = i3c_master_register(&master->base, &pdev->dev, 1635 &svc_i3c_master_ops, false); 1636 if (ret) 1637 goto rpm_disable; 1638 1639 pm_runtime_mark_last_busy(&pdev->dev); 1640 pm_runtime_put_autosuspend(&pdev->dev); 1641 1642 return 0; 1643 1644 rpm_disable: 1645 pm_runtime_dont_use_autosuspend(&pdev->dev); 1646 pm_runtime_put_noidle(&pdev->dev); 1647 pm_runtime_set_suspended(&pdev->dev); 1648 pm_runtime_disable(&pdev->dev); 1649 1650 err_disable_clks: 1651 svc_i3c_master_unprepare_clks(master); 1652 1653 return ret; 1654 } 1655 1656 static void svc_i3c_master_remove(struct platform_device *pdev) 1657 { 1658 struct svc_i3c_master *master = platform_get_drvdata(pdev); 1659 1660 i3c_master_unregister(&master->base); 1661 1662 pm_runtime_dont_use_autosuspend(&pdev->dev); 1663 pm_runtime_disable(&pdev->dev); 1664 } 1665 1666 static void svc_i3c_save_regs(struct svc_i3c_master *master) 1667 { 1668 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG); 1669 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR); 1670 } 1671 1672 static void svc_i3c_restore_regs(struct svc_i3c_master *master) 1673 { 1674 if (readl(master->regs + SVC_I3C_MDYNADDR) != 1675 master->saved_regs.mdynaddr) { 1676 writel(master->saved_regs.mconfig, 1677 master->regs + SVC_I3C_MCONFIG); 1678 writel(master->saved_regs.mdynaddr, 1679 master->regs + SVC_I3C_MDYNADDR); 1680 } 1681 } 1682 1683 static int __maybe_unused svc_i3c_runtime_suspend(struct device *dev) 1684 { 1685 struct svc_i3c_master *master = dev_get_drvdata(dev); 1686 1687 svc_i3c_save_regs(master); 1688 svc_i3c_master_unprepare_clks(master); 1689 pinctrl_pm_select_sleep_state(dev); 1690 1691 return 0; 1692 } 1693 1694 static int __maybe_unused svc_i3c_runtime_resume(struct device *dev) 1695 { 1696 struct svc_i3c_master *master = dev_get_drvdata(dev); 1697 1698 pinctrl_pm_select_default_state(dev); 1699 svc_i3c_master_prepare_clks(master); 1700 1701 svc_i3c_restore_regs(master); 1702 1703 return 0; 1704 } 1705 1706 static const struct dev_pm_ops svc_i3c_pm_ops = { 1707 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1708 pm_runtime_force_resume) 1709 SET_RUNTIME_PM_OPS(svc_i3c_runtime_suspend, 1710 svc_i3c_runtime_resume, NULL) 1711 }; 1712 1713 static const struct of_device_id svc_i3c_master_of_match_tbl[] = { 1714 { .compatible = "silvaco,i3c-master" }, 1715 { /* sentinel */ }, 1716 }; 1717 MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl); 1718 1719 static struct platform_driver svc_i3c_master = { 1720 .probe = svc_i3c_master_probe, 1721 .remove_new = svc_i3c_master_remove, 1722 .driver = { 1723 .name = "silvaco-i3c-master", 1724 .of_match_table = svc_i3c_master_of_match_tbl, 1725 .pm = &svc_i3c_pm_ops, 1726 }, 1727 }; 1728 module_platform_driver(svc_i3c_master); 1729 1730 MODULE_AUTHOR("Conor Culhane <conor.culhane@silvaco.com>"); 1731 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>"); 1732 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver"); 1733 MODULE_LICENSE("GPL v2"); 1734