1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * 5 * Author: Vitor Soares <vitor.soares@synopsys.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/i3c/master.h> 14 #include <linux/interrupt.h> 15 #include <linux/ioport.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 24 #define DEVICE_CTRL 0x0 25 #define DEV_CTRL_ENABLE BIT(31) 26 #define DEV_CTRL_RESUME BIT(30) 27 #define DEV_CTRL_HOT_JOIN_NACK BIT(8) 28 #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7) 29 30 #define DEVICE_ADDR 0x4 31 #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31) 32 #define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16)) 33 34 #define HW_CAPABILITY 0x8 35 #define COMMAND_QUEUE_PORT 0xc 36 #define COMMAND_PORT_TOC BIT(30) 37 #define COMMAND_PORT_READ_TRANSFER BIT(28) 38 #define COMMAND_PORT_SDAP BIT(27) 39 #define COMMAND_PORT_ROC BIT(26) 40 #define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21)) 41 #define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16)) 42 #define COMMAND_PORT_CP BIT(15) 43 #define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7)) 44 #define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3)) 45 46 #define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16)) 47 #define COMMAND_PORT_ARG_DATA_LEN_MAX 65536 48 #define COMMAND_PORT_TRANSFER_ARG 0x01 49 50 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24)) 51 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16)) 52 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8)) 53 #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5) 54 #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4) 55 #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3) 56 #define COMMAND_PORT_SHORT_DATA_ARG 0x02 57 58 #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21)) 59 #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03 60 61 #define RESPONSE_QUEUE_PORT 0x10 62 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28) 63 #define RESPONSE_NO_ERROR 0 64 #define RESPONSE_ERROR_CRC 1 65 #define RESPONSE_ERROR_PARITY 2 66 #define RESPONSE_ERROR_FRAME 3 67 #define RESPONSE_ERROR_IBA_NACK 4 68 #define RESPONSE_ERROR_ADDRESS_NACK 5 69 #define RESPONSE_ERROR_OVER_UNDER_FLOW 6 70 #define RESPONSE_ERROR_TRANSF_ABORT 8 71 #define RESPONSE_ERROR_I2C_W_NACK_ERR 9 72 #define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24) 73 #define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0)) 74 75 #define RX_TX_DATA_PORT 0x14 76 #define IBI_QUEUE_STATUS 0x18 77 #define QUEUE_THLD_CTRL 0x1c 78 #define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8) 79 #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8) 80 81 #define DATA_BUFFER_THLD_CTRL 0x20 82 #define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8) 83 84 #define IBI_QUEUE_CTRL 0x24 85 #define IBI_MR_REQ_REJECT 0x2C 86 #define IBI_SIR_REQ_REJECT 0x30 87 #define IBI_REQ_REJECT_ALL GENMASK(31, 0) 88 89 #define RESET_CTRL 0x34 90 #define RESET_CTRL_IBI_QUEUE BIT(5) 91 #define RESET_CTRL_RX_FIFO BIT(4) 92 #define RESET_CTRL_TX_FIFO BIT(3) 93 #define RESET_CTRL_RESP_QUEUE BIT(2) 94 #define RESET_CTRL_CMD_QUEUE BIT(1) 95 #define RESET_CTRL_SOFT BIT(0) 96 97 #define SLV_EVENT_CTRL 0x38 98 #define INTR_STATUS 0x3c 99 #define INTR_STATUS_EN 0x40 100 #define INTR_SIGNAL_EN 0x44 101 #define INTR_FORCE 0x48 102 #define INTR_BUSOWNER_UPDATE_STAT BIT(13) 103 #define INTR_IBI_UPDATED_STAT BIT(12) 104 #define INTR_READ_REQ_RECV_STAT BIT(11) 105 #define INTR_DEFSLV_STAT BIT(10) 106 #define INTR_TRANSFER_ERR_STAT BIT(9) 107 #define INTR_DYN_ADDR_ASSGN_STAT BIT(8) 108 #define INTR_CCC_UPDATED_STAT BIT(6) 109 #define INTR_TRANSFER_ABORT_STAT BIT(5) 110 #define INTR_RESP_READY_STAT BIT(4) 111 #define INTR_CMD_QUEUE_READY_STAT BIT(3) 112 #define INTR_IBI_THLD_STAT BIT(2) 113 #define INTR_RX_THLD_STAT BIT(1) 114 #define INTR_TX_THLD_STAT BIT(0) 115 #define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \ 116 INTR_IBI_UPDATED_STAT | \ 117 INTR_READ_REQ_RECV_STAT | \ 118 INTR_DEFSLV_STAT | \ 119 INTR_TRANSFER_ERR_STAT | \ 120 INTR_DYN_ADDR_ASSGN_STAT | \ 121 INTR_CCC_UPDATED_STAT | \ 122 INTR_TRANSFER_ABORT_STAT | \ 123 INTR_RESP_READY_STAT | \ 124 INTR_CMD_QUEUE_READY_STAT | \ 125 INTR_IBI_THLD_STAT | \ 126 INTR_TX_THLD_STAT | \ 127 INTR_RX_THLD_STAT) 128 129 #define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \ 130 INTR_RESP_READY_STAT) 131 132 #define QUEUE_STATUS_LEVEL 0x4c 133 #define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24) 134 #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16) 135 #define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8) 136 #define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0)) 137 138 #define DATA_BUFFER_STATUS_LEVEL 0x50 139 #define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0)) 140 141 #define PRESENT_STATE 0x54 142 #define CCC_DEVICE_STATUS 0x58 143 #define DEVICE_ADDR_TABLE_POINTER 0x5c 144 #define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16) 145 #define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0)) 146 147 #define DEV_CHAR_TABLE_POINTER 0x60 148 #define VENDOR_SPECIFIC_REG_POINTER 0x6c 149 #define SLV_PID_VALUE 0x74 150 #define SLV_CHAR_CTRL 0x78 151 #define SLV_MAX_LEN 0x7c 152 #define MAX_READ_TURNAROUND 0x80 153 #define MAX_DATA_SPEED 0x84 154 #define SLV_DEBUG_STATUS 0x88 155 #define SLV_INTR_REQ 0x8c 156 #define DEVICE_CTRL_EXTENDED 0xb0 157 #define SCL_I3C_OD_TIMING 0xb4 158 #define SCL_I3C_PP_TIMING 0xb8 159 #define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 160 #define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0)) 161 #define SCL_I3C_TIMING_CNT_MIN 5 162 163 #define SCL_I2C_FM_TIMING 0xbc 164 #define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16)) 165 #define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 166 167 #define SCL_I2C_FMP_TIMING 0xc0 168 #define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 169 #define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 170 171 #define SCL_EXT_LCNT_TIMING 0xc8 172 #define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24)) 173 #define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16)) 174 #define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8)) 175 #define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0)) 176 177 #define SCL_EXT_TERMN_LCNT_TIMING 0xcc 178 #define BUS_FREE_TIMING 0xd4 179 #define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0)) 180 181 #define BUS_IDLE_TIMING 0xd8 182 #define I3C_VER_ID 0xe0 183 #define I3C_VER_TYPE 0xe4 184 #define EXTENDED_CAPABILITY 0xe8 185 #define SLAVE_CONFIG 0xec 186 187 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31) 188 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16)) 189 #define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0)) 190 #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2)) 191 192 #define MAX_DEVS 32 193 194 #define I3C_BUS_SDR1_SCL_RATE 8000000 195 #define I3C_BUS_SDR2_SCL_RATE 6000000 196 #define I3C_BUS_SDR3_SCL_RATE 4000000 197 #define I3C_BUS_SDR4_SCL_RATE 2000000 198 #define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300 199 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500 200 #define I3C_BUS_THIGH_MAX_NS 41 201 202 #define XFER_TIMEOUT (msecs_to_jiffies(1000)) 203 204 struct dw_i3c_master_caps { 205 u8 cmdfifodepth; 206 u8 datafifodepth; 207 }; 208 209 struct dw_i3c_cmd { 210 u32 cmd_lo; 211 u32 cmd_hi; 212 u16 tx_len; 213 const void *tx_buf; 214 u16 rx_len; 215 void *rx_buf; 216 u8 error; 217 }; 218 219 struct dw_i3c_xfer { 220 struct list_head node; 221 struct completion comp; 222 int ret; 223 unsigned int ncmds; 224 struct dw_i3c_cmd cmds[0]; 225 }; 226 227 struct dw_i3c_master { 228 struct i3c_master_controller base; 229 u16 maxdevs; 230 u16 datstartaddr; 231 u32 free_pos; 232 struct { 233 struct list_head list; 234 struct dw_i3c_xfer *cur; 235 spinlock_t lock; 236 } xferqueue; 237 struct dw_i3c_master_caps caps; 238 void __iomem *regs; 239 struct reset_control *core_rst; 240 struct clk *core_clk; 241 char version[5]; 242 char type[5]; 243 u8 addrs[MAX_DEVS]; 244 }; 245 246 struct dw_i3c_i2c_dev_data { 247 u8 index; 248 }; 249 250 static u8 even_parity(u8 p) 251 { 252 p ^= p >> 4; 253 p &= 0xf; 254 255 return (0x9669 >> p) & 1; 256 } 257 258 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 259 const struct i3c_ccc_cmd *cmd) 260 { 261 if (cmd->ndests > 1) 262 return false; 263 264 switch (cmd->id) { 265 case I3C_CCC_ENEC(true): 266 case I3C_CCC_ENEC(false): 267 case I3C_CCC_DISEC(true): 268 case I3C_CCC_DISEC(false): 269 case I3C_CCC_ENTAS(0, true): 270 case I3C_CCC_ENTAS(0, false): 271 case I3C_CCC_RSTDAA(true): 272 case I3C_CCC_RSTDAA(false): 273 case I3C_CCC_ENTDAA: 274 case I3C_CCC_SETMWL(true): 275 case I3C_CCC_SETMWL(false): 276 case I3C_CCC_SETMRL(true): 277 case I3C_CCC_SETMRL(false): 278 case I3C_CCC_ENTHDR(0): 279 case I3C_CCC_SETDASA: 280 case I3C_CCC_SETNEWDA: 281 case I3C_CCC_GETMWL: 282 case I3C_CCC_GETMRL: 283 case I3C_CCC_GETPID: 284 case I3C_CCC_GETBCR: 285 case I3C_CCC_GETDCR: 286 case I3C_CCC_GETSTATUS: 287 case I3C_CCC_GETMXDS: 288 case I3C_CCC_GETHDRCAP: 289 return true; 290 default: 291 return false; 292 } 293 } 294 295 static inline struct dw_i3c_master * 296 to_dw_i3c_master(struct i3c_master_controller *master) 297 { 298 return container_of(master, struct dw_i3c_master, base); 299 } 300 301 static void dw_i3c_master_disable(struct dw_i3c_master *master) 302 { 303 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE, 304 master->regs + DEVICE_CTRL); 305 } 306 307 static void dw_i3c_master_enable(struct dw_i3c_master *master) 308 { 309 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE, 310 master->regs + DEVICE_CTRL); 311 } 312 313 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr) 314 { 315 int pos; 316 317 for (pos = 0; pos < master->maxdevs; pos++) { 318 if (addr == master->addrs[pos]) 319 return pos; 320 } 321 322 return -EINVAL; 323 } 324 325 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master) 326 { 327 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0))) 328 return -ENOSPC; 329 330 return ffs(master->free_pos) - 1; 331 } 332 333 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master, 334 const u8 *bytes, int nbytes) 335 { 336 writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4); 337 if (nbytes & 3) { 338 u32 tmp = 0; 339 340 memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3); 341 writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1); 342 } 343 } 344 345 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master, 346 u8 *bytes, int nbytes) 347 { 348 readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4); 349 if (nbytes & 3) { 350 u32 tmp; 351 352 readsl(master->regs + RX_TX_DATA_PORT, &tmp, 1); 353 memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3); 354 } 355 } 356 357 static struct dw_i3c_xfer * 358 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) 359 { 360 struct dw_i3c_xfer *xfer; 361 362 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL); 363 if (!xfer) 364 return NULL; 365 366 INIT_LIST_HEAD(&xfer->node); 367 xfer->ncmds = ncmds; 368 xfer->ret = -ETIMEDOUT; 369 370 return xfer; 371 } 372 373 static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer) 374 { 375 kfree(xfer); 376 } 377 378 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) 379 { 380 struct dw_i3c_xfer *xfer = master->xferqueue.cur; 381 unsigned int i; 382 u32 thld_ctrl; 383 384 if (!xfer) 385 return; 386 387 for (i = 0; i < xfer->ncmds; i++) { 388 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 389 390 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len); 391 } 392 393 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 394 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK; 395 thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds); 396 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 397 398 for (i = 0; i < xfer->ncmds; i++) { 399 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 400 401 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT); 402 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT); 403 } 404 } 405 406 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, 407 struct dw_i3c_xfer *xfer) 408 { 409 unsigned long flags; 410 411 init_completion(&xfer->comp); 412 spin_lock_irqsave(&master->xferqueue.lock, flags); 413 if (master->xferqueue.cur) { 414 list_add_tail(&xfer->node, &master->xferqueue.list); 415 } else { 416 master->xferqueue.cur = xfer; 417 dw_i3c_master_start_xfer_locked(master); 418 } 419 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 420 } 421 422 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, 423 struct dw_i3c_xfer *xfer) 424 { 425 if (master->xferqueue.cur == xfer) { 426 u32 status; 427 428 master->xferqueue.cur = NULL; 429 430 writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | 431 RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE, 432 master->regs + RESET_CTRL); 433 434 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status, 435 !status, 10, 1000000); 436 } else { 437 list_del_init(&xfer->node); 438 } 439 } 440 441 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, 442 struct dw_i3c_xfer *xfer) 443 { 444 unsigned long flags; 445 446 spin_lock_irqsave(&master->xferqueue.lock, flags); 447 dw_i3c_master_dequeue_xfer_locked(master, xfer); 448 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 449 } 450 451 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) 452 { 453 struct dw_i3c_xfer *xfer = master->xferqueue.cur; 454 int i, ret = 0; 455 u32 nresp; 456 457 if (!xfer) 458 return; 459 460 nresp = readl(master->regs + QUEUE_STATUS_LEVEL); 461 nresp = QUEUE_STATUS_LEVEL_RESP(nresp); 462 463 for (i = 0; i < nresp; i++) { 464 struct dw_i3c_cmd *cmd; 465 u32 resp; 466 467 resp = readl(master->regs + RESPONSE_QUEUE_PORT); 468 469 cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)]; 470 cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp); 471 cmd->error = RESPONSE_PORT_ERR_STATUS(resp); 472 if (cmd->rx_len && !cmd->error) 473 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf, 474 cmd->rx_len); 475 } 476 477 for (i = 0; i < nresp; i++) { 478 switch (xfer->cmds[i].error) { 479 case RESPONSE_NO_ERROR: 480 break; 481 case RESPONSE_ERROR_PARITY: 482 case RESPONSE_ERROR_IBA_NACK: 483 case RESPONSE_ERROR_TRANSF_ABORT: 484 case RESPONSE_ERROR_CRC: 485 case RESPONSE_ERROR_FRAME: 486 ret = -EIO; 487 break; 488 case RESPONSE_ERROR_OVER_UNDER_FLOW: 489 ret = -ENOSPC; 490 break; 491 case RESPONSE_ERROR_I2C_W_NACK_ERR: 492 case RESPONSE_ERROR_ADDRESS_NACK: 493 default: 494 ret = -EINVAL; 495 break; 496 } 497 } 498 499 xfer->ret = ret; 500 complete(&xfer->comp); 501 502 if (ret < 0) { 503 dw_i3c_master_dequeue_xfer_locked(master, xfer); 504 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME, 505 master->regs + DEVICE_CTRL); 506 } 507 508 xfer = list_first_entry_or_null(&master->xferqueue.list, 509 struct dw_i3c_xfer, 510 node); 511 if (xfer) 512 list_del_init(&xfer->node); 513 514 master->xferqueue.cur = xfer; 515 dw_i3c_master_start_xfer_locked(master); 516 } 517 518 static int dw_i3c_clk_cfg(struct dw_i3c_master *master) 519 { 520 unsigned long core_rate, core_period; 521 u32 scl_timing; 522 u8 hcnt, lcnt; 523 524 core_rate = clk_get_rate(master->core_clk); 525 if (!core_rate) 526 return -EINVAL; 527 528 core_period = DIV_ROUND_UP(1000000000, core_rate); 529 530 hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1; 531 if (hcnt < SCL_I3C_TIMING_CNT_MIN) 532 hcnt = SCL_I3C_TIMING_CNT_MIN; 533 534 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_TYP_I3C_SCL_RATE) - hcnt; 535 if (lcnt < SCL_I3C_TIMING_CNT_MIN) 536 lcnt = SCL_I3C_TIMING_CNT_MIN; 537 538 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); 539 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING); 540 541 if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT)) 542 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); 543 544 lcnt = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period); 545 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); 546 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); 547 548 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt; 549 scl_timing = SCL_EXT_LCNT_1(lcnt); 550 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt; 551 scl_timing |= SCL_EXT_LCNT_2(lcnt); 552 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt; 553 scl_timing |= SCL_EXT_LCNT_3(lcnt); 554 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt; 555 scl_timing |= SCL_EXT_LCNT_4(lcnt); 556 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING); 557 558 return 0; 559 } 560 561 static int dw_i2c_clk_cfg(struct dw_i3c_master *master) 562 { 563 unsigned long core_rate, core_period; 564 u16 hcnt, lcnt; 565 u32 scl_timing; 566 567 core_rate = clk_get_rate(master->core_clk); 568 if (!core_rate) 569 return -EINVAL; 570 571 core_period = DIV_ROUND_UP(1000000000, core_rate); 572 573 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period); 574 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_RATE) - lcnt; 575 scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) | 576 SCL_I2C_FMP_TIMING_LCNT(lcnt); 577 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING); 578 579 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period); 580 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt; 581 scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) | 582 SCL_I2C_FM_TIMING_LCNT(lcnt); 583 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING); 584 585 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); 586 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT, 587 master->regs + DEVICE_CTRL); 588 589 return 0; 590 } 591 592 static int dw_i3c_master_bus_init(struct i3c_master_controller *m) 593 { 594 struct dw_i3c_master *master = to_dw_i3c_master(m); 595 struct i3c_bus *bus = i3c_master_get_bus(m); 596 struct i3c_device_info info = { }; 597 u32 thld_ctrl; 598 int ret; 599 600 switch (bus->mode) { 601 case I3C_BUS_MODE_MIXED_FAST: 602 ret = dw_i2c_clk_cfg(master); 603 if (ret) 604 return ret; 605 /* fall through */ 606 case I3C_BUS_MODE_PURE: 607 ret = dw_i3c_clk_cfg(master); 608 if (ret) 609 return ret; 610 break; 611 default: 612 return -EINVAL; 613 } 614 615 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 616 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK; 617 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 618 619 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL); 620 thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF; 621 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); 622 623 writel(INTR_ALL, master->regs + INTR_STATUS); 624 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); 625 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); 626 627 ret = i3c_master_get_free_addr(m, 0); 628 if (ret < 0) 629 return ret; 630 631 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret), 632 master->regs + DEVICE_ADDR); 633 634 memset(&info, 0, sizeof(info)); 635 info.dyn_addr = ret; 636 637 ret = i3c_master_set_info(&master->base, &info); 638 if (ret) 639 return ret; 640 641 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT); 642 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); 643 644 /* For now don't support Hot-Join */ 645 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK, 646 master->regs + DEVICE_CTRL); 647 648 dw_i3c_master_enable(master); 649 650 return 0; 651 } 652 653 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m) 654 { 655 struct dw_i3c_master *master = to_dw_i3c_master(m); 656 657 dw_i3c_master_disable(master); 658 } 659 660 static int dw_i3c_ccc_set(struct dw_i3c_master *master, 661 struct i3c_ccc_cmd *ccc) 662 { 663 struct dw_i3c_xfer *xfer; 664 struct dw_i3c_cmd *cmd; 665 int ret, pos = 0; 666 667 if (ccc->id & I3C_CCC_DIRECT) { 668 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); 669 if (pos < 0) 670 return pos; 671 } 672 673 xfer = dw_i3c_master_alloc_xfer(master, 1); 674 if (!xfer) 675 return -ENOMEM; 676 677 cmd = xfer->cmds; 678 cmd->tx_buf = ccc->dests[0].payload.data; 679 cmd->tx_len = ccc->dests[0].payload.len; 680 681 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | 682 COMMAND_PORT_TRANSFER_ARG; 683 684 cmd->cmd_lo = COMMAND_PORT_CP | 685 COMMAND_PORT_DEV_INDEX(pos) | 686 COMMAND_PORT_CMD(ccc->id) | 687 COMMAND_PORT_TOC | 688 COMMAND_PORT_ROC; 689 690 dw_i3c_master_enqueue_xfer(master, xfer); 691 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 692 dw_i3c_master_dequeue_xfer(master, xfer); 693 694 ret = xfer->ret; 695 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) 696 ccc->err = I3C_ERROR_M2; 697 698 dw_i3c_master_free_xfer(xfer); 699 700 return ret; 701 } 702 703 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) 704 { 705 struct dw_i3c_xfer *xfer; 706 struct dw_i3c_cmd *cmd; 707 int ret, pos; 708 709 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); 710 if (pos < 0) 711 return pos; 712 713 xfer = dw_i3c_master_alloc_xfer(master, 1); 714 if (!xfer) 715 return -ENOMEM; 716 717 cmd = xfer->cmds; 718 cmd->rx_buf = ccc->dests[0].payload.data; 719 cmd->rx_len = ccc->dests[0].payload.len; 720 721 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | 722 COMMAND_PORT_TRANSFER_ARG; 723 724 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | 725 COMMAND_PORT_CP | 726 COMMAND_PORT_DEV_INDEX(pos) | 727 COMMAND_PORT_CMD(ccc->id) | 728 COMMAND_PORT_TOC | 729 COMMAND_PORT_ROC; 730 731 dw_i3c_master_enqueue_xfer(master, xfer); 732 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 733 dw_i3c_master_dequeue_xfer(master, xfer); 734 735 ret = xfer->ret; 736 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) 737 ccc->err = I3C_ERROR_M2; 738 dw_i3c_master_free_xfer(xfer); 739 740 return ret; 741 } 742 743 static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 744 struct i3c_ccc_cmd *ccc) 745 { 746 struct dw_i3c_master *master = to_dw_i3c_master(m); 747 int ret = 0; 748 749 if (ccc->id == I3C_CCC_ENTDAA) 750 return -EINVAL; 751 752 if (ccc->rnw) 753 ret = dw_i3c_ccc_get(master, ccc); 754 else 755 ret = dw_i3c_ccc_set(master, ccc); 756 757 return ret; 758 } 759 760 static int dw_i3c_master_daa(struct i3c_master_controller *m) 761 { 762 struct dw_i3c_master *master = to_dw_i3c_master(m); 763 struct dw_i3c_xfer *xfer; 764 struct dw_i3c_cmd *cmd; 765 u32 olddevs, newdevs; 766 u8 p, last_addr = 0; 767 int ret, pos; 768 769 olddevs = ~(master->free_pos); 770 771 /* Prepare DAT before launching DAA. */ 772 for (pos = 0; pos < master->maxdevs; pos++) { 773 if (olddevs & BIT(pos)) 774 continue; 775 776 ret = i3c_master_get_free_addr(m, last_addr + 1); 777 if (ret < 0) 778 return -ENOSPC; 779 780 master->addrs[pos] = ret; 781 p = even_parity(ret); 782 last_addr = ret; 783 ret |= (p << 7); 784 785 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret), 786 master->regs + 787 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 788 } 789 790 xfer = dw_i3c_master_alloc_xfer(master, 1); 791 if (!xfer) 792 return -ENOMEM; 793 794 pos = dw_i3c_master_get_free_pos(master); 795 cmd = &xfer->cmds[0]; 796 cmd->cmd_hi = 0x1; 797 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) | 798 COMMAND_PORT_DEV_INDEX(pos) | 799 COMMAND_PORT_CMD(I3C_CCC_ENTDAA) | 800 COMMAND_PORT_ADDR_ASSGN_CMD | 801 COMMAND_PORT_TOC | 802 COMMAND_PORT_ROC; 803 804 dw_i3c_master_enqueue_xfer(master, xfer); 805 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 806 dw_i3c_master_dequeue_xfer(master, xfer); 807 808 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0); 809 newdevs &= ~olddevs; 810 811 for (pos = 0; pos < master->maxdevs; pos++) { 812 if (newdevs & BIT(pos)) 813 i3c_master_add_i3c_dev_locked(m, master->addrs[pos]); 814 } 815 816 dw_i3c_master_free_xfer(xfer); 817 818 i3c_master_disec_locked(m, I3C_BROADCAST_ADDR, 819 I3C_CCC_EVENT_HJ | 820 I3C_CCC_EVENT_MR | 821 I3C_CCC_EVENT_SIR); 822 823 return 0; 824 } 825 826 static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev, 827 struct i3c_priv_xfer *i3c_xfers, 828 int i3c_nxfers) 829 { 830 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 831 struct i3c_master_controller *m = i3c_dev_get_master(dev); 832 struct dw_i3c_master *master = to_dw_i3c_master(m); 833 unsigned int nrxwords = 0, ntxwords = 0; 834 struct dw_i3c_xfer *xfer; 835 int i, ret = 0; 836 837 if (!i3c_nxfers) 838 return 0; 839 840 if (i3c_nxfers > master->caps.cmdfifodepth) 841 return -ENOTSUPP; 842 843 for (i = 0; i < i3c_nxfers; i++) { 844 if (i3c_xfers[i].rnw) 845 nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); 846 else 847 ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); 848 } 849 850 if (ntxwords > master->caps.datafifodepth || 851 nrxwords > master->caps.datafifodepth) 852 return -ENOTSUPP; 853 854 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers); 855 if (!xfer) 856 return -ENOMEM; 857 858 for (i = 0; i < i3c_nxfers; i++) { 859 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 860 861 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) | 862 COMMAND_PORT_TRANSFER_ARG; 863 864 if (i3c_xfers[i].rnw) { 865 cmd->rx_buf = i3c_xfers[i].data.in; 866 cmd->rx_len = i3c_xfers[i].len; 867 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | 868 COMMAND_PORT_SPEED(dev->info.max_read_ds); 869 870 } else { 871 cmd->tx_buf = i3c_xfers[i].data.out; 872 cmd->tx_len = i3c_xfers[i].len; 873 cmd->cmd_lo = 874 COMMAND_PORT_SPEED(dev->info.max_write_ds); 875 } 876 877 cmd->cmd_lo |= COMMAND_PORT_TID(i) | 878 COMMAND_PORT_DEV_INDEX(data->index) | 879 COMMAND_PORT_ROC; 880 881 if (i == (i3c_nxfers - 1)) 882 cmd->cmd_lo |= COMMAND_PORT_TOC; 883 } 884 885 dw_i3c_master_enqueue_xfer(master, xfer); 886 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 887 dw_i3c_master_dequeue_xfer(master, xfer); 888 889 ret = xfer->ret; 890 dw_i3c_master_free_xfer(xfer); 891 892 return ret; 893 } 894 895 static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, 896 u8 old_dyn_addr) 897 { 898 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 899 struct i3c_master_controller *m = i3c_dev_get_master(dev); 900 struct dw_i3c_master *master = to_dw_i3c_master(m); 901 902 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr), 903 master->regs + 904 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 905 906 master->addrs[data->index] = dev->info.dyn_addr; 907 908 return 0; 909 } 910 911 static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 912 { 913 struct i3c_master_controller *m = i3c_dev_get_master(dev); 914 struct dw_i3c_master *master = to_dw_i3c_master(m); 915 struct dw_i3c_i2c_dev_data *data; 916 int pos; 917 918 pos = dw_i3c_master_get_free_pos(master); 919 if (pos < 0) 920 return pos; 921 922 data = kzalloc(sizeof(*data), GFP_KERNEL); 923 if (!data) 924 return -ENOMEM; 925 926 data->index = pos; 927 master->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr; 928 master->free_pos &= ~BIT(pos); 929 i3c_dev_set_master_data(dev, data); 930 931 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->addrs[pos]), 932 master->regs + 933 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 934 935 return 0; 936 } 937 938 static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 939 { 940 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 941 struct i3c_master_controller *m = i3c_dev_get_master(dev); 942 struct dw_i3c_master *master = to_dw_i3c_master(m); 943 944 writel(0, 945 master->regs + 946 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 947 948 i3c_dev_set_master_data(dev, NULL); 949 master->addrs[data->index] = 0; 950 master->free_pos |= BIT(data->index); 951 kfree(data); 952 } 953 954 static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 955 const struct i2c_msg *i2c_xfers, 956 int i2c_nxfers) 957 { 958 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 959 struct i3c_master_controller *m = i2c_dev_get_master(dev); 960 struct dw_i3c_master *master = to_dw_i3c_master(m); 961 unsigned int nrxwords = 0, ntxwords = 0; 962 struct dw_i3c_xfer *xfer; 963 int i, ret = 0; 964 965 if (!i2c_nxfers) 966 return 0; 967 968 if (i2c_nxfers > master->caps.cmdfifodepth) 969 return -ENOTSUPP; 970 971 for (i = 0; i < i2c_nxfers; i++) { 972 if (i2c_xfers[i].flags & I2C_M_RD) 973 nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); 974 else 975 ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); 976 } 977 978 if (ntxwords > master->caps.datafifodepth || 979 nrxwords > master->caps.datafifodepth) 980 return -ENOTSUPP; 981 982 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers); 983 if (!xfer) 984 return -ENOMEM; 985 986 for (i = 0; i < i2c_nxfers; i++) { 987 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 988 989 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) | 990 COMMAND_PORT_TRANSFER_ARG; 991 992 cmd->cmd_lo = COMMAND_PORT_TID(i) | 993 COMMAND_PORT_DEV_INDEX(data->index) | 994 COMMAND_PORT_ROC; 995 996 if (i2c_xfers[i].flags & I2C_M_RD) { 997 cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER; 998 cmd->rx_buf = i2c_xfers[i].buf; 999 cmd->rx_len = i2c_xfers[i].len; 1000 } else { 1001 cmd->tx_buf = i2c_xfers[i].buf; 1002 cmd->tx_len = i2c_xfers[i].len; 1003 } 1004 1005 if (i == (i2c_nxfers - 1)) 1006 cmd->cmd_lo |= COMMAND_PORT_TOC; 1007 } 1008 1009 dw_i3c_master_enqueue_xfer(master, xfer); 1010 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 1011 dw_i3c_master_dequeue_xfer(master, xfer); 1012 1013 ret = xfer->ret; 1014 dw_i3c_master_free_xfer(xfer); 1015 1016 return ret; 1017 } 1018 1019 static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 1020 { 1021 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1022 struct dw_i3c_master *master = to_dw_i3c_master(m); 1023 struct dw_i3c_i2c_dev_data *data; 1024 int pos; 1025 1026 pos = dw_i3c_master_get_free_pos(master); 1027 if (pos < 0) 1028 return pos; 1029 1030 data = kzalloc(sizeof(*data), GFP_KERNEL); 1031 if (!data) 1032 return -ENOMEM; 1033 1034 data->index = pos; 1035 master->addrs[pos] = dev->boardinfo->base.addr; 1036 master->free_pos &= ~BIT(pos); 1037 i2c_dev_set_master_data(dev, data); 1038 1039 writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV | 1040 DEV_ADDR_TABLE_STATIC_ADDR(dev->boardinfo->base.addr), 1041 master->regs + 1042 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1043 1044 return 0; 1045 } 1046 1047 static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 1048 { 1049 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1050 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1051 struct dw_i3c_master *master = to_dw_i3c_master(m); 1052 1053 writel(0, 1054 master->regs + 1055 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1056 1057 i2c_dev_set_master_data(dev, NULL); 1058 master->addrs[data->index] = 0; 1059 master->free_pos |= BIT(data->index); 1060 kfree(data); 1061 } 1062 1063 static u32 dw_i3c_master_i2c_funcs(struct i3c_master_controller *m) 1064 { 1065 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1066 } 1067 1068 static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id) 1069 { 1070 struct dw_i3c_master *master = dev_id; 1071 u32 status; 1072 1073 status = readl(master->regs + INTR_STATUS); 1074 1075 if (!(status & readl(master->regs + INTR_STATUS_EN))) { 1076 writel(INTR_ALL, master->regs + INTR_STATUS); 1077 return IRQ_NONE; 1078 } 1079 1080 spin_lock(&master->xferqueue.lock); 1081 dw_i3c_master_end_xfer_locked(master, status); 1082 if (status & INTR_TRANSFER_ERR_STAT) 1083 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); 1084 spin_unlock(&master->xferqueue.lock); 1085 1086 return IRQ_HANDLED; 1087 } 1088 1089 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = { 1090 .bus_init = dw_i3c_master_bus_init, 1091 .bus_cleanup = dw_i3c_master_bus_cleanup, 1092 .attach_i3c_dev = dw_i3c_master_attach_i3c_dev, 1093 .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev, 1094 .detach_i3c_dev = dw_i3c_master_detach_i3c_dev, 1095 .do_daa = dw_i3c_master_daa, 1096 .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd, 1097 .send_ccc_cmd = dw_i3c_master_send_ccc_cmd, 1098 .priv_xfers = dw_i3c_master_priv_xfers, 1099 .attach_i2c_dev = dw_i3c_master_attach_i2c_dev, 1100 .detach_i2c_dev = dw_i3c_master_detach_i2c_dev, 1101 .i2c_xfers = dw_i3c_master_i2c_xfers, 1102 .i2c_funcs = dw_i3c_master_i2c_funcs, 1103 }; 1104 1105 static int dw_i3c_probe(struct platform_device *pdev) 1106 { 1107 struct dw_i3c_master *master; 1108 struct resource *res; 1109 int ret, irq; 1110 1111 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1112 if (!master) 1113 return -ENOMEM; 1114 1115 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1116 master->regs = devm_ioremap_resource(&pdev->dev, res); 1117 if (IS_ERR(master->regs)) 1118 return PTR_ERR(master->regs); 1119 1120 master->core_clk = devm_clk_get(&pdev->dev, NULL); 1121 if (IS_ERR(master->core_clk)) 1122 return PTR_ERR(master->core_clk); 1123 1124 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, 1125 "core_rst"); 1126 if (IS_ERR(master->core_rst)) 1127 return PTR_ERR(master->core_rst); 1128 1129 ret = clk_prepare_enable(master->core_clk); 1130 if (ret) 1131 goto err_disable_core_clk; 1132 1133 reset_control_deassert(master->core_rst); 1134 1135 spin_lock_init(&master->xferqueue.lock); 1136 INIT_LIST_HEAD(&master->xferqueue.list); 1137 1138 writel(INTR_ALL, master->regs + INTR_STATUS); 1139 irq = platform_get_irq(pdev, 0); 1140 ret = devm_request_irq(&pdev->dev, irq, 1141 dw_i3c_master_irq_handler, 0, 1142 dev_name(&pdev->dev), master); 1143 if (ret) 1144 goto err_assert_rst; 1145 1146 platform_set_drvdata(pdev, master); 1147 1148 /* Information regarding the FIFOs/QUEUEs depth */ 1149 ret = readl(master->regs + QUEUE_STATUS_LEVEL); 1150 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret); 1151 1152 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL); 1153 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret); 1154 1155 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER); 1156 master->datstartaddr = ret; 1157 master->maxdevs = ret >> 16; 1158 master->free_pos = GENMASK(master->maxdevs - 1, 0); 1159 1160 ret = i3c_master_register(&master->base, &pdev->dev, 1161 &dw_mipi_i3c_ops, false); 1162 if (ret) 1163 goto err_assert_rst; 1164 1165 return 0; 1166 1167 err_assert_rst: 1168 reset_control_assert(master->core_rst); 1169 1170 err_disable_core_clk: 1171 clk_disable_unprepare(master->core_clk); 1172 1173 return ret; 1174 } 1175 1176 static int dw_i3c_remove(struct platform_device *pdev) 1177 { 1178 struct dw_i3c_master *master = platform_get_drvdata(pdev); 1179 int ret; 1180 1181 ret = i3c_master_unregister(&master->base); 1182 if (ret) 1183 return ret; 1184 1185 reset_control_assert(master->core_rst); 1186 1187 clk_disable_unprepare(master->core_clk); 1188 1189 return 0; 1190 } 1191 1192 static const struct of_device_id dw_i3c_master_of_match[] = { 1193 { .compatible = "snps,dw-i3c-master-1.00a", }, 1194 {}, 1195 }; 1196 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); 1197 1198 static struct platform_driver dw_i3c_driver = { 1199 .probe = dw_i3c_probe, 1200 .remove = dw_i3c_remove, 1201 .driver = { 1202 .name = "dw-i3c-master", 1203 .of_match_table = of_match_ptr(dw_i3c_master_of_match), 1204 }, 1205 }; 1206 module_platform_driver(dw_i3c_driver); 1207 1208 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>"); 1209 MODULE_DESCRIPTION("DesignWare MIPI I3C driver"); 1210 MODULE_LICENSE("GPL v2"); 1211