1 /* 2 Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com> 3 4 National Semiconductor SCx200 ACCESS.bus support 5 Also supports the AMD CS5535 and AMD CS5536 6 7 Based on i2c-keywest.c which is: 8 Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org> 9 Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> 10 11 This program is free software; you can redistribute it and/or 12 modify it under the terms of the GNU General Public License as 13 published by the Free Software Foundation; either version 2 of the 14 License, or (at your option) any later version. 15 16 This program is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software 23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/kernel.h> 29 #include <linux/init.h> 30 #include <linux/i2c.h> 31 #include <linux/pci.h> 32 #include <linux/delay.h> 33 #include <linux/mutex.h> 34 #include <asm/io.h> 35 36 #include <linux/scx200.h> 37 38 #define NAME "scx200_acb" 39 40 MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>"); 41 MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver"); 42 MODULE_LICENSE("GPL"); 43 44 #define MAX_DEVICES 4 45 static int base[MAX_DEVICES] = { 0x820, 0x840 }; 46 module_param_array(base, int, NULL, 0); 47 MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers"); 48 49 #define POLL_TIMEOUT (HZ/5) 50 51 enum scx200_acb_state { 52 state_idle, 53 state_address, 54 state_command, 55 state_repeat_start, 56 state_quick, 57 state_read, 58 state_write, 59 }; 60 61 static const char *scx200_acb_state_name[] = { 62 "idle", 63 "address", 64 "command", 65 "repeat_start", 66 "quick", 67 "read", 68 "write", 69 }; 70 71 /* Physical interface */ 72 struct scx200_acb_iface { 73 struct scx200_acb_iface *next; 74 struct i2c_adapter adapter; 75 unsigned base; 76 struct mutex mutex; 77 78 /* State machine data */ 79 enum scx200_acb_state state; 80 int result; 81 u8 address_byte; 82 u8 command; 83 u8 *ptr; 84 char needs_reset; 85 unsigned len; 86 87 /* PCI device info */ 88 struct pci_dev *pdev; 89 int bar; 90 }; 91 92 /* Register Definitions */ 93 #define ACBSDA (iface->base + 0) 94 #define ACBST (iface->base + 1) 95 #define ACBST_SDAST 0x40 /* SDA Status */ 96 #define ACBST_BER 0x20 97 #define ACBST_NEGACK 0x10 /* Negative Acknowledge */ 98 #define ACBST_STASTR 0x08 /* Stall After Start */ 99 #define ACBST_MASTER 0x02 100 #define ACBCST (iface->base + 2) 101 #define ACBCST_BB 0x02 102 #define ACBCTL1 (iface->base + 3) 103 #define ACBCTL1_STASTRE 0x80 104 #define ACBCTL1_NMINTE 0x40 105 #define ACBCTL1_ACK 0x10 106 #define ACBCTL1_STOP 0x02 107 #define ACBCTL1_START 0x01 108 #define ACBADDR (iface->base + 4) 109 #define ACBCTL2 (iface->base + 5) 110 #define ACBCTL2_ENABLE 0x01 111 112 /************************************************************************/ 113 114 static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status) 115 { 116 const char *errmsg; 117 118 dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n", 119 scx200_acb_state_name[iface->state], status); 120 121 if (status & ACBST_BER) { 122 errmsg = "bus error"; 123 goto error; 124 } 125 if (!(status & ACBST_MASTER)) { 126 errmsg = "not master"; 127 goto error; 128 } 129 if (status & ACBST_NEGACK) { 130 dev_dbg(&iface->adapter.dev, "negative ack in state %s\n", 131 scx200_acb_state_name[iface->state]); 132 133 iface->state = state_idle; 134 iface->result = -ENXIO; 135 136 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); 137 outb(ACBST_STASTR | ACBST_NEGACK, ACBST); 138 139 /* Reset the status register */ 140 outb(0, ACBST); 141 return; 142 } 143 144 switch (iface->state) { 145 case state_idle: 146 dev_warn(&iface->adapter.dev, "interrupt in idle state\n"); 147 break; 148 149 case state_address: 150 /* Do a pointer write first */ 151 outb(iface->address_byte & ~1, ACBSDA); 152 153 iface->state = state_command; 154 break; 155 156 case state_command: 157 outb(iface->command, ACBSDA); 158 159 if (iface->address_byte & 1) 160 iface->state = state_repeat_start; 161 else 162 iface->state = state_write; 163 break; 164 165 case state_repeat_start: 166 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1); 167 /* fallthrough */ 168 169 case state_quick: 170 if (iface->address_byte & 1) { 171 if (iface->len == 1) 172 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1); 173 else 174 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1); 175 outb(iface->address_byte, ACBSDA); 176 177 iface->state = state_read; 178 } else { 179 outb(iface->address_byte, ACBSDA); 180 181 iface->state = state_write; 182 } 183 break; 184 185 case state_read: 186 /* Set ACK if _next_ byte will be the last one */ 187 if (iface->len == 2) 188 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1); 189 else 190 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1); 191 192 if (iface->len == 1) { 193 iface->result = 0; 194 iface->state = state_idle; 195 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); 196 } 197 198 *iface->ptr++ = inb(ACBSDA); 199 --iface->len; 200 201 break; 202 203 case state_write: 204 if (iface->len == 0) { 205 iface->result = 0; 206 iface->state = state_idle; 207 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); 208 break; 209 } 210 211 outb(*iface->ptr++, ACBSDA); 212 --iface->len; 213 214 break; 215 } 216 217 return; 218 219 error: 220 dev_err(&iface->adapter.dev, 221 "%s in state %s (addr=0x%02x, len=%d, status=0x%02x)\n", errmsg, 222 scx200_acb_state_name[iface->state], iface->address_byte, 223 iface->len, status); 224 225 iface->state = state_idle; 226 iface->result = -EIO; 227 iface->needs_reset = 1; 228 } 229 230 static void scx200_acb_poll(struct scx200_acb_iface *iface) 231 { 232 u8 status; 233 unsigned long timeout; 234 235 timeout = jiffies + POLL_TIMEOUT; 236 while (1) { 237 status = inb(ACBST); 238 239 /* Reset the status register to avoid the hang */ 240 outb(0, ACBST); 241 242 if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) { 243 scx200_acb_machine(iface, status); 244 return; 245 } 246 if (time_after(jiffies, timeout)) 247 break; 248 cpu_relax(); 249 cond_resched(); 250 } 251 252 dev_err(&iface->adapter.dev, "timeout in state %s\n", 253 scx200_acb_state_name[iface->state]); 254 255 iface->state = state_idle; 256 iface->result = -EIO; 257 iface->needs_reset = 1; 258 } 259 260 static void scx200_acb_reset(struct scx200_acb_iface *iface) 261 { 262 /* Disable the ACCESS.bus device and Configure the SCL 263 frequency: 16 clock cycles */ 264 outb(0x70, ACBCTL2); 265 /* Polling mode */ 266 outb(0, ACBCTL1); 267 /* Disable slave address */ 268 outb(0, ACBADDR); 269 /* Enable the ACCESS.bus device */ 270 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); 271 /* Free STALL after START */ 272 outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1); 273 /* Send a STOP */ 274 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); 275 /* Clear BER, NEGACK and STASTR bits */ 276 outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST); 277 /* Clear BB bit */ 278 outb(inb(ACBCST) | ACBCST_BB, ACBCST); 279 } 280 281 static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter, 282 u16 address, unsigned short flags, 283 char rw, u8 command, int size, 284 union i2c_smbus_data *data) 285 { 286 struct scx200_acb_iface *iface = i2c_get_adapdata(adapter); 287 int len; 288 u8 *buffer; 289 u16 cur_word; 290 int rc; 291 292 switch (size) { 293 case I2C_SMBUS_QUICK: 294 len = 0; 295 buffer = NULL; 296 break; 297 298 case I2C_SMBUS_BYTE: 299 len = 1; 300 buffer = rw ? &data->byte : &command; 301 break; 302 303 case I2C_SMBUS_BYTE_DATA: 304 len = 1; 305 buffer = &data->byte; 306 break; 307 308 case I2C_SMBUS_WORD_DATA: 309 len = 2; 310 cur_word = cpu_to_le16(data->word); 311 buffer = (u8 *)&cur_word; 312 break; 313 314 case I2C_SMBUS_I2C_BLOCK_DATA: 315 len = data->block[0]; 316 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 317 return -EINVAL; 318 buffer = &data->block[1]; 319 break; 320 321 default: 322 return -EINVAL; 323 } 324 325 dev_dbg(&adapter->dev, 326 "size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n", 327 size, address, command, len, rw); 328 329 if (!len && rw == I2C_SMBUS_READ) { 330 dev_dbg(&adapter->dev, "zero length read\n"); 331 return -EINVAL; 332 } 333 334 mutex_lock(&iface->mutex); 335 336 iface->address_byte = (address << 1) | rw; 337 iface->command = command; 338 iface->ptr = buffer; 339 iface->len = len; 340 iface->result = -EINVAL; 341 iface->needs_reset = 0; 342 343 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1); 344 345 if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE) 346 iface->state = state_quick; 347 else 348 iface->state = state_address; 349 350 while (iface->state != state_idle) 351 scx200_acb_poll(iface); 352 353 if (iface->needs_reset) 354 scx200_acb_reset(iface); 355 356 rc = iface->result; 357 358 mutex_unlock(&iface->mutex); 359 360 if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ) 361 data->word = le16_to_cpu(cur_word); 362 363 #ifdef DEBUG 364 dev_dbg(&adapter->dev, "transfer done, result: %d", rc); 365 if (buffer) { 366 int i; 367 printk(" data:"); 368 for (i = 0; i < len; ++i) 369 printk(" %02x", buffer[i]); 370 } 371 printk("\n"); 372 #endif 373 374 return rc; 375 } 376 377 static u32 scx200_acb_func(struct i2c_adapter *adapter) 378 { 379 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 380 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 381 I2C_FUNC_SMBUS_I2C_BLOCK; 382 } 383 384 /* For now, we only handle combined mode (smbus) */ 385 static const struct i2c_algorithm scx200_acb_algorithm = { 386 .smbus_xfer = scx200_acb_smbus_xfer, 387 .functionality = scx200_acb_func, 388 }; 389 390 static struct scx200_acb_iface *scx200_acb_list; 391 static DEFINE_MUTEX(scx200_acb_list_mutex); 392 393 static __init int scx200_acb_probe(struct scx200_acb_iface *iface) 394 { 395 u8 val; 396 397 /* Disable the ACCESS.bus device and Configure the SCL 398 frequency: 16 clock cycles */ 399 outb(0x70, ACBCTL2); 400 401 if (inb(ACBCTL2) != 0x70) { 402 pr_debug(NAME ": ACBCTL2 readback failed\n"); 403 return -ENXIO; 404 } 405 406 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1); 407 408 val = inb(ACBCTL1); 409 if (val) { 410 pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n", 411 val); 412 return -ENXIO; 413 } 414 415 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); 416 417 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1); 418 419 val = inb(ACBCTL1); 420 if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) { 421 pr_debug(NAME ": enabled, but NMINTE won't be set, " 422 "ACBCTL1=0x%02x\n", val); 423 return -ENXIO; 424 } 425 426 return 0; 427 } 428 429 static __init struct scx200_acb_iface *scx200_create_iface(const char *text, 430 struct device *dev, int index) 431 { 432 struct scx200_acb_iface *iface; 433 struct i2c_adapter *adapter; 434 435 iface = kzalloc(sizeof(*iface), GFP_KERNEL); 436 if (!iface) { 437 printk(KERN_ERR NAME ": can't allocate memory\n"); 438 return NULL; 439 } 440 441 adapter = &iface->adapter; 442 i2c_set_adapdata(adapter, iface); 443 snprintf(adapter->name, sizeof(adapter->name), "%s ACB%d", text, index); 444 adapter->owner = THIS_MODULE; 445 adapter->algo = &scx200_acb_algorithm; 446 adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 447 adapter->dev.parent = dev; 448 449 mutex_init(&iface->mutex); 450 451 return iface; 452 } 453 454 static int __init scx200_acb_create(struct scx200_acb_iface *iface) 455 { 456 struct i2c_adapter *adapter; 457 int rc; 458 459 adapter = &iface->adapter; 460 461 rc = scx200_acb_probe(iface); 462 if (rc) { 463 printk(KERN_WARNING NAME ": probe failed\n"); 464 return rc; 465 } 466 467 scx200_acb_reset(iface); 468 469 if (i2c_add_adapter(adapter) < 0) { 470 printk(KERN_ERR NAME ": failed to register\n"); 471 return -ENODEV; 472 } 473 474 mutex_lock(&scx200_acb_list_mutex); 475 iface->next = scx200_acb_list; 476 scx200_acb_list = iface; 477 mutex_unlock(&scx200_acb_list_mutex); 478 479 return 0; 480 } 481 482 static __init int scx200_create_pci(const char *text, struct pci_dev *pdev, 483 int bar) 484 { 485 struct scx200_acb_iface *iface; 486 int rc; 487 488 iface = scx200_create_iface(text, &pdev->dev, 0); 489 490 if (iface == NULL) 491 return -ENOMEM; 492 493 iface->pdev = pdev; 494 iface->bar = bar; 495 496 rc = pci_enable_device_io(iface->pdev); 497 if (rc) 498 goto errout_free; 499 500 rc = pci_request_region(iface->pdev, iface->bar, iface->adapter.name); 501 if (rc) { 502 printk(KERN_ERR NAME ": can't allocate PCI BAR %d\n", 503 iface->bar); 504 goto errout_free; 505 } 506 507 iface->base = pci_resource_start(iface->pdev, iface->bar); 508 rc = scx200_acb_create(iface); 509 510 if (rc == 0) 511 return 0; 512 513 pci_release_region(iface->pdev, iface->bar); 514 pci_dev_put(iface->pdev); 515 errout_free: 516 kfree(iface); 517 return rc; 518 } 519 520 static int __init scx200_create_isa(const char *text, unsigned long base, 521 int index) 522 { 523 struct scx200_acb_iface *iface; 524 int rc; 525 526 iface = scx200_create_iface(text, NULL, index); 527 528 if (iface == NULL) 529 return -ENOMEM; 530 531 if (!request_region(base, 8, iface->adapter.name)) { 532 printk(KERN_ERR NAME ": can't allocate io 0x%lx-0x%lx\n", 533 base, base + 8 - 1); 534 rc = -EBUSY; 535 goto errout_free; 536 } 537 538 iface->base = base; 539 rc = scx200_acb_create(iface); 540 541 if (rc == 0) 542 return 0; 543 544 release_region(base, 8); 545 errout_free: 546 kfree(iface); 547 return rc; 548 } 549 550 /* Driver data is an index into the scx200_data array that indicates 551 * the name and the BAR where the I/O address resource is located. ISA 552 * devices are flagged with a bar value of -1 */ 553 554 static struct pci_device_id scx200_pci[] = { 555 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE), 556 .driver_data = 0 }, 557 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE), 558 .driver_data = 0 }, 559 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA), 560 .driver_data = 1 }, 561 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA), 562 .driver_data = 2 } 563 }; 564 565 static struct { 566 const char *name; 567 int bar; 568 } scx200_data[] = { 569 { "SCx200", -1 }, 570 { "CS5535", 0 }, 571 { "CS5536", 0 } 572 }; 573 574 static __init int scx200_scan_pci(void) 575 { 576 int data, dev; 577 int rc = -ENODEV; 578 struct pci_dev *pdev; 579 580 for(dev = 0; dev < ARRAY_SIZE(scx200_pci); dev++) { 581 pdev = pci_get_device(scx200_pci[dev].vendor, 582 scx200_pci[dev].device, NULL); 583 584 if (pdev == NULL) 585 continue; 586 587 data = scx200_pci[dev].driver_data; 588 589 /* if .bar is greater or equal to zero, this is a 590 * PCI device - otherwise, we assume 591 that the ports are ISA based 592 */ 593 594 if (scx200_data[data].bar >= 0) 595 rc = scx200_create_pci(scx200_data[data].name, pdev, 596 scx200_data[data].bar); 597 else { 598 int i; 599 600 pci_dev_put(pdev); 601 for (i = 0; i < MAX_DEVICES; ++i) { 602 if (base[i] == 0) 603 continue; 604 605 rc = scx200_create_isa(scx200_data[data].name, 606 base[i], 607 i); 608 } 609 } 610 611 break; 612 } 613 614 return rc; 615 } 616 617 static int __init scx200_acb_init(void) 618 { 619 int rc; 620 621 pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n"); 622 623 rc = scx200_scan_pci(); 624 625 /* If at least one bus was created, init must succeed */ 626 if (scx200_acb_list) 627 return 0; 628 return rc; 629 } 630 631 static void __exit scx200_acb_cleanup(void) 632 { 633 struct scx200_acb_iface *iface; 634 635 mutex_lock(&scx200_acb_list_mutex); 636 while ((iface = scx200_acb_list) != NULL) { 637 scx200_acb_list = iface->next; 638 mutex_unlock(&scx200_acb_list_mutex); 639 640 i2c_del_adapter(&iface->adapter); 641 642 if (iface->pdev) { 643 pci_release_region(iface->pdev, iface->bar); 644 pci_dev_put(iface->pdev); 645 } 646 else 647 release_region(iface->base, 8); 648 649 kfree(iface); 650 mutex_lock(&scx200_acb_list_mutex); 651 } 652 mutex_unlock(&scx200_acb_list_mutex); 653 } 654 655 module_init(scx200_acb_init); 656 module_exit(scx200_acb_cleanup); 657