1 /* 2 * Copyright (c) 2003-2015 Broadcom Corporation 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/completion.h> 11 #include <linux/i2c.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 19 #define XLP9XX_I2C_DIV 0x0 20 #define XLP9XX_I2C_CTRL 0x1 21 #define XLP9XX_I2C_CMD 0x2 22 #define XLP9XX_I2C_STATUS 0x3 23 #define XLP9XX_I2C_MTXFIFO 0x4 24 #define XLP9XX_I2C_MRXFIFO 0x5 25 #define XLP9XX_I2C_MFIFOCTRL 0x6 26 #define XLP9XX_I2C_STXFIFO 0x7 27 #define XLP9XX_I2C_SRXFIFO 0x8 28 #define XLP9XX_I2C_SFIFOCTRL 0x9 29 #define XLP9XX_I2C_SLAVEADDR 0xA 30 #define XLP9XX_I2C_OWNADDR 0xB 31 #define XLP9XX_I2C_FIFOWCNT 0xC 32 #define XLP9XX_I2C_INTEN 0xD 33 #define XLP9XX_I2C_INTST 0xE 34 #define XLP9XX_I2C_WAITCNT 0xF 35 #define XLP9XX_I2C_TIMEOUT 0X10 36 #define XLP9XX_I2C_GENCALLADDR 0x11 37 38 #define XLP9XX_I2C_CMD_START BIT(7) 39 #define XLP9XX_I2C_CMD_STOP BIT(6) 40 #define XLP9XX_I2C_CMD_READ BIT(5) 41 #define XLP9XX_I2C_CMD_WRITE BIT(4) 42 #define XLP9XX_I2C_CMD_ACK BIT(3) 43 44 #define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16 45 #define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000 46 #define XLP9XX_I2C_CTRL_RST BIT(8) 47 #define XLP9XX_I2C_CTRL_EN BIT(6) 48 #define XLP9XX_I2C_CTRL_MASTER BIT(4) 49 #define XLP9XX_I2C_CTRL_FIFORD BIT(1) 50 #define XLP9XX_I2C_CTRL_ADDMODE BIT(0) 51 52 #define XLP9XX_I2C_INTEN_NACKADDR BIT(25) 53 #define XLP9XX_I2C_INTEN_SADDR BIT(13) 54 #define XLP9XX_I2C_INTEN_DATADONE BIT(12) 55 #define XLP9XX_I2C_INTEN_ARLOST BIT(11) 56 #define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4) 57 #define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3) 58 #define XLP9XX_I2C_INTEN_MFIFOHI BIT(2) 59 #define XLP9XX_I2C_INTEN_BUSERR BIT(0) 60 61 #define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8 62 #define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0 63 #define XLP9XX_I2C_MFIFOCTRL_RST BIT(16) 64 65 #define XLP9XX_I2C_SLAVEADDR_RW BIT(0) 66 #define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1 67 68 #define XLP9XX_I2C_IP_CLK_FREQ 133000000UL 69 #define XLP9XX_I2C_DEFAULT_FREQ 100000 70 #define XLP9XX_I2C_HIGH_FREQ 400000 71 #define XLP9XX_I2C_FIFO_SIZE 0x80U 72 #define XLP9XX_I2C_TIMEOUT_MS 1000 73 74 #define XLP9XX_I2C_FIFO_WCNT_MASK 0xff 75 #define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \ 76 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR) 77 78 struct xlp9xx_i2c_dev { 79 struct device *dev; 80 struct i2c_adapter adapter; 81 struct completion msg_complete; 82 int irq; 83 bool msg_read; 84 u32 __iomem *base; 85 u32 msg_buf_remaining; 86 u32 msg_len; 87 u32 clk_hz; 88 u32 msg_err; 89 u8 *msg_buf; 90 }; 91 92 static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv, 93 unsigned long reg, u32 val) 94 { 95 writel(val, priv->base + reg); 96 } 97 98 static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv, 99 unsigned long reg) 100 { 101 return readl(priv->base + reg); 102 } 103 104 static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) 105 { 106 u32 inten; 107 108 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask; 109 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten); 110 } 111 112 static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) 113 { 114 u32 inten; 115 116 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask; 117 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten); 118 } 119 120 static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv) 121 { 122 u32 thres; 123 124 thres = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE); 125 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL, 126 thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT); 127 } 128 129 static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv) 130 { 131 u32 len, i; 132 u8 *buf = priv->msg_buf; 133 134 len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE); 135 for (i = 0; i < len; i++) 136 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]); 137 priv->msg_buf_remaining -= len; 138 priv->msg_buf += len; 139 } 140 141 static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv) 142 { 143 u32 len, i; 144 u8 *buf = priv->msg_buf; 145 146 len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) & 147 XLP9XX_I2C_FIFO_WCNT_MASK; 148 len = min(priv->msg_buf_remaining, len); 149 for (i = 0; i < len; i++, buf++) 150 *buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO); 151 152 priv->msg_buf_remaining -= len; 153 priv->msg_buf = buf; 154 155 if (priv->msg_buf_remaining) 156 xlp9xx_i2c_update_rx_fifo_thres(priv); 157 } 158 159 static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id) 160 { 161 struct xlp9xx_i2c_dev *priv = dev_id; 162 u32 status; 163 164 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST); 165 if (status == 0) 166 return IRQ_NONE; 167 168 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status); 169 if (status & XLP9XX_I2C_STATUS_ERRMASK) { 170 priv->msg_err = status; 171 goto xfer_done; 172 } 173 174 /* SADDR ACK for SMBUS_QUICK */ 175 if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0)) 176 goto xfer_done; 177 178 if (!priv->msg_read) { 179 if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) { 180 /* TX FIFO got empty, fill it up again */ 181 if (priv->msg_buf_remaining) 182 xlp9xx_i2c_fill_tx_fifo(priv); 183 else 184 xlp9xx_i2c_mask_irq(priv, 185 XLP9XX_I2C_INTEN_MFIFOEMTY); 186 } 187 } else { 188 if (status & (XLP9XX_I2C_INTEN_DATADONE | 189 XLP9XX_I2C_INTEN_MFIFOHI)) { 190 /* data is in FIFO, read it */ 191 if (priv->msg_buf_remaining) 192 xlp9xx_i2c_drain_rx_fifo(priv); 193 } 194 } 195 196 /* Transfer complete */ 197 if (status & XLP9XX_I2C_INTEN_DATADONE) 198 goto xfer_done; 199 200 return IRQ_HANDLED; 201 202 xfer_done: 203 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 204 complete(&priv->msg_complete); 205 return IRQ_HANDLED; 206 } 207 208 static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv) 209 { 210 u32 prescale; 211 212 /* 213 * The controller uses 5 * SCL clock internally. 214 * So prescale value should be divided by 5. 215 */ 216 prescale = DIV_ROUND_UP(XLP9XX_I2C_IP_CLK_FREQ, priv->clk_hz); 217 prescale = ((prescale - 8) / 5) - 1; 218 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST); 219 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN | 220 XLP9XX_I2C_CTRL_MASTER); 221 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale); 222 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 223 224 return 0; 225 } 226 227 static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg, 228 int last_msg) 229 { 230 unsigned long timeleft; 231 u32 intr_mask, cmd, val; 232 233 priv->msg_buf = msg->buf; 234 priv->msg_buf_remaining = priv->msg_len = msg->len; 235 priv->msg_err = 0; 236 priv->msg_read = (msg->flags & I2C_M_RD); 237 reinit_completion(&priv->msg_complete); 238 239 /* Reset FIFO */ 240 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL, 241 XLP9XX_I2C_MFIFOCTRL_RST); 242 243 /* set FIFO threshold if reading */ 244 if (priv->msg_read) 245 xlp9xx_i2c_update_rx_fifo_thres(priv); 246 247 /* set slave addr */ 248 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR, 249 (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) | 250 (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0)); 251 252 /* Build control word for transfer */ 253 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL); 254 if (!priv->msg_read) 255 val &= ~XLP9XX_I2C_CTRL_FIFORD; 256 else 257 val |= XLP9XX_I2C_CTRL_FIFORD; /* read */ 258 259 if (msg->flags & I2C_M_TEN) 260 val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/ 261 else 262 val &= ~XLP9XX_I2C_CTRL_ADDMODE; 263 264 /* set data length to be transferred */ 265 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) | 266 (msg->len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT); 267 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val); 268 269 /* fill fifo during tx */ 270 if (!priv->msg_read) 271 xlp9xx_i2c_fill_tx_fifo(priv); 272 273 /* set interrupt mask */ 274 intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR | 275 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE); 276 277 if (priv->msg_read) { 278 intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI; 279 if (msg->len == 0) 280 intr_mask |= XLP9XX_I2C_INTEN_SADDR; 281 } else { 282 if (msg->len == 0) 283 intr_mask |= XLP9XX_I2C_INTEN_SADDR; 284 else 285 intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY; 286 } 287 xlp9xx_i2c_unmask_irq(priv, intr_mask); 288 289 /* set cmd reg */ 290 cmd = XLP9XX_I2C_CMD_START; 291 cmd |= (priv->msg_read ? XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE); 292 if (last_msg) 293 cmd |= XLP9XX_I2C_CMD_STOP; 294 295 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd); 296 297 timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS); 298 timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft); 299 300 if (priv->msg_err) { 301 dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err); 302 if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) 303 xlp9xx_i2c_init(priv); 304 return -EIO; 305 } 306 307 if (timeleft == 0) { 308 dev_dbg(priv->dev, "i2c transfer timed out!\n"); 309 xlp9xx_i2c_init(priv); 310 return -ETIMEDOUT; 311 } 312 313 return 0; 314 } 315 316 static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 317 int num) 318 { 319 int i, ret; 320 struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap); 321 322 for (i = 0; i < num; i++) { 323 ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1); 324 if (ret != 0) 325 return ret; 326 } 327 328 return num; 329 } 330 331 static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter) 332 { 333 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | 334 I2C_FUNC_10BIT_ADDR; 335 } 336 337 static const struct i2c_algorithm xlp9xx_i2c_algo = { 338 .master_xfer = xlp9xx_i2c_xfer, 339 .functionality = xlp9xx_i2c_functionality, 340 }; 341 342 static int xlp9xx_i2c_get_frequency(struct platform_device *pdev, 343 struct xlp9xx_i2c_dev *priv) 344 { 345 u32 freq; 346 int err; 347 348 err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq); 349 if (err) { 350 freq = XLP9XX_I2C_DEFAULT_FREQ; 351 dev_dbg(&pdev->dev, "using default frequency %u\n", freq); 352 } else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) { 353 dev_warn(&pdev->dev, "invalid frequency %u, using default\n", 354 freq); 355 freq = XLP9XX_I2C_DEFAULT_FREQ; 356 } 357 priv->clk_hz = freq; 358 359 return 0; 360 } 361 362 static int xlp9xx_i2c_probe(struct platform_device *pdev) 363 { 364 struct xlp9xx_i2c_dev *priv; 365 struct resource *res; 366 int err = 0; 367 368 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 369 if (!priv) 370 return -ENOMEM; 371 372 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 373 priv->base = devm_ioremap_resource(&pdev->dev, res); 374 if (IS_ERR(priv->base)) 375 return PTR_ERR(priv->base); 376 377 priv->irq = platform_get_irq(pdev, 0); 378 if (priv->irq <= 0) { 379 dev_err(&pdev->dev, "invalid irq!\n"); 380 return priv->irq; 381 } 382 383 xlp9xx_i2c_get_frequency(pdev, priv); 384 xlp9xx_i2c_init(priv); 385 386 err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0, 387 pdev->name, priv); 388 if (err) { 389 dev_err(&pdev->dev, "IRQ request failed!\n"); 390 return err; 391 } 392 393 init_completion(&priv->msg_complete); 394 priv->adapter.dev.parent = &pdev->dev; 395 priv->adapter.algo = &xlp9xx_i2c_algo; 396 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); 397 priv->adapter.dev.of_node = pdev->dev.of_node; 398 priv->dev = &pdev->dev; 399 400 snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c"); 401 i2c_set_adapdata(&priv->adapter, priv); 402 403 err = i2c_add_adapter(&priv->adapter); 404 if (err) 405 return err; 406 407 platform_set_drvdata(pdev, priv); 408 dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr); 409 410 return 0; 411 } 412 413 static int xlp9xx_i2c_remove(struct platform_device *pdev) 414 { 415 struct xlp9xx_i2c_dev *priv; 416 417 priv = platform_get_drvdata(pdev); 418 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 419 synchronize_irq(priv->irq); 420 i2c_del_adapter(&priv->adapter); 421 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0); 422 423 return 0; 424 } 425 426 static const struct of_device_id xlp9xx_i2c_of_match[] = { 427 { .compatible = "netlogic,xlp980-i2c", }, 428 { /* sentinel */ }, 429 }; 430 MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match); 431 432 #ifdef CONFIG_ACPI 433 static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = { 434 {"BRCM9007", 0}, 435 {} 436 }; 437 MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids); 438 #endif 439 440 static struct platform_driver xlp9xx_i2c_driver = { 441 .probe = xlp9xx_i2c_probe, 442 .remove = xlp9xx_i2c_remove, 443 .driver = { 444 .name = "xlp9xx-i2c", 445 .of_match_table = xlp9xx_i2c_of_match, 446 .acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids), 447 }, 448 }; 449 450 module_platform_driver(xlp9xx_i2c_driver); 451 452 MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>"); 453 MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver"); 454 MODULE_LICENSE("GPL v2"); 455