1 /* 2 * Copyright (c) 2003-2015 Broadcom Corporation 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/i2c.h> 13 #include <linux/i2c-smbus.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/delay.h> 21 22 #define XLP9XX_I2C_DIV 0x0 23 #define XLP9XX_I2C_CTRL 0x1 24 #define XLP9XX_I2C_CMD 0x2 25 #define XLP9XX_I2C_STATUS 0x3 26 #define XLP9XX_I2C_MTXFIFO 0x4 27 #define XLP9XX_I2C_MRXFIFO 0x5 28 #define XLP9XX_I2C_MFIFOCTRL 0x6 29 #define XLP9XX_I2C_STXFIFO 0x7 30 #define XLP9XX_I2C_SRXFIFO 0x8 31 #define XLP9XX_I2C_SFIFOCTRL 0x9 32 #define XLP9XX_I2C_SLAVEADDR 0xA 33 #define XLP9XX_I2C_OWNADDR 0xB 34 #define XLP9XX_I2C_FIFOWCNT 0xC 35 #define XLP9XX_I2C_INTEN 0xD 36 #define XLP9XX_I2C_INTST 0xE 37 #define XLP9XX_I2C_WAITCNT 0xF 38 #define XLP9XX_I2C_TIMEOUT 0X10 39 #define XLP9XX_I2C_GENCALLADDR 0x11 40 41 #define XLP9XX_I2C_STATUS_BUSY BIT(0) 42 43 #define XLP9XX_I2C_CMD_START BIT(7) 44 #define XLP9XX_I2C_CMD_STOP BIT(6) 45 #define XLP9XX_I2C_CMD_READ BIT(5) 46 #define XLP9XX_I2C_CMD_WRITE BIT(4) 47 #define XLP9XX_I2C_CMD_ACK BIT(3) 48 49 #define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16 50 #define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000 51 #define XLP9XX_I2C_CTRL_RST BIT(8) 52 #define XLP9XX_I2C_CTRL_EN BIT(6) 53 #define XLP9XX_I2C_CTRL_MASTER BIT(4) 54 #define XLP9XX_I2C_CTRL_FIFORD BIT(1) 55 #define XLP9XX_I2C_CTRL_ADDMODE BIT(0) 56 57 #define XLP9XX_I2C_INTEN_NACKADDR BIT(25) 58 #define XLP9XX_I2C_INTEN_SADDR BIT(13) 59 #define XLP9XX_I2C_INTEN_DATADONE BIT(12) 60 #define XLP9XX_I2C_INTEN_ARLOST BIT(11) 61 #define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4) 62 #define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3) 63 #define XLP9XX_I2C_INTEN_MFIFOHI BIT(2) 64 #define XLP9XX_I2C_INTEN_BUSERR BIT(0) 65 66 #define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8 67 #define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0 68 #define XLP9XX_I2C_MFIFOCTRL_RST BIT(16) 69 70 #define XLP9XX_I2C_SLAVEADDR_RW BIT(0) 71 #define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1 72 73 #define XLP9XX_I2C_IP_CLK_FREQ 133000000UL 74 #define XLP9XX_I2C_DEFAULT_FREQ 100000 75 #define XLP9XX_I2C_HIGH_FREQ 400000 76 #define XLP9XX_I2C_FIFO_SIZE 0x80U 77 #define XLP9XX_I2C_TIMEOUT_MS 1000 78 #define XLP9XX_I2C_BUSY_TIMEOUT 50 79 80 #define XLP9XX_I2C_FIFO_WCNT_MASK 0xff 81 #define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \ 82 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR) 83 84 struct xlp9xx_i2c_dev { 85 struct device *dev; 86 struct i2c_adapter adapter; 87 struct completion msg_complete; 88 struct i2c_smbus_alert_setup alert_data; 89 struct i2c_client *ara; 90 int irq; 91 bool msg_read; 92 bool len_recv; 93 bool client_pec; 94 u32 __iomem *base; 95 u32 msg_buf_remaining; 96 u32 msg_len; 97 u32 ip_clk_hz; 98 u32 clk_hz; 99 u32 msg_err; 100 u8 *msg_buf; 101 }; 102 103 static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv, 104 unsigned long reg, u32 val) 105 { 106 writel(val, priv->base + reg); 107 } 108 109 static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv, 110 unsigned long reg) 111 { 112 return readl(priv->base + reg); 113 } 114 115 static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) 116 { 117 u32 inten; 118 119 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask; 120 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten); 121 } 122 123 static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) 124 { 125 u32 inten; 126 127 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask; 128 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten); 129 } 130 131 static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv) 132 { 133 u32 thres; 134 135 if (priv->len_recv) 136 /* interrupt after the first read to examine 137 * the length byte before proceeding further 138 */ 139 thres = 1; 140 else if (priv->msg_buf_remaining > XLP9XX_I2C_FIFO_SIZE) 141 thres = XLP9XX_I2C_FIFO_SIZE; 142 else 143 thres = priv->msg_buf_remaining; 144 145 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL, 146 thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT); 147 } 148 149 static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv) 150 { 151 u32 len, i; 152 u8 *buf = priv->msg_buf; 153 154 len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE); 155 for (i = 0; i < len; i++) 156 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]); 157 priv->msg_buf_remaining -= len; 158 priv->msg_buf += len; 159 } 160 161 static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv) 162 { 163 u32 len, i, val; 164 u8 rlen, *buf = priv->msg_buf; 165 166 len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) & 167 XLP9XX_I2C_FIFO_WCNT_MASK; 168 if (!len) 169 return; 170 if (priv->len_recv) { 171 /* read length byte */ 172 rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO); 173 *buf++ = rlen; 174 len--; 175 176 if (priv->client_pec) 177 ++rlen; 178 /* update remaining bytes and message length */ 179 priv->msg_buf_remaining = rlen; 180 priv->msg_len = rlen + 1; 181 priv->len_recv = false; 182 183 /* Update transfer length to read only actual data */ 184 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL); 185 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) | 186 ((rlen + 1) << XLP9XX_I2C_CTRL_MCTLEN_SHIFT); 187 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val); 188 } else { 189 len = min(priv->msg_buf_remaining, len); 190 for (i = 0; i < len; i++, buf++) 191 *buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO); 192 193 priv->msg_buf_remaining -= len; 194 } 195 196 priv->msg_buf = buf; 197 198 if (priv->msg_buf_remaining) 199 xlp9xx_i2c_update_rx_fifo_thres(priv); 200 } 201 202 static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id) 203 { 204 struct xlp9xx_i2c_dev *priv = dev_id; 205 u32 status; 206 207 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST); 208 if (status == 0) 209 return IRQ_NONE; 210 211 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status); 212 if (status & XLP9XX_I2C_STATUS_ERRMASK) { 213 priv->msg_err = status; 214 goto xfer_done; 215 } 216 217 /* SADDR ACK for SMBUS_QUICK */ 218 if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0)) 219 goto xfer_done; 220 221 if (!priv->msg_read) { 222 if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) { 223 /* TX FIFO got empty, fill it up again */ 224 if (priv->msg_buf_remaining) 225 xlp9xx_i2c_fill_tx_fifo(priv); 226 else 227 xlp9xx_i2c_mask_irq(priv, 228 XLP9XX_I2C_INTEN_MFIFOEMTY); 229 } 230 } else { 231 if (status & (XLP9XX_I2C_INTEN_DATADONE | 232 XLP9XX_I2C_INTEN_MFIFOHI)) { 233 /* data is in FIFO, read it */ 234 if (priv->msg_buf_remaining) 235 xlp9xx_i2c_drain_rx_fifo(priv); 236 } 237 } 238 239 /* Transfer complete */ 240 if (status & XLP9XX_I2C_INTEN_DATADONE) 241 goto xfer_done; 242 243 return IRQ_HANDLED; 244 245 xfer_done: 246 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 247 complete(&priv->msg_complete); 248 return IRQ_HANDLED; 249 } 250 251 static int xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev *priv) 252 { 253 u32 status; 254 u32 busy_timeout = XLP9XX_I2C_BUSY_TIMEOUT; 255 256 while (busy_timeout) { 257 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_STATUS); 258 if ((status & XLP9XX_I2C_STATUS_BUSY) == 0) 259 break; 260 261 busy_timeout--; 262 usleep_range(1000, 1100); 263 } 264 265 if (!busy_timeout) 266 return -EIO; 267 268 return 0; 269 } 270 271 static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv) 272 { 273 u32 prescale; 274 275 /* 276 * The controller uses 5 * SCL clock internally. 277 * So prescale value should be divided by 5. 278 */ 279 prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz); 280 prescale = ((prescale - 8) / 5) - 1; 281 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST); 282 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN | 283 XLP9XX_I2C_CTRL_MASTER); 284 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale); 285 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 286 287 return 0; 288 } 289 290 static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg, 291 int last_msg) 292 { 293 unsigned long timeleft; 294 u32 intr_mask, cmd, val, len; 295 296 priv->msg_buf = msg->buf; 297 priv->msg_buf_remaining = priv->msg_len = msg->len; 298 priv->msg_err = 0; 299 priv->msg_read = (msg->flags & I2C_M_RD); 300 reinit_completion(&priv->msg_complete); 301 302 /* Reset FIFO */ 303 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL, 304 XLP9XX_I2C_MFIFOCTRL_RST); 305 306 /* set FIFO threshold if reading */ 307 if (priv->msg_read) 308 xlp9xx_i2c_update_rx_fifo_thres(priv); 309 310 /* set slave addr */ 311 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR, 312 (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) | 313 (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0)); 314 315 /* Build control word for transfer */ 316 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL); 317 if (!priv->msg_read) 318 val &= ~XLP9XX_I2C_CTRL_FIFORD; 319 else 320 val |= XLP9XX_I2C_CTRL_FIFORD; /* read */ 321 322 if (msg->flags & I2C_M_TEN) 323 val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/ 324 else 325 val &= ~XLP9XX_I2C_CTRL_ADDMODE; 326 327 priv->len_recv = msg->flags & I2C_M_RECV_LEN; 328 len = priv->len_recv ? XLP9XX_I2C_FIFO_SIZE : msg->len; 329 priv->client_pec = msg->flags & I2C_CLIENT_PEC; 330 331 /* set data length to be transferred */ 332 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) | 333 (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT); 334 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val); 335 336 /* fill fifo during tx */ 337 if (!priv->msg_read) 338 xlp9xx_i2c_fill_tx_fifo(priv); 339 340 /* set interrupt mask */ 341 intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR | 342 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE); 343 344 if (priv->msg_read) { 345 intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI; 346 if (msg->len == 0) 347 intr_mask |= XLP9XX_I2C_INTEN_SADDR; 348 } else { 349 if (msg->len == 0) 350 intr_mask |= XLP9XX_I2C_INTEN_SADDR; 351 else 352 intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY; 353 } 354 xlp9xx_i2c_unmask_irq(priv, intr_mask); 355 356 /* set cmd reg */ 357 cmd = XLP9XX_I2C_CMD_START; 358 if (msg->len) 359 cmd |= (priv->msg_read ? 360 XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE); 361 if (last_msg) 362 cmd |= XLP9XX_I2C_CMD_STOP; 363 364 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd); 365 366 timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS); 367 timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft); 368 369 if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) { 370 dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err); 371 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, XLP9XX_I2C_CMD_STOP); 372 return -EIO; 373 } else if (priv->msg_err & XLP9XX_I2C_INTEN_NACKADDR) { 374 return -ENXIO; 375 } 376 377 if (timeleft == 0) { 378 dev_dbg(priv->dev, "i2c transfer timed out!\n"); 379 xlp9xx_i2c_init(priv); 380 return -ETIMEDOUT; 381 } 382 383 /* update msg->len with actual received length */ 384 if (msg->flags & I2C_M_RECV_LEN) 385 msg->len = priv->msg_len; 386 return 0; 387 } 388 389 static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 390 int num) 391 { 392 int i, ret; 393 struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap); 394 395 ret = xlp9xx_i2c_check_bus_status(priv); 396 if (ret) { 397 xlp9xx_i2c_init(priv); 398 ret = xlp9xx_i2c_check_bus_status(priv); 399 if (ret) 400 return ret; 401 } 402 403 for (i = 0; i < num; i++) { 404 ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1); 405 if (ret != 0) 406 return ret; 407 } 408 409 return num; 410 } 411 412 static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter) 413 { 414 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA | 415 I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; 416 } 417 418 static const struct i2c_algorithm xlp9xx_i2c_algo = { 419 .master_xfer = xlp9xx_i2c_xfer, 420 .functionality = xlp9xx_i2c_functionality, 421 }; 422 423 static int xlp9xx_i2c_get_frequency(struct platform_device *pdev, 424 struct xlp9xx_i2c_dev *priv) 425 { 426 struct clk *clk; 427 u32 freq; 428 int err; 429 430 clk = devm_clk_get(&pdev->dev, NULL); 431 if (IS_ERR(clk)) { 432 priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ; 433 dev_dbg(&pdev->dev, "using default input frequency %u\n", 434 priv->ip_clk_hz); 435 } else { 436 priv->ip_clk_hz = clk_get_rate(clk); 437 } 438 439 err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq); 440 if (err) { 441 freq = XLP9XX_I2C_DEFAULT_FREQ; 442 dev_dbg(&pdev->dev, "using default frequency %u\n", freq); 443 } else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) { 444 dev_warn(&pdev->dev, "invalid frequency %u, using default\n", 445 freq); 446 freq = XLP9XX_I2C_DEFAULT_FREQ; 447 } 448 priv->clk_hz = freq; 449 450 return 0; 451 } 452 453 static int xlp9xx_i2c_smbus_setup(struct xlp9xx_i2c_dev *priv, 454 struct platform_device *pdev) 455 { 456 if (!priv->alert_data.irq) 457 return -EINVAL; 458 459 priv->ara = i2c_setup_smbus_alert(&priv->adapter, &priv->alert_data); 460 if (!priv->ara) 461 return -ENODEV; 462 463 return 0; 464 } 465 466 static int xlp9xx_i2c_probe(struct platform_device *pdev) 467 { 468 struct xlp9xx_i2c_dev *priv; 469 struct resource *res; 470 int err = 0; 471 472 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 473 if (!priv) 474 return -ENOMEM; 475 476 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 477 priv->base = devm_ioremap_resource(&pdev->dev, res); 478 if (IS_ERR(priv->base)) 479 return PTR_ERR(priv->base); 480 481 priv->irq = platform_get_irq(pdev, 0); 482 if (priv->irq <= 0) { 483 dev_err(&pdev->dev, "invalid irq!\n"); 484 return priv->irq; 485 } 486 /* SMBAlert irq */ 487 priv->alert_data.irq = platform_get_irq(pdev, 1); 488 if (priv->alert_data.irq <= 0) 489 priv->alert_data.irq = 0; 490 491 xlp9xx_i2c_get_frequency(pdev, priv); 492 xlp9xx_i2c_init(priv); 493 494 err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0, 495 pdev->name, priv); 496 if (err) { 497 dev_err(&pdev->dev, "IRQ request failed!\n"); 498 return err; 499 } 500 501 init_completion(&priv->msg_complete); 502 priv->adapter.dev.parent = &pdev->dev; 503 priv->adapter.algo = &xlp9xx_i2c_algo; 504 priv->adapter.class = I2C_CLASS_HWMON; 505 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); 506 priv->adapter.dev.of_node = pdev->dev.of_node; 507 priv->dev = &pdev->dev; 508 509 snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c"); 510 i2c_set_adapdata(&priv->adapter, priv); 511 512 err = i2c_add_adapter(&priv->adapter); 513 if (err) 514 return err; 515 516 err = xlp9xx_i2c_smbus_setup(priv, pdev); 517 if (err) 518 dev_dbg(&pdev->dev, "No active SMBus alert %d\n", err); 519 520 platform_set_drvdata(pdev, priv); 521 dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr); 522 523 return 0; 524 } 525 526 static int xlp9xx_i2c_remove(struct platform_device *pdev) 527 { 528 struct xlp9xx_i2c_dev *priv; 529 530 priv = platform_get_drvdata(pdev); 531 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 532 synchronize_irq(priv->irq); 533 i2c_del_adapter(&priv->adapter); 534 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0); 535 536 return 0; 537 } 538 539 static const struct of_device_id xlp9xx_i2c_of_match[] = { 540 { .compatible = "netlogic,xlp980-i2c", }, 541 { /* sentinel */ }, 542 }; 543 MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match); 544 545 #ifdef CONFIG_ACPI 546 static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = { 547 {"BRCM9007", 0}, 548 {"CAV9007", 0}, 549 {} 550 }; 551 MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids); 552 #endif 553 554 static struct platform_driver xlp9xx_i2c_driver = { 555 .probe = xlp9xx_i2c_probe, 556 .remove = xlp9xx_i2c_remove, 557 .driver = { 558 .name = "xlp9xx-i2c", 559 .of_match_table = xlp9xx_i2c_of_match, 560 .acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids), 561 }, 562 }; 563 564 module_platform_driver(xlp9xx_i2c_driver); 565 566 MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>"); 567 MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver"); 568 MODULE_LICENSE("GPL v2"); 569