1 /* 2 * Copyright (c) 2003-2015 Broadcom Corporation 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/i2c.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 20 #define XLP9XX_I2C_DIV 0x0 21 #define XLP9XX_I2C_CTRL 0x1 22 #define XLP9XX_I2C_CMD 0x2 23 #define XLP9XX_I2C_STATUS 0x3 24 #define XLP9XX_I2C_MTXFIFO 0x4 25 #define XLP9XX_I2C_MRXFIFO 0x5 26 #define XLP9XX_I2C_MFIFOCTRL 0x6 27 #define XLP9XX_I2C_STXFIFO 0x7 28 #define XLP9XX_I2C_SRXFIFO 0x8 29 #define XLP9XX_I2C_SFIFOCTRL 0x9 30 #define XLP9XX_I2C_SLAVEADDR 0xA 31 #define XLP9XX_I2C_OWNADDR 0xB 32 #define XLP9XX_I2C_FIFOWCNT 0xC 33 #define XLP9XX_I2C_INTEN 0xD 34 #define XLP9XX_I2C_INTST 0xE 35 #define XLP9XX_I2C_WAITCNT 0xF 36 #define XLP9XX_I2C_TIMEOUT 0X10 37 #define XLP9XX_I2C_GENCALLADDR 0x11 38 39 #define XLP9XX_I2C_CMD_START BIT(7) 40 #define XLP9XX_I2C_CMD_STOP BIT(6) 41 #define XLP9XX_I2C_CMD_READ BIT(5) 42 #define XLP9XX_I2C_CMD_WRITE BIT(4) 43 #define XLP9XX_I2C_CMD_ACK BIT(3) 44 45 #define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16 46 #define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000 47 #define XLP9XX_I2C_CTRL_RST BIT(8) 48 #define XLP9XX_I2C_CTRL_EN BIT(6) 49 #define XLP9XX_I2C_CTRL_MASTER BIT(4) 50 #define XLP9XX_I2C_CTRL_FIFORD BIT(1) 51 #define XLP9XX_I2C_CTRL_ADDMODE BIT(0) 52 53 #define XLP9XX_I2C_INTEN_NACKADDR BIT(25) 54 #define XLP9XX_I2C_INTEN_SADDR BIT(13) 55 #define XLP9XX_I2C_INTEN_DATADONE BIT(12) 56 #define XLP9XX_I2C_INTEN_ARLOST BIT(11) 57 #define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4) 58 #define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3) 59 #define XLP9XX_I2C_INTEN_MFIFOHI BIT(2) 60 #define XLP9XX_I2C_INTEN_BUSERR BIT(0) 61 62 #define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8 63 #define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0 64 #define XLP9XX_I2C_MFIFOCTRL_RST BIT(16) 65 66 #define XLP9XX_I2C_SLAVEADDR_RW BIT(0) 67 #define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1 68 69 #define XLP9XX_I2C_IP_CLK_FREQ 133000000UL 70 #define XLP9XX_I2C_DEFAULT_FREQ 100000 71 #define XLP9XX_I2C_HIGH_FREQ 400000 72 #define XLP9XX_I2C_FIFO_SIZE 0x80U 73 #define XLP9XX_I2C_TIMEOUT_MS 1000 74 75 #define XLP9XX_I2C_FIFO_WCNT_MASK 0xff 76 #define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \ 77 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR) 78 79 struct xlp9xx_i2c_dev { 80 struct device *dev; 81 struct i2c_adapter adapter; 82 struct completion msg_complete; 83 int irq; 84 bool msg_read; 85 bool len_recv; 86 bool client_pec; 87 u32 __iomem *base; 88 u32 msg_buf_remaining; 89 u32 msg_len; 90 u32 ip_clk_hz; 91 u32 clk_hz; 92 u32 msg_err; 93 u8 *msg_buf; 94 }; 95 96 static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv, 97 unsigned long reg, u32 val) 98 { 99 writel(val, priv->base + reg); 100 } 101 102 static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv, 103 unsigned long reg) 104 { 105 return readl(priv->base + reg); 106 } 107 108 static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) 109 { 110 u32 inten; 111 112 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask; 113 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten); 114 } 115 116 static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) 117 { 118 u32 inten; 119 120 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask; 121 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten); 122 } 123 124 static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv) 125 { 126 u32 thres; 127 128 thres = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE); 129 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL, 130 thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT); 131 } 132 133 static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv) 134 { 135 u32 len, i; 136 u8 *buf = priv->msg_buf; 137 138 len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE); 139 for (i = 0; i < len; i++) 140 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]); 141 priv->msg_buf_remaining -= len; 142 priv->msg_buf += len; 143 } 144 145 static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv) 146 { 147 u32 len, i; 148 u8 rlen, *buf = priv->msg_buf; 149 150 len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) & 151 XLP9XX_I2C_FIFO_WCNT_MASK; 152 if (!len) 153 return; 154 if (priv->len_recv) { 155 /* read length byte */ 156 rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO); 157 *buf++ = rlen; 158 len--; 159 if (priv->client_pec) 160 ++rlen; 161 /* update remaining bytes and message length */ 162 priv->msg_buf_remaining = rlen; 163 priv->msg_len = rlen + 1; 164 priv->len_recv = false; 165 } 166 167 len = min(priv->msg_buf_remaining, len); 168 for (i = 0; i < len; i++, buf++) 169 *buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO); 170 171 priv->msg_buf_remaining -= len; 172 priv->msg_buf = buf; 173 174 if (priv->msg_buf_remaining) 175 xlp9xx_i2c_update_rx_fifo_thres(priv); 176 } 177 178 static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id) 179 { 180 struct xlp9xx_i2c_dev *priv = dev_id; 181 u32 status; 182 183 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST); 184 if (status == 0) 185 return IRQ_NONE; 186 187 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status); 188 if (status & XLP9XX_I2C_STATUS_ERRMASK) { 189 priv->msg_err = status; 190 goto xfer_done; 191 } 192 193 /* SADDR ACK for SMBUS_QUICK */ 194 if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0)) 195 goto xfer_done; 196 197 if (!priv->msg_read) { 198 if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) { 199 /* TX FIFO got empty, fill it up again */ 200 if (priv->msg_buf_remaining) 201 xlp9xx_i2c_fill_tx_fifo(priv); 202 else 203 xlp9xx_i2c_mask_irq(priv, 204 XLP9XX_I2C_INTEN_MFIFOEMTY); 205 } 206 } else { 207 if (status & (XLP9XX_I2C_INTEN_DATADONE | 208 XLP9XX_I2C_INTEN_MFIFOHI)) { 209 /* data is in FIFO, read it */ 210 if (priv->msg_buf_remaining) 211 xlp9xx_i2c_drain_rx_fifo(priv); 212 } 213 } 214 215 /* Transfer complete */ 216 if (status & XLP9XX_I2C_INTEN_DATADONE) 217 goto xfer_done; 218 219 return IRQ_HANDLED; 220 221 xfer_done: 222 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 223 complete(&priv->msg_complete); 224 return IRQ_HANDLED; 225 } 226 227 static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv) 228 { 229 u32 prescale; 230 231 /* 232 * The controller uses 5 * SCL clock internally. 233 * So prescale value should be divided by 5. 234 */ 235 prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz); 236 prescale = ((prescale - 8) / 5) - 1; 237 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST); 238 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN | 239 XLP9XX_I2C_CTRL_MASTER); 240 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale); 241 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 242 243 return 0; 244 } 245 246 static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg, 247 int last_msg) 248 { 249 unsigned long timeleft; 250 u32 intr_mask, cmd, val, len; 251 252 priv->msg_buf = msg->buf; 253 priv->msg_buf_remaining = priv->msg_len = msg->len; 254 priv->msg_err = 0; 255 priv->msg_read = (msg->flags & I2C_M_RD); 256 reinit_completion(&priv->msg_complete); 257 258 /* Reset FIFO */ 259 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL, 260 XLP9XX_I2C_MFIFOCTRL_RST); 261 262 /* set FIFO threshold if reading */ 263 if (priv->msg_read) 264 xlp9xx_i2c_update_rx_fifo_thres(priv); 265 266 /* set slave addr */ 267 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR, 268 (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) | 269 (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0)); 270 271 /* Build control word for transfer */ 272 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL); 273 if (!priv->msg_read) 274 val &= ~XLP9XX_I2C_CTRL_FIFORD; 275 else 276 val |= XLP9XX_I2C_CTRL_FIFORD; /* read */ 277 278 if (msg->flags & I2C_M_TEN) 279 val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/ 280 else 281 val &= ~XLP9XX_I2C_CTRL_ADDMODE; 282 283 priv->len_recv = msg->flags & I2C_M_RECV_LEN; 284 len = priv->len_recv ? XLP9XX_I2C_FIFO_SIZE : msg->len; 285 priv->client_pec = msg->flags & I2C_CLIENT_PEC; 286 287 /* set data length to be transferred */ 288 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) | 289 (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT); 290 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val); 291 292 /* fill fifo during tx */ 293 if (!priv->msg_read) 294 xlp9xx_i2c_fill_tx_fifo(priv); 295 296 /* set interrupt mask */ 297 intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR | 298 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE); 299 300 if (priv->msg_read) { 301 intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI; 302 if (msg->len == 0) 303 intr_mask |= XLP9XX_I2C_INTEN_SADDR; 304 } else { 305 if (msg->len == 0) 306 intr_mask |= XLP9XX_I2C_INTEN_SADDR; 307 else 308 intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY; 309 } 310 xlp9xx_i2c_unmask_irq(priv, intr_mask); 311 312 /* set cmd reg */ 313 cmd = XLP9XX_I2C_CMD_START; 314 cmd |= (priv->msg_read ? XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE); 315 if (last_msg) 316 cmd |= XLP9XX_I2C_CMD_STOP; 317 318 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd); 319 320 timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS); 321 timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft); 322 323 if (priv->msg_err) { 324 dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err); 325 if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) 326 xlp9xx_i2c_init(priv); 327 return -EIO; 328 } 329 330 if (timeleft == 0) { 331 dev_dbg(priv->dev, "i2c transfer timed out!\n"); 332 xlp9xx_i2c_init(priv); 333 return -ETIMEDOUT; 334 } 335 336 /* update msg->len with actual received length */ 337 if (msg->flags & I2C_M_RECV_LEN) 338 msg->len = priv->msg_len; 339 return 0; 340 } 341 342 static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 343 int num) 344 { 345 int i, ret; 346 struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap); 347 348 for (i = 0; i < num; i++) { 349 ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1); 350 if (ret != 0) 351 return ret; 352 } 353 354 return num; 355 } 356 357 static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter) 358 { 359 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | 360 I2C_FUNC_10BIT_ADDR; 361 } 362 363 static const struct i2c_algorithm xlp9xx_i2c_algo = { 364 .master_xfer = xlp9xx_i2c_xfer, 365 .functionality = xlp9xx_i2c_functionality, 366 }; 367 368 static int xlp9xx_i2c_get_frequency(struct platform_device *pdev, 369 struct xlp9xx_i2c_dev *priv) 370 { 371 struct clk *clk; 372 u32 freq; 373 int err; 374 375 clk = devm_clk_get(&pdev->dev, NULL); 376 if (IS_ERR(clk)) { 377 priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ; 378 dev_dbg(&pdev->dev, "using default input frequency %u\n", 379 priv->ip_clk_hz); 380 } else { 381 priv->ip_clk_hz = clk_get_rate(clk); 382 } 383 384 err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq); 385 if (err) { 386 freq = XLP9XX_I2C_DEFAULT_FREQ; 387 dev_dbg(&pdev->dev, "using default frequency %u\n", freq); 388 } else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) { 389 dev_warn(&pdev->dev, "invalid frequency %u, using default\n", 390 freq); 391 freq = XLP9XX_I2C_DEFAULT_FREQ; 392 } 393 priv->clk_hz = freq; 394 395 return 0; 396 } 397 398 static int xlp9xx_i2c_probe(struct platform_device *pdev) 399 { 400 struct xlp9xx_i2c_dev *priv; 401 struct resource *res; 402 int err = 0; 403 404 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 405 if (!priv) 406 return -ENOMEM; 407 408 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 409 priv->base = devm_ioremap_resource(&pdev->dev, res); 410 if (IS_ERR(priv->base)) 411 return PTR_ERR(priv->base); 412 413 priv->irq = platform_get_irq(pdev, 0); 414 if (priv->irq <= 0) { 415 dev_err(&pdev->dev, "invalid irq!\n"); 416 return priv->irq; 417 } 418 419 xlp9xx_i2c_get_frequency(pdev, priv); 420 xlp9xx_i2c_init(priv); 421 422 err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0, 423 pdev->name, priv); 424 if (err) { 425 dev_err(&pdev->dev, "IRQ request failed!\n"); 426 return err; 427 } 428 429 init_completion(&priv->msg_complete); 430 priv->adapter.dev.parent = &pdev->dev; 431 priv->adapter.algo = &xlp9xx_i2c_algo; 432 priv->adapter.class = I2C_CLASS_HWMON; 433 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); 434 priv->adapter.dev.of_node = pdev->dev.of_node; 435 priv->dev = &pdev->dev; 436 437 snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c"); 438 i2c_set_adapdata(&priv->adapter, priv); 439 440 err = i2c_add_adapter(&priv->adapter); 441 if (err) 442 return err; 443 444 platform_set_drvdata(pdev, priv); 445 dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr); 446 447 return 0; 448 } 449 450 static int xlp9xx_i2c_remove(struct platform_device *pdev) 451 { 452 struct xlp9xx_i2c_dev *priv; 453 454 priv = platform_get_drvdata(pdev); 455 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0); 456 synchronize_irq(priv->irq); 457 i2c_del_adapter(&priv->adapter); 458 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0); 459 460 return 0; 461 } 462 463 static const struct of_device_id xlp9xx_i2c_of_match[] = { 464 { .compatible = "netlogic,xlp980-i2c", }, 465 { /* sentinel */ }, 466 }; 467 MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match); 468 469 #ifdef CONFIG_ACPI 470 static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = { 471 {"BRCM9007", 0}, 472 {"CAV9007", 0}, 473 {} 474 }; 475 MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids); 476 #endif 477 478 static struct platform_driver xlp9xx_i2c_driver = { 479 .probe = xlp9xx_i2c_probe, 480 .remove = xlp9xx_i2c_remove, 481 .driver = { 482 .name = "xlp9xx-i2c", 483 .of_match_table = xlp9xx_i2c_of_match, 484 .acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids), 485 }, 486 }; 487 488 module_platform_driver(xlp9xx_i2c_driver); 489 490 MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>"); 491 MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver"); 492 MODULE_LICENSE("GPL v2"); 493