1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i2c-xiic.c 4 * Copyright (c) 2002-2007 Xilinx Inc. 5 * Copyright (c) 2009-2010 Intel Corporation 6 * 7 * This code was implemented by Mocean Laboratories AB when porting linux 8 * to the automotive development board Russellville. The copyright holder 9 * as seen in the header is Intel corporation. 10 * Mocean Laboratories forked off the GNU/Linux platform work into a 11 * separate company called Pelagicore AB, which committed the code to the 12 * kernel. 13 */ 14 15 /* Supports: 16 * Xilinx IIC 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/i2c.h> 25 #include <linux/interrupt.h> 26 #include <linux/completion.h> 27 #include <linux/platform_data/i2c-xiic.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 #include <linux/pm_runtime.h> 33 34 #define DRIVER_NAME "xiic-i2c" 35 36 enum xilinx_i2c_state { 37 STATE_DONE, 38 STATE_ERROR, 39 STATE_START 40 }; 41 42 enum xiic_endian { 43 LITTLE, 44 BIG 45 }; 46 47 /** 48 * struct xiic_i2c - Internal representation of the XIIC I2C bus 49 * @dev: Pointer to device structure 50 * @base: Memory base of the HW registers 51 * @completion: Completion for callers 52 * @adap: Kernel adapter representation 53 * @tx_msg: Messages from above to be sent 54 * @lock: Mutual exclusion 55 * @tx_pos: Current pos in TX message 56 * @nmsgs: Number of messages in tx_msg 57 * @rx_msg: Current RX message 58 * @rx_pos: Position within current RX message 59 * @endianness: big/little-endian byte order 60 * @clk: Pointer to AXI4-lite input clock 61 * @state: See STATE_ 62 * @singlemaster: Indicates bus is single master 63 */ 64 struct xiic_i2c { 65 struct device *dev; 66 void __iomem *base; 67 struct completion completion; 68 struct i2c_adapter adap; 69 struct i2c_msg *tx_msg; 70 struct mutex lock; 71 unsigned int tx_pos; 72 unsigned int nmsgs; 73 struct i2c_msg *rx_msg; 74 int rx_pos; 75 enum xiic_endian endianness; 76 struct clk *clk; 77 enum xilinx_i2c_state state; 78 bool singlemaster; 79 }; 80 81 82 #define XIIC_MSB_OFFSET 0 83 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 84 85 /* 86 * Register offsets in bytes from RegisterBase. Three is added to the 87 * base offset to access LSB (IBM style) of the word 88 */ 89 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 90 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 91 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 92 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 93 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 94 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 95 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 96 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 97 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 98 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 99 100 /* Control Register masks */ 101 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 102 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 103 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 104 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 105 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 106 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 107 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 108 109 /* Status Register masks */ 110 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 111 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 112 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 113 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 114 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 115 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 116 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 117 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 118 119 /* Interrupt Status Register masks Interrupt occurs when... */ 120 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 121 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 122 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 123 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 124 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 125 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 126 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 127 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 128 129 /* The following constants specify the depth of the FIFOs */ 130 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 131 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 132 133 /* The following constants specify groups of interrupts that are typically 134 * enabled or disables at the same time 135 */ 136 #define XIIC_TX_INTERRUPTS \ 137 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 138 139 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 140 141 /* 142 * Tx Fifo upper bit masks. 143 */ 144 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 145 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 146 147 /* 148 * The following constants define the register offsets for the Interrupt 149 * registers. There are some holes in the memory map for reserved addresses 150 * to allow other registers to be added and still match the memory map of the 151 * interrupt controller registers 152 */ 153 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 154 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 155 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 156 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 157 158 #define XIIC_RESET_MASK 0xAUL 159 160 #define XIIC_PM_TIMEOUT 1000 /* ms */ 161 /* timeout waiting for the controller to respond */ 162 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 163 /* timeout waiting for the controller finish transfers */ 164 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 165 166 /* 167 * The following constant is used for the device global interrupt enable 168 * register, to enable all interrupts for the device, this is the only bit 169 * in the register 170 */ 171 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 172 173 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 174 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 175 176 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 177 static void __xiic_start_xfer(struct xiic_i2c *i2c); 178 179 /* 180 * For the register read and write functions, a little-endian and big-endian 181 * version are necessary. Endianness is detected during the probe function. 182 * Only the least significant byte [doublet] of the register are ever 183 * accessed. This requires an offset of 3 [2] from the base address for 184 * big-endian systems. 185 */ 186 187 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 188 { 189 if (i2c->endianness == LITTLE) 190 iowrite8(value, i2c->base + reg); 191 else 192 iowrite8(value, i2c->base + reg + 3); 193 } 194 195 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 196 { 197 u8 ret; 198 199 if (i2c->endianness == LITTLE) 200 ret = ioread8(i2c->base + reg); 201 else 202 ret = ioread8(i2c->base + reg + 3); 203 return ret; 204 } 205 206 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 207 { 208 if (i2c->endianness == LITTLE) 209 iowrite16(value, i2c->base + reg); 210 else 211 iowrite16be(value, i2c->base + reg + 2); 212 } 213 214 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 215 { 216 if (i2c->endianness == LITTLE) 217 iowrite32(value, i2c->base + reg); 218 else 219 iowrite32be(value, i2c->base + reg); 220 } 221 222 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 223 { 224 u32 ret; 225 226 if (i2c->endianness == LITTLE) 227 ret = ioread32(i2c->base + reg); 228 else 229 ret = ioread32be(i2c->base + reg); 230 return ret; 231 } 232 233 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 234 { 235 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 236 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 237 } 238 239 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 240 { 241 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 242 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 243 } 244 245 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 246 { 247 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 248 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 249 } 250 251 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 252 { 253 xiic_irq_clr(i2c, mask); 254 xiic_irq_en(i2c, mask); 255 } 256 257 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 258 { 259 u8 sr; 260 unsigned long timeout; 261 262 timeout = jiffies + XIIC_I2C_TIMEOUT; 263 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 264 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 265 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 266 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 267 if (time_after(jiffies, timeout)) { 268 dev_err(i2c->dev, "Failed to clear rx fifo\n"); 269 return -ETIMEDOUT; 270 } 271 } 272 273 return 0; 274 } 275 276 static int xiic_reinit(struct xiic_i2c *i2c) 277 { 278 int ret; 279 280 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 281 282 /* Set receive Fifo depth to maximum (zero based). */ 283 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 284 285 /* Reset Tx Fifo. */ 286 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 287 288 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 289 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 290 291 /* make sure RX fifo is empty */ 292 ret = xiic_clear_rx_fifo(i2c); 293 if (ret) 294 return ret; 295 296 /* Enable interrupts */ 297 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 298 299 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 300 301 return 0; 302 } 303 304 static void xiic_deinit(struct xiic_i2c *i2c) 305 { 306 u8 cr; 307 308 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 309 310 /* Disable IIC Device. */ 311 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 312 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 313 } 314 315 static void xiic_read_rx(struct xiic_i2c *i2c) 316 { 317 u8 bytes_in_fifo; 318 int i; 319 320 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 321 322 dev_dbg(i2c->adap.dev.parent, 323 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 324 __func__, bytes_in_fifo, xiic_rx_space(i2c), 325 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 326 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 327 328 if (bytes_in_fifo > xiic_rx_space(i2c)) 329 bytes_in_fifo = xiic_rx_space(i2c); 330 331 for (i = 0; i < bytes_in_fifo; i++) 332 i2c->rx_msg->buf[i2c->rx_pos++] = 333 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 334 335 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 336 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 337 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 338 } 339 340 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 341 { 342 /* return the actual space left in the FIFO */ 343 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 344 } 345 346 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 347 { 348 u8 fifo_space = xiic_tx_fifo_space(i2c); 349 int len = xiic_tx_space(i2c); 350 351 len = (len > fifo_space) ? fifo_space : len; 352 353 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 354 __func__, len, fifo_space); 355 356 while (len--) { 357 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 358 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 359 /* last message in transfer -> STOP */ 360 data |= XIIC_TX_DYN_STOP_MASK; 361 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 362 } 363 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 364 } 365 } 366 367 static void xiic_wakeup(struct xiic_i2c *i2c, int code) 368 { 369 i2c->tx_msg = NULL; 370 i2c->rx_msg = NULL; 371 i2c->nmsgs = 0; 372 i2c->state = code; 373 complete(&i2c->completion); 374 } 375 376 static irqreturn_t xiic_process(int irq, void *dev_id) 377 { 378 struct xiic_i2c *i2c = dev_id; 379 u32 pend, isr, ier; 380 u32 clr = 0; 381 int xfer_more = 0; 382 int wakeup_req = 0; 383 int wakeup_code = 0; 384 385 /* Get the interrupt Status from the IPIF. There is no clearing of 386 * interrupts in the IPIF. Interrupts must be cleared at the source. 387 * To find which interrupts are pending; AND interrupts pending with 388 * interrupts masked. 389 */ 390 mutex_lock(&i2c->lock); 391 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 392 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 393 pend = isr & ier; 394 395 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 396 __func__, ier, isr, pend); 397 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 398 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 399 i2c->tx_msg, i2c->nmsgs); 400 401 402 /* Service requesting interrupt */ 403 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 404 ((pend & XIIC_INTR_TX_ERROR_MASK) && 405 !(pend & XIIC_INTR_RX_FULL_MASK))) { 406 /* bus arbritration lost, or... 407 * Transmit error _OR_ RX completed 408 * if this happens when RX_FULL is not set 409 * this is probably a TX error 410 */ 411 412 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 413 414 /* dynamic mode seem to suffer from problems if we just flushes 415 * fifos and the next message is a TX with len 0 (only addr) 416 * reset the IP instead of just flush fifos 417 */ 418 xiic_reinit(i2c); 419 420 if (i2c->rx_msg) { 421 wakeup_req = 1; 422 wakeup_code = STATE_ERROR; 423 } 424 if (i2c->tx_msg) { 425 wakeup_req = 1; 426 wakeup_code = STATE_ERROR; 427 } 428 } 429 if (pend & XIIC_INTR_RX_FULL_MASK) { 430 /* Receive register/FIFO is full */ 431 432 clr |= XIIC_INTR_RX_FULL_MASK; 433 if (!i2c->rx_msg) { 434 dev_dbg(i2c->adap.dev.parent, 435 "%s unexpected RX IRQ\n", __func__); 436 xiic_clear_rx_fifo(i2c); 437 goto out; 438 } 439 440 xiic_read_rx(i2c); 441 if (xiic_rx_space(i2c) == 0) { 442 /* this is the last part of the message */ 443 i2c->rx_msg = NULL; 444 445 /* also clear TX error if there (RX complete) */ 446 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 447 448 dev_dbg(i2c->adap.dev.parent, 449 "%s end of message, nmsgs: %d\n", 450 __func__, i2c->nmsgs); 451 452 /* send next message if this wasn't the last, 453 * otherwise the transfer will be finialise when 454 * receiving the bus not busy interrupt 455 */ 456 if (i2c->nmsgs > 1) { 457 i2c->nmsgs--; 458 i2c->tx_msg++; 459 dev_dbg(i2c->adap.dev.parent, 460 "%s will start next...\n", __func__); 461 xfer_more = 1; 462 } 463 } 464 } 465 if (pend & XIIC_INTR_BNB_MASK) { 466 /* IIC bus has transitioned to not busy */ 467 clr |= XIIC_INTR_BNB_MASK; 468 469 /* The bus is not busy, disable BusNotBusy interrupt */ 470 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 471 472 if (!i2c->tx_msg) 473 goto out; 474 475 wakeup_req = 1; 476 477 if (i2c->nmsgs == 1 && !i2c->rx_msg && 478 xiic_tx_space(i2c) == 0) 479 wakeup_code = STATE_DONE; 480 else 481 wakeup_code = STATE_ERROR; 482 } 483 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 484 /* Transmit register/FIFO is empty or ½ empty */ 485 486 clr |= (pend & 487 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 488 489 if (!i2c->tx_msg) { 490 dev_dbg(i2c->adap.dev.parent, 491 "%s unexpected TX IRQ\n", __func__); 492 goto out; 493 } 494 495 xiic_fill_tx_fifo(i2c); 496 497 /* current message sent and there is space in the fifo */ 498 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 499 dev_dbg(i2c->adap.dev.parent, 500 "%s end of message sent, nmsgs: %d\n", 501 __func__, i2c->nmsgs); 502 if (i2c->nmsgs > 1) { 503 i2c->nmsgs--; 504 i2c->tx_msg++; 505 xfer_more = 1; 506 } else { 507 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 508 509 dev_dbg(i2c->adap.dev.parent, 510 "%s Got TX IRQ but no more to do...\n", 511 __func__); 512 } 513 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 514 /* current frame is sent and is last, 515 * make sure to disable tx half 516 */ 517 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 518 } 519 out: 520 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 521 522 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 523 if (xfer_more) 524 __xiic_start_xfer(i2c); 525 if (wakeup_req) 526 xiic_wakeup(i2c, wakeup_code); 527 528 WARN_ON(xfer_more && wakeup_req); 529 530 mutex_unlock(&i2c->lock); 531 return IRQ_HANDLED; 532 } 533 534 static int xiic_bus_busy(struct xiic_i2c *i2c) 535 { 536 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 537 538 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 539 } 540 541 static int xiic_busy(struct xiic_i2c *i2c) 542 { 543 int tries = 3; 544 int err; 545 546 if (i2c->tx_msg || i2c->rx_msg) 547 return -EBUSY; 548 549 /* In single master mode bus can only be busy, when in use by this 550 * driver. If the register indicates bus being busy for some reason we 551 * should ignore it, since bus will never be released and i2c will be 552 * stuck forever. 553 */ 554 if (i2c->singlemaster) { 555 return 0; 556 } 557 558 /* for instance if previous transfer was terminated due to TX error 559 * it might be that the bus is on it's way to become available 560 * give it at most 3 ms to wake 561 */ 562 err = xiic_bus_busy(i2c); 563 while (err && tries--) { 564 msleep(1); 565 err = xiic_bus_busy(i2c); 566 } 567 568 return err; 569 } 570 571 static void xiic_start_recv(struct xiic_i2c *i2c) 572 { 573 u8 rx_watermark; 574 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 575 576 /* Clear and enable Rx full interrupt. */ 577 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 578 579 /* we want to get all but last byte, because the TX_ERROR IRQ is used 580 * to inidicate error ACK on the address, and negative ack on the last 581 * received byte, so to not mix them receive all but last. 582 * In the case where there is only one byte to receive 583 * we can check if ERROR and RX full is set at the same time 584 */ 585 rx_watermark = msg->len; 586 if (rx_watermark > IIC_RX_FIFO_DEPTH) 587 rx_watermark = IIC_RX_FIFO_DEPTH; 588 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 589 590 if (!(msg->flags & I2C_M_NOSTART)) 591 /* write the address */ 592 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 593 i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); 594 595 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 596 597 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 598 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 599 600 if (i2c->nmsgs == 1) 601 /* very last, enable bus not busy as well */ 602 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 603 604 /* the message is tx:ed */ 605 i2c->tx_pos = msg->len; 606 } 607 608 static void xiic_start_send(struct xiic_i2c *i2c) 609 { 610 struct i2c_msg *msg = i2c->tx_msg; 611 612 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 613 __func__, msg, msg->len); 614 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 615 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 616 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 617 618 if (!(msg->flags & I2C_M_NOSTART)) { 619 /* write the address */ 620 u16 data = i2c_8bit_addr_from_msg(msg) | 621 XIIC_TX_DYN_START_MASK; 622 if ((i2c->nmsgs == 1) && msg->len == 0) 623 /* no data and last message -> add STOP */ 624 data |= XIIC_TX_DYN_STOP_MASK; 625 626 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 627 } 628 629 /* Clear any pending Tx empty, Tx Error and then enable them. */ 630 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 631 XIIC_INTR_BNB_MASK | 632 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? 633 XIIC_INTR_TX_HALF_MASK : 0)); 634 635 xiic_fill_tx_fifo(i2c); 636 } 637 638 static void __xiic_start_xfer(struct xiic_i2c *i2c) 639 { 640 int fifo_space = xiic_tx_fifo_space(i2c); 641 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 642 __func__, i2c->tx_msg, fifo_space); 643 644 if (!i2c->tx_msg) 645 return; 646 647 i2c->rx_pos = 0; 648 i2c->tx_pos = 0; 649 i2c->state = STATE_START; 650 if (i2c->tx_msg->flags & I2C_M_RD) { 651 /* we dont date putting several reads in the FIFO */ 652 xiic_start_recv(i2c); 653 } else { 654 xiic_start_send(i2c); 655 } 656 } 657 658 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) 659 { 660 int ret; 661 662 mutex_lock(&i2c->lock); 663 664 ret = xiic_busy(i2c); 665 if (ret) 666 goto out; 667 668 i2c->tx_msg = msgs; 669 i2c->rx_msg = NULL; 670 i2c->nmsgs = num; 671 init_completion(&i2c->completion); 672 673 ret = xiic_reinit(i2c); 674 if (!ret) 675 __xiic_start_xfer(i2c); 676 677 out: 678 mutex_unlock(&i2c->lock); 679 680 return ret; 681 } 682 683 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 684 { 685 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 686 int err; 687 688 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 689 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 690 691 err = pm_runtime_resume_and_get(i2c->dev); 692 if (err < 0) 693 return err; 694 695 err = xiic_start_xfer(i2c, msgs, num); 696 if (err < 0) { 697 dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 698 return err; 699 } 700 701 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); 702 mutex_lock(&i2c->lock); 703 if (err == 0) { /* Timeout */ 704 i2c->tx_msg = NULL; 705 i2c->rx_msg = NULL; 706 i2c->nmsgs = 0; 707 err = -ETIMEDOUT; 708 } else if (err < 0) { /* Completion error */ 709 i2c->tx_msg = NULL; 710 i2c->rx_msg = NULL; 711 i2c->nmsgs = 0; 712 } else { 713 err = (i2c->state == STATE_DONE) ? num : -EIO; 714 } 715 mutex_unlock(&i2c->lock); 716 pm_runtime_mark_last_busy(i2c->dev); 717 pm_runtime_put_autosuspend(i2c->dev); 718 return err; 719 } 720 721 static u32 xiic_func(struct i2c_adapter *adap) 722 { 723 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 724 } 725 726 static const struct i2c_algorithm xiic_algorithm = { 727 .master_xfer = xiic_xfer, 728 .functionality = xiic_func, 729 }; 730 731 static const struct i2c_adapter_quirks xiic_quirks = { 732 .max_read_len = 255, 733 }; 734 735 static const struct i2c_adapter xiic_adapter = { 736 .owner = THIS_MODULE, 737 .name = DRIVER_NAME, 738 .class = I2C_CLASS_DEPRECATED, 739 .algo = &xiic_algorithm, 740 .quirks = &xiic_quirks, 741 }; 742 743 744 static int xiic_i2c_probe(struct platform_device *pdev) 745 { 746 struct xiic_i2c *i2c; 747 struct xiic_i2c_platform_data *pdata; 748 struct resource *res; 749 int ret, irq; 750 u8 i; 751 u32 sr; 752 753 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 754 if (!i2c) 755 return -ENOMEM; 756 757 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 758 i2c->base = devm_ioremap_resource(&pdev->dev, res); 759 if (IS_ERR(i2c->base)) 760 return PTR_ERR(i2c->base); 761 762 irq = platform_get_irq(pdev, 0); 763 if (irq < 0) 764 return irq; 765 766 pdata = dev_get_platdata(&pdev->dev); 767 768 /* hook up driver to tree */ 769 platform_set_drvdata(pdev, i2c); 770 i2c->adap = xiic_adapter; 771 i2c_set_adapdata(&i2c->adap, i2c); 772 i2c->adap.dev.parent = &pdev->dev; 773 i2c->adap.dev.of_node = pdev->dev.of_node; 774 775 mutex_init(&i2c->lock); 776 777 i2c->clk = devm_clk_get(&pdev->dev, NULL); 778 if (IS_ERR(i2c->clk)) 779 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 780 "input clock not found.\n"); 781 782 ret = clk_prepare_enable(i2c->clk); 783 if (ret) { 784 dev_err(&pdev->dev, "Unable to enable clock.\n"); 785 return ret; 786 } 787 i2c->dev = &pdev->dev; 788 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 789 pm_runtime_use_autosuspend(i2c->dev); 790 pm_runtime_set_active(i2c->dev); 791 pm_runtime_enable(i2c->dev); 792 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 793 xiic_process, IRQF_ONESHOT, 794 pdev->name, i2c); 795 796 if (ret < 0) { 797 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 798 goto err_clk_dis; 799 } 800 801 i2c->singlemaster = 802 of_property_read_bool(pdev->dev.of_node, "single-master"); 803 804 /* 805 * Detect endianness 806 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 807 * set, assume that the endianness was wrong and swap. 808 */ 809 i2c->endianness = LITTLE; 810 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 811 /* Reset is cleared in xiic_reinit */ 812 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 813 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 814 i2c->endianness = BIG; 815 816 ret = xiic_reinit(i2c); 817 if (ret < 0) { 818 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 819 goto err_clk_dis; 820 } 821 822 /* add i2c adapter to i2c tree */ 823 ret = i2c_add_adapter(&i2c->adap); 824 if (ret) { 825 xiic_deinit(i2c); 826 goto err_clk_dis; 827 } 828 829 if (pdata) { 830 /* add in known devices to the bus */ 831 for (i = 0; i < pdata->num_devices; i++) 832 i2c_new_client_device(&i2c->adap, pdata->devices + i); 833 } 834 835 return 0; 836 837 err_clk_dis: 838 pm_runtime_set_suspended(&pdev->dev); 839 pm_runtime_disable(&pdev->dev); 840 clk_disable_unprepare(i2c->clk); 841 return ret; 842 } 843 844 static int xiic_i2c_remove(struct platform_device *pdev) 845 { 846 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 847 int ret; 848 849 /* remove adapter & data */ 850 i2c_del_adapter(&i2c->adap); 851 852 ret = pm_runtime_resume_and_get(i2c->dev); 853 if (ret < 0) 854 return ret; 855 856 xiic_deinit(i2c); 857 pm_runtime_put_sync(i2c->dev); 858 clk_disable_unprepare(i2c->clk); 859 pm_runtime_disable(&pdev->dev); 860 pm_runtime_set_suspended(&pdev->dev); 861 pm_runtime_dont_use_autosuspend(&pdev->dev); 862 863 return 0; 864 } 865 866 #if defined(CONFIG_OF) 867 static const struct of_device_id xiic_of_match[] = { 868 { .compatible = "xlnx,xps-iic-2.00.a", }, 869 {}, 870 }; 871 MODULE_DEVICE_TABLE(of, xiic_of_match); 872 #endif 873 874 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 875 { 876 struct xiic_i2c *i2c = dev_get_drvdata(dev); 877 878 clk_disable(i2c->clk); 879 880 return 0; 881 } 882 883 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 884 { 885 struct xiic_i2c *i2c = dev_get_drvdata(dev); 886 int ret; 887 888 ret = clk_enable(i2c->clk); 889 if (ret) { 890 dev_err(dev, "Cannot enable clock.\n"); 891 return ret; 892 } 893 894 return 0; 895 } 896 897 static const struct dev_pm_ops xiic_dev_pm_ops = { 898 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 899 xiic_i2c_runtime_resume, NULL) 900 }; 901 static struct platform_driver xiic_i2c_driver = { 902 .probe = xiic_i2c_probe, 903 .remove = xiic_i2c_remove, 904 .driver = { 905 .name = DRIVER_NAME, 906 .of_match_table = of_match_ptr(xiic_of_match), 907 .pm = &xiic_dev_pm_ops, 908 }, 909 }; 910 911 module_platform_driver(xiic_i2c_driver); 912 913 MODULE_AUTHOR("info@mocean-labs.com"); 914 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 915 MODULE_LICENSE("GPL v2"); 916 MODULE_ALIAS("platform:"DRIVER_NAME); 917