1 /* 2 * i2c-xiic.c 3 * Copyright (c) 2002-2007 Xilinx Inc. 4 * Copyright (c) 2009-2010 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * 16 * This code was implemented by Mocean Laboratories AB when porting linux 17 * to the automotive development board Russellville. The copyright holder 18 * as seen in the header is Intel corporation. 19 * Mocean Laboratories forked off the GNU/Linux platform work into a 20 * separate company called Pelagicore AB, which committed the code to the 21 * kernel. 22 */ 23 24 /* Supports: 25 * Xilinx IIC 26 */ 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/errno.h> 30 #include <linux/err.h> 31 #include <linux/delay.h> 32 #include <linux/platform_device.h> 33 #include <linux/i2c.h> 34 #include <linux/interrupt.h> 35 #include <linux/wait.h> 36 #include <linux/i2c-xiic.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 41 #define DRIVER_NAME "xiic-i2c" 42 43 enum xilinx_i2c_state { 44 STATE_DONE, 45 STATE_ERROR, 46 STATE_START 47 }; 48 49 enum xiic_endian { 50 LITTLE, 51 BIG 52 }; 53 54 /** 55 * struct xiic_i2c - Internal representation of the XIIC I2C bus 56 * @base: Memory base of the HW registers 57 * @wait: Wait queue for callers 58 * @adap: Kernel adapter representation 59 * @tx_msg: Messages from above to be sent 60 * @lock: Mutual exclusion 61 * @tx_pos: Current pos in TX message 62 * @nmsgs: Number of messages in tx_msg 63 * @state: See STATE_ 64 * @rx_msg: Current RX message 65 * @rx_pos: Position within current RX message 66 * @endianness: big/little-endian byte order 67 */ 68 struct xiic_i2c { 69 void __iomem *base; 70 wait_queue_head_t wait; 71 struct i2c_adapter adap; 72 struct i2c_msg *tx_msg; 73 spinlock_t lock; 74 unsigned int tx_pos; 75 unsigned int nmsgs; 76 enum xilinx_i2c_state state; 77 struct i2c_msg *rx_msg; 78 int rx_pos; 79 enum xiic_endian endianness; 80 }; 81 82 83 #define XIIC_MSB_OFFSET 0 84 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 85 86 /* 87 * Register offsets in bytes from RegisterBase. Three is added to the 88 * base offset to access LSB (IBM style) of the word 89 */ 90 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 91 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 92 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 93 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 94 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 95 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 96 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 97 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 98 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 99 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 100 101 /* Control Register masks */ 102 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 103 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 104 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 105 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 106 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 107 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 108 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 109 110 /* Status Register masks */ 111 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 112 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 113 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 114 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 115 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 116 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 117 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 118 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 119 120 /* Interrupt Status Register masks Interrupt occurs when... */ 121 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 122 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 123 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 124 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 125 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 126 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 127 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 128 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 129 130 /* The following constants specify the depth of the FIFOs */ 131 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 132 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 133 134 /* The following constants specify groups of interrupts that are typically 135 * enabled or disables at the same time 136 */ 137 #define XIIC_TX_INTERRUPTS \ 138 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 139 140 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 141 142 /* The following constants are used with the following macros to specify the 143 * operation, a read or write operation. 144 */ 145 #define XIIC_READ_OPERATION 1 146 #define XIIC_WRITE_OPERATION 0 147 148 /* 149 * Tx Fifo upper bit masks. 150 */ 151 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 152 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 153 154 /* 155 * The following constants define the register offsets for the Interrupt 156 * registers. There are some holes in the memory map for reserved addresses 157 * to allow other registers to be added and still match the memory map of the 158 * interrupt controller registers 159 */ 160 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 161 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 162 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 163 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 164 165 #define XIIC_RESET_MASK 0xAUL 166 167 /* 168 * The following constant is used for the device global interrupt enable 169 * register, to enable all interrupts for the device, this is the only bit 170 * in the register 171 */ 172 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 173 174 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 175 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 176 177 static void xiic_start_xfer(struct xiic_i2c *i2c); 178 static void __xiic_start_xfer(struct xiic_i2c *i2c); 179 180 /* 181 * For the register read and write functions, a little-endian and big-endian 182 * version are necessary. Endianness is detected during the probe function. 183 * Only the least significant byte [doublet] of the register are ever 184 * accessed. This requires an offset of 3 [2] from the base address for 185 * big-endian systems. 186 */ 187 188 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 189 { 190 if (i2c->endianness == LITTLE) 191 iowrite8(value, i2c->base + reg); 192 else 193 iowrite8(value, i2c->base + reg + 3); 194 } 195 196 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 197 { 198 u8 ret; 199 200 if (i2c->endianness == LITTLE) 201 ret = ioread8(i2c->base + reg); 202 else 203 ret = ioread8(i2c->base + reg + 3); 204 return ret; 205 } 206 207 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 208 { 209 if (i2c->endianness == LITTLE) 210 iowrite16(value, i2c->base + reg); 211 else 212 iowrite16be(value, i2c->base + reg + 2); 213 } 214 215 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 216 { 217 if (i2c->endianness == LITTLE) 218 iowrite32(value, i2c->base + reg); 219 else 220 iowrite32be(value, i2c->base + reg); 221 } 222 223 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 224 { 225 u32 ret; 226 227 if (i2c->endianness == LITTLE) 228 ret = ioread32(i2c->base + reg); 229 else 230 ret = ioread32be(i2c->base + reg); 231 return ret; 232 } 233 234 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 235 { 236 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 237 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 238 } 239 240 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 241 { 242 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 243 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 244 } 245 246 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 247 { 248 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 249 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 250 } 251 252 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 253 { 254 xiic_irq_clr(i2c, mask); 255 xiic_irq_en(i2c, mask); 256 } 257 258 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) 259 { 260 u8 sr; 261 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 262 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 263 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) 264 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 265 } 266 267 static void xiic_reinit(struct xiic_i2c *i2c) 268 { 269 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 270 271 /* Set receive Fifo depth to maximum (zero based). */ 272 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 273 274 /* Reset Tx Fifo. */ 275 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 276 277 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 278 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 279 280 /* make sure RX fifo is empty */ 281 xiic_clear_rx_fifo(i2c); 282 283 /* Enable interrupts */ 284 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 285 286 xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK); 287 } 288 289 static void xiic_deinit(struct xiic_i2c *i2c) 290 { 291 u8 cr; 292 293 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 294 295 /* Disable IIC Device. */ 296 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 297 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 298 } 299 300 static void xiic_read_rx(struct xiic_i2c *i2c) 301 { 302 u8 bytes_in_fifo; 303 int i; 304 305 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 306 307 dev_dbg(i2c->adap.dev.parent, 308 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 309 __func__, bytes_in_fifo, xiic_rx_space(i2c), 310 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 311 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 312 313 if (bytes_in_fifo > xiic_rx_space(i2c)) 314 bytes_in_fifo = xiic_rx_space(i2c); 315 316 for (i = 0; i < bytes_in_fifo; i++) 317 i2c->rx_msg->buf[i2c->rx_pos++] = 318 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 319 320 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 321 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 322 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 323 } 324 325 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 326 { 327 /* return the actual space left in the FIFO */ 328 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 329 } 330 331 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 332 { 333 u8 fifo_space = xiic_tx_fifo_space(i2c); 334 int len = xiic_tx_space(i2c); 335 336 len = (len > fifo_space) ? fifo_space : len; 337 338 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 339 __func__, len, fifo_space); 340 341 while (len--) { 342 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 343 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 344 /* last message in transfer -> STOP */ 345 data |= XIIC_TX_DYN_STOP_MASK; 346 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 347 } 348 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 349 } 350 } 351 352 static void xiic_wakeup(struct xiic_i2c *i2c, int code) 353 { 354 i2c->tx_msg = NULL; 355 i2c->rx_msg = NULL; 356 i2c->nmsgs = 0; 357 i2c->state = code; 358 wake_up(&i2c->wait); 359 } 360 361 static irqreturn_t xiic_process(int irq, void *dev_id) 362 { 363 struct xiic_i2c *i2c = dev_id; 364 u32 pend, isr, ier; 365 u32 clr = 0; 366 367 /* Get the interrupt Status from the IPIF. There is no clearing of 368 * interrupts in the IPIF. Interrupts must be cleared at the source. 369 * To find which interrupts are pending; AND interrupts pending with 370 * interrupts masked. 371 */ 372 spin_lock(&i2c->lock); 373 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 374 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 375 pend = isr & ier; 376 377 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 378 __func__, ier, isr, pend); 379 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 380 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 381 i2c->tx_msg, i2c->nmsgs); 382 383 384 /* Service requesting interrupt */ 385 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 386 ((pend & XIIC_INTR_TX_ERROR_MASK) && 387 !(pend & XIIC_INTR_RX_FULL_MASK))) { 388 /* bus arbritration lost, or... 389 * Transmit error _OR_ RX completed 390 * if this happens when RX_FULL is not set 391 * this is probably a TX error 392 */ 393 394 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 395 396 /* dynamic mode seem to suffer from problems if we just flushes 397 * fifos and the next message is a TX with len 0 (only addr) 398 * reset the IP instead of just flush fifos 399 */ 400 xiic_reinit(i2c); 401 402 if (i2c->tx_msg) 403 xiic_wakeup(i2c, STATE_ERROR); 404 405 } else if (pend & XIIC_INTR_RX_FULL_MASK) { 406 /* Receive register/FIFO is full */ 407 408 clr = XIIC_INTR_RX_FULL_MASK; 409 if (!i2c->rx_msg) { 410 dev_dbg(i2c->adap.dev.parent, 411 "%s unexpexted RX IRQ\n", __func__); 412 xiic_clear_rx_fifo(i2c); 413 goto out; 414 } 415 416 xiic_read_rx(i2c); 417 if (xiic_rx_space(i2c) == 0) { 418 /* this is the last part of the message */ 419 i2c->rx_msg = NULL; 420 421 /* also clear TX error if there (RX complete) */ 422 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 423 424 dev_dbg(i2c->adap.dev.parent, 425 "%s end of message, nmsgs: %d\n", 426 __func__, i2c->nmsgs); 427 428 /* send next message if this wasn't the last, 429 * otherwise the transfer will be finialise when 430 * receiving the bus not busy interrupt 431 */ 432 if (i2c->nmsgs > 1) { 433 i2c->nmsgs--; 434 i2c->tx_msg++; 435 dev_dbg(i2c->adap.dev.parent, 436 "%s will start next...\n", __func__); 437 438 __xiic_start_xfer(i2c); 439 } 440 } 441 } else if (pend & XIIC_INTR_BNB_MASK) { 442 /* IIC bus has transitioned to not busy */ 443 clr = XIIC_INTR_BNB_MASK; 444 445 /* The bus is not busy, disable BusNotBusy interrupt */ 446 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 447 448 if (!i2c->tx_msg) 449 goto out; 450 451 if ((i2c->nmsgs == 1) && !i2c->rx_msg && 452 xiic_tx_space(i2c) == 0) 453 xiic_wakeup(i2c, STATE_DONE); 454 else 455 xiic_wakeup(i2c, STATE_ERROR); 456 457 } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 458 /* Transmit register/FIFO is empty or ½ empty */ 459 460 clr = pend & 461 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK); 462 463 if (!i2c->tx_msg) { 464 dev_dbg(i2c->adap.dev.parent, 465 "%s unexpexted TX IRQ\n", __func__); 466 goto out; 467 } 468 469 xiic_fill_tx_fifo(i2c); 470 471 /* current message sent and there is space in the fifo */ 472 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 473 dev_dbg(i2c->adap.dev.parent, 474 "%s end of message sent, nmsgs: %d\n", 475 __func__, i2c->nmsgs); 476 if (i2c->nmsgs > 1) { 477 i2c->nmsgs--; 478 i2c->tx_msg++; 479 __xiic_start_xfer(i2c); 480 } else { 481 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 482 483 dev_dbg(i2c->adap.dev.parent, 484 "%s Got TX IRQ but no more to do...\n", 485 __func__); 486 } 487 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 488 /* current frame is sent and is last, 489 * make sure to disable tx half 490 */ 491 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 492 } else { 493 /* got IRQ which is not acked */ 494 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n", 495 __func__); 496 clr = pend; 497 } 498 out: 499 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 500 501 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 502 spin_unlock(&i2c->lock); 503 return IRQ_HANDLED; 504 } 505 506 static int xiic_bus_busy(struct xiic_i2c *i2c) 507 { 508 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 509 510 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 511 } 512 513 static int xiic_busy(struct xiic_i2c *i2c) 514 { 515 int tries = 3; 516 int err; 517 518 if (i2c->tx_msg) 519 return -EBUSY; 520 521 /* for instance if previous transfer was terminated due to TX error 522 * it might be that the bus is on it's way to become available 523 * give it at most 3 ms to wake 524 */ 525 err = xiic_bus_busy(i2c); 526 while (err && tries--) { 527 mdelay(1); 528 err = xiic_bus_busy(i2c); 529 } 530 531 return err; 532 } 533 534 static void xiic_start_recv(struct xiic_i2c *i2c) 535 { 536 u8 rx_watermark; 537 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 538 539 /* Clear and enable Rx full interrupt. */ 540 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 541 542 /* we want to get all but last byte, because the TX_ERROR IRQ is used 543 * to inidicate error ACK on the address, and negative ack on the last 544 * received byte, so to not mix them receive all but last. 545 * In the case where there is only one byte to receive 546 * we can check if ERROR and RX full is set at the same time 547 */ 548 rx_watermark = msg->len; 549 if (rx_watermark > IIC_RX_FIFO_DEPTH) 550 rx_watermark = IIC_RX_FIFO_DEPTH; 551 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 552 553 if (!(msg->flags & I2C_M_NOSTART)) 554 /* write the address */ 555 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 556 (msg->addr << 1) | XIIC_READ_OPERATION | 557 XIIC_TX_DYN_START_MASK); 558 559 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 560 561 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 562 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 563 if (i2c->nmsgs == 1) 564 /* very last, enable bus not busy as well */ 565 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 566 567 /* the message is tx:ed */ 568 i2c->tx_pos = msg->len; 569 } 570 571 static void xiic_start_send(struct xiic_i2c *i2c) 572 { 573 struct i2c_msg *msg = i2c->tx_msg; 574 575 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); 576 577 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 578 __func__, msg, msg->len); 579 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 580 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 581 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 582 583 if (!(msg->flags & I2C_M_NOSTART)) { 584 /* write the address */ 585 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION | 586 XIIC_TX_DYN_START_MASK; 587 if ((i2c->nmsgs == 1) && msg->len == 0) 588 /* no data and last message -> add STOP */ 589 data |= XIIC_TX_DYN_STOP_MASK; 590 591 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 592 } 593 594 xiic_fill_tx_fifo(i2c); 595 596 /* Clear any pending Tx empty, Tx Error and then enable them. */ 597 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 598 XIIC_INTR_BNB_MASK); 599 } 600 601 static irqreturn_t xiic_isr(int irq, void *dev_id) 602 { 603 struct xiic_i2c *i2c = dev_id; 604 u32 pend, isr, ier; 605 irqreturn_t ret = IRQ_NONE; 606 /* Do not processes a devices interrupts if the device has no 607 * interrupts pending 608 */ 609 610 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); 611 612 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 613 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 614 pend = isr & ier; 615 if (pend) 616 ret = IRQ_WAKE_THREAD; 617 618 return ret; 619 } 620 621 static void __xiic_start_xfer(struct xiic_i2c *i2c) 622 { 623 int first = 1; 624 int fifo_space = xiic_tx_fifo_space(i2c); 625 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 626 __func__, i2c->tx_msg, fifo_space); 627 628 if (!i2c->tx_msg) 629 return; 630 631 i2c->rx_pos = 0; 632 i2c->tx_pos = 0; 633 i2c->state = STATE_START; 634 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { 635 if (!first) { 636 i2c->nmsgs--; 637 i2c->tx_msg++; 638 i2c->tx_pos = 0; 639 } else 640 first = 0; 641 642 if (i2c->tx_msg->flags & I2C_M_RD) { 643 /* we dont date putting several reads in the FIFO */ 644 xiic_start_recv(i2c); 645 return; 646 } else { 647 xiic_start_send(i2c); 648 if (xiic_tx_space(i2c) != 0) { 649 /* the message could not be completely sent */ 650 break; 651 } 652 } 653 654 fifo_space = xiic_tx_fifo_space(i2c); 655 } 656 657 /* there are more messages or the current one could not be completely 658 * put into the FIFO, also enable the half empty interrupt 659 */ 660 if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) 661 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); 662 663 } 664 665 static void xiic_start_xfer(struct xiic_i2c *i2c) 666 { 667 668 __xiic_start_xfer(i2c); 669 } 670 671 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 672 { 673 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 674 int err; 675 676 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 677 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 678 679 err = xiic_busy(i2c); 680 if (err) 681 return err; 682 683 i2c->tx_msg = msgs; 684 i2c->nmsgs = num; 685 686 xiic_start_xfer(i2c); 687 688 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 689 (i2c->state == STATE_DONE), HZ)) 690 return (i2c->state == STATE_DONE) ? num : -EIO; 691 else { 692 i2c->tx_msg = NULL; 693 i2c->rx_msg = NULL; 694 i2c->nmsgs = 0; 695 return -ETIMEDOUT; 696 } 697 } 698 699 static u32 xiic_func(struct i2c_adapter *adap) 700 { 701 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 702 } 703 704 static const struct i2c_algorithm xiic_algorithm = { 705 .master_xfer = xiic_xfer, 706 .functionality = xiic_func, 707 }; 708 709 static struct i2c_adapter xiic_adapter = { 710 .owner = THIS_MODULE, 711 .name = DRIVER_NAME, 712 .class = I2C_CLASS_DEPRECATED, 713 .algo = &xiic_algorithm, 714 }; 715 716 717 static int xiic_i2c_probe(struct platform_device *pdev) 718 { 719 struct xiic_i2c *i2c; 720 struct xiic_i2c_platform_data *pdata; 721 struct resource *res; 722 int ret, irq; 723 u8 i; 724 u32 sr; 725 726 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 727 if (!i2c) 728 return -ENOMEM; 729 730 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 731 i2c->base = devm_ioremap_resource(&pdev->dev, res); 732 if (IS_ERR(i2c->base)) 733 return PTR_ERR(i2c->base); 734 735 irq = platform_get_irq(pdev, 0); 736 if (irq < 0) 737 return irq; 738 739 pdata = dev_get_platdata(&pdev->dev); 740 741 /* hook up driver to tree */ 742 platform_set_drvdata(pdev, i2c); 743 i2c->adap = xiic_adapter; 744 i2c_set_adapdata(&i2c->adap, i2c); 745 i2c->adap.dev.parent = &pdev->dev; 746 i2c->adap.dev.of_node = pdev->dev.of_node; 747 748 spin_lock_init(&i2c->lock); 749 init_waitqueue_head(&i2c->wait); 750 751 ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr, 752 xiic_process, IRQF_ONESHOT, 753 pdev->name, i2c); 754 755 if (ret < 0) { 756 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 757 return ret; 758 } 759 760 /* 761 * Detect endianness 762 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 763 * set, assume that the endianness was wrong and swap. 764 */ 765 i2c->endianness = LITTLE; 766 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 767 /* Reset is cleared in xiic_reinit */ 768 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 769 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 770 i2c->endianness = BIG; 771 772 xiic_reinit(i2c); 773 774 /* add i2c adapter to i2c tree */ 775 ret = i2c_add_adapter(&i2c->adap); 776 if (ret) { 777 dev_err(&pdev->dev, "Failed to add adapter\n"); 778 xiic_deinit(i2c); 779 return ret; 780 } 781 782 if (pdata) { 783 /* add in known devices to the bus */ 784 for (i = 0; i < pdata->num_devices; i++) 785 i2c_new_device(&i2c->adap, pdata->devices + i); 786 } 787 788 return 0; 789 } 790 791 static int xiic_i2c_remove(struct platform_device *pdev) 792 { 793 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 794 795 /* remove adapter & data */ 796 i2c_del_adapter(&i2c->adap); 797 798 xiic_deinit(i2c); 799 800 return 0; 801 } 802 803 #if defined(CONFIG_OF) 804 static const struct of_device_id xiic_of_match[] = { 805 { .compatible = "xlnx,xps-iic-2.00.a", }, 806 {}, 807 }; 808 MODULE_DEVICE_TABLE(of, xiic_of_match); 809 #endif 810 811 static struct platform_driver xiic_i2c_driver = { 812 .probe = xiic_i2c_probe, 813 .remove = xiic_i2c_remove, 814 .driver = { 815 .name = DRIVER_NAME, 816 .of_match_table = of_match_ptr(xiic_of_match), 817 }, 818 }; 819 820 module_platform_driver(xiic_i2c_driver); 821 822 MODULE_AUTHOR("info@mocean-labs.com"); 823 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 824 MODULE_LICENSE("GPL v2"); 825 MODULE_ALIAS("platform:"DRIVER_NAME); 826