1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i2c-xiic.c 4 * Copyright (c) 2002-2007 Xilinx Inc. 5 * Copyright (c) 2009-2010 Intel Corporation 6 * 7 * This code was implemented by Mocean Laboratories AB when porting linux 8 * to the automotive development board Russellville. The copyright holder 9 * as seen in the header is Intel corporation. 10 * Mocean Laboratories forked off the GNU/Linux platform work into a 11 * separate company called Pelagicore AB, which committed the code to the 12 * kernel. 13 */ 14 15 /* Supports: 16 * Xilinx IIC 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/i2c.h> 25 #include <linux/interrupt.h> 26 #include <linux/completion.h> 27 #include <linux/platform_data/i2c-xiic.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 #include <linux/pm_runtime.h> 33 34 #define DRIVER_NAME "xiic-i2c" 35 #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0) 36 #define SMBUS_BLOCK_READ_MIN_LEN 3 37 38 enum xilinx_i2c_state { 39 STATE_DONE, 40 STATE_ERROR, 41 STATE_START 42 }; 43 44 enum xiic_endian { 45 LITTLE, 46 BIG 47 }; 48 49 /** 50 * struct xiic_i2c - Internal representation of the XIIC I2C bus 51 * @dev: Pointer to device structure 52 * @base: Memory base of the HW registers 53 * @completion: Completion for callers 54 * @adap: Kernel adapter representation 55 * @tx_msg: Messages from above to be sent 56 * @lock: Mutual exclusion 57 * @tx_pos: Current pos in TX message 58 * @nmsgs: Number of messages in tx_msg 59 * @rx_msg: Current RX message 60 * @rx_pos: Position within current RX message 61 * @endianness: big/little-endian byte order 62 * @clk: Pointer to AXI4-lite input clock 63 * @state: See STATE_ 64 * @singlemaster: Indicates bus is single master 65 * @dynamic: Mode of controller 66 * @prev_msg_tx: Previous message is Tx 67 * @quirks: To hold platform specific bug info 68 * @smbus_block_read: Flag to handle block read 69 */ 70 struct xiic_i2c { 71 struct device *dev; 72 void __iomem *base; 73 struct completion completion; 74 struct i2c_adapter adap; 75 struct i2c_msg *tx_msg; 76 struct mutex lock; 77 unsigned int tx_pos; 78 unsigned int nmsgs; 79 struct i2c_msg *rx_msg; 80 int rx_pos; 81 enum xiic_endian endianness; 82 struct clk *clk; 83 enum xilinx_i2c_state state; 84 bool singlemaster; 85 bool dynamic; 86 bool prev_msg_tx; 87 u32 quirks; 88 bool smbus_block_read; 89 }; 90 91 struct xiic_version_data { 92 u32 quirks; 93 }; 94 95 #define XIIC_MSB_OFFSET 0 96 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET) 97 98 /* 99 * Register offsets in bytes from RegisterBase. Three is added to the 100 * base offset to access LSB (IBM style) of the word 101 */ 102 #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */ 103 #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */ 104 #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */ 105 #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */ 106 #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */ 107 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 108 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 109 #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */ 110 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 111 #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */ 112 113 /* Control Register masks */ 114 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 115 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 116 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 117 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 118 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 119 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 120 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 121 122 /* Status Register masks */ 123 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 124 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 125 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 126 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 127 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 128 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 129 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 130 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 131 132 /* Interrupt Status Register masks Interrupt occurs when... */ 133 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 134 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 135 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 136 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 137 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 138 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 139 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 140 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 141 142 /* The following constants specify the depth of the FIFOs */ 143 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 144 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 145 146 /* The following constants specify groups of interrupts that are typically 147 * enabled or disables at the same time 148 */ 149 #define XIIC_TX_INTERRUPTS \ 150 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 151 152 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 153 154 /* 155 * Tx Fifo upper bit masks. 156 */ 157 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 158 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 159 160 /* Dynamic mode constants */ 161 #define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */ 162 163 /* 164 * The following constants define the register offsets for the Interrupt 165 * registers. There are some holes in the memory map for reserved addresses 166 * to allow other registers to be added and still match the memory map of the 167 * interrupt controller registers 168 */ 169 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 170 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 171 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 172 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 173 174 #define XIIC_RESET_MASK 0xAUL 175 176 #define XIIC_PM_TIMEOUT 1000 /* ms */ 177 /* timeout waiting for the controller to respond */ 178 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 179 /* timeout waiting for the controller finish transfers */ 180 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 181 182 /* 183 * The following constant is used for the device global interrupt enable 184 * register, to enable all interrupts for the device, this is the only bit 185 * in the register 186 */ 187 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 188 189 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 190 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 191 192 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 193 static void __xiic_start_xfer(struct xiic_i2c *i2c); 194 195 /* 196 * For the register read and write functions, a little-endian and big-endian 197 * version are necessary. Endianness is detected during the probe function. 198 * Only the least significant byte [doublet] of the register are ever 199 * accessed. This requires an offset of 3 [2] from the base address for 200 * big-endian systems. 201 */ 202 203 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 204 { 205 if (i2c->endianness == LITTLE) 206 iowrite8(value, i2c->base + reg); 207 else 208 iowrite8(value, i2c->base + reg + 3); 209 } 210 211 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 212 { 213 u8 ret; 214 215 if (i2c->endianness == LITTLE) 216 ret = ioread8(i2c->base + reg); 217 else 218 ret = ioread8(i2c->base + reg + 3); 219 return ret; 220 } 221 222 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 223 { 224 if (i2c->endianness == LITTLE) 225 iowrite16(value, i2c->base + reg); 226 else 227 iowrite16be(value, i2c->base + reg + 2); 228 } 229 230 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 231 { 232 if (i2c->endianness == LITTLE) 233 iowrite32(value, i2c->base + reg); 234 else 235 iowrite32be(value, i2c->base + reg); 236 } 237 238 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 239 { 240 u32 ret; 241 242 if (i2c->endianness == LITTLE) 243 ret = ioread32(i2c->base + reg); 244 else 245 ret = ioread32be(i2c->base + reg); 246 return ret; 247 } 248 249 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 250 { 251 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 252 253 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 254 } 255 256 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 257 { 258 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 259 260 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 261 } 262 263 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 264 { 265 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 266 267 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 268 } 269 270 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 271 { 272 xiic_irq_clr(i2c, mask); 273 xiic_irq_en(i2c, mask); 274 } 275 276 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 277 { 278 u8 sr; 279 unsigned long timeout; 280 281 timeout = jiffies + XIIC_I2C_TIMEOUT; 282 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 283 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 284 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 285 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 286 if (time_after(jiffies, timeout)) { 287 dev_err(i2c->dev, "Failed to clear rx fifo\n"); 288 return -ETIMEDOUT; 289 } 290 } 291 292 return 0; 293 } 294 295 static int xiic_wait_tx_empty(struct xiic_i2c *i2c) 296 { 297 u8 isr; 298 unsigned long timeout; 299 300 timeout = jiffies + XIIC_I2C_TIMEOUT; 301 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 302 !(isr & XIIC_INTR_TX_EMPTY_MASK); 303 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { 304 if (time_after(jiffies, timeout)) { 305 dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); 306 return -ETIMEDOUT; 307 } 308 } 309 310 return 0; 311 } 312 313 static int xiic_reinit(struct xiic_i2c *i2c) 314 { 315 int ret; 316 317 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 318 319 /* Set receive Fifo depth to maximum (zero based). */ 320 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 321 322 /* Reset Tx Fifo. */ 323 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 324 325 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 326 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 327 328 /* make sure RX fifo is empty */ 329 ret = xiic_clear_rx_fifo(i2c); 330 if (ret) 331 return ret; 332 333 /* Enable interrupts */ 334 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 335 336 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 337 338 return 0; 339 } 340 341 static void xiic_deinit(struct xiic_i2c *i2c) 342 { 343 u8 cr; 344 345 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 346 347 /* Disable IIC Device. */ 348 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 349 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 350 } 351 352 static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) 353 { 354 u8 rxmsg_len, rfd_set = 0; 355 356 /* 357 * Clear the I2C_M_RECV_LEN flag to avoid setting 358 * message length again 359 */ 360 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN; 361 362 /* Set smbus_block_read flag to identify in isr */ 363 i2c->smbus_block_read = true; 364 365 /* Read byte from rx fifo and set message length */ 366 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 367 368 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len; 369 370 /* Check if received length is valid */ 371 if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) { 372 /* Set Receive fifo depth */ 373 if (rxmsg_len > IIC_RX_FIFO_DEPTH) { 374 /* 375 * When Rx msg len greater than or equal to Rx fifo capacity 376 * Receive fifo depth should set to Rx fifo capacity minus 1 377 */ 378 rfd_set = IIC_RX_FIFO_DEPTH - 1; 379 i2c->rx_msg->len = rxmsg_len + 1; 380 } else if ((rxmsg_len == 1) || 381 (rxmsg_len == 0)) { 382 /* 383 * Minimum of 3 bytes required to exit cleanly. 1 byte 384 * already received, Second byte is being received. Have 385 * to set NACK in read_rx before receiving the last byte 386 */ 387 rfd_set = 0; 388 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN; 389 } else { 390 /* 391 * When Rx msg len less than Rx fifo capacity 392 * Receive fifo depth should set to Rx msg len minus 2 393 */ 394 rfd_set = rxmsg_len - 2; 395 i2c->rx_msg->len = rxmsg_len + 1; 396 } 397 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); 398 399 return; 400 } 401 402 /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */ 403 i2c->tx_msg->len = 3; 404 i2c->smbus_block_read = false; 405 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); 406 } 407 408 static void xiic_read_rx(struct xiic_i2c *i2c) 409 { 410 u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; 411 u32 bytes_rem = 0; 412 int i; 413 414 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 415 416 dev_dbg(i2c->adap.dev.parent, 417 "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", 418 __func__, bytes_in_fifo, xiic_rx_space(i2c), 419 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 420 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 421 422 if (bytes_in_fifo > xiic_rx_space(i2c)) 423 bytes_in_fifo = xiic_rx_space(i2c); 424 425 bytes_to_read = bytes_in_fifo; 426 427 if (!i2c->dynamic) { 428 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; 429 430 /* Set msg length if smbus_block_read */ 431 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) { 432 xiic_smbus_block_read_setup(i2c); 433 return; 434 } 435 436 if (bytes_rem > IIC_RX_FIFO_DEPTH) { 437 bytes_to_read = bytes_in_fifo; 438 } else if (bytes_rem > 1) { 439 bytes_to_read = bytes_rem - 1; 440 } else if (bytes_rem == 1) { 441 bytes_to_read = 1; 442 /* Set NACK in CR to indicate slave transmitter */ 443 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 444 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | 445 XIIC_CR_NO_ACK_MASK); 446 } else if (bytes_rem == 0) { 447 bytes_to_read = bytes_in_fifo; 448 449 /* Generate stop on the bus if it is last message */ 450 if (i2c->nmsgs == 1) { 451 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 452 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 453 ~XIIC_CR_MSMS_MASK); 454 } 455 456 /* Make TXACK=0, clean up for next transaction */ 457 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 458 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 459 ~XIIC_CR_NO_ACK_MASK); 460 } 461 } 462 463 /* Read the fifo */ 464 for (i = 0; i < bytes_to_read; i++) { 465 i2c->rx_msg->buf[i2c->rx_pos++] = 466 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 467 } 468 469 if (i2c->dynamic) { 470 u8 bytes; 471 472 /* Receive remaining bytes if less than fifo depth */ 473 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); 474 bytes--; 475 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); 476 } 477 } 478 479 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 480 { 481 /* return the actual space left in the FIFO */ 482 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 483 } 484 485 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 486 { 487 u8 fifo_space = xiic_tx_fifo_space(i2c); 488 int len = xiic_tx_space(i2c); 489 490 len = (len > fifo_space) ? fifo_space : len; 491 492 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 493 __func__, len, fifo_space); 494 495 while (len--) { 496 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 497 498 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { 499 /* last message in transfer -> STOP */ 500 if (i2c->dynamic) { 501 data |= XIIC_TX_DYN_STOP_MASK; 502 } else { 503 u8 cr; 504 int status; 505 506 /* Wait till FIFO is empty so STOP is sent last */ 507 status = xiic_wait_tx_empty(i2c); 508 if (status) 509 return; 510 511 /* Write to CR to stop */ 512 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 513 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 514 ~XIIC_CR_MSMS_MASK); 515 } 516 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 517 } 518 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 519 } 520 } 521 522 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) 523 { 524 i2c->tx_msg = NULL; 525 i2c->rx_msg = NULL; 526 i2c->nmsgs = 0; 527 i2c->state = code; 528 complete(&i2c->completion); 529 } 530 531 static irqreturn_t xiic_process(int irq, void *dev_id) 532 { 533 struct xiic_i2c *i2c = dev_id; 534 u32 pend, isr, ier; 535 u32 clr = 0; 536 int xfer_more = 0; 537 int wakeup_req = 0; 538 enum xilinx_i2c_state wakeup_code = STATE_DONE; 539 int ret; 540 541 /* Get the interrupt Status from the IPIF. There is no clearing of 542 * interrupts in the IPIF. Interrupts must be cleared at the source. 543 * To find which interrupts are pending; AND interrupts pending with 544 * interrupts masked. 545 */ 546 mutex_lock(&i2c->lock); 547 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 548 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 549 pend = isr & ier; 550 551 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 552 __func__, ier, isr, pend); 553 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 554 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 555 i2c->tx_msg, i2c->nmsgs); 556 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", 557 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 558 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 559 560 /* Service requesting interrupt */ 561 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 562 ((pend & XIIC_INTR_TX_ERROR_MASK) && 563 !(pend & XIIC_INTR_RX_FULL_MASK))) { 564 /* bus arbritration lost, or... 565 * Transmit error _OR_ RX completed 566 * if this happens when RX_FULL is not set 567 * this is probably a TX error 568 */ 569 570 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 571 572 /* dynamic mode seem to suffer from problems if we just flushes 573 * fifos and the next message is a TX with len 0 (only addr) 574 * reset the IP instead of just flush fifos 575 */ 576 ret = xiic_reinit(i2c); 577 if (!ret) 578 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); 579 580 if (i2c->rx_msg) { 581 wakeup_req = 1; 582 wakeup_code = STATE_ERROR; 583 } 584 if (i2c->tx_msg) { 585 wakeup_req = 1; 586 wakeup_code = STATE_ERROR; 587 } 588 } 589 if (pend & XIIC_INTR_RX_FULL_MASK) { 590 /* Receive register/FIFO is full */ 591 592 clr |= XIIC_INTR_RX_FULL_MASK; 593 if (!i2c->rx_msg) { 594 dev_dbg(i2c->adap.dev.parent, 595 "%s unexpected RX IRQ\n", __func__); 596 xiic_clear_rx_fifo(i2c); 597 goto out; 598 } 599 600 xiic_read_rx(i2c); 601 if (xiic_rx_space(i2c) == 0) { 602 /* this is the last part of the message */ 603 i2c->rx_msg = NULL; 604 605 /* also clear TX error if there (RX complete) */ 606 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 607 608 dev_dbg(i2c->adap.dev.parent, 609 "%s end of message, nmsgs: %d\n", 610 __func__, i2c->nmsgs); 611 612 /* send next message if this wasn't the last, 613 * otherwise the transfer will be finialise when 614 * receiving the bus not busy interrupt 615 */ 616 if (i2c->nmsgs > 1) { 617 i2c->nmsgs--; 618 i2c->tx_msg++; 619 dev_dbg(i2c->adap.dev.parent, 620 "%s will start next...\n", __func__); 621 xfer_more = 1; 622 } 623 } 624 } 625 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 626 /* Transmit register/FIFO is empty or ½ empty */ 627 628 clr |= (pend & 629 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 630 631 if (!i2c->tx_msg) { 632 dev_dbg(i2c->adap.dev.parent, 633 "%s unexpected TX IRQ\n", __func__); 634 goto out; 635 } 636 637 xiic_fill_tx_fifo(i2c); 638 639 /* current message sent and there is space in the fifo */ 640 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 641 dev_dbg(i2c->adap.dev.parent, 642 "%s end of message sent, nmsgs: %d\n", 643 __func__, i2c->nmsgs); 644 if (i2c->nmsgs > 1) { 645 i2c->nmsgs--; 646 i2c->tx_msg++; 647 xfer_more = 1; 648 } else { 649 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 650 651 dev_dbg(i2c->adap.dev.parent, 652 "%s Got TX IRQ but no more to do...\n", 653 __func__); 654 } 655 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 656 /* current frame is sent and is last, 657 * make sure to disable tx half 658 */ 659 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 660 } 661 662 if (pend & XIIC_INTR_BNB_MASK) { 663 /* IIC bus has transitioned to not busy */ 664 clr |= XIIC_INTR_BNB_MASK; 665 666 /* The bus is not busy, disable BusNotBusy interrupt */ 667 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 668 669 if (i2c->tx_msg && i2c->smbus_block_read) { 670 i2c->smbus_block_read = false; 671 /* Set requested message len=1 to indicate STATE_DONE */ 672 i2c->tx_msg->len = 1; 673 } 674 675 if (!i2c->tx_msg) 676 goto out; 677 678 wakeup_req = 1; 679 680 if (i2c->nmsgs == 1 && !i2c->rx_msg && 681 xiic_tx_space(i2c) == 0) 682 wakeup_code = STATE_DONE; 683 else 684 wakeup_code = STATE_ERROR; 685 } 686 687 out: 688 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 689 690 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 691 if (xfer_more) 692 __xiic_start_xfer(i2c); 693 if (wakeup_req) 694 xiic_wakeup(i2c, wakeup_code); 695 696 WARN_ON(xfer_more && wakeup_req); 697 698 mutex_unlock(&i2c->lock); 699 return IRQ_HANDLED; 700 } 701 702 static int xiic_bus_busy(struct xiic_i2c *i2c) 703 { 704 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 705 706 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 707 } 708 709 static int xiic_busy(struct xiic_i2c *i2c) 710 { 711 int tries = 3; 712 int err; 713 714 if (i2c->tx_msg || i2c->rx_msg) 715 return -EBUSY; 716 717 /* In single master mode bus can only be busy, when in use by this 718 * driver. If the register indicates bus being busy for some reason we 719 * should ignore it, since bus will never be released and i2c will be 720 * stuck forever. 721 */ 722 if (i2c->singlemaster) { 723 return 0; 724 } 725 726 /* for instance if previous transfer was terminated due to TX error 727 * it might be that the bus is on it's way to become available 728 * give it at most 3 ms to wake 729 */ 730 err = xiic_bus_busy(i2c); 731 while (err && tries--) { 732 msleep(1); 733 err = xiic_bus_busy(i2c); 734 } 735 736 return err; 737 } 738 739 static void xiic_start_recv(struct xiic_i2c *i2c) 740 { 741 u16 rx_watermark; 742 u8 cr = 0, rfd_set = 0; 743 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 744 unsigned long flags; 745 746 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 747 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 748 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 749 750 /* Disable Tx interrupts */ 751 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); 752 753 if (i2c->dynamic) { 754 u8 bytes; 755 u16 val; 756 757 /* Clear and enable Rx full interrupt. */ 758 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 759 XIIC_INTR_TX_ERROR_MASK); 760 761 /* 762 * We want to get all but last byte, because the TX_ERROR IRQ 763 * is used to indicate error ACK on the address, and 764 * negative ack on the last received byte, so to not mix 765 * them receive all but last. 766 * In the case where there is only one byte to receive 767 * we can check if ERROR and RX full is set at the same time 768 */ 769 rx_watermark = msg->len; 770 bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH); 771 772 if (rx_watermark > 0) 773 bytes--; 774 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); 775 776 local_irq_save(flags); 777 778 /* write the address */ 779 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 780 i2c_8bit_addr_from_msg(msg) | 781 XIIC_TX_DYN_START_MASK); 782 783 /* If last message, include dynamic stop bit with length */ 784 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; 785 val |= msg->len; 786 787 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); 788 789 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 790 791 local_irq_restore(flags); 792 } else { 793 /* 794 * If previous message is Tx, make sure that Tx FIFO is empty 795 * before starting a new transfer as the repeated start in 796 * standard mode can corrupt the transaction if there are 797 * still bytes to be transmitted in FIFO 798 */ 799 if (i2c->prev_msg_tx) { 800 int status; 801 802 status = xiic_wait_tx_empty(i2c); 803 if (status) 804 return; 805 } 806 807 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 808 809 /* Set Receive fifo depth */ 810 rx_watermark = msg->len; 811 if (rx_watermark > IIC_RX_FIFO_DEPTH) { 812 rfd_set = IIC_RX_FIFO_DEPTH - 1; 813 } else if (rx_watermark == 1) { 814 rfd_set = rx_watermark - 1; 815 816 /* Set No_ACK, except for smbus_block_read */ 817 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) { 818 /* Handle single byte transfer separately */ 819 cr |= XIIC_CR_NO_ACK_MASK; 820 } 821 } else if (rx_watermark == 0) { 822 rfd_set = rx_watermark; 823 } else { 824 rfd_set = rx_watermark - 2; 825 } 826 /* Check if RSTA should be set */ 827 if (cr & XIIC_CR_MSMS_MASK) { 828 /* Already a master, RSTA should be set */ 829 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 830 XIIC_CR_REPEATED_START_MASK) & 831 ~(XIIC_CR_DIR_IS_TX_MASK)); 832 } 833 834 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); 835 836 /* Clear and enable Rx full and transmit complete interrupts */ 837 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 838 XIIC_INTR_TX_ERROR_MASK); 839 840 /* Write the address */ 841 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 842 i2c_8bit_addr_from_msg(msg)); 843 844 /* Write to Control Register,to start transaction in Rx mode */ 845 if ((cr & XIIC_CR_MSMS_MASK) == 0) { 846 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 847 XIIC_CR_MSMS_MASK) 848 & ~(XIIC_CR_DIR_IS_TX_MASK)); 849 } 850 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", 851 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 852 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 853 } 854 855 if (i2c->nmsgs == 1) 856 /* very last, enable bus not busy as well */ 857 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 858 859 /* the message is tx:ed */ 860 i2c->tx_pos = msg->len; 861 862 /* Enable interrupts */ 863 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 864 865 i2c->prev_msg_tx = false; 866 } 867 868 static void xiic_start_send(struct xiic_i2c *i2c) 869 { 870 u8 cr = 0; 871 u16 data; 872 struct i2c_msg *msg = i2c->tx_msg; 873 874 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 875 __func__, msg, msg->len); 876 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 877 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 878 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 879 880 if (i2c->dynamic) { 881 /* write the address */ 882 data = i2c_8bit_addr_from_msg(msg) | 883 XIIC_TX_DYN_START_MASK; 884 885 if (i2c->nmsgs == 1 && msg->len == 0) 886 /* no data and last message -> add STOP */ 887 data |= XIIC_TX_DYN_STOP_MASK; 888 889 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 890 891 /* Clear any pending Tx empty, Tx Error and then enable them */ 892 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | 893 XIIC_INTR_TX_ERROR_MASK | 894 XIIC_INTR_BNB_MASK | 895 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? 896 XIIC_INTR_TX_HALF_MASK : 0)); 897 898 xiic_fill_tx_fifo(i2c); 899 } else { 900 /* 901 * If previous message is Tx, make sure that Tx FIFO is empty 902 * before starting a new transfer as the repeated start in 903 * standard mode can corrupt the transaction if there are 904 * still bytes to be transmitted in FIFO 905 */ 906 if (i2c->prev_msg_tx) { 907 int status; 908 909 status = xiic_wait_tx_empty(i2c); 910 if (status) 911 return; 912 } 913 /* Check if RSTA should be set */ 914 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 915 if (cr & XIIC_CR_MSMS_MASK) { 916 /* Already a master, RSTA should be set */ 917 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 918 XIIC_CR_REPEATED_START_MASK | 919 XIIC_CR_DIR_IS_TX_MASK) & 920 ~(XIIC_CR_NO_ACK_MASK)); 921 } 922 923 /* Write address to FIFO */ 924 data = i2c_8bit_addr_from_msg(msg); 925 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 926 927 /* Fill fifo */ 928 xiic_fill_tx_fifo(i2c); 929 930 if ((cr & XIIC_CR_MSMS_MASK) == 0) { 931 /* Start Tx by writing to CR */ 932 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 933 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | 934 XIIC_CR_MSMS_MASK | 935 XIIC_CR_DIR_IS_TX_MASK); 936 } 937 938 /* Clear any pending Tx empty, Tx Error and then enable them */ 939 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | 940 XIIC_INTR_TX_ERROR_MASK | 941 XIIC_INTR_BNB_MASK); 942 } 943 i2c->prev_msg_tx = true; 944 } 945 946 static void __xiic_start_xfer(struct xiic_i2c *i2c) 947 { 948 int fifo_space = xiic_tx_fifo_space(i2c); 949 950 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 951 __func__, i2c->tx_msg, fifo_space); 952 953 if (!i2c->tx_msg) 954 return; 955 956 i2c->rx_pos = 0; 957 i2c->tx_pos = 0; 958 i2c->state = STATE_START; 959 if (i2c->tx_msg->flags & I2C_M_RD) { 960 /* we dont date putting several reads in the FIFO */ 961 xiic_start_recv(i2c); 962 } else { 963 xiic_start_send(i2c); 964 } 965 } 966 967 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) 968 { 969 bool broken_read, max_read_len, smbus_blk_read; 970 int ret, count; 971 972 mutex_lock(&i2c->lock); 973 974 ret = xiic_busy(i2c); 975 if (ret) 976 goto out; 977 978 i2c->tx_msg = msgs; 979 i2c->rx_msg = NULL; 980 i2c->nmsgs = num; 981 init_completion(&i2c->completion); 982 983 /* Decide standard mode or Dynamic mode */ 984 i2c->dynamic = true; 985 986 /* Initialize prev message type */ 987 i2c->prev_msg_tx = false; 988 989 /* 990 * Scan through nmsgs, use dynamic mode when none of the below three 991 * conditions occur. We need standard mode even if one condition holds 992 * true in the entire array of messages in a single transfer. 993 * If read transaction as dynamic mode is broken for delayed reads 994 * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions. 995 * If read length is > 255 bytes. 996 * If smbus_block_read transaction. 997 */ 998 for (count = 0; count < i2c->nmsgs; count++) { 999 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && 1000 (i2c->tx_msg[count].flags & I2C_M_RD); 1001 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && 1002 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); 1003 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); 1004 1005 if (broken_read || max_read_len || smbus_blk_read) { 1006 i2c->dynamic = false; 1007 break; 1008 } 1009 } 1010 1011 ret = xiic_reinit(i2c); 1012 if (!ret) 1013 __xiic_start_xfer(i2c); 1014 1015 out: 1016 mutex_unlock(&i2c->lock); 1017 1018 return ret; 1019 } 1020 1021 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 1022 { 1023 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 1024 int err; 1025 1026 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 1027 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 1028 1029 err = pm_runtime_resume_and_get(i2c->dev); 1030 if (err < 0) 1031 return err; 1032 1033 err = xiic_start_xfer(i2c, msgs, num); 1034 if (err < 0) { 1035 dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 1036 return err; 1037 } 1038 1039 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); 1040 mutex_lock(&i2c->lock); 1041 if (err == 0) { /* Timeout */ 1042 i2c->tx_msg = NULL; 1043 i2c->rx_msg = NULL; 1044 i2c->nmsgs = 0; 1045 err = -ETIMEDOUT; 1046 } else if (err < 0) { /* Completion error */ 1047 i2c->tx_msg = NULL; 1048 i2c->rx_msg = NULL; 1049 i2c->nmsgs = 0; 1050 } else { 1051 err = (i2c->state == STATE_DONE) ? num : -EIO; 1052 } 1053 mutex_unlock(&i2c->lock); 1054 pm_runtime_mark_last_busy(i2c->dev); 1055 pm_runtime_put_autosuspend(i2c->dev); 1056 return err; 1057 } 1058 1059 static u32 xiic_func(struct i2c_adapter *adap) 1060 { 1061 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; 1062 } 1063 1064 static const struct i2c_algorithm xiic_algorithm = { 1065 .master_xfer = xiic_xfer, 1066 .functionality = xiic_func, 1067 }; 1068 1069 static const struct i2c_adapter xiic_adapter = { 1070 .owner = THIS_MODULE, 1071 .class = I2C_CLASS_DEPRECATED, 1072 .algo = &xiic_algorithm, 1073 }; 1074 1075 static const struct xiic_version_data xiic_2_00 = { 1076 .quirks = DYNAMIC_MODE_READ_BROKEN_BIT, 1077 }; 1078 1079 #if defined(CONFIG_OF) 1080 static const struct of_device_id xiic_of_match[] = { 1081 { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 }, 1082 {}, 1083 }; 1084 MODULE_DEVICE_TABLE(of, xiic_of_match); 1085 #endif 1086 1087 static int xiic_i2c_probe(struct platform_device *pdev) 1088 { 1089 struct xiic_i2c *i2c; 1090 struct xiic_i2c_platform_data *pdata; 1091 const struct of_device_id *match; 1092 struct resource *res; 1093 int ret, irq; 1094 u8 i; 1095 u32 sr; 1096 1097 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1098 if (!i2c) 1099 return -ENOMEM; 1100 1101 match = of_match_node(xiic_of_match, pdev->dev.of_node); 1102 if (match && match->data) { 1103 const struct xiic_version_data *data = match->data; 1104 1105 i2c->quirks = data->quirks; 1106 } 1107 1108 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1109 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1110 if (IS_ERR(i2c->base)) 1111 return PTR_ERR(i2c->base); 1112 1113 irq = platform_get_irq(pdev, 0); 1114 if (irq < 0) 1115 return irq; 1116 1117 pdata = dev_get_platdata(&pdev->dev); 1118 1119 /* hook up driver to tree */ 1120 platform_set_drvdata(pdev, i2c); 1121 i2c->adap = xiic_adapter; 1122 i2c_set_adapdata(&i2c->adap, i2c); 1123 i2c->adap.dev.parent = &pdev->dev; 1124 i2c->adap.dev.of_node = pdev->dev.of_node; 1125 snprintf(i2c->adap.name, sizeof(i2c->adap.name), 1126 DRIVER_NAME " %s", pdev->name); 1127 1128 mutex_init(&i2c->lock); 1129 1130 i2c->clk = devm_clk_get(&pdev->dev, NULL); 1131 if (IS_ERR(i2c->clk)) 1132 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 1133 "input clock not found.\n"); 1134 1135 ret = clk_prepare_enable(i2c->clk); 1136 if (ret) { 1137 dev_err(&pdev->dev, "Unable to enable clock.\n"); 1138 return ret; 1139 } 1140 i2c->dev = &pdev->dev; 1141 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 1142 pm_runtime_use_autosuspend(i2c->dev); 1143 pm_runtime_set_active(i2c->dev); 1144 pm_runtime_enable(i2c->dev); 1145 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1146 xiic_process, IRQF_ONESHOT, 1147 pdev->name, i2c); 1148 1149 if (ret < 0) { 1150 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 1151 goto err_clk_dis; 1152 } 1153 1154 i2c->singlemaster = 1155 of_property_read_bool(pdev->dev.of_node, "single-master"); 1156 1157 /* 1158 * Detect endianness 1159 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 1160 * set, assume that the endianness was wrong and swap. 1161 */ 1162 i2c->endianness = LITTLE; 1163 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 1164 /* Reset is cleared in xiic_reinit */ 1165 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 1166 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 1167 i2c->endianness = BIG; 1168 1169 ret = xiic_reinit(i2c); 1170 if (ret < 0) { 1171 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 1172 goto err_clk_dis; 1173 } 1174 1175 /* add i2c adapter to i2c tree */ 1176 ret = i2c_add_adapter(&i2c->adap); 1177 if (ret) { 1178 xiic_deinit(i2c); 1179 goto err_clk_dis; 1180 } 1181 1182 if (pdata) { 1183 /* add in known devices to the bus */ 1184 for (i = 0; i < pdata->num_devices; i++) 1185 i2c_new_client_device(&i2c->adap, pdata->devices + i); 1186 } 1187 1188 return 0; 1189 1190 err_clk_dis: 1191 pm_runtime_set_suspended(&pdev->dev); 1192 pm_runtime_disable(&pdev->dev); 1193 clk_disable_unprepare(i2c->clk); 1194 return ret; 1195 } 1196 1197 static int xiic_i2c_remove(struct platform_device *pdev) 1198 { 1199 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 1200 int ret; 1201 1202 /* remove adapter & data */ 1203 i2c_del_adapter(&i2c->adap); 1204 1205 ret = pm_runtime_get_sync(i2c->dev); 1206 1207 if (ret < 0) 1208 dev_warn(&pdev->dev, "Failed to activate device for removal (%pe)\n", 1209 ERR_PTR(ret)); 1210 else 1211 xiic_deinit(i2c); 1212 1213 pm_runtime_put_sync(i2c->dev); 1214 clk_disable_unprepare(i2c->clk); 1215 pm_runtime_disable(&pdev->dev); 1216 pm_runtime_set_suspended(&pdev->dev); 1217 pm_runtime_dont_use_autosuspend(&pdev->dev); 1218 1219 return 0; 1220 } 1221 1222 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 1223 { 1224 struct xiic_i2c *i2c = dev_get_drvdata(dev); 1225 1226 clk_disable(i2c->clk); 1227 1228 return 0; 1229 } 1230 1231 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 1232 { 1233 struct xiic_i2c *i2c = dev_get_drvdata(dev); 1234 int ret; 1235 1236 ret = clk_enable(i2c->clk); 1237 if (ret) { 1238 dev_err(dev, "Cannot enable clock.\n"); 1239 return ret; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static const struct dev_pm_ops xiic_dev_pm_ops = { 1246 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 1247 xiic_i2c_runtime_resume, NULL) 1248 }; 1249 1250 static struct platform_driver xiic_i2c_driver = { 1251 .probe = xiic_i2c_probe, 1252 .remove = xiic_i2c_remove, 1253 .driver = { 1254 .name = DRIVER_NAME, 1255 .of_match_table = of_match_ptr(xiic_of_match), 1256 .pm = &xiic_dev_pm_ops, 1257 }, 1258 }; 1259 1260 module_platform_driver(xiic_i2c_driver); 1261 1262 MODULE_ALIAS("platform:" DRIVER_NAME); 1263 MODULE_AUTHOR("info@mocean-labs.com"); 1264 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 1265 MODULE_LICENSE("GPL v2"); 1266