1 /* 2 * i2c-xiic.c 3 * Copyright (c) 2002-2007 Xilinx Inc. 4 * Copyright (c) 2009-2010 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * 20 * This code was implemented by Mocean Laboratories AB when porting linux 21 * to the automotive development board Russellville. The copyright holder 22 * as seen in the header is Intel corporation. 23 * Mocean Laboratories forked off the GNU/Linux platform work into a 24 * separate company called Pelagicore AB, which committed the code to the 25 * kernel. 26 */ 27 28 /* Supports: 29 * Xilinx IIC 30 */ 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/errno.h> 34 #include <linux/err.h> 35 #include <linux/delay.h> 36 #include <linux/platform_device.h> 37 #include <linux/i2c.h> 38 #include <linux/interrupt.h> 39 #include <linux/wait.h> 40 #include <linux/i2c-xiic.h> 41 #include <linux/io.h> 42 #include <linux/slab.h> 43 #include <linux/of.h> 44 45 #define DRIVER_NAME "xiic-i2c" 46 47 enum xilinx_i2c_state { 48 STATE_DONE, 49 STATE_ERROR, 50 STATE_START 51 }; 52 53 /** 54 * struct xiic_i2c - Internal representation of the XIIC I2C bus 55 * @base: Memory base of the HW registers 56 * @wait: Wait queue for callers 57 * @adap: Kernel adapter representation 58 * @tx_msg: Messages from above to be sent 59 * @lock: Mutual exclusion 60 * @tx_pos: Current pos in TX message 61 * @nmsgs: Number of messages in tx_msg 62 * @state: See STATE_ 63 * @rx_msg: Current RX message 64 * @rx_pos: Position within current RX message 65 */ 66 struct xiic_i2c { 67 void __iomem *base; 68 wait_queue_head_t wait; 69 struct i2c_adapter adap; 70 struct i2c_msg *tx_msg; 71 spinlock_t lock; 72 unsigned int tx_pos; 73 unsigned int nmsgs; 74 enum xilinx_i2c_state state; 75 struct i2c_msg *rx_msg; 76 int rx_pos; 77 }; 78 79 80 #define XIIC_MSB_OFFSET 0 81 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 82 83 /* 84 * Register offsets in bytes from RegisterBase. Three is added to the 85 * base offset to access LSB (IBM style) of the word 86 */ 87 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 88 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 89 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 90 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 91 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 92 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 93 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 94 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 95 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 96 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 97 98 /* Control Register masks */ 99 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 100 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 101 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 102 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 103 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 104 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 105 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 106 107 /* Status Register masks */ 108 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 109 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 110 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 111 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 112 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 113 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 114 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 115 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 116 117 /* Interrupt Status Register masks Interrupt occurs when... */ 118 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 119 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 120 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 121 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 122 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 123 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 124 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 125 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 126 127 /* The following constants specify the depth of the FIFOs */ 128 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 129 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 130 131 /* The following constants specify groups of interrupts that are typically 132 * enabled or disables at the same time 133 */ 134 #define XIIC_TX_INTERRUPTS \ 135 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 136 137 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 138 139 /* The following constants are used with the following macros to specify the 140 * operation, a read or write operation. 141 */ 142 #define XIIC_READ_OPERATION 1 143 #define XIIC_WRITE_OPERATION 0 144 145 /* 146 * Tx Fifo upper bit masks. 147 */ 148 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 149 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 150 151 /* 152 * The following constants define the register offsets for the Interrupt 153 * registers. There are some holes in the memory map for reserved addresses 154 * to allow other registers to be added and still match the memory map of the 155 * interrupt controller registers 156 */ 157 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 158 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 159 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 160 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 161 162 #define XIIC_RESET_MASK 0xAUL 163 164 /* 165 * The following constant is used for the device global interrupt enable 166 * register, to enable all interrupts for the device, this is the only bit 167 * in the register 168 */ 169 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 170 171 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 172 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 173 174 static void xiic_start_xfer(struct xiic_i2c *i2c); 175 static void __xiic_start_xfer(struct xiic_i2c *i2c); 176 177 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 178 { 179 iowrite8(value, i2c->base + reg); 180 } 181 182 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 183 { 184 return ioread8(i2c->base + reg); 185 } 186 187 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 188 { 189 iowrite16(value, i2c->base + reg); 190 } 191 192 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 193 { 194 iowrite32(value, i2c->base + reg); 195 } 196 197 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 198 { 199 return ioread32(i2c->base + reg); 200 } 201 202 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 203 { 204 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 205 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 206 } 207 208 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 209 { 210 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 211 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 212 } 213 214 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 215 { 216 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 217 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 218 } 219 220 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 221 { 222 xiic_irq_clr(i2c, mask); 223 xiic_irq_en(i2c, mask); 224 } 225 226 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) 227 { 228 u8 sr; 229 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 230 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 231 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) 232 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 233 } 234 235 static void xiic_reinit(struct xiic_i2c *i2c) 236 { 237 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 238 239 /* Set receive Fifo depth to maximum (zero based). */ 240 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 241 242 /* Reset Tx Fifo. */ 243 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 244 245 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 246 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 247 248 /* make sure RX fifo is empty */ 249 xiic_clear_rx_fifo(i2c); 250 251 /* Enable interrupts */ 252 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 253 254 xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK); 255 } 256 257 static void xiic_deinit(struct xiic_i2c *i2c) 258 { 259 u8 cr; 260 261 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 262 263 /* Disable IIC Device. */ 264 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 265 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 266 } 267 268 static void xiic_read_rx(struct xiic_i2c *i2c) 269 { 270 u8 bytes_in_fifo; 271 int i; 272 273 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 274 275 dev_dbg(i2c->adap.dev.parent, 276 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 277 __func__, bytes_in_fifo, xiic_rx_space(i2c), 278 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 279 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 280 281 if (bytes_in_fifo > xiic_rx_space(i2c)) 282 bytes_in_fifo = xiic_rx_space(i2c); 283 284 for (i = 0; i < bytes_in_fifo; i++) 285 i2c->rx_msg->buf[i2c->rx_pos++] = 286 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 287 288 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 289 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 290 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 291 } 292 293 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 294 { 295 /* return the actual space left in the FIFO */ 296 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 297 } 298 299 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 300 { 301 u8 fifo_space = xiic_tx_fifo_space(i2c); 302 int len = xiic_tx_space(i2c); 303 304 len = (len > fifo_space) ? fifo_space : len; 305 306 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 307 __func__, len, fifo_space); 308 309 while (len--) { 310 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 311 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 312 /* last message in transfer -> STOP */ 313 data |= XIIC_TX_DYN_STOP_MASK; 314 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 315 } 316 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 317 } 318 } 319 320 static void xiic_wakeup(struct xiic_i2c *i2c, int code) 321 { 322 i2c->tx_msg = NULL; 323 i2c->rx_msg = NULL; 324 i2c->nmsgs = 0; 325 i2c->state = code; 326 wake_up(&i2c->wait); 327 } 328 329 static void xiic_process(struct xiic_i2c *i2c) 330 { 331 u32 pend, isr, ier; 332 u32 clr = 0; 333 334 /* Get the interrupt Status from the IPIF. There is no clearing of 335 * interrupts in the IPIF. Interrupts must be cleared at the source. 336 * To find which interrupts are pending; AND interrupts pending with 337 * interrupts masked. 338 */ 339 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 340 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 341 pend = isr & ier; 342 343 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 344 __func__, ier, isr, pend); 345 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 346 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 347 i2c->tx_msg, i2c->nmsgs); 348 349 /* Do not processes a devices interrupts if the device has no 350 * interrupts pending 351 */ 352 if (!pend) 353 return; 354 355 /* Service requesting interrupt */ 356 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 357 ((pend & XIIC_INTR_TX_ERROR_MASK) && 358 !(pend & XIIC_INTR_RX_FULL_MASK))) { 359 /* bus arbritration lost, or... 360 * Transmit error _OR_ RX completed 361 * if this happens when RX_FULL is not set 362 * this is probably a TX error 363 */ 364 365 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 366 367 /* dynamic mode seem to suffer from problems if we just flushes 368 * fifos and the next message is a TX with len 0 (only addr) 369 * reset the IP instead of just flush fifos 370 */ 371 xiic_reinit(i2c); 372 373 if (i2c->tx_msg) 374 xiic_wakeup(i2c, STATE_ERROR); 375 376 } else if (pend & XIIC_INTR_RX_FULL_MASK) { 377 /* Receive register/FIFO is full */ 378 379 clr = XIIC_INTR_RX_FULL_MASK; 380 if (!i2c->rx_msg) { 381 dev_dbg(i2c->adap.dev.parent, 382 "%s unexpexted RX IRQ\n", __func__); 383 xiic_clear_rx_fifo(i2c); 384 goto out; 385 } 386 387 xiic_read_rx(i2c); 388 if (xiic_rx_space(i2c) == 0) { 389 /* this is the last part of the message */ 390 i2c->rx_msg = NULL; 391 392 /* also clear TX error if there (RX complete) */ 393 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 394 395 dev_dbg(i2c->adap.dev.parent, 396 "%s end of message, nmsgs: %d\n", 397 __func__, i2c->nmsgs); 398 399 /* send next message if this wasn't the last, 400 * otherwise the transfer will be finialise when 401 * receiving the bus not busy interrupt 402 */ 403 if (i2c->nmsgs > 1) { 404 i2c->nmsgs--; 405 i2c->tx_msg++; 406 dev_dbg(i2c->adap.dev.parent, 407 "%s will start next...\n", __func__); 408 409 __xiic_start_xfer(i2c); 410 } 411 } 412 } else if (pend & XIIC_INTR_BNB_MASK) { 413 /* IIC bus has transitioned to not busy */ 414 clr = XIIC_INTR_BNB_MASK; 415 416 /* The bus is not busy, disable BusNotBusy interrupt */ 417 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 418 419 if (!i2c->tx_msg) 420 goto out; 421 422 if ((i2c->nmsgs == 1) && !i2c->rx_msg && 423 xiic_tx_space(i2c) == 0) 424 xiic_wakeup(i2c, STATE_DONE); 425 else 426 xiic_wakeup(i2c, STATE_ERROR); 427 428 } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 429 /* Transmit register/FIFO is empty or ½ empty */ 430 431 clr = pend & 432 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK); 433 434 if (!i2c->tx_msg) { 435 dev_dbg(i2c->adap.dev.parent, 436 "%s unexpexted TX IRQ\n", __func__); 437 goto out; 438 } 439 440 xiic_fill_tx_fifo(i2c); 441 442 /* current message sent and there is space in the fifo */ 443 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 444 dev_dbg(i2c->adap.dev.parent, 445 "%s end of message sent, nmsgs: %d\n", 446 __func__, i2c->nmsgs); 447 if (i2c->nmsgs > 1) { 448 i2c->nmsgs--; 449 i2c->tx_msg++; 450 __xiic_start_xfer(i2c); 451 } else { 452 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 453 454 dev_dbg(i2c->adap.dev.parent, 455 "%s Got TX IRQ but no more to do...\n", 456 __func__); 457 } 458 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 459 /* current frame is sent and is last, 460 * make sure to disable tx half 461 */ 462 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 463 } else { 464 /* got IRQ which is not acked */ 465 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n", 466 __func__); 467 clr = pend; 468 } 469 out: 470 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 471 472 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 473 } 474 475 static int xiic_bus_busy(struct xiic_i2c *i2c) 476 { 477 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 478 479 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 480 } 481 482 static int xiic_busy(struct xiic_i2c *i2c) 483 { 484 int tries = 3; 485 int err; 486 487 if (i2c->tx_msg) 488 return -EBUSY; 489 490 /* for instance if previous transfer was terminated due to TX error 491 * it might be that the bus is on it's way to become available 492 * give it at most 3 ms to wake 493 */ 494 err = xiic_bus_busy(i2c); 495 while (err && tries--) { 496 mdelay(1); 497 err = xiic_bus_busy(i2c); 498 } 499 500 return err; 501 } 502 503 static void xiic_start_recv(struct xiic_i2c *i2c) 504 { 505 u8 rx_watermark; 506 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 507 508 /* Clear and enable Rx full interrupt. */ 509 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 510 511 /* we want to get all but last byte, because the TX_ERROR IRQ is used 512 * to inidicate error ACK on the address, and negative ack on the last 513 * received byte, so to not mix them receive all but last. 514 * In the case where there is only one byte to receive 515 * we can check if ERROR and RX full is set at the same time 516 */ 517 rx_watermark = msg->len; 518 if (rx_watermark > IIC_RX_FIFO_DEPTH) 519 rx_watermark = IIC_RX_FIFO_DEPTH; 520 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 521 522 if (!(msg->flags & I2C_M_NOSTART)) 523 /* write the address */ 524 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 525 (msg->addr << 1) | XIIC_READ_OPERATION | 526 XIIC_TX_DYN_START_MASK); 527 528 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 529 530 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 531 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 532 if (i2c->nmsgs == 1) 533 /* very last, enable bus not busy as well */ 534 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 535 536 /* the message is tx:ed */ 537 i2c->tx_pos = msg->len; 538 } 539 540 static void xiic_start_send(struct xiic_i2c *i2c) 541 { 542 struct i2c_msg *msg = i2c->tx_msg; 543 544 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); 545 546 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 547 __func__, msg, msg->len); 548 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 549 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 550 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 551 552 if (!(msg->flags & I2C_M_NOSTART)) { 553 /* write the address */ 554 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION | 555 XIIC_TX_DYN_START_MASK; 556 if ((i2c->nmsgs == 1) && msg->len == 0) 557 /* no data and last message -> add STOP */ 558 data |= XIIC_TX_DYN_STOP_MASK; 559 560 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 561 } 562 563 xiic_fill_tx_fifo(i2c); 564 565 /* Clear any pending Tx empty, Tx Error and then enable them. */ 566 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 567 XIIC_INTR_BNB_MASK); 568 } 569 570 static irqreturn_t xiic_isr(int irq, void *dev_id) 571 { 572 struct xiic_i2c *i2c = dev_id; 573 574 spin_lock(&i2c->lock); 575 /* disable interrupts globally */ 576 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); 577 578 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); 579 580 xiic_process(i2c); 581 582 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 583 spin_unlock(&i2c->lock); 584 585 return IRQ_HANDLED; 586 } 587 588 static void __xiic_start_xfer(struct xiic_i2c *i2c) 589 { 590 int first = 1; 591 int fifo_space = xiic_tx_fifo_space(i2c); 592 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 593 __func__, i2c->tx_msg, fifo_space); 594 595 if (!i2c->tx_msg) 596 return; 597 598 i2c->rx_pos = 0; 599 i2c->tx_pos = 0; 600 i2c->state = STATE_START; 601 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { 602 if (!first) { 603 i2c->nmsgs--; 604 i2c->tx_msg++; 605 i2c->tx_pos = 0; 606 } else 607 first = 0; 608 609 if (i2c->tx_msg->flags & I2C_M_RD) { 610 /* we dont date putting several reads in the FIFO */ 611 xiic_start_recv(i2c); 612 return; 613 } else { 614 xiic_start_send(i2c); 615 if (xiic_tx_space(i2c) != 0) { 616 /* the message could not be completely sent */ 617 break; 618 } 619 } 620 621 fifo_space = xiic_tx_fifo_space(i2c); 622 } 623 624 /* there are more messages or the current one could not be completely 625 * put into the FIFO, also enable the half empty interrupt 626 */ 627 if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) 628 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); 629 630 } 631 632 static void xiic_start_xfer(struct xiic_i2c *i2c) 633 { 634 unsigned long flags; 635 636 spin_lock_irqsave(&i2c->lock, flags); 637 xiic_reinit(i2c); 638 /* disable interrupts globally */ 639 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); 640 spin_unlock_irqrestore(&i2c->lock, flags); 641 642 __xiic_start_xfer(i2c); 643 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 644 } 645 646 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 647 { 648 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 649 int err; 650 651 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 652 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 653 654 err = xiic_busy(i2c); 655 if (err) 656 return err; 657 658 i2c->tx_msg = msgs; 659 i2c->nmsgs = num; 660 661 xiic_start_xfer(i2c); 662 663 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 664 (i2c->state == STATE_DONE), HZ)) 665 return (i2c->state == STATE_DONE) ? num : -EIO; 666 else { 667 i2c->tx_msg = NULL; 668 i2c->rx_msg = NULL; 669 i2c->nmsgs = 0; 670 return -ETIMEDOUT; 671 } 672 } 673 674 static u32 xiic_func(struct i2c_adapter *adap) 675 { 676 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 677 } 678 679 static const struct i2c_algorithm xiic_algorithm = { 680 .master_xfer = xiic_xfer, 681 .functionality = xiic_func, 682 }; 683 684 static struct i2c_adapter xiic_adapter = { 685 .owner = THIS_MODULE, 686 .name = DRIVER_NAME, 687 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED, 688 .algo = &xiic_algorithm, 689 }; 690 691 692 static int xiic_i2c_probe(struct platform_device *pdev) 693 { 694 struct xiic_i2c *i2c; 695 struct xiic_i2c_platform_data *pdata; 696 struct resource *res; 697 int ret, irq; 698 u8 i; 699 700 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 701 if (!i2c) 702 return -ENOMEM; 703 704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 705 i2c->base = devm_ioremap_resource(&pdev->dev, res); 706 if (IS_ERR(i2c->base)) 707 return PTR_ERR(i2c->base); 708 709 irq = platform_get_irq(pdev, 0); 710 if (irq < 0) 711 return irq; 712 713 pdata = dev_get_platdata(&pdev->dev); 714 715 /* hook up driver to tree */ 716 platform_set_drvdata(pdev, i2c); 717 i2c->adap = xiic_adapter; 718 i2c_set_adapdata(&i2c->adap, i2c); 719 i2c->adap.dev.parent = &pdev->dev; 720 i2c->adap.dev.of_node = pdev->dev.of_node; 721 722 spin_lock_init(&i2c->lock); 723 init_waitqueue_head(&i2c->wait); 724 725 ret = devm_request_irq(&pdev->dev, irq, xiic_isr, 0, pdev->name, i2c); 726 if (ret < 0) { 727 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 728 return ret; 729 } 730 731 xiic_reinit(i2c); 732 733 /* add i2c adapter to i2c tree */ 734 ret = i2c_add_adapter(&i2c->adap); 735 if (ret) { 736 dev_err(&pdev->dev, "Failed to add adapter\n"); 737 xiic_deinit(i2c); 738 return ret; 739 } 740 741 if (pdata) { 742 /* add in known devices to the bus */ 743 for (i = 0; i < pdata->num_devices; i++) 744 i2c_new_device(&i2c->adap, pdata->devices + i); 745 } 746 747 return 0; 748 } 749 750 static int xiic_i2c_remove(struct platform_device *pdev) 751 { 752 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 753 754 /* remove adapter & data */ 755 i2c_del_adapter(&i2c->adap); 756 757 xiic_deinit(i2c); 758 759 return 0; 760 } 761 762 #if defined(CONFIG_OF) 763 static const struct of_device_id xiic_of_match[] = { 764 { .compatible = "xlnx,xps-iic-2.00.a", }, 765 {}, 766 }; 767 MODULE_DEVICE_TABLE(of, xiic_of_match); 768 #endif 769 770 static struct platform_driver xiic_i2c_driver = { 771 .probe = xiic_i2c_probe, 772 .remove = xiic_i2c_remove, 773 .driver = { 774 .owner = THIS_MODULE, 775 .name = DRIVER_NAME, 776 .of_match_table = of_match_ptr(xiic_of_match), 777 }, 778 }; 779 780 module_platform_driver(xiic_i2c_driver); 781 782 MODULE_AUTHOR("info@mocean-labs.com"); 783 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 784 MODULE_LICENSE("GPL v2"); 785 MODULE_ALIAS("platform:"DRIVER_NAME); 786