1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i2c-xiic.c 4 * Copyright (c) 2002-2007 Xilinx Inc. 5 * Copyright (c) 2009-2010 Intel Corporation 6 * 7 * This code was implemented by Mocean Laboratories AB when porting linux 8 * to the automotive development board Russellville. The copyright holder 9 * as seen in the header is Intel corporation. 10 * Mocean Laboratories forked off the GNU/Linux platform work into a 11 * separate company called Pelagicore AB, which committed the code to the 12 * kernel. 13 */ 14 15 /* Supports: 16 * Xilinx IIC 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/i2c.h> 25 #include <linux/interrupt.h> 26 #include <linux/completion.h> 27 #include <linux/platform_data/i2c-xiic.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 #include <linux/pm_runtime.h> 33 34 #define DRIVER_NAME "xiic-i2c" 35 36 enum xilinx_i2c_state { 37 STATE_DONE, 38 STATE_ERROR, 39 STATE_START 40 }; 41 42 enum xiic_endian { 43 LITTLE, 44 BIG 45 }; 46 47 /** 48 * struct xiic_i2c - Internal representation of the XIIC I2C bus 49 * @dev: Pointer to device structure 50 * @base: Memory base of the HW registers 51 * @completion: Completion for callers 52 * @adap: Kernel adapter representation 53 * @tx_msg: Messages from above to be sent 54 * @lock: Mutual exclusion 55 * @tx_pos: Current pos in TX message 56 * @nmsgs: Number of messages in tx_msg 57 * @rx_msg: Current RX message 58 * @rx_pos: Position within current RX message 59 * @endianness: big/little-endian byte order 60 * @clk: Pointer to AXI4-lite input clock 61 * @state: See STATE_ 62 * @singlemaster: Indicates bus is single master 63 * @dynamic: Mode of controller 64 */ 65 struct xiic_i2c { 66 struct device *dev; 67 void __iomem *base; 68 struct completion completion; 69 struct i2c_adapter adap; 70 struct i2c_msg *tx_msg; 71 struct mutex lock; 72 unsigned int tx_pos; 73 unsigned int nmsgs; 74 struct i2c_msg *rx_msg; 75 int rx_pos; 76 enum xiic_endian endianness; 77 struct clk *clk; 78 enum xilinx_i2c_state state; 79 bool singlemaster; 80 bool dynamic; 81 }; 82 83 #define XIIC_MSB_OFFSET 0 84 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET) 85 86 /* 87 * Register offsets in bytes from RegisterBase. Three is added to the 88 * base offset to access LSB (IBM style) of the word 89 */ 90 #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */ 91 #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */ 92 #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */ 93 #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */ 94 #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */ 95 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 96 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 97 #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */ 98 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 99 #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */ 100 101 /* Control Register masks */ 102 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 103 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 104 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 105 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 106 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 107 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 108 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 109 110 /* Status Register masks */ 111 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 112 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 113 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 114 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 115 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 116 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 117 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 118 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 119 120 /* Interrupt Status Register masks Interrupt occurs when... */ 121 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 122 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 123 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 124 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 125 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 126 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 127 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 128 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 129 130 /* The following constants specify the depth of the FIFOs */ 131 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 132 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 133 134 /* The following constants specify groups of interrupts that are typically 135 * enabled or disables at the same time 136 */ 137 #define XIIC_TX_INTERRUPTS \ 138 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 139 140 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 141 142 /* 143 * Tx Fifo upper bit masks. 144 */ 145 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 146 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 147 148 /* Dynamic mode constants */ 149 #define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */ 150 151 /* 152 * The following constants define the register offsets for the Interrupt 153 * registers. There are some holes in the memory map for reserved addresses 154 * to allow other registers to be added and still match the memory map of the 155 * interrupt controller registers 156 */ 157 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 158 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 159 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 160 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 161 162 #define XIIC_RESET_MASK 0xAUL 163 164 #define XIIC_PM_TIMEOUT 1000 /* ms */ 165 /* timeout waiting for the controller to respond */ 166 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 167 /* timeout waiting for the controller finish transfers */ 168 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 169 170 /* 171 * The following constant is used for the device global interrupt enable 172 * register, to enable all interrupts for the device, this is the only bit 173 * in the register 174 */ 175 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 176 177 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 178 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 179 180 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 181 static void __xiic_start_xfer(struct xiic_i2c *i2c); 182 183 /* 184 * For the register read and write functions, a little-endian and big-endian 185 * version are necessary. Endianness is detected during the probe function. 186 * Only the least significant byte [doublet] of the register are ever 187 * accessed. This requires an offset of 3 [2] from the base address for 188 * big-endian systems. 189 */ 190 191 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 192 { 193 if (i2c->endianness == LITTLE) 194 iowrite8(value, i2c->base + reg); 195 else 196 iowrite8(value, i2c->base + reg + 3); 197 } 198 199 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 200 { 201 u8 ret; 202 203 if (i2c->endianness == LITTLE) 204 ret = ioread8(i2c->base + reg); 205 else 206 ret = ioread8(i2c->base + reg + 3); 207 return ret; 208 } 209 210 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 211 { 212 if (i2c->endianness == LITTLE) 213 iowrite16(value, i2c->base + reg); 214 else 215 iowrite16be(value, i2c->base + reg + 2); 216 } 217 218 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 219 { 220 if (i2c->endianness == LITTLE) 221 iowrite32(value, i2c->base + reg); 222 else 223 iowrite32be(value, i2c->base + reg); 224 } 225 226 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 227 { 228 u32 ret; 229 230 if (i2c->endianness == LITTLE) 231 ret = ioread32(i2c->base + reg); 232 else 233 ret = ioread32be(i2c->base + reg); 234 return ret; 235 } 236 237 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 238 { 239 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 240 241 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 242 } 243 244 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 245 { 246 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 247 248 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 249 } 250 251 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 252 { 253 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 254 255 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 256 } 257 258 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 259 { 260 xiic_irq_clr(i2c, mask); 261 xiic_irq_en(i2c, mask); 262 } 263 264 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 265 { 266 u8 sr; 267 unsigned long timeout; 268 269 timeout = jiffies + XIIC_I2C_TIMEOUT; 270 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 271 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 272 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 273 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 274 if (time_after(jiffies, timeout)) { 275 dev_err(i2c->dev, "Failed to clear rx fifo\n"); 276 return -ETIMEDOUT; 277 } 278 } 279 280 return 0; 281 } 282 283 static int xiic_reinit(struct xiic_i2c *i2c) 284 { 285 int ret; 286 287 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 288 289 /* Set receive Fifo depth to maximum (zero based). */ 290 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 291 292 /* Reset Tx Fifo. */ 293 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 294 295 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 296 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 297 298 /* make sure RX fifo is empty */ 299 ret = xiic_clear_rx_fifo(i2c); 300 if (ret) 301 return ret; 302 303 /* Enable interrupts */ 304 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 305 306 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 307 308 return 0; 309 } 310 311 static void xiic_deinit(struct xiic_i2c *i2c) 312 { 313 u8 cr; 314 315 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 316 317 /* Disable IIC Device. */ 318 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 319 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 320 } 321 322 static void xiic_read_rx(struct xiic_i2c *i2c) 323 { 324 u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; 325 u32 bytes_rem = 0; 326 int i; 327 328 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 329 330 dev_dbg(i2c->adap.dev.parent, 331 "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", 332 __func__, bytes_in_fifo, xiic_rx_space(i2c), 333 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 334 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 335 336 if (bytes_in_fifo > xiic_rx_space(i2c)) 337 bytes_in_fifo = xiic_rx_space(i2c); 338 339 bytes_to_read = bytes_in_fifo; 340 341 if (!i2c->dynamic) { 342 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; 343 344 if (bytes_rem > IIC_RX_FIFO_DEPTH) { 345 bytes_to_read = bytes_in_fifo; 346 } else if (bytes_rem > 1) { 347 bytes_to_read = bytes_rem - 1; 348 } else if (bytes_rem == 1) { 349 bytes_to_read = 1; 350 /* Set NACK in CR to indicate slave transmitter */ 351 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 352 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | 353 XIIC_CR_NO_ACK_MASK); 354 } else if (bytes_rem == 0) { 355 bytes_to_read = bytes_in_fifo; 356 357 /* Generate stop on the bus if it is last message */ 358 if (i2c->nmsgs == 1) { 359 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 360 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 361 ~XIIC_CR_MSMS_MASK); 362 } 363 364 /* Make TXACK=0, clean up for next transaction */ 365 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 366 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 367 ~XIIC_CR_NO_ACK_MASK); 368 } 369 } 370 371 /* Read the fifo */ 372 for (i = 0; i < bytes_to_read; i++) { 373 i2c->rx_msg->buf[i2c->rx_pos++] = 374 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 375 } 376 377 if (i2c->dynamic) { 378 u8 bytes; 379 380 /* Receive remaining bytes if less than fifo depth */ 381 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); 382 bytes--; 383 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); 384 } 385 } 386 387 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 388 { 389 /* return the actual space left in the FIFO */ 390 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 391 } 392 393 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 394 { 395 u8 fifo_space = xiic_tx_fifo_space(i2c); 396 int len = xiic_tx_space(i2c); 397 398 len = (len > fifo_space) ? fifo_space : len; 399 400 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 401 __func__, len, fifo_space); 402 403 while (len--) { 404 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 405 406 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { 407 /* last message in transfer -> STOP */ 408 if (i2c->dynamic) { 409 data |= XIIC_TX_DYN_STOP_MASK; 410 } else { 411 u8 cr; 412 /* Write to CR to stop */ 413 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 414 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 415 ~XIIC_CR_MSMS_MASK); 416 } 417 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 418 } 419 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 420 } 421 } 422 423 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) 424 { 425 i2c->tx_msg = NULL; 426 i2c->rx_msg = NULL; 427 i2c->nmsgs = 0; 428 i2c->state = code; 429 complete(&i2c->completion); 430 } 431 432 static irqreturn_t xiic_process(int irq, void *dev_id) 433 { 434 struct xiic_i2c *i2c = dev_id; 435 u32 pend, isr, ier; 436 u32 clr = 0; 437 int xfer_more = 0; 438 int wakeup_req = 0; 439 enum xilinx_i2c_state wakeup_code = STATE_DONE; 440 int ret; 441 442 /* Get the interrupt Status from the IPIF. There is no clearing of 443 * interrupts in the IPIF. Interrupts must be cleared at the source. 444 * To find which interrupts are pending; AND interrupts pending with 445 * interrupts masked. 446 */ 447 mutex_lock(&i2c->lock); 448 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 449 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 450 pend = isr & ier; 451 452 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 453 __func__, ier, isr, pend); 454 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 455 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 456 i2c->tx_msg, i2c->nmsgs); 457 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", 458 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 459 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 460 461 /* Service requesting interrupt */ 462 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 463 ((pend & XIIC_INTR_TX_ERROR_MASK) && 464 !(pend & XIIC_INTR_RX_FULL_MASK))) { 465 /* bus arbritration lost, or... 466 * Transmit error _OR_ RX completed 467 * if this happens when RX_FULL is not set 468 * this is probably a TX error 469 */ 470 471 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 472 473 /* dynamic mode seem to suffer from problems if we just flushes 474 * fifos and the next message is a TX with len 0 (only addr) 475 * reset the IP instead of just flush fifos 476 */ 477 ret = xiic_reinit(i2c); 478 if (!ret) 479 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); 480 481 if (i2c->rx_msg) { 482 wakeup_req = 1; 483 wakeup_code = STATE_ERROR; 484 } 485 if (i2c->tx_msg) { 486 wakeup_req = 1; 487 wakeup_code = STATE_ERROR; 488 } 489 } 490 if (pend & XIIC_INTR_RX_FULL_MASK) { 491 /* Receive register/FIFO is full */ 492 493 clr |= XIIC_INTR_RX_FULL_MASK; 494 if (!i2c->rx_msg) { 495 dev_dbg(i2c->adap.dev.parent, 496 "%s unexpected RX IRQ\n", __func__); 497 xiic_clear_rx_fifo(i2c); 498 goto out; 499 } 500 501 xiic_read_rx(i2c); 502 if (xiic_rx_space(i2c) == 0) { 503 /* this is the last part of the message */ 504 i2c->rx_msg = NULL; 505 506 /* also clear TX error if there (RX complete) */ 507 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 508 509 dev_dbg(i2c->adap.dev.parent, 510 "%s end of message, nmsgs: %d\n", 511 __func__, i2c->nmsgs); 512 513 /* send next message if this wasn't the last, 514 * otherwise the transfer will be finialise when 515 * receiving the bus not busy interrupt 516 */ 517 if (i2c->nmsgs > 1) { 518 i2c->nmsgs--; 519 i2c->tx_msg++; 520 dev_dbg(i2c->adap.dev.parent, 521 "%s will start next...\n", __func__); 522 xfer_more = 1; 523 } 524 } 525 } 526 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 527 /* Transmit register/FIFO is empty or ½ empty */ 528 529 clr |= (pend & 530 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 531 532 if (!i2c->tx_msg) { 533 dev_dbg(i2c->adap.dev.parent, 534 "%s unexpected TX IRQ\n", __func__); 535 goto out; 536 } 537 538 xiic_fill_tx_fifo(i2c); 539 540 /* current message sent and there is space in the fifo */ 541 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 542 dev_dbg(i2c->adap.dev.parent, 543 "%s end of message sent, nmsgs: %d\n", 544 __func__, i2c->nmsgs); 545 if (i2c->nmsgs > 1) { 546 i2c->nmsgs--; 547 i2c->tx_msg++; 548 xfer_more = 1; 549 } else { 550 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 551 552 dev_dbg(i2c->adap.dev.parent, 553 "%s Got TX IRQ but no more to do...\n", 554 __func__); 555 } 556 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 557 /* current frame is sent and is last, 558 * make sure to disable tx half 559 */ 560 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 561 } 562 563 if (pend & XIIC_INTR_BNB_MASK) { 564 /* IIC bus has transitioned to not busy */ 565 clr |= XIIC_INTR_BNB_MASK; 566 567 /* The bus is not busy, disable BusNotBusy interrupt */ 568 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 569 570 if (!i2c->tx_msg) 571 goto out; 572 573 wakeup_req = 1; 574 575 if (i2c->nmsgs == 1 && !i2c->rx_msg && 576 xiic_tx_space(i2c) == 0) 577 wakeup_code = STATE_DONE; 578 else 579 wakeup_code = STATE_ERROR; 580 } 581 582 out: 583 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 584 585 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 586 if (xfer_more) 587 __xiic_start_xfer(i2c); 588 if (wakeup_req) 589 xiic_wakeup(i2c, wakeup_code); 590 591 WARN_ON(xfer_more && wakeup_req); 592 593 mutex_unlock(&i2c->lock); 594 return IRQ_HANDLED; 595 } 596 597 static int xiic_bus_busy(struct xiic_i2c *i2c) 598 { 599 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 600 601 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 602 } 603 604 static int xiic_busy(struct xiic_i2c *i2c) 605 { 606 int tries = 3; 607 int err; 608 609 if (i2c->tx_msg || i2c->rx_msg) 610 return -EBUSY; 611 612 /* In single master mode bus can only be busy, when in use by this 613 * driver. If the register indicates bus being busy for some reason we 614 * should ignore it, since bus will never be released and i2c will be 615 * stuck forever. 616 */ 617 if (i2c->singlemaster) { 618 return 0; 619 } 620 621 /* for instance if previous transfer was terminated due to TX error 622 * it might be that the bus is on it's way to become available 623 * give it at most 3 ms to wake 624 */ 625 err = xiic_bus_busy(i2c); 626 while (err && tries--) { 627 msleep(1); 628 err = xiic_bus_busy(i2c); 629 } 630 631 return err; 632 } 633 634 static void xiic_start_recv(struct xiic_i2c *i2c) 635 { 636 u16 rx_watermark; 637 u8 cr = 0, rfd_set = 0; 638 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 639 unsigned long flags; 640 641 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 642 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 643 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 644 645 /* Disable Tx interrupts */ 646 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); 647 648 if (i2c->dynamic) { 649 u8 bytes; 650 u16 val; 651 652 /* Clear and enable Rx full interrupt. */ 653 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 654 XIIC_INTR_TX_ERROR_MASK); 655 656 /* 657 * We want to get all but last byte, because the TX_ERROR IRQ 658 * is used to indicate error ACK on the address, and 659 * negative ack on the last received byte, so to not mix 660 * them receive all but last. 661 * In the case where there is only one byte to receive 662 * we can check if ERROR and RX full is set at the same time 663 */ 664 rx_watermark = msg->len; 665 bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH); 666 667 if (rx_watermark > 0) 668 bytes--; 669 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); 670 671 local_irq_save(flags); 672 673 /* write the address */ 674 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 675 i2c_8bit_addr_from_msg(msg) | 676 XIIC_TX_DYN_START_MASK); 677 678 /* If last message, include dynamic stop bit with length */ 679 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; 680 val |= msg->len; 681 682 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); 683 684 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 685 686 local_irq_restore(flags); 687 } else { 688 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 689 690 /* Set Receive fifo depth */ 691 rx_watermark = msg->len; 692 if (rx_watermark > IIC_RX_FIFO_DEPTH) { 693 rfd_set = IIC_RX_FIFO_DEPTH - 1; 694 } else if (rx_watermark == 1) { 695 rfd_set = rx_watermark - 1; 696 /* Handle single byte transfer separately */ 697 cr |= XIIC_CR_NO_ACK_MASK; 698 } else if (rx_watermark == 0) { 699 rfd_set = rx_watermark; 700 cr |= XIIC_CR_NO_ACK_MASK; 701 } else { 702 rfd_set = rx_watermark - 2; 703 } 704 /* Check if RSTA should be set */ 705 if (cr & XIIC_CR_MSMS_MASK) { 706 /* Already a master, RSTA should be set */ 707 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 708 XIIC_CR_REPEATED_START_MASK) & 709 ~(XIIC_CR_DIR_IS_TX_MASK)); 710 } 711 712 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); 713 714 /* Clear and enable Rx full and transmit complete interrupts */ 715 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 716 XIIC_INTR_TX_ERROR_MASK); 717 718 /* Write the address */ 719 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 720 i2c_8bit_addr_from_msg(msg)); 721 722 /* Write to Control Register,to start transaction in Rx mode */ 723 if ((cr & XIIC_CR_MSMS_MASK) == 0) { 724 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 725 XIIC_CR_MSMS_MASK) 726 & ~(XIIC_CR_DIR_IS_TX_MASK)); 727 } 728 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", 729 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 730 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 731 } 732 733 if (i2c->nmsgs == 1) 734 /* very last, enable bus not busy as well */ 735 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 736 737 /* the message is tx:ed */ 738 i2c->tx_pos = msg->len; 739 740 /* Enable interrupts */ 741 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 742 } 743 744 static void xiic_start_send(struct xiic_i2c *i2c) 745 { 746 u8 cr = 0; 747 u16 data; 748 struct i2c_msg *msg = i2c->tx_msg; 749 750 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 751 __func__, msg, msg->len); 752 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 753 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 754 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 755 756 if (i2c->dynamic) { 757 /* write the address */ 758 data = i2c_8bit_addr_from_msg(msg) | 759 XIIC_TX_DYN_START_MASK; 760 761 if (i2c->nmsgs == 1 && msg->len == 0) 762 /* no data and last message -> add STOP */ 763 data |= XIIC_TX_DYN_STOP_MASK; 764 765 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 766 767 /* Clear any pending Tx empty, Tx Error and then enable them */ 768 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | 769 XIIC_INTR_TX_ERROR_MASK | 770 XIIC_INTR_BNB_MASK | 771 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? 772 XIIC_INTR_TX_HALF_MASK : 0)); 773 774 xiic_fill_tx_fifo(i2c); 775 } else { 776 /* Check if RSTA should be set */ 777 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 778 if (cr & XIIC_CR_MSMS_MASK) { 779 /* Already a master, RSTA should be set */ 780 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 781 XIIC_CR_REPEATED_START_MASK | 782 XIIC_CR_DIR_IS_TX_MASK) & 783 ~(XIIC_CR_NO_ACK_MASK)); 784 } 785 786 /* Write address to FIFO */ 787 data = i2c_8bit_addr_from_msg(msg); 788 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 789 790 /* Fill fifo */ 791 xiic_fill_tx_fifo(i2c); 792 793 if ((cr & XIIC_CR_MSMS_MASK) == 0) { 794 /* Start Tx by writing to CR */ 795 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 796 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | 797 XIIC_CR_MSMS_MASK | 798 XIIC_CR_DIR_IS_TX_MASK); 799 } 800 801 /* Clear any pending Tx empty, Tx Error and then enable them */ 802 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | 803 XIIC_INTR_TX_ERROR_MASK | 804 XIIC_INTR_BNB_MASK); 805 } 806 } 807 808 static void __xiic_start_xfer(struct xiic_i2c *i2c) 809 { 810 int fifo_space = xiic_tx_fifo_space(i2c); 811 812 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 813 __func__, i2c->tx_msg, fifo_space); 814 815 if (!i2c->tx_msg) 816 return; 817 818 i2c->rx_pos = 0; 819 i2c->tx_pos = 0; 820 i2c->state = STATE_START; 821 if (i2c->tx_msg->flags & I2C_M_RD) { 822 /* we dont date putting several reads in the FIFO */ 823 xiic_start_recv(i2c); 824 } else { 825 xiic_start_send(i2c); 826 } 827 } 828 829 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) 830 { 831 int ret; 832 833 mutex_lock(&i2c->lock); 834 835 ret = xiic_busy(i2c); 836 if (ret) 837 goto out; 838 839 i2c->tx_msg = msgs; 840 i2c->rx_msg = NULL; 841 i2c->nmsgs = num; 842 init_completion(&i2c->completion); 843 844 ret = xiic_reinit(i2c); 845 if (!ret) 846 __xiic_start_xfer(i2c); 847 848 out: 849 mutex_unlock(&i2c->lock); 850 851 return ret; 852 } 853 854 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 855 { 856 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 857 int err; 858 859 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 860 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 861 862 err = pm_runtime_resume_and_get(i2c->dev); 863 if (err < 0) 864 return err; 865 866 /* Decide standard mode or Dynamic mode */ 867 i2c->dynamic = true; 868 869 /* 870 * If number of messages is 1 and read length is > 255 bytes, 871 * enter standard mode 872 */ 873 874 if (i2c->nmsgs == 1 && (i2c->tx_msg->flags & I2C_M_RD) && 875 i2c->tx_msg->len > MAX_READ_LENGTH_DYNAMIC) { 876 i2c->dynamic = false; 877 } else if (i2c->nmsgs > 1) { 878 int count; 879 880 /* 881 * If number of messages is more than 1 and one of them is 882 * a read message, enter standard mode. Since repeated start 883 * operation in dynamic mode read is not happenning 884 */ 885 for (count = 0; count < i2c->nmsgs; count++) { 886 if (i2c->tx_msg[count].flags & I2C_M_RD) { 887 i2c->dynamic = false; 888 break; 889 } 890 } 891 } 892 893 err = xiic_start_xfer(i2c, msgs, num); 894 if (err < 0) { 895 dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 896 return err; 897 } 898 899 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); 900 mutex_lock(&i2c->lock); 901 if (err == 0) { /* Timeout */ 902 i2c->tx_msg = NULL; 903 i2c->rx_msg = NULL; 904 i2c->nmsgs = 0; 905 err = -ETIMEDOUT; 906 } else if (err < 0) { /* Completion error */ 907 i2c->tx_msg = NULL; 908 i2c->rx_msg = NULL; 909 i2c->nmsgs = 0; 910 } else { 911 err = (i2c->state == STATE_DONE) ? num : -EIO; 912 } 913 mutex_unlock(&i2c->lock); 914 pm_runtime_mark_last_busy(i2c->dev); 915 pm_runtime_put_autosuspend(i2c->dev); 916 return err; 917 } 918 919 static u32 xiic_func(struct i2c_adapter *adap) 920 { 921 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 922 } 923 924 static const struct i2c_algorithm xiic_algorithm = { 925 .master_xfer = xiic_xfer, 926 .functionality = xiic_func, 927 }; 928 929 static const struct i2c_adapter xiic_adapter = { 930 .owner = THIS_MODULE, 931 .class = I2C_CLASS_DEPRECATED, 932 .algo = &xiic_algorithm, 933 }; 934 935 static int xiic_i2c_probe(struct platform_device *pdev) 936 { 937 struct xiic_i2c *i2c; 938 struct xiic_i2c_platform_data *pdata; 939 struct resource *res; 940 int ret, irq; 941 u8 i; 942 u32 sr; 943 944 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 945 if (!i2c) 946 return -ENOMEM; 947 948 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 949 i2c->base = devm_ioremap_resource(&pdev->dev, res); 950 if (IS_ERR(i2c->base)) 951 return PTR_ERR(i2c->base); 952 953 irq = platform_get_irq(pdev, 0); 954 if (irq < 0) 955 return irq; 956 957 pdata = dev_get_platdata(&pdev->dev); 958 959 /* hook up driver to tree */ 960 platform_set_drvdata(pdev, i2c); 961 i2c->adap = xiic_adapter; 962 i2c_set_adapdata(&i2c->adap, i2c); 963 i2c->adap.dev.parent = &pdev->dev; 964 i2c->adap.dev.of_node = pdev->dev.of_node; 965 snprintf(i2c->adap.name, sizeof(i2c->adap.name), 966 DRIVER_NAME " %s", pdev->name); 967 968 mutex_init(&i2c->lock); 969 970 i2c->clk = devm_clk_get(&pdev->dev, NULL); 971 if (IS_ERR(i2c->clk)) 972 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 973 "input clock not found.\n"); 974 975 ret = clk_prepare_enable(i2c->clk); 976 if (ret) { 977 dev_err(&pdev->dev, "Unable to enable clock.\n"); 978 return ret; 979 } 980 i2c->dev = &pdev->dev; 981 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 982 pm_runtime_use_autosuspend(i2c->dev); 983 pm_runtime_set_active(i2c->dev); 984 pm_runtime_enable(i2c->dev); 985 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 986 xiic_process, IRQF_ONESHOT, 987 pdev->name, i2c); 988 989 if (ret < 0) { 990 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 991 goto err_clk_dis; 992 } 993 994 i2c->singlemaster = 995 of_property_read_bool(pdev->dev.of_node, "single-master"); 996 997 /* 998 * Detect endianness 999 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 1000 * set, assume that the endianness was wrong and swap. 1001 */ 1002 i2c->endianness = LITTLE; 1003 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 1004 /* Reset is cleared in xiic_reinit */ 1005 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 1006 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 1007 i2c->endianness = BIG; 1008 1009 ret = xiic_reinit(i2c); 1010 if (ret < 0) { 1011 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 1012 goto err_clk_dis; 1013 } 1014 1015 /* add i2c adapter to i2c tree */ 1016 ret = i2c_add_adapter(&i2c->adap); 1017 if (ret) { 1018 xiic_deinit(i2c); 1019 goto err_clk_dis; 1020 } 1021 1022 if (pdata) { 1023 /* add in known devices to the bus */ 1024 for (i = 0; i < pdata->num_devices; i++) 1025 i2c_new_client_device(&i2c->adap, pdata->devices + i); 1026 } 1027 1028 return 0; 1029 1030 err_clk_dis: 1031 pm_runtime_set_suspended(&pdev->dev); 1032 pm_runtime_disable(&pdev->dev); 1033 clk_disable_unprepare(i2c->clk); 1034 return ret; 1035 } 1036 1037 static int xiic_i2c_remove(struct platform_device *pdev) 1038 { 1039 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 1040 int ret; 1041 1042 /* remove adapter & data */ 1043 i2c_del_adapter(&i2c->adap); 1044 1045 ret = pm_runtime_get_sync(i2c->dev); 1046 1047 if (ret < 0) 1048 dev_warn(&pdev->dev, "Failed to activate device for removal (%pe)\n", 1049 ERR_PTR(ret)); 1050 else 1051 xiic_deinit(i2c); 1052 1053 pm_runtime_put_sync(i2c->dev); 1054 clk_disable_unprepare(i2c->clk); 1055 pm_runtime_disable(&pdev->dev); 1056 pm_runtime_set_suspended(&pdev->dev); 1057 pm_runtime_dont_use_autosuspend(&pdev->dev); 1058 1059 return 0; 1060 } 1061 1062 #if defined(CONFIG_OF) 1063 static const struct of_device_id xiic_of_match[] = { 1064 { .compatible = "xlnx,xps-iic-2.00.a", }, 1065 {}, 1066 }; 1067 MODULE_DEVICE_TABLE(of, xiic_of_match); 1068 #endif 1069 1070 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 1071 { 1072 struct xiic_i2c *i2c = dev_get_drvdata(dev); 1073 1074 clk_disable(i2c->clk); 1075 1076 return 0; 1077 } 1078 1079 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 1080 { 1081 struct xiic_i2c *i2c = dev_get_drvdata(dev); 1082 int ret; 1083 1084 ret = clk_enable(i2c->clk); 1085 if (ret) { 1086 dev_err(dev, "Cannot enable clock.\n"); 1087 return ret; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static const struct dev_pm_ops xiic_dev_pm_ops = { 1094 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 1095 xiic_i2c_runtime_resume, NULL) 1096 }; 1097 1098 static struct platform_driver xiic_i2c_driver = { 1099 .probe = xiic_i2c_probe, 1100 .remove = xiic_i2c_remove, 1101 .driver = { 1102 .name = DRIVER_NAME, 1103 .of_match_table = of_match_ptr(xiic_of_match), 1104 .pm = &xiic_dev_pm_ops, 1105 }, 1106 }; 1107 1108 module_platform_driver(xiic_i2c_driver); 1109 1110 MODULE_ALIAS("platform:" DRIVER_NAME); 1111 MODULE_AUTHOR("info@mocean-labs.com"); 1112 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 1113 MODULE_LICENSE("GPL v2"); 1114