1 /* 2 * i2c-xiic.c 3 * Copyright (c) 2002-2007 Xilinx Inc. 4 * Copyright (c) 2009-2010 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * 20 * This code was implemented by Mocean Laboratories AB when porting linux 21 * to the automotive development board Russellville. The copyright holder 22 * as seen in the header is Intel corporation. 23 * Mocean Laboratories forked off the GNU/Linux platform work into a 24 * separate company called Pelagicore AB, which committed the code to the 25 * kernel. 26 */ 27 28 /* Supports: 29 * Xilinx IIC 30 */ 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/init.h> 34 #include <linux/errno.h> 35 #include <linux/delay.h> 36 #include <linux/platform_device.h> 37 #include <linux/i2c.h> 38 #include <linux/interrupt.h> 39 #include <linux/wait.h> 40 #include <linux/i2c-xiic.h> 41 #include <linux/io.h> 42 #include <linux/slab.h> 43 44 #define DRIVER_NAME "xiic-i2c" 45 46 enum xilinx_i2c_state { 47 STATE_DONE, 48 STATE_ERROR, 49 STATE_START 50 }; 51 52 /** 53 * struct xiic_i2c - Internal representation of the XIIC I2C bus 54 * @base: Memory base of the HW registers 55 * @wait: Wait queue for callers 56 * @adap: Kernel adapter representation 57 * @tx_msg: Messages from above to be sent 58 * @lock: Mutual exclusion 59 * @tx_pos: Current pos in TX message 60 * @nmsgs: Number of messages in tx_msg 61 * @state: See STATE_ 62 * @rx_msg: Current RX message 63 * @rx_pos: Position within current RX message 64 */ 65 struct xiic_i2c { 66 void __iomem *base; 67 wait_queue_head_t wait; 68 struct i2c_adapter adap; 69 struct i2c_msg *tx_msg; 70 spinlock_t lock; 71 unsigned int tx_pos; 72 unsigned int nmsgs; 73 enum xilinx_i2c_state state; 74 struct i2c_msg *rx_msg; 75 int rx_pos; 76 }; 77 78 79 #define XIIC_MSB_OFFSET 0 80 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 81 82 /* 83 * Register offsets in bytes from RegisterBase. Three is added to the 84 * base offset to access LSB (IBM style) of the word 85 */ 86 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 87 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 88 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 89 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 90 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 91 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 92 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 93 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 94 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 95 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 96 97 /* Control Register masks */ 98 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 99 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 100 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 101 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 102 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 103 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 104 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 105 106 /* Status Register masks */ 107 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 108 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 109 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 110 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 111 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 112 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 113 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 114 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 115 116 /* Interrupt Status Register masks Interrupt occurs when... */ 117 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 118 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 119 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 120 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 121 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 122 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 123 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 124 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 125 126 /* The following constants specify the depth of the FIFOs */ 127 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 128 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 129 130 /* The following constants specify groups of interrupts that are typically 131 * enabled or disables at the same time 132 */ 133 #define XIIC_TX_INTERRUPTS \ 134 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 135 136 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 137 138 /* The following constants are used with the following macros to specify the 139 * operation, a read or write operation. 140 */ 141 #define XIIC_READ_OPERATION 1 142 #define XIIC_WRITE_OPERATION 0 143 144 /* 145 * Tx Fifo upper bit masks. 146 */ 147 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 148 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 149 150 /* 151 * The following constants define the register offsets for the Interrupt 152 * registers. There are some holes in the memory map for reserved addresses 153 * to allow other registers to be added and still match the memory map of the 154 * interrupt controller registers 155 */ 156 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 157 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 158 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 159 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 160 161 #define XIIC_RESET_MASK 0xAUL 162 163 /* 164 * The following constant is used for the device global interrupt enable 165 * register, to enable all interrupts for the device, this is the only bit 166 * in the register 167 */ 168 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 169 170 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 171 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 172 173 static void xiic_start_xfer(struct xiic_i2c *i2c); 174 static void __xiic_start_xfer(struct xiic_i2c *i2c); 175 176 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 177 { 178 iowrite8(value, i2c->base + reg); 179 } 180 181 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 182 { 183 return ioread8(i2c->base + reg); 184 } 185 186 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 187 { 188 iowrite16(value, i2c->base + reg); 189 } 190 191 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 192 { 193 iowrite32(value, i2c->base + reg); 194 } 195 196 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 197 { 198 return ioread32(i2c->base + reg); 199 } 200 201 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 202 { 203 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 204 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 205 } 206 207 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 208 { 209 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 210 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 211 } 212 213 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 214 { 215 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 216 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 217 } 218 219 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 220 { 221 xiic_irq_clr(i2c, mask); 222 xiic_irq_en(i2c, mask); 223 } 224 225 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) 226 { 227 u8 sr; 228 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 229 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 230 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) 231 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 232 } 233 234 static void xiic_reinit(struct xiic_i2c *i2c) 235 { 236 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 237 238 /* Set receive Fifo depth to maximum (zero based). */ 239 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 240 241 /* Reset Tx Fifo. */ 242 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 243 244 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 245 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 246 247 /* make sure RX fifo is empty */ 248 xiic_clear_rx_fifo(i2c); 249 250 /* Enable interrupts */ 251 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 252 253 xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK); 254 } 255 256 static void xiic_deinit(struct xiic_i2c *i2c) 257 { 258 u8 cr; 259 260 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 261 262 /* Disable IIC Device. */ 263 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 264 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 265 } 266 267 static void xiic_read_rx(struct xiic_i2c *i2c) 268 { 269 u8 bytes_in_fifo; 270 int i; 271 272 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 273 274 dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d" 275 ", SR: 0x%x, CR: 0x%x\n", 276 __func__, bytes_in_fifo, xiic_rx_space(i2c), 277 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 278 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 279 280 if (bytes_in_fifo > xiic_rx_space(i2c)) 281 bytes_in_fifo = xiic_rx_space(i2c); 282 283 for (i = 0; i < bytes_in_fifo; i++) 284 i2c->rx_msg->buf[i2c->rx_pos++] = 285 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 286 287 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 288 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 289 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 290 } 291 292 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 293 { 294 /* return the actual space left in the FIFO */ 295 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 296 } 297 298 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 299 { 300 u8 fifo_space = xiic_tx_fifo_space(i2c); 301 int len = xiic_tx_space(i2c); 302 303 len = (len > fifo_space) ? fifo_space : len; 304 305 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 306 __func__, len, fifo_space); 307 308 while (len--) { 309 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 310 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 311 /* last message in transfer -> STOP */ 312 data |= XIIC_TX_DYN_STOP_MASK; 313 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 314 } 315 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 316 } 317 } 318 319 static void xiic_wakeup(struct xiic_i2c *i2c, int code) 320 { 321 i2c->tx_msg = NULL; 322 i2c->rx_msg = NULL; 323 i2c->nmsgs = 0; 324 i2c->state = code; 325 wake_up(&i2c->wait); 326 } 327 328 static void xiic_process(struct xiic_i2c *i2c) 329 { 330 u32 pend, isr, ier; 331 u32 clr = 0; 332 333 /* Get the interrupt Status from the IPIF. There is no clearing of 334 * interrupts in the IPIF. Interrupts must be cleared at the source. 335 * To find which interrupts are pending; AND interrupts pending with 336 * interrupts masked. 337 */ 338 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 339 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 340 pend = isr & ier; 341 342 dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, " 343 "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n", 344 __func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 345 i2c->tx_msg, i2c->nmsgs); 346 347 /* Do not processes a devices interrupts if the device has no 348 * interrupts pending 349 */ 350 if (!pend) 351 return; 352 353 /* Service requesting interrupt */ 354 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 355 ((pend & XIIC_INTR_TX_ERROR_MASK) && 356 !(pend & XIIC_INTR_RX_FULL_MASK))) { 357 /* bus arbritration lost, or... 358 * Transmit error _OR_ RX completed 359 * if this happens when RX_FULL is not set 360 * this is probably a TX error 361 */ 362 363 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 364 365 /* dynamic mode seem to suffer from problems if we just flushes 366 * fifos and the next message is a TX with len 0 (only addr) 367 * reset the IP instead of just flush fifos 368 */ 369 xiic_reinit(i2c); 370 371 if (i2c->tx_msg) 372 xiic_wakeup(i2c, STATE_ERROR); 373 374 } else if (pend & XIIC_INTR_RX_FULL_MASK) { 375 /* Receive register/FIFO is full */ 376 377 clr = XIIC_INTR_RX_FULL_MASK; 378 if (!i2c->rx_msg) { 379 dev_dbg(i2c->adap.dev.parent, 380 "%s unexpexted RX IRQ\n", __func__); 381 xiic_clear_rx_fifo(i2c); 382 goto out; 383 } 384 385 xiic_read_rx(i2c); 386 if (xiic_rx_space(i2c) == 0) { 387 /* this is the last part of the message */ 388 i2c->rx_msg = NULL; 389 390 /* also clear TX error if there (RX complete) */ 391 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 392 393 dev_dbg(i2c->adap.dev.parent, 394 "%s end of message, nmsgs: %d\n", 395 __func__, i2c->nmsgs); 396 397 /* send next message if this wasn't the last, 398 * otherwise the transfer will be finialise when 399 * receiving the bus not busy interrupt 400 */ 401 if (i2c->nmsgs > 1) { 402 i2c->nmsgs--; 403 i2c->tx_msg++; 404 dev_dbg(i2c->adap.dev.parent, 405 "%s will start next...\n", __func__); 406 407 __xiic_start_xfer(i2c); 408 } 409 } 410 } else if (pend & XIIC_INTR_BNB_MASK) { 411 /* IIC bus has transitioned to not busy */ 412 clr = XIIC_INTR_BNB_MASK; 413 414 /* The bus is not busy, disable BusNotBusy interrupt */ 415 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 416 417 if (!i2c->tx_msg) 418 goto out; 419 420 if ((i2c->nmsgs == 1) && !i2c->rx_msg && 421 xiic_tx_space(i2c) == 0) 422 xiic_wakeup(i2c, STATE_DONE); 423 else 424 xiic_wakeup(i2c, STATE_ERROR); 425 426 } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 427 /* Transmit register/FIFO is empty or ½ empty */ 428 429 clr = pend & 430 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK); 431 432 if (!i2c->tx_msg) { 433 dev_dbg(i2c->adap.dev.parent, 434 "%s unexpexted TX IRQ\n", __func__); 435 goto out; 436 } 437 438 xiic_fill_tx_fifo(i2c); 439 440 /* current message sent and there is space in the fifo */ 441 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 442 dev_dbg(i2c->adap.dev.parent, 443 "%s end of message sent, nmsgs: %d\n", 444 __func__, i2c->nmsgs); 445 if (i2c->nmsgs > 1) { 446 i2c->nmsgs--; 447 i2c->tx_msg++; 448 __xiic_start_xfer(i2c); 449 } else { 450 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 451 452 dev_dbg(i2c->adap.dev.parent, 453 "%s Got TX IRQ but no more to do...\n", 454 __func__); 455 } 456 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 457 /* current frame is sent and is last, 458 * make sure to disable tx half 459 */ 460 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 461 } else { 462 /* got IRQ which is not acked */ 463 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n", 464 __func__); 465 clr = pend; 466 } 467 out: 468 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 469 470 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 471 } 472 473 static int xiic_bus_busy(struct xiic_i2c *i2c) 474 { 475 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 476 477 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 478 } 479 480 static int xiic_busy(struct xiic_i2c *i2c) 481 { 482 int tries = 3; 483 int err; 484 485 if (i2c->tx_msg) 486 return -EBUSY; 487 488 /* for instance if previous transfer was terminated due to TX error 489 * it might be that the bus is on it's way to become available 490 * give it at most 3 ms to wake 491 */ 492 err = xiic_bus_busy(i2c); 493 while (err && tries--) { 494 mdelay(1); 495 err = xiic_bus_busy(i2c); 496 } 497 498 return err; 499 } 500 501 static void xiic_start_recv(struct xiic_i2c *i2c) 502 { 503 u8 rx_watermark; 504 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 505 506 /* Clear and enable Rx full interrupt. */ 507 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 508 509 /* we want to get all but last byte, because the TX_ERROR IRQ is used 510 * to inidicate error ACK on the address, and negative ack on the last 511 * received byte, so to not mix them receive all but last. 512 * In the case where there is only one byte to receive 513 * we can check if ERROR and RX full is set at the same time 514 */ 515 rx_watermark = msg->len; 516 if (rx_watermark > IIC_RX_FIFO_DEPTH) 517 rx_watermark = IIC_RX_FIFO_DEPTH; 518 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 519 520 if (!(msg->flags & I2C_M_NOSTART)) 521 /* write the address */ 522 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 523 (msg->addr << 1) | XIIC_READ_OPERATION | 524 XIIC_TX_DYN_START_MASK); 525 526 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 527 528 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 529 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 530 if (i2c->nmsgs == 1) 531 /* very last, enable bus not busy as well */ 532 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 533 534 /* the message is tx:ed */ 535 i2c->tx_pos = msg->len; 536 } 537 538 static void xiic_start_send(struct xiic_i2c *i2c) 539 { 540 struct i2c_msg *msg = i2c->tx_msg; 541 542 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); 543 544 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d, " 545 "ISR: 0x%x, CR: 0x%x\n", 546 __func__, msg, msg->len, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 547 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 548 549 if (!(msg->flags & I2C_M_NOSTART)) { 550 /* write the address */ 551 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION | 552 XIIC_TX_DYN_START_MASK; 553 if ((i2c->nmsgs == 1) && msg->len == 0) 554 /* no data and last message -> add STOP */ 555 data |= XIIC_TX_DYN_STOP_MASK; 556 557 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 558 } 559 560 xiic_fill_tx_fifo(i2c); 561 562 /* Clear any pending Tx empty, Tx Error and then enable them. */ 563 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 564 XIIC_INTR_BNB_MASK); 565 } 566 567 static irqreturn_t xiic_isr(int irq, void *dev_id) 568 { 569 struct xiic_i2c *i2c = dev_id; 570 571 spin_lock(&i2c->lock); 572 /* disable interrupts globally */ 573 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); 574 575 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); 576 577 xiic_process(i2c); 578 579 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 580 spin_unlock(&i2c->lock); 581 582 return IRQ_HANDLED; 583 } 584 585 static void __xiic_start_xfer(struct xiic_i2c *i2c) 586 { 587 int first = 1; 588 int fifo_space = xiic_tx_fifo_space(i2c); 589 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 590 __func__, i2c->tx_msg, fifo_space); 591 592 if (!i2c->tx_msg) 593 return; 594 595 i2c->rx_pos = 0; 596 i2c->tx_pos = 0; 597 i2c->state = STATE_START; 598 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { 599 if (!first) { 600 i2c->nmsgs--; 601 i2c->tx_msg++; 602 i2c->tx_pos = 0; 603 } else 604 first = 0; 605 606 if (i2c->tx_msg->flags & I2C_M_RD) { 607 /* we dont date putting several reads in the FIFO */ 608 xiic_start_recv(i2c); 609 return; 610 } else { 611 xiic_start_send(i2c); 612 if (xiic_tx_space(i2c) != 0) { 613 /* the message could not be completely sent */ 614 break; 615 } 616 } 617 618 fifo_space = xiic_tx_fifo_space(i2c); 619 } 620 621 /* there are more messages or the current one could not be completely 622 * put into the FIFO, also enable the half empty interrupt 623 */ 624 if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) 625 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); 626 627 } 628 629 static void xiic_start_xfer(struct xiic_i2c *i2c) 630 { 631 unsigned long flags; 632 633 spin_lock_irqsave(&i2c->lock, flags); 634 xiic_reinit(i2c); 635 /* disable interrupts globally */ 636 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); 637 spin_unlock_irqrestore(&i2c->lock, flags); 638 639 __xiic_start_xfer(i2c); 640 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 641 } 642 643 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 644 { 645 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 646 int err; 647 648 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 649 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 650 651 err = xiic_busy(i2c); 652 if (err) 653 return err; 654 655 i2c->tx_msg = msgs; 656 i2c->nmsgs = num; 657 658 xiic_start_xfer(i2c); 659 660 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 661 (i2c->state == STATE_DONE), HZ)) 662 return (i2c->state == STATE_DONE) ? num : -EIO; 663 else { 664 i2c->tx_msg = NULL; 665 i2c->rx_msg = NULL; 666 i2c->nmsgs = 0; 667 return -ETIMEDOUT; 668 } 669 } 670 671 static u32 xiic_func(struct i2c_adapter *adap) 672 { 673 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 674 } 675 676 static const struct i2c_algorithm xiic_algorithm = { 677 .master_xfer = xiic_xfer, 678 .functionality = xiic_func, 679 }; 680 681 static struct i2c_adapter xiic_adapter = { 682 .owner = THIS_MODULE, 683 .name = DRIVER_NAME, 684 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 685 .algo = &xiic_algorithm, 686 }; 687 688 689 static int xiic_i2c_probe(struct platform_device *pdev) 690 { 691 struct xiic_i2c *i2c; 692 struct xiic_i2c_platform_data *pdata; 693 struct resource *res; 694 int ret, irq; 695 u8 i; 696 697 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 698 if (!res) 699 goto resource_missing; 700 701 irq = platform_get_irq(pdev, 0); 702 if (irq < 0) 703 goto resource_missing; 704 705 pdata = dev_get_platdata(&pdev->dev); 706 707 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); 708 if (!i2c) 709 return -ENOMEM; 710 711 if (!request_mem_region(res->start, resource_size(res), pdev->name)) { 712 dev_err(&pdev->dev, "Memory region busy\n"); 713 ret = -EBUSY; 714 goto request_mem_failed; 715 } 716 717 i2c->base = ioremap(res->start, resource_size(res)); 718 if (!i2c->base) { 719 dev_err(&pdev->dev, "Unable to map registers\n"); 720 ret = -EIO; 721 goto map_failed; 722 } 723 724 /* hook up driver to tree */ 725 platform_set_drvdata(pdev, i2c); 726 i2c->adap = xiic_adapter; 727 i2c_set_adapdata(&i2c->adap, i2c); 728 i2c->adap.dev.parent = &pdev->dev; 729 i2c->adap.dev.of_node = pdev->dev.of_node; 730 731 xiic_reinit(i2c); 732 733 spin_lock_init(&i2c->lock); 734 init_waitqueue_head(&i2c->wait); 735 ret = request_irq(irq, xiic_isr, 0, pdev->name, i2c); 736 if (ret) { 737 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 738 goto request_irq_failed; 739 } 740 741 /* add i2c adapter to i2c tree */ 742 ret = i2c_add_adapter(&i2c->adap); 743 if (ret) { 744 dev_err(&pdev->dev, "Failed to add adapter\n"); 745 goto add_adapter_failed; 746 } 747 748 if (pdata) { 749 /* add in known devices to the bus */ 750 for (i = 0; i < pdata->num_devices; i++) 751 i2c_new_device(&i2c->adap, pdata->devices + i); 752 } 753 754 return 0; 755 756 add_adapter_failed: 757 free_irq(irq, i2c); 758 request_irq_failed: 759 xiic_deinit(i2c); 760 iounmap(i2c->base); 761 map_failed: 762 release_mem_region(res->start, resource_size(res)); 763 request_mem_failed: 764 kfree(i2c); 765 766 return ret; 767 resource_missing: 768 dev_err(&pdev->dev, "IRQ or Memory resource is missing\n"); 769 return -ENOENT; 770 } 771 772 static int xiic_i2c_remove(struct platform_device *pdev) 773 { 774 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 775 struct resource *res; 776 777 /* remove adapter & data */ 778 i2c_del_adapter(&i2c->adap); 779 780 xiic_deinit(i2c); 781 782 free_irq(platform_get_irq(pdev, 0), i2c); 783 784 iounmap(i2c->base); 785 786 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 787 if (res) 788 release_mem_region(res->start, resource_size(res)); 789 790 kfree(i2c); 791 792 return 0; 793 } 794 795 #if defined(CONFIG_OF) 796 static const struct of_device_id xiic_of_match[] = { 797 { .compatible = "xlnx,xps-iic-2.00.a", }, 798 {}, 799 }; 800 MODULE_DEVICE_TABLE(of, xiic_of_match); 801 #endif 802 803 static struct platform_driver xiic_i2c_driver = { 804 .probe = xiic_i2c_probe, 805 .remove = xiic_i2c_remove, 806 .driver = { 807 .owner = THIS_MODULE, 808 .name = DRIVER_NAME, 809 .of_match_table = of_match_ptr(xiic_of_match), 810 }, 811 }; 812 813 module_platform_driver(xiic_i2c_driver); 814 815 MODULE_AUTHOR("info@mocean-labs.com"); 816 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 817 MODULE_LICENSE("GPL v2"); 818 MODULE_ALIAS("platform:"DRIVER_NAME); 819