1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i2c-xiic.c 4 * Copyright (c) 2002-2007 Xilinx Inc. 5 * Copyright (c) 2009-2010 Intel Corporation 6 * 7 * This code was implemented by Mocean Laboratories AB when porting linux 8 * to the automotive development board Russellville. The copyright holder 9 * as seen in the header is Intel corporation. 10 * Mocean Laboratories forked off the GNU/Linux platform work into a 11 * separate company called Pelagicore AB, which committed the code to the 12 * kernel. 13 */ 14 15 /* Supports: 16 * Xilinx IIC 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/i2c.h> 25 #include <linux/interrupt.h> 26 #include <linux/completion.h> 27 #include <linux/platform_data/i2c-xiic.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 #include <linux/pm_runtime.h> 33 34 #define DRIVER_NAME "xiic-i2c" 35 #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0) 36 37 enum xilinx_i2c_state { 38 STATE_DONE, 39 STATE_ERROR, 40 STATE_START 41 }; 42 43 enum xiic_endian { 44 LITTLE, 45 BIG 46 }; 47 48 /** 49 * struct xiic_i2c - Internal representation of the XIIC I2C bus 50 * @dev: Pointer to device structure 51 * @base: Memory base of the HW registers 52 * @completion: Completion for callers 53 * @adap: Kernel adapter representation 54 * @tx_msg: Messages from above to be sent 55 * @lock: Mutual exclusion 56 * @tx_pos: Current pos in TX message 57 * @nmsgs: Number of messages in tx_msg 58 * @rx_msg: Current RX message 59 * @rx_pos: Position within current RX message 60 * @endianness: big/little-endian byte order 61 * @clk: Pointer to AXI4-lite input clock 62 * @state: See STATE_ 63 * @singlemaster: Indicates bus is single master 64 * @dynamic: Mode of controller 65 * @prev_msg_tx: Previous message is Tx 66 * @quirks: To hold platform specific bug info 67 */ 68 struct xiic_i2c { 69 struct device *dev; 70 void __iomem *base; 71 struct completion completion; 72 struct i2c_adapter adap; 73 struct i2c_msg *tx_msg; 74 struct mutex lock; 75 unsigned int tx_pos; 76 unsigned int nmsgs; 77 struct i2c_msg *rx_msg; 78 int rx_pos; 79 enum xiic_endian endianness; 80 struct clk *clk; 81 enum xilinx_i2c_state state; 82 bool singlemaster; 83 bool dynamic; 84 bool prev_msg_tx; 85 u32 quirks; 86 }; 87 88 struct xiic_version_data { 89 u32 quirks; 90 }; 91 92 #define XIIC_MSB_OFFSET 0 93 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET) 94 95 /* 96 * Register offsets in bytes from RegisterBase. Three is added to the 97 * base offset to access LSB (IBM style) of the word 98 */ 99 #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */ 100 #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */ 101 #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */ 102 #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */ 103 #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */ 104 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 105 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 106 #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */ 107 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 108 #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */ 109 110 /* Control Register masks */ 111 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 112 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 113 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 114 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 115 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 116 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 117 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 118 119 /* Status Register masks */ 120 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 121 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 122 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 123 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 124 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 125 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 126 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 127 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 128 129 /* Interrupt Status Register masks Interrupt occurs when... */ 130 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 131 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 132 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 133 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 134 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 135 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 136 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 137 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 138 139 /* The following constants specify the depth of the FIFOs */ 140 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 141 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 142 143 /* The following constants specify groups of interrupts that are typically 144 * enabled or disables at the same time 145 */ 146 #define XIIC_TX_INTERRUPTS \ 147 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 148 149 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 150 151 /* 152 * Tx Fifo upper bit masks. 153 */ 154 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 155 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 156 157 /* Dynamic mode constants */ 158 #define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */ 159 160 /* 161 * The following constants define the register offsets for the Interrupt 162 * registers. There are some holes in the memory map for reserved addresses 163 * to allow other registers to be added and still match the memory map of the 164 * interrupt controller registers 165 */ 166 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 167 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 168 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 169 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 170 171 #define XIIC_RESET_MASK 0xAUL 172 173 #define XIIC_PM_TIMEOUT 1000 /* ms */ 174 /* timeout waiting for the controller to respond */ 175 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 176 /* timeout waiting for the controller finish transfers */ 177 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 178 179 /* 180 * The following constant is used for the device global interrupt enable 181 * register, to enable all interrupts for the device, this is the only bit 182 * in the register 183 */ 184 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 185 186 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 187 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 188 189 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 190 static void __xiic_start_xfer(struct xiic_i2c *i2c); 191 192 /* 193 * For the register read and write functions, a little-endian and big-endian 194 * version are necessary. Endianness is detected during the probe function. 195 * Only the least significant byte [doublet] of the register are ever 196 * accessed. This requires an offset of 3 [2] from the base address for 197 * big-endian systems. 198 */ 199 200 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 201 { 202 if (i2c->endianness == LITTLE) 203 iowrite8(value, i2c->base + reg); 204 else 205 iowrite8(value, i2c->base + reg + 3); 206 } 207 208 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 209 { 210 u8 ret; 211 212 if (i2c->endianness == LITTLE) 213 ret = ioread8(i2c->base + reg); 214 else 215 ret = ioread8(i2c->base + reg + 3); 216 return ret; 217 } 218 219 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 220 { 221 if (i2c->endianness == LITTLE) 222 iowrite16(value, i2c->base + reg); 223 else 224 iowrite16be(value, i2c->base + reg + 2); 225 } 226 227 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 228 { 229 if (i2c->endianness == LITTLE) 230 iowrite32(value, i2c->base + reg); 231 else 232 iowrite32be(value, i2c->base + reg); 233 } 234 235 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 236 { 237 u32 ret; 238 239 if (i2c->endianness == LITTLE) 240 ret = ioread32(i2c->base + reg); 241 else 242 ret = ioread32be(i2c->base + reg); 243 return ret; 244 } 245 246 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 247 { 248 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 249 250 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 251 } 252 253 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 254 { 255 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 256 257 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 258 } 259 260 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 261 { 262 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 263 264 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 265 } 266 267 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 268 { 269 xiic_irq_clr(i2c, mask); 270 xiic_irq_en(i2c, mask); 271 } 272 273 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 274 { 275 u8 sr; 276 unsigned long timeout; 277 278 timeout = jiffies + XIIC_I2C_TIMEOUT; 279 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 280 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 281 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 282 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 283 if (time_after(jiffies, timeout)) { 284 dev_err(i2c->dev, "Failed to clear rx fifo\n"); 285 return -ETIMEDOUT; 286 } 287 } 288 289 return 0; 290 } 291 292 static int xiic_wait_tx_empty(struct xiic_i2c *i2c) 293 { 294 u8 isr; 295 unsigned long timeout; 296 297 timeout = jiffies + XIIC_I2C_TIMEOUT; 298 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 299 !(isr & XIIC_INTR_TX_EMPTY_MASK); 300 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { 301 if (time_after(jiffies, timeout)) { 302 dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); 303 return -ETIMEDOUT; 304 } 305 } 306 307 return 0; 308 } 309 310 static int xiic_reinit(struct xiic_i2c *i2c) 311 { 312 int ret; 313 314 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 315 316 /* Set receive Fifo depth to maximum (zero based). */ 317 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 318 319 /* Reset Tx Fifo. */ 320 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 321 322 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 323 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 324 325 /* make sure RX fifo is empty */ 326 ret = xiic_clear_rx_fifo(i2c); 327 if (ret) 328 return ret; 329 330 /* Enable interrupts */ 331 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 332 333 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 334 335 return 0; 336 } 337 338 static void xiic_deinit(struct xiic_i2c *i2c) 339 { 340 u8 cr; 341 342 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 343 344 /* Disable IIC Device. */ 345 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 346 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 347 } 348 349 static void xiic_read_rx(struct xiic_i2c *i2c) 350 { 351 u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; 352 u32 bytes_rem = 0; 353 int i; 354 355 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 356 357 dev_dbg(i2c->adap.dev.parent, 358 "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", 359 __func__, bytes_in_fifo, xiic_rx_space(i2c), 360 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 361 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 362 363 if (bytes_in_fifo > xiic_rx_space(i2c)) 364 bytes_in_fifo = xiic_rx_space(i2c); 365 366 bytes_to_read = bytes_in_fifo; 367 368 if (!i2c->dynamic) { 369 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; 370 371 if (bytes_rem > IIC_RX_FIFO_DEPTH) { 372 bytes_to_read = bytes_in_fifo; 373 } else if (bytes_rem > 1) { 374 bytes_to_read = bytes_rem - 1; 375 } else if (bytes_rem == 1) { 376 bytes_to_read = 1; 377 /* Set NACK in CR to indicate slave transmitter */ 378 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 379 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | 380 XIIC_CR_NO_ACK_MASK); 381 } else if (bytes_rem == 0) { 382 bytes_to_read = bytes_in_fifo; 383 384 /* Generate stop on the bus if it is last message */ 385 if (i2c->nmsgs == 1) { 386 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 387 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 388 ~XIIC_CR_MSMS_MASK); 389 } 390 391 /* Make TXACK=0, clean up for next transaction */ 392 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 393 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 394 ~XIIC_CR_NO_ACK_MASK); 395 } 396 } 397 398 /* Read the fifo */ 399 for (i = 0; i < bytes_to_read; i++) { 400 i2c->rx_msg->buf[i2c->rx_pos++] = 401 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 402 } 403 404 if (i2c->dynamic) { 405 u8 bytes; 406 407 /* Receive remaining bytes if less than fifo depth */ 408 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); 409 bytes--; 410 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); 411 } 412 } 413 414 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 415 { 416 /* return the actual space left in the FIFO */ 417 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 418 } 419 420 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 421 { 422 u8 fifo_space = xiic_tx_fifo_space(i2c); 423 int len = xiic_tx_space(i2c); 424 425 len = (len > fifo_space) ? fifo_space : len; 426 427 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 428 __func__, len, fifo_space); 429 430 while (len--) { 431 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 432 433 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { 434 /* last message in transfer -> STOP */ 435 if (i2c->dynamic) { 436 data |= XIIC_TX_DYN_STOP_MASK; 437 } else { 438 u8 cr; 439 /* Write to CR to stop */ 440 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 441 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 442 ~XIIC_CR_MSMS_MASK); 443 } 444 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 445 } 446 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 447 } 448 } 449 450 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) 451 { 452 i2c->tx_msg = NULL; 453 i2c->rx_msg = NULL; 454 i2c->nmsgs = 0; 455 i2c->state = code; 456 complete(&i2c->completion); 457 } 458 459 static irqreturn_t xiic_process(int irq, void *dev_id) 460 { 461 struct xiic_i2c *i2c = dev_id; 462 u32 pend, isr, ier; 463 u32 clr = 0; 464 int xfer_more = 0; 465 int wakeup_req = 0; 466 enum xilinx_i2c_state wakeup_code = STATE_DONE; 467 int ret; 468 469 /* Get the interrupt Status from the IPIF. There is no clearing of 470 * interrupts in the IPIF. Interrupts must be cleared at the source. 471 * To find which interrupts are pending; AND interrupts pending with 472 * interrupts masked. 473 */ 474 mutex_lock(&i2c->lock); 475 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 476 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 477 pend = isr & ier; 478 479 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 480 __func__, ier, isr, pend); 481 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 482 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 483 i2c->tx_msg, i2c->nmsgs); 484 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", 485 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 486 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 487 488 /* Service requesting interrupt */ 489 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 490 ((pend & XIIC_INTR_TX_ERROR_MASK) && 491 !(pend & XIIC_INTR_RX_FULL_MASK))) { 492 /* bus arbritration lost, or... 493 * Transmit error _OR_ RX completed 494 * if this happens when RX_FULL is not set 495 * this is probably a TX error 496 */ 497 498 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 499 500 /* dynamic mode seem to suffer from problems if we just flushes 501 * fifos and the next message is a TX with len 0 (only addr) 502 * reset the IP instead of just flush fifos 503 */ 504 ret = xiic_reinit(i2c); 505 if (!ret) 506 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); 507 508 if (i2c->rx_msg) { 509 wakeup_req = 1; 510 wakeup_code = STATE_ERROR; 511 } 512 if (i2c->tx_msg) { 513 wakeup_req = 1; 514 wakeup_code = STATE_ERROR; 515 } 516 } 517 if (pend & XIIC_INTR_RX_FULL_MASK) { 518 /* Receive register/FIFO is full */ 519 520 clr |= XIIC_INTR_RX_FULL_MASK; 521 if (!i2c->rx_msg) { 522 dev_dbg(i2c->adap.dev.parent, 523 "%s unexpected RX IRQ\n", __func__); 524 xiic_clear_rx_fifo(i2c); 525 goto out; 526 } 527 528 xiic_read_rx(i2c); 529 if (xiic_rx_space(i2c) == 0) { 530 /* this is the last part of the message */ 531 i2c->rx_msg = NULL; 532 533 /* also clear TX error if there (RX complete) */ 534 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 535 536 dev_dbg(i2c->adap.dev.parent, 537 "%s end of message, nmsgs: %d\n", 538 __func__, i2c->nmsgs); 539 540 /* send next message if this wasn't the last, 541 * otherwise the transfer will be finialise when 542 * receiving the bus not busy interrupt 543 */ 544 if (i2c->nmsgs > 1) { 545 i2c->nmsgs--; 546 i2c->tx_msg++; 547 dev_dbg(i2c->adap.dev.parent, 548 "%s will start next...\n", __func__); 549 xfer_more = 1; 550 } 551 } 552 } 553 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 554 /* Transmit register/FIFO is empty or ½ empty */ 555 556 clr |= (pend & 557 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 558 559 if (!i2c->tx_msg) { 560 dev_dbg(i2c->adap.dev.parent, 561 "%s unexpected TX IRQ\n", __func__); 562 goto out; 563 } 564 565 xiic_fill_tx_fifo(i2c); 566 567 /* current message sent and there is space in the fifo */ 568 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 569 dev_dbg(i2c->adap.dev.parent, 570 "%s end of message sent, nmsgs: %d\n", 571 __func__, i2c->nmsgs); 572 if (i2c->nmsgs > 1) { 573 i2c->nmsgs--; 574 i2c->tx_msg++; 575 xfer_more = 1; 576 } else { 577 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 578 579 dev_dbg(i2c->adap.dev.parent, 580 "%s Got TX IRQ but no more to do...\n", 581 __func__); 582 } 583 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 584 /* current frame is sent and is last, 585 * make sure to disable tx half 586 */ 587 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 588 } 589 590 if (pend & XIIC_INTR_BNB_MASK) { 591 /* IIC bus has transitioned to not busy */ 592 clr |= XIIC_INTR_BNB_MASK; 593 594 /* The bus is not busy, disable BusNotBusy interrupt */ 595 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 596 597 if (!i2c->tx_msg) 598 goto out; 599 600 wakeup_req = 1; 601 602 if (i2c->nmsgs == 1 && !i2c->rx_msg && 603 xiic_tx_space(i2c) == 0) 604 wakeup_code = STATE_DONE; 605 else 606 wakeup_code = STATE_ERROR; 607 } 608 609 out: 610 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 611 612 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 613 if (xfer_more) 614 __xiic_start_xfer(i2c); 615 if (wakeup_req) 616 xiic_wakeup(i2c, wakeup_code); 617 618 WARN_ON(xfer_more && wakeup_req); 619 620 mutex_unlock(&i2c->lock); 621 return IRQ_HANDLED; 622 } 623 624 static int xiic_bus_busy(struct xiic_i2c *i2c) 625 { 626 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 627 628 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 629 } 630 631 static int xiic_busy(struct xiic_i2c *i2c) 632 { 633 int tries = 3; 634 int err; 635 636 if (i2c->tx_msg || i2c->rx_msg) 637 return -EBUSY; 638 639 /* In single master mode bus can only be busy, when in use by this 640 * driver. If the register indicates bus being busy for some reason we 641 * should ignore it, since bus will never be released and i2c will be 642 * stuck forever. 643 */ 644 if (i2c->singlemaster) { 645 return 0; 646 } 647 648 /* for instance if previous transfer was terminated due to TX error 649 * it might be that the bus is on it's way to become available 650 * give it at most 3 ms to wake 651 */ 652 err = xiic_bus_busy(i2c); 653 while (err && tries--) { 654 msleep(1); 655 err = xiic_bus_busy(i2c); 656 } 657 658 return err; 659 } 660 661 static void xiic_start_recv(struct xiic_i2c *i2c) 662 { 663 u16 rx_watermark; 664 u8 cr = 0, rfd_set = 0; 665 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 666 unsigned long flags; 667 668 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 669 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 670 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 671 672 /* Disable Tx interrupts */ 673 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); 674 675 if (i2c->dynamic) { 676 u8 bytes; 677 u16 val; 678 679 /* Clear and enable Rx full interrupt. */ 680 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 681 XIIC_INTR_TX_ERROR_MASK); 682 683 /* 684 * We want to get all but last byte, because the TX_ERROR IRQ 685 * is used to indicate error ACK on the address, and 686 * negative ack on the last received byte, so to not mix 687 * them receive all but last. 688 * In the case where there is only one byte to receive 689 * we can check if ERROR and RX full is set at the same time 690 */ 691 rx_watermark = msg->len; 692 bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH); 693 694 if (rx_watermark > 0) 695 bytes--; 696 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); 697 698 local_irq_save(flags); 699 700 /* write the address */ 701 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 702 i2c_8bit_addr_from_msg(msg) | 703 XIIC_TX_DYN_START_MASK); 704 705 /* If last message, include dynamic stop bit with length */ 706 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; 707 val |= msg->len; 708 709 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); 710 711 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 712 713 local_irq_restore(flags); 714 } else { 715 /* 716 * If previous message is Tx, make sure that Tx FIFO is empty 717 * before starting a new transfer as the repeated start in 718 * standard mode can corrupt the transaction if there are 719 * still bytes to be transmitted in FIFO 720 */ 721 if (i2c->prev_msg_tx) { 722 int status; 723 724 status = xiic_wait_tx_empty(i2c); 725 if (status) 726 return; 727 } 728 729 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 730 731 /* Set Receive fifo depth */ 732 rx_watermark = msg->len; 733 if (rx_watermark > IIC_RX_FIFO_DEPTH) { 734 rfd_set = IIC_RX_FIFO_DEPTH - 1; 735 } else if (rx_watermark == 1) { 736 rfd_set = rx_watermark - 1; 737 /* Handle single byte transfer separately */ 738 cr |= XIIC_CR_NO_ACK_MASK; 739 } else if (rx_watermark == 0) { 740 rfd_set = rx_watermark; 741 cr |= XIIC_CR_NO_ACK_MASK; 742 } else { 743 rfd_set = rx_watermark - 2; 744 } 745 /* Check if RSTA should be set */ 746 if (cr & XIIC_CR_MSMS_MASK) { 747 /* Already a master, RSTA should be set */ 748 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 749 XIIC_CR_REPEATED_START_MASK) & 750 ~(XIIC_CR_DIR_IS_TX_MASK)); 751 } 752 753 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); 754 755 /* Clear and enable Rx full and transmit complete interrupts */ 756 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 757 XIIC_INTR_TX_ERROR_MASK); 758 759 /* Write the address */ 760 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 761 i2c_8bit_addr_from_msg(msg)); 762 763 /* Write to Control Register,to start transaction in Rx mode */ 764 if ((cr & XIIC_CR_MSMS_MASK) == 0) { 765 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 766 XIIC_CR_MSMS_MASK) 767 & ~(XIIC_CR_DIR_IS_TX_MASK)); 768 } 769 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", 770 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 771 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 772 } 773 774 if (i2c->nmsgs == 1) 775 /* very last, enable bus not busy as well */ 776 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 777 778 /* the message is tx:ed */ 779 i2c->tx_pos = msg->len; 780 781 /* Enable interrupts */ 782 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 783 784 i2c->prev_msg_tx = false; 785 } 786 787 static void xiic_start_send(struct xiic_i2c *i2c) 788 { 789 u8 cr = 0; 790 u16 data; 791 struct i2c_msg *msg = i2c->tx_msg; 792 793 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 794 __func__, msg, msg->len); 795 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 796 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 797 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 798 799 if (i2c->dynamic) { 800 /* write the address */ 801 data = i2c_8bit_addr_from_msg(msg) | 802 XIIC_TX_DYN_START_MASK; 803 804 if (i2c->nmsgs == 1 && msg->len == 0) 805 /* no data and last message -> add STOP */ 806 data |= XIIC_TX_DYN_STOP_MASK; 807 808 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 809 810 /* Clear any pending Tx empty, Tx Error and then enable them */ 811 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | 812 XIIC_INTR_TX_ERROR_MASK | 813 XIIC_INTR_BNB_MASK | 814 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? 815 XIIC_INTR_TX_HALF_MASK : 0)); 816 817 xiic_fill_tx_fifo(i2c); 818 } else { 819 /* 820 * If previous message is Tx, make sure that Tx FIFO is empty 821 * before starting a new transfer as the repeated start in 822 * standard mode can corrupt the transaction if there are 823 * still bytes to be transmitted in FIFO 824 */ 825 if (i2c->prev_msg_tx) { 826 int status; 827 828 status = xiic_wait_tx_empty(i2c); 829 if (status) 830 return; 831 } 832 /* Check if RSTA should be set */ 833 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 834 if (cr & XIIC_CR_MSMS_MASK) { 835 /* Already a master, RSTA should be set */ 836 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | 837 XIIC_CR_REPEATED_START_MASK | 838 XIIC_CR_DIR_IS_TX_MASK) & 839 ~(XIIC_CR_NO_ACK_MASK)); 840 } 841 842 /* Write address to FIFO */ 843 data = i2c_8bit_addr_from_msg(msg); 844 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 845 846 /* Fill fifo */ 847 xiic_fill_tx_fifo(i2c); 848 849 if ((cr & XIIC_CR_MSMS_MASK) == 0) { 850 /* Start Tx by writing to CR */ 851 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 852 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | 853 XIIC_CR_MSMS_MASK | 854 XIIC_CR_DIR_IS_TX_MASK); 855 } 856 857 /* Clear any pending Tx empty, Tx Error and then enable them */ 858 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | 859 XIIC_INTR_TX_ERROR_MASK | 860 XIIC_INTR_BNB_MASK); 861 } 862 i2c->prev_msg_tx = true; 863 } 864 865 static void __xiic_start_xfer(struct xiic_i2c *i2c) 866 { 867 int fifo_space = xiic_tx_fifo_space(i2c); 868 869 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 870 __func__, i2c->tx_msg, fifo_space); 871 872 if (!i2c->tx_msg) 873 return; 874 875 i2c->rx_pos = 0; 876 i2c->tx_pos = 0; 877 i2c->state = STATE_START; 878 if (i2c->tx_msg->flags & I2C_M_RD) { 879 /* we dont date putting several reads in the FIFO */ 880 xiic_start_recv(i2c); 881 } else { 882 xiic_start_send(i2c); 883 } 884 } 885 886 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) 887 { 888 bool broken_read, max_read_len, smbus_blk_read; 889 int ret, count; 890 891 mutex_lock(&i2c->lock); 892 893 ret = xiic_busy(i2c); 894 if (ret) 895 goto out; 896 897 i2c->tx_msg = msgs; 898 i2c->rx_msg = NULL; 899 i2c->nmsgs = num; 900 init_completion(&i2c->completion); 901 902 /* Decide standard mode or Dynamic mode */ 903 i2c->dynamic = true; 904 905 /* Initialize prev message type */ 906 i2c->prev_msg_tx = false; 907 908 /* 909 * Scan through nmsgs, use dynamic mode when none of the below three 910 * conditions occur. We need standard mode even if one condition holds 911 * true in the entire array of messages in a single transfer. 912 * If read transaction as dynamic mode is broken for delayed reads 913 * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions. 914 * If read length is > 255 bytes. 915 * If smbus_block_read transaction. 916 */ 917 for (count = 0; count < i2c->nmsgs; count++) { 918 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && 919 (i2c->tx_msg[count].flags & I2C_M_RD); 920 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && 921 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); 922 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); 923 924 if (broken_read || max_read_len || smbus_blk_read) { 925 i2c->dynamic = false; 926 break; 927 } 928 } 929 930 ret = xiic_reinit(i2c); 931 if (!ret) 932 __xiic_start_xfer(i2c); 933 934 out: 935 mutex_unlock(&i2c->lock); 936 937 return ret; 938 } 939 940 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 941 { 942 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 943 int err; 944 945 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 946 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 947 948 err = pm_runtime_resume_and_get(i2c->dev); 949 if (err < 0) 950 return err; 951 952 err = xiic_start_xfer(i2c, msgs, num); 953 if (err < 0) { 954 dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 955 return err; 956 } 957 958 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); 959 mutex_lock(&i2c->lock); 960 if (err == 0) { /* Timeout */ 961 i2c->tx_msg = NULL; 962 i2c->rx_msg = NULL; 963 i2c->nmsgs = 0; 964 err = -ETIMEDOUT; 965 } else if (err < 0) { /* Completion error */ 966 i2c->tx_msg = NULL; 967 i2c->rx_msg = NULL; 968 i2c->nmsgs = 0; 969 } else { 970 err = (i2c->state == STATE_DONE) ? num : -EIO; 971 } 972 mutex_unlock(&i2c->lock); 973 pm_runtime_mark_last_busy(i2c->dev); 974 pm_runtime_put_autosuspend(i2c->dev); 975 return err; 976 } 977 978 static u32 xiic_func(struct i2c_adapter *adap) 979 { 980 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 981 } 982 983 static const struct i2c_algorithm xiic_algorithm = { 984 .master_xfer = xiic_xfer, 985 .functionality = xiic_func, 986 }; 987 988 static const struct i2c_adapter xiic_adapter = { 989 .owner = THIS_MODULE, 990 .class = I2C_CLASS_DEPRECATED, 991 .algo = &xiic_algorithm, 992 }; 993 994 static const struct xiic_version_data xiic_2_00 = { 995 .quirks = DYNAMIC_MODE_READ_BROKEN_BIT, 996 }; 997 998 #if defined(CONFIG_OF) 999 static const struct of_device_id xiic_of_match[] = { 1000 { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 }, 1001 {}, 1002 }; 1003 MODULE_DEVICE_TABLE(of, xiic_of_match); 1004 #endif 1005 1006 static int xiic_i2c_probe(struct platform_device *pdev) 1007 { 1008 struct xiic_i2c *i2c; 1009 struct xiic_i2c_platform_data *pdata; 1010 const struct of_device_id *match; 1011 struct resource *res; 1012 int ret, irq; 1013 u8 i; 1014 u32 sr; 1015 1016 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1017 if (!i2c) 1018 return -ENOMEM; 1019 1020 match = of_match_node(xiic_of_match, pdev->dev.of_node); 1021 if (match && match->data) { 1022 const struct xiic_version_data *data = match->data; 1023 1024 i2c->quirks = data->quirks; 1025 } 1026 1027 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1028 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1029 if (IS_ERR(i2c->base)) 1030 return PTR_ERR(i2c->base); 1031 1032 irq = platform_get_irq(pdev, 0); 1033 if (irq < 0) 1034 return irq; 1035 1036 pdata = dev_get_platdata(&pdev->dev); 1037 1038 /* hook up driver to tree */ 1039 platform_set_drvdata(pdev, i2c); 1040 i2c->adap = xiic_adapter; 1041 i2c_set_adapdata(&i2c->adap, i2c); 1042 i2c->adap.dev.parent = &pdev->dev; 1043 i2c->adap.dev.of_node = pdev->dev.of_node; 1044 snprintf(i2c->adap.name, sizeof(i2c->adap.name), 1045 DRIVER_NAME " %s", pdev->name); 1046 1047 mutex_init(&i2c->lock); 1048 1049 i2c->clk = devm_clk_get(&pdev->dev, NULL); 1050 if (IS_ERR(i2c->clk)) 1051 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 1052 "input clock not found.\n"); 1053 1054 ret = clk_prepare_enable(i2c->clk); 1055 if (ret) { 1056 dev_err(&pdev->dev, "Unable to enable clock.\n"); 1057 return ret; 1058 } 1059 i2c->dev = &pdev->dev; 1060 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 1061 pm_runtime_use_autosuspend(i2c->dev); 1062 pm_runtime_set_active(i2c->dev); 1063 pm_runtime_enable(i2c->dev); 1064 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1065 xiic_process, IRQF_ONESHOT, 1066 pdev->name, i2c); 1067 1068 if (ret < 0) { 1069 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 1070 goto err_clk_dis; 1071 } 1072 1073 i2c->singlemaster = 1074 of_property_read_bool(pdev->dev.of_node, "single-master"); 1075 1076 /* 1077 * Detect endianness 1078 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 1079 * set, assume that the endianness was wrong and swap. 1080 */ 1081 i2c->endianness = LITTLE; 1082 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 1083 /* Reset is cleared in xiic_reinit */ 1084 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 1085 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 1086 i2c->endianness = BIG; 1087 1088 ret = xiic_reinit(i2c); 1089 if (ret < 0) { 1090 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 1091 goto err_clk_dis; 1092 } 1093 1094 /* add i2c adapter to i2c tree */ 1095 ret = i2c_add_adapter(&i2c->adap); 1096 if (ret) { 1097 xiic_deinit(i2c); 1098 goto err_clk_dis; 1099 } 1100 1101 if (pdata) { 1102 /* add in known devices to the bus */ 1103 for (i = 0; i < pdata->num_devices; i++) 1104 i2c_new_client_device(&i2c->adap, pdata->devices + i); 1105 } 1106 1107 return 0; 1108 1109 err_clk_dis: 1110 pm_runtime_set_suspended(&pdev->dev); 1111 pm_runtime_disable(&pdev->dev); 1112 clk_disable_unprepare(i2c->clk); 1113 return ret; 1114 } 1115 1116 static int xiic_i2c_remove(struct platform_device *pdev) 1117 { 1118 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 1119 int ret; 1120 1121 /* remove adapter & data */ 1122 i2c_del_adapter(&i2c->adap); 1123 1124 ret = pm_runtime_get_sync(i2c->dev); 1125 1126 if (ret < 0) 1127 dev_warn(&pdev->dev, "Failed to activate device for removal (%pe)\n", 1128 ERR_PTR(ret)); 1129 else 1130 xiic_deinit(i2c); 1131 1132 pm_runtime_put_sync(i2c->dev); 1133 clk_disable_unprepare(i2c->clk); 1134 pm_runtime_disable(&pdev->dev); 1135 pm_runtime_set_suspended(&pdev->dev); 1136 pm_runtime_dont_use_autosuspend(&pdev->dev); 1137 1138 return 0; 1139 } 1140 1141 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 1142 { 1143 struct xiic_i2c *i2c = dev_get_drvdata(dev); 1144 1145 clk_disable(i2c->clk); 1146 1147 return 0; 1148 } 1149 1150 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 1151 { 1152 struct xiic_i2c *i2c = dev_get_drvdata(dev); 1153 int ret; 1154 1155 ret = clk_enable(i2c->clk); 1156 if (ret) { 1157 dev_err(dev, "Cannot enable clock.\n"); 1158 return ret; 1159 } 1160 1161 return 0; 1162 } 1163 1164 static const struct dev_pm_ops xiic_dev_pm_ops = { 1165 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 1166 xiic_i2c_runtime_resume, NULL) 1167 }; 1168 1169 static struct platform_driver xiic_i2c_driver = { 1170 .probe = xiic_i2c_probe, 1171 .remove = xiic_i2c_remove, 1172 .driver = { 1173 .name = DRIVER_NAME, 1174 .of_match_table = of_match_ptr(xiic_of_match), 1175 .pm = &xiic_dev_pm_ops, 1176 }, 1177 }; 1178 1179 module_platform_driver(xiic_i2c_driver); 1180 1181 MODULE_ALIAS("platform:" DRIVER_NAME); 1182 MODULE_AUTHOR("info@mocean-labs.com"); 1183 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 1184 MODULE_LICENSE("GPL v2"); 1185