11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e1d5b659SRichard Röjfors /* 3e1d5b659SRichard Röjfors * i2c-xiic.c 4e1d5b659SRichard Röjfors * Copyright (c) 2002-2007 Xilinx Inc. 5e1d5b659SRichard Röjfors * Copyright (c) 2009-2010 Intel Corporation 6e1d5b659SRichard Röjfors * 7e1d5b659SRichard Röjfors * This code was implemented by Mocean Laboratories AB when porting linux 8e1d5b659SRichard Röjfors * to the automotive development board Russellville. The copyright holder 9e1d5b659SRichard Röjfors * as seen in the header is Intel corporation. 10e1d5b659SRichard Röjfors * Mocean Laboratories forked off the GNU/Linux platform work into a 1125985edcSLucas De Marchi * separate company called Pelagicore AB, which committed the code to the 12e1d5b659SRichard Röjfors * kernel. 13e1d5b659SRichard Röjfors */ 14e1d5b659SRichard Röjfors 15e1d5b659SRichard Röjfors /* Supports: 16e1d5b659SRichard Röjfors * Xilinx IIC 17e1d5b659SRichard Röjfors */ 18e1d5b659SRichard Röjfors #include <linux/kernel.h> 19e1d5b659SRichard Röjfors #include <linux/module.h> 20e1d5b659SRichard Röjfors #include <linux/errno.h> 21168e722dSKedareswara rao Appana #include <linux/err.h> 2202ca6c40SRandy Dunlap #include <linux/delay.h> 23e1d5b659SRichard Röjfors #include <linux/platform_device.h> 24e1d5b659SRichard Röjfors #include <linux/i2c.h> 25e1d5b659SRichard Röjfors #include <linux/interrupt.h> 26fdacc3c7SMarek Vasut #include <linux/completion.h> 277072b75cSWolfram Sang #include <linux/platform_data/i2c-xiic.h> 28e1d5b659SRichard Röjfors #include <linux/io.h> 295a0e3ad6STejun Heo #include <linux/slab.h> 304edd65e6SSachin Kamat #include <linux/of.h> 3136ecbcabSShubhrajyoti Datta #include <linux/clk.h> 3236ecbcabSShubhrajyoti Datta #include <linux/pm_runtime.h> 33e1d5b659SRichard Röjfors 34e1d5b659SRichard Röjfors #define DRIVER_NAME "xiic-i2c" 35e1d5b659SRichard Röjfors 36e1d5b659SRichard Röjfors enum xilinx_i2c_state { 37e1d5b659SRichard Röjfors STATE_DONE, 38e1d5b659SRichard Röjfors STATE_ERROR, 39e1d5b659SRichard Röjfors STATE_START 40e1d5b659SRichard Röjfors }; 41e1d5b659SRichard Röjfors 4248ef3ca9SThomas Gessler enum xiic_endian { 4348ef3ca9SThomas Gessler LITTLE, 4448ef3ca9SThomas Gessler BIG 4548ef3ca9SThomas Gessler }; 4648ef3ca9SThomas Gessler 47e1d5b659SRichard Röjfors /** 48e1d5b659SRichard Röjfors * struct xiic_i2c - Internal representation of the XIIC I2C bus 49bcc156e2SShubhrajyoti Datta * @dev: Pointer to device structure 50e1d5b659SRichard Röjfors * @base: Memory base of the HW registers 51fdacc3c7SMarek Vasut * @completion: Completion for callers 52e1d5b659SRichard Röjfors * @adap: Kernel adapter representation 53e1d5b659SRichard Röjfors * @tx_msg: Messages from above to be sent 54e1d5b659SRichard Röjfors * @lock: Mutual exclusion 55e1d5b659SRichard Röjfors * @tx_pos: Current pos in TX message 56e1d5b659SRichard Röjfors * @nmsgs: Number of messages in tx_msg 57e1d5b659SRichard Röjfors * @rx_msg: Current RX message 58e1d5b659SRichard Röjfors * @rx_pos: Position within current RX message 59bea6ff02SShubhrajyoti Datta * @endianness: big/little-endian byte order 60bcc156e2SShubhrajyoti Datta * @clk: Pointer to AXI4-lite input clock 619106e45cSJaakko Laine * @state: See STATE_ 629e3b184bSJaakko Laine * @singlemaster: Indicates bus is single master 63e1d5b659SRichard Röjfors */ 64e1d5b659SRichard Röjfors struct xiic_i2c { 6536ecbcabSShubhrajyoti Datta struct device *dev; 66e1d5b659SRichard Röjfors void __iomem *base; 67fdacc3c7SMarek Vasut struct completion completion; 68e1d5b659SRichard Röjfors struct i2c_adapter adap; 69e1d5b659SRichard Röjfors struct i2c_msg *tx_msg; 7077c68019SLars-Peter Clausen struct mutex lock; 71e1d5b659SRichard Röjfors unsigned int tx_pos; 72e1d5b659SRichard Röjfors unsigned int nmsgs; 73e1d5b659SRichard Röjfors struct i2c_msg *rx_msg; 74e1d5b659SRichard Röjfors int rx_pos; 7548ef3ca9SThomas Gessler enum xiic_endian endianness; 7636ecbcabSShubhrajyoti Datta struct clk *clk; 779106e45cSJaakko Laine enum xilinx_i2c_state state; 789e3b184bSJaakko Laine bool singlemaster; 79e1d5b659SRichard Röjfors }; 80e1d5b659SRichard Röjfors 81e1d5b659SRichard Röjfors #define XIIC_MSB_OFFSET 0 82e1d5b659SRichard Röjfors #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET) 83e1d5b659SRichard Röjfors 84e1d5b659SRichard Röjfors /* 85e1d5b659SRichard Röjfors * Register offsets in bytes from RegisterBase. Three is added to the 86e1d5b659SRichard Röjfors * base offset to access LSB (IBM style) of the word 87e1d5b659SRichard Röjfors */ 88e1d5b659SRichard Röjfors #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */ 89e1d5b659SRichard Röjfors #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */ 90e1d5b659SRichard Röjfors #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */ 91e1d5b659SRichard Röjfors #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */ 92e1d5b659SRichard Röjfors #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */ 93e1d5b659SRichard Röjfors #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 94e1d5b659SRichard Röjfors #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 95e1d5b659SRichard Röjfors #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */ 96e1d5b659SRichard Röjfors #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 97e1d5b659SRichard Röjfors #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */ 98e1d5b659SRichard Röjfors 99e1d5b659SRichard Röjfors /* Control Register masks */ 100e1d5b659SRichard Röjfors #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 101e1d5b659SRichard Röjfors #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 102e1d5b659SRichard Röjfors #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 103e1d5b659SRichard Röjfors #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 104e1d5b659SRichard Röjfors #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 105e1d5b659SRichard Röjfors #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 106e1d5b659SRichard Röjfors #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 107e1d5b659SRichard Röjfors 108e1d5b659SRichard Röjfors /* Status Register masks */ 109e1d5b659SRichard Röjfors #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 110e1d5b659SRichard Röjfors #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 111e1d5b659SRichard Röjfors #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 112e1d5b659SRichard Röjfors #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 113e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 114e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 115e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 116e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 117e1d5b659SRichard Röjfors 118e1d5b659SRichard Röjfors /* Interrupt Status Register masks Interrupt occurs when... */ 119e1d5b659SRichard Röjfors #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 120e1d5b659SRichard Röjfors #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 121e1d5b659SRichard Röjfors #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 122e1d5b659SRichard Röjfors #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 123e1d5b659SRichard Röjfors #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 124e1d5b659SRichard Röjfors #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 125e1d5b659SRichard Röjfors #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 126e1d5b659SRichard Röjfors #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 127e1d5b659SRichard Röjfors 128e1d5b659SRichard Röjfors /* The following constants specify the depth of the FIFOs */ 129e1d5b659SRichard Röjfors #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 130e1d5b659SRichard Röjfors #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 131e1d5b659SRichard Röjfors 132e1d5b659SRichard Röjfors /* The following constants specify groups of interrupts that are typically 133e1d5b659SRichard Röjfors * enabled or disables at the same time 134e1d5b659SRichard Röjfors */ 135e1d5b659SRichard Röjfors #define XIIC_TX_INTERRUPTS \ 136e1d5b659SRichard Röjfors (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 137e1d5b659SRichard Röjfors 138e1d5b659SRichard Röjfors #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 139e1d5b659SRichard Röjfors 140e1d5b659SRichard Röjfors /* 141e1d5b659SRichard Röjfors * Tx Fifo upper bit masks. 142e1d5b659SRichard Röjfors */ 143e1d5b659SRichard Röjfors #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 144e1d5b659SRichard Röjfors #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 145e1d5b659SRichard Röjfors 146e1d5b659SRichard Röjfors /* 147e1d5b659SRichard Röjfors * The following constants define the register offsets for the Interrupt 148e1d5b659SRichard Röjfors * registers. There are some holes in the memory map for reserved addresses 149e1d5b659SRichard Röjfors * to allow other registers to be added and still match the memory map of the 150e1d5b659SRichard Röjfors * interrupt controller registers 151e1d5b659SRichard Röjfors */ 152e1d5b659SRichard Röjfors #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 153e1d5b659SRichard Röjfors #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 154e1d5b659SRichard Röjfors #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 155e1d5b659SRichard Röjfors #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 156e1d5b659SRichard Röjfors 157e1d5b659SRichard Röjfors #define XIIC_RESET_MASK 0xAUL 158e1d5b659SRichard Röjfors 15936ecbcabSShubhrajyoti Datta #define XIIC_PM_TIMEOUT 1000 /* ms */ 160b4c119dbSShubhrajyoti Datta /* timeout waiting for the controller to respond */ 161b4c119dbSShubhrajyoti Datta #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 162fdacc3c7SMarek Vasut /* timeout waiting for the controller finish transfers */ 163fdacc3c7SMarek Vasut #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 164fdacc3c7SMarek Vasut 165e1d5b659SRichard Röjfors /* 166e1d5b659SRichard Röjfors * The following constant is used for the device global interrupt enable 167e1d5b659SRichard Röjfors * register, to enable all interrupts for the device, this is the only bit 168e1d5b659SRichard Röjfors * in the register 169e1d5b659SRichard Röjfors */ 170e1d5b659SRichard Röjfors #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 171e1d5b659SRichard Röjfors 172e1d5b659SRichard Röjfors #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 173e1d5b659SRichard Röjfors #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 174e1d5b659SRichard Röjfors 175c119e7d0SMarek Vasut static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 176e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c); 177e1d5b659SRichard Röjfors 17848ef3ca9SThomas Gessler /* 17948ef3ca9SThomas Gessler * For the register read and write functions, a little-endian and big-endian 18048ef3ca9SThomas Gessler * version are necessary. Endianness is detected during the probe function. 18148ef3ca9SThomas Gessler * Only the least significant byte [doublet] of the register are ever 18248ef3ca9SThomas Gessler * accessed. This requires an offset of 3 [2] from the base address for 18348ef3ca9SThomas Gessler * big-endian systems. 18448ef3ca9SThomas Gessler */ 18548ef3ca9SThomas Gessler 186e1d5b659SRichard Röjfors static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 187e1d5b659SRichard Röjfors { 18848ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 189e1d5b659SRichard Röjfors iowrite8(value, i2c->base + reg); 19048ef3ca9SThomas Gessler else 19148ef3ca9SThomas Gessler iowrite8(value, i2c->base + reg + 3); 192e1d5b659SRichard Röjfors } 193e1d5b659SRichard Röjfors 194e1d5b659SRichard Röjfors static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 195e1d5b659SRichard Röjfors { 19648ef3ca9SThomas Gessler u8 ret; 19748ef3ca9SThomas Gessler 19848ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 19948ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg); 20048ef3ca9SThomas Gessler else 20148ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg + 3); 20248ef3ca9SThomas Gessler return ret; 203e1d5b659SRichard Röjfors } 204e1d5b659SRichard Röjfors 205e1d5b659SRichard Röjfors static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 206e1d5b659SRichard Röjfors { 20748ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 208e1d5b659SRichard Röjfors iowrite16(value, i2c->base + reg); 20948ef3ca9SThomas Gessler else 21048ef3ca9SThomas Gessler iowrite16be(value, i2c->base + reg + 2); 211e1d5b659SRichard Röjfors } 212e1d5b659SRichard Röjfors 213e1d5b659SRichard Röjfors static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 214e1d5b659SRichard Röjfors { 21548ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 216e1d5b659SRichard Röjfors iowrite32(value, i2c->base + reg); 21748ef3ca9SThomas Gessler else 21848ef3ca9SThomas Gessler iowrite32be(value, i2c->base + reg); 219e1d5b659SRichard Röjfors } 220e1d5b659SRichard Röjfors 221e1d5b659SRichard Röjfors static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 222e1d5b659SRichard Röjfors { 22348ef3ca9SThomas Gessler u32 ret; 22448ef3ca9SThomas Gessler 22548ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 22648ef3ca9SThomas Gessler ret = ioread32(i2c->base + reg); 22748ef3ca9SThomas Gessler else 22848ef3ca9SThomas Gessler ret = ioread32be(i2c->base + reg); 22948ef3ca9SThomas Gessler return ret; 230e1d5b659SRichard Röjfors } 231e1d5b659SRichard Röjfors 232e1d5b659SRichard Röjfors static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 233e1d5b659SRichard Röjfors { 234e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 235b822039bSMichal Simek 236e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 237e1d5b659SRichard Röjfors } 238e1d5b659SRichard Röjfors 239e1d5b659SRichard Röjfors static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 240e1d5b659SRichard Röjfors { 241e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 242b822039bSMichal Simek 243e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 244e1d5b659SRichard Röjfors } 245e1d5b659SRichard Röjfors 246e1d5b659SRichard Röjfors static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 247e1d5b659SRichard Röjfors { 248e1d5b659SRichard Röjfors u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 249b822039bSMichal Simek 250e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 251e1d5b659SRichard Röjfors } 252e1d5b659SRichard Röjfors 253e1d5b659SRichard Röjfors static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 254e1d5b659SRichard Röjfors { 255e1d5b659SRichard Röjfors xiic_irq_clr(i2c, mask); 256e1d5b659SRichard Röjfors xiic_irq_en(i2c, mask); 257e1d5b659SRichard Röjfors } 258e1d5b659SRichard Röjfors 259b4c119dbSShubhrajyoti Datta static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 260e1d5b659SRichard Röjfors { 261e1d5b659SRichard Röjfors u8 sr; 262b4c119dbSShubhrajyoti Datta unsigned long timeout; 263b4c119dbSShubhrajyoti Datta 264b4c119dbSShubhrajyoti Datta timeout = jiffies + XIIC_I2C_TIMEOUT; 265e1d5b659SRichard Röjfors for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 266e1d5b659SRichard Röjfors !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 267b4c119dbSShubhrajyoti Datta sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 268e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 269b4c119dbSShubhrajyoti Datta if (time_after(jiffies, timeout)) { 270b4c119dbSShubhrajyoti Datta dev_err(i2c->dev, "Failed to clear rx fifo\n"); 271b4c119dbSShubhrajyoti Datta return -ETIMEDOUT; 272b4c119dbSShubhrajyoti Datta } 273e1d5b659SRichard Röjfors } 274e1d5b659SRichard Röjfors 275b4c119dbSShubhrajyoti Datta return 0; 276b4c119dbSShubhrajyoti Datta } 277b4c119dbSShubhrajyoti Datta 278b4c119dbSShubhrajyoti Datta static int xiic_reinit(struct xiic_i2c *i2c) 279e1d5b659SRichard Röjfors { 280b4c119dbSShubhrajyoti Datta int ret; 281b4c119dbSShubhrajyoti Datta 282e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 283e1d5b659SRichard Röjfors 284e1d5b659SRichard Röjfors /* Set receive Fifo depth to maximum (zero based). */ 285e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 286e1d5b659SRichard Röjfors 287e1d5b659SRichard Röjfors /* Reset Tx Fifo. */ 288e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 289e1d5b659SRichard Röjfors 290e1d5b659SRichard Röjfors /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 291e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 292e1d5b659SRichard Röjfors 293e1d5b659SRichard Röjfors /* make sure RX fifo is empty */ 294b4c119dbSShubhrajyoti Datta ret = xiic_clear_rx_fifo(i2c); 295b4c119dbSShubhrajyoti Datta if (ret) 296b4c119dbSShubhrajyoti Datta return ret; 297e1d5b659SRichard Röjfors 298e1d5b659SRichard Röjfors /* Enable interrupts */ 299e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 300e1d5b659SRichard Röjfors 301542e2a9bSShubhrajyoti Datta xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 302b4c119dbSShubhrajyoti Datta 303b4c119dbSShubhrajyoti Datta return 0; 304e1d5b659SRichard Röjfors } 305e1d5b659SRichard Röjfors 306e1d5b659SRichard Röjfors static void xiic_deinit(struct xiic_i2c *i2c) 307e1d5b659SRichard Röjfors { 308e1d5b659SRichard Röjfors u8 cr; 309e1d5b659SRichard Röjfors 310e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 311e1d5b659SRichard Röjfors 312e1d5b659SRichard Röjfors /* Disable IIC Device. */ 313e1d5b659SRichard Röjfors cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 314e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 315e1d5b659SRichard Röjfors } 316e1d5b659SRichard Röjfors 317e1d5b659SRichard Röjfors static void xiic_read_rx(struct xiic_i2c *i2c) 318e1d5b659SRichard Röjfors { 319e1d5b659SRichard Röjfors u8 bytes_in_fifo; 320e1d5b659SRichard Röjfors int i; 321e1d5b659SRichard Röjfors 322e1d5b659SRichard Röjfors bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 323e1d5b659SRichard Röjfors 324f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, 325f1e9f89aSKedareswara rao Appana "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 326e1d5b659SRichard Röjfors __func__, bytes_in_fifo, xiic_rx_space(i2c), 327e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 328e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 329e1d5b659SRichard Röjfors 330e1d5b659SRichard Röjfors if (bytes_in_fifo > xiic_rx_space(i2c)) 331e1d5b659SRichard Röjfors bytes_in_fifo = xiic_rx_space(i2c); 332e1d5b659SRichard Röjfors 333e1d5b659SRichard Röjfors for (i = 0; i < bytes_in_fifo; i++) 334e1d5b659SRichard Röjfors i2c->rx_msg->buf[i2c->rx_pos++] = 335e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 336e1d5b659SRichard Röjfors 337e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 338e1d5b659SRichard Röjfors (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 339e1d5b659SRichard Röjfors IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 340e1d5b659SRichard Röjfors } 341e1d5b659SRichard Röjfors 342e1d5b659SRichard Röjfors static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 343e1d5b659SRichard Röjfors { 344e1d5b659SRichard Röjfors /* return the actual space left in the FIFO */ 345e1d5b659SRichard Röjfors return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 346e1d5b659SRichard Röjfors } 347e1d5b659SRichard Röjfors 348e1d5b659SRichard Röjfors static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 349e1d5b659SRichard Röjfors { 350e1d5b659SRichard Röjfors u8 fifo_space = xiic_tx_fifo_space(i2c); 351e1d5b659SRichard Röjfors int len = xiic_tx_space(i2c); 352e1d5b659SRichard Röjfors 353e1d5b659SRichard Röjfors len = (len > fifo_space) ? fifo_space : len; 354e1d5b659SRichard Röjfors 355e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 356e1d5b659SRichard Röjfors __func__, len, fifo_space); 357e1d5b659SRichard Röjfors 358e1d5b659SRichard Röjfors while (len--) { 359e1d5b659SRichard Röjfors u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 360b822039bSMichal Simek 361b822039bSMichal Simek if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { 362e1d5b659SRichard Röjfors /* last message in transfer -> STOP */ 363e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 364e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 365c39e8e43SSteven A. Falco } 366e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 367e1d5b659SRichard Röjfors } 368e1d5b659SRichard Röjfors } 369e1d5b659SRichard Röjfors 370e749e4fcSShubhrajyoti Datta static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) 371e1d5b659SRichard Röjfors { 372e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 373e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 374e1d5b659SRichard Röjfors i2c->nmsgs = 0; 375e1d5b659SRichard Röjfors i2c->state = code; 376fdacc3c7SMarek Vasut complete(&i2c->completion); 377e1d5b659SRichard Röjfors } 378e1d5b659SRichard Röjfors 379fcc2fac6SShubhrajyoti Datta static irqreturn_t xiic_process(int irq, void *dev_id) 380e1d5b659SRichard Röjfors { 381fcc2fac6SShubhrajyoti Datta struct xiic_i2c *i2c = dev_id; 382e1d5b659SRichard Röjfors u32 pend, isr, ier; 383e1d5b659SRichard Röjfors u32 clr = 0; 384743e227aSMarek Vasut int xfer_more = 0; 385743e227aSMarek Vasut int wakeup_req = 0; 386e749e4fcSShubhrajyoti Datta enum xilinx_i2c_state wakeup_code = STATE_DONE; 3878fa9c938SShubhrajyoti Datta int ret; 388e1d5b659SRichard Röjfors 389e1d5b659SRichard Röjfors /* Get the interrupt Status from the IPIF. There is no clearing of 390e1d5b659SRichard Röjfors * interrupts in the IPIF. Interrupts must be cleared at the source. 391e1d5b659SRichard Röjfors * To find which interrupts are pending; AND interrupts pending with 392e1d5b659SRichard Röjfors * interrupts masked. 393e1d5b659SRichard Röjfors */ 39477c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 395e1d5b659SRichard Röjfors isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 396e1d5b659SRichard Röjfors ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 397e1d5b659SRichard Röjfors pend = isr & ier; 398e1d5b659SRichard Röjfors 399f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 400f1e9f89aSKedareswara rao Appana __func__, ier, isr, pend); 401f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 402f1e9f89aSKedareswara rao Appana __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 403e1d5b659SRichard Röjfors i2c->tx_msg, i2c->nmsgs); 404e1d5b659SRichard Röjfors 405e1d5b659SRichard Röjfors 406e1d5b659SRichard Röjfors /* Service requesting interrupt */ 407e1d5b659SRichard Röjfors if ((pend & XIIC_INTR_ARB_LOST_MASK) || 408e1d5b659SRichard Röjfors ((pend & XIIC_INTR_TX_ERROR_MASK) && 409e1d5b659SRichard Röjfors !(pend & XIIC_INTR_RX_FULL_MASK))) { 410e1d5b659SRichard Röjfors /* bus arbritration lost, or... 411e1d5b659SRichard Röjfors * Transmit error _OR_ RX completed 412e1d5b659SRichard Röjfors * if this happens when RX_FULL is not set 413e1d5b659SRichard Röjfors * this is probably a TX error 414e1d5b659SRichard Röjfors */ 415e1d5b659SRichard Röjfors 416e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 417e1d5b659SRichard Röjfors 418e1d5b659SRichard Röjfors /* dynamic mode seem to suffer from problems if we just flushes 419e1d5b659SRichard Röjfors * fifos and the next message is a TX with len 0 (only addr) 420e1d5b659SRichard Röjfors * reset the IP instead of just flush fifos 421e1d5b659SRichard Röjfors */ 4228fa9c938SShubhrajyoti Datta ret = xiic_reinit(i2c); 4238fa9c938SShubhrajyoti Datta if (!ret) 4248fa9c938SShubhrajyoti Datta dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); 425e1d5b659SRichard Röjfors 426743e227aSMarek Vasut if (i2c->rx_msg) { 427743e227aSMarek Vasut wakeup_req = 1; 428743e227aSMarek Vasut wakeup_code = STATE_ERROR; 429743e227aSMarek Vasut } 430743e227aSMarek Vasut if (i2c->tx_msg) { 431743e227aSMarek Vasut wakeup_req = 1; 432743e227aSMarek Vasut wakeup_code = STATE_ERROR; 433743e227aSMarek Vasut } 4347f9906bdSShubhrajyoti Datta } 4357f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_RX_FULL_MASK) { 436e1d5b659SRichard Röjfors /* Receive register/FIFO is full */ 437e1d5b659SRichard Röjfors 4387f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_RX_FULL_MASK; 439e1d5b659SRichard Röjfors if (!i2c->rx_msg) { 440e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 4411ee7cdbfSColin Ian King "%s unexpected RX IRQ\n", __func__); 442e1d5b659SRichard Röjfors xiic_clear_rx_fifo(i2c); 443e1d5b659SRichard Röjfors goto out; 444e1d5b659SRichard Röjfors } 445e1d5b659SRichard Röjfors 446e1d5b659SRichard Röjfors xiic_read_rx(i2c); 447e1d5b659SRichard Röjfors if (xiic_rx_space(i2c) == 0) { 448e1d5b659SRichard Röjfors /* this is the last part of the message */ 449e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 450e1d5b659SRichard Röjfors 451e1d5b659SRichard Röjfors /* also clear TX error if there (RX complete) */ 452e1d5b659SRichard Röjfors clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 453e1d5b659SRichard Röjfors 454e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 455e1d5b659SRichard Röjfors "%s end of message, nmsgs: %d\n", 456e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 457e1d5b659SRichard Röjfors 458e1d5b659SRichard Röjfors /* send next message if this wasn't the last, 459e1d5b659SRichard Röjfors * otherwise the transfer will be finialise when 460e1d5b659SRichard Röjfors * receiving the bus not busy interrupt 461e1d5b659SRichard Röjfors */ 462e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 463e1d5b659SRichard Röjfors i2c->nmsgs--; 464e1d5b659SRichard Röjfors i2c->tx_msg++; 465e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 466e1d5b659SRichard Röjfors "%s will start next...\n", __func__); 467743e227aSMarek Vasut xfer_more = 1; 468e1d5b659SRichard Röjfors } 469e1d5b659SRichard Röjfors } 4707f9906bdSShubhrajyoti Datta } 4717f9906bdSShubhrajyoti Datta if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 472d36b6910SAl Viro /* Transmit register/FIFO is empty or ½ empty */ 473e1d5b659SRichard Röjfors 4747f9906bdSShubhrajyoti Datta clr |= (pend & 4757f9906bdSShubhrajyoti Datta (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 476e1d5b659SRichard Röjfors 477e1d5b659SRichard Röjfors if (!i2c->tx_msg) { 478e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 4791ee7cdbfSColin Ian King "%s unexpected TX IRQ\n", __func__); 480e1d5b659SRichard Röjfors goto out; 481e1d5b659SRichard Röjfors } 482e1d5b659SRichard Röjfors 483e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c); 484e1d5b659SRichard Röjfors 485e1d5b659SRichard Röjfors /* current message sent and there is space in the fifo */ 486e1d5b659SRichard Röjfors if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 487e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 488e1d5b659SRichard Röjfors "%s end of message sent, nmsgs: %d\n", 489e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 490e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 491e1d5b659SRichard Röjfors i2c->nmsgs--; 492e1d5b659SRichard Röjfors i2c->tx_msg++; 493743e227aSMarek Vasut xfer_more = 1; 494e1d5b659SRichard Röjfors } else { 495e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 496e1d5b659SRichard Röjfors 497e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 498e1d5b659SRichard Röjfors "%s Got TX IRQ but no more to do...\n", 499e1d5b659SRichard Röjfors __func__); 500e1d5b659SRichard Röjfors } 501e1d5b659SRichard Röjfors } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 502e1d5b659SRichard Röjfors /* current frame is sent and is last, 503e1d5b659SRichard Röjfors * make sure to disable tx half 504e1d5b659SRichard Röjfors */ 505e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 506e1d5b659SRichard Röjfors } 5074bca93abSRaviteja Narayanam 5084bca93abSRaviteja Narayanam if (pend & XIIC_INTR_BNB_MASK) { 5094bca93abSRaviteja Narayanam /* IIC bus has transitioned to not busy */ 5104bca93abSRaviteja Narayanam clr |= XIIC_INTR_BNB_MASK; 5114bca93abSRaviteja Narayanam 5124bca93abSRaviteja Narayanam /* The bus is not busy, disable BusNotBusy interrupt */ 5134bca93abSRaviteja Narayanam xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 5144bca93abSRaviteja Narayanam 5154bca93abSRaviteja Narayanam if (!i2c->tx_msg) 5164bca93abSRaviteja Narayanam goto out; 5174bca93abSRaviteja Narayanam 5184bca93abSRaviteja Narayanam wakeup_req = 1; 5194bca93abSRaviteja Narayanam 5204bca93abSRaviteja Narayanam if (i2c->nmsgs == 1 && !i2c->rx_msg && 5214bca93abSRaviteja Narayanam xiic_tx_space(i2c) == 0) 5224bca93abSRaviteja Narayanam wakeup_code = STATE_DONE; 5234bca93abSRaviteja Narayanam else 5244bca93abSRaviteja Narayanam wakeup_code = STATE_ERROR; 5254bca93abSRaviteja Narayanam } 5264bca93abSRaviteja Narayanam 527e1d5b659SRichard Röjfors out: 528e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 529e1d5b659SRichard Röjfors 530e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 531743e227aSMarek Vasut if (xfer_more) 532743e227aSMarek Vasut __xiic_start_xfer(i2c); 533743e227aSMarek Vasut if (wakeup_req) 534743e227aSMarek Vasut xiic_wakeup(i2c, wakeup_code); 535743e227aSMarek Vasut 536743e227aSMarek Vasut WARN_ON(xfer_more && wakeup_req); 537743e227aSMarek Vasut 53877c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 539fcc2fac6SShubhrajyoti Datta return IRQ_HANDLED; 540e1d5b659SRichard Röjfors } 541e1d5b659SRichard Röjfors 542e1d5b659SRichard Röjfors static int xiic_bus_busy(struct xiic_i2c *i2c) 543e1d5b659SRichard Röjfors { 544e1d5b659SRichard Röjfors u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 545e1d5b659SRichard Röjfors 546e1d5b659SRichard Röjfors return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 547e1d5b659SRichard Röjfors } 548e1d5b659SRichard Röjfors 549e1d5b659SRichard Röjfors static int xiic_busy(struct xiic_i2c *i2c) 550e1d5b659SRichard Röjfors { 551e1d5b659SRichard Röjfors int tries = 3; 552e1d5b659SRichard Röjfors int err; 553e1d5b659SRichard Röjfors 554294b29f1SMarek Vasut if (i2c->tx_msg || i2c->rx_msg) 555e1d5b659SRichard Röjfors return -EBUSY; 556e1d5b659SRichard Röjfors 5579e3b184bSJaakko Laine /* In single master mode bus can only be busy, when in use by this 5589e3b184bSJaakko Laine * driver. If the register indicates bus being busy for some reason we 5599e3b184bSJaakko Laine * should ignore it, since bus will never be released and i2c will be 5609e3b184bSJaakko Laine * stuck forever. 5619e3b184bSJaakko Laine */ 5629e3b184bSJaakko Laine if (i2c->singlemaster) { 5639e3b184bSJaakko Laine return 0; 5649e3b184bSJaakko Laine } 5659e3b184bSJaakko Laine 566e1d5b659SRichard Röjfors /* for instance if previous transfer was terminated due to TX error 567e1d5b659SRichard Röjfors * it might be that the bus is on it's way to become available 568e1d5b659SRichard Röjfors * give it at most 3 ms to wake 569e1d5b659SRichard Röjfors */ 570e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 571e1d5b659SRichard Röjfors while (err && tries--) { 572b33aa252SShubhrajyoti Datta msleep(1); 573e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 574e1d5b659SRichard Röjfors } 575e1d5b659SRichard Röjfors 576e1d5b659SRichard Röjfors return err; 577e1d5b659SRichard Röjfors } 578e1d5b659SRichard Röjfors 579e1d5b659SRichard Röjfors static void xiic_start_recv(struct xiic_i2c *i2c) 580e1d5b659SRichard Röjfors { 5813c9fedf9SShubhrajyoti Datta u16 rx_watermark; 582e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 583e1d5b659SRichard Röjfors 584e1d5b659SRichard Röjfors /* Clear and enable Rx full interrupt. */ 585e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 586e1d5b659SRichard Röjfors 587e1d5b659SRichard Röjfors /* we want to get all but last byte, because the TX_ERROR IRQ is used 588e1d5b659SRichard Röjfors * to inidicate error ACK on the address, and negative ack on the last 589e1d5b659SRichard Röjfors * received byte, so to not mix them receive all but last. 590e1d5b659SRichard Röjfors * In the case where there is only one byte to receive 591e1d5b659SRichard Röjfors * we can check if ERROR and RX full is set at the same time 592e1d5b659SRichard Röjfors */ 593e1d5b659SRichard Röjfors rx_watermark = msg->len; 594e1d5b659SRichard Röjfors if (rx_watermark > IIC_RX_FIFO_DEPTH) 595e1d5b659SRichard Röjfors rx_watermark = IIC_RX_FIFO_DEPTH; 5963c9fedf9SShubhrajyoti Datta xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, (u8)(rx_watermark - 1)); 597e1d5b659SRichard Röjfors 598e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) 599e1d5b659SRichard Röjfors /* write the address */ 600e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 60130a64757SPeter Rosin i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); 602e1d5b659SRichard Röjfors 603e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 604e1d5b659SRichard Röjfors 605e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 606e1d5b659SRichard Röjfors msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 607ae7304c3SShubhrajyoti Datta 608e1d5b659SRichard Röjfors if (i2c->nmsgs == 1) 609e1d5b659SRichard Röjfors /* very last, enable bus not busy as well */ 610e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 611e1d5b659SRichard Röjfors 612e1d5b659SRichard Röjfors /* the message is tx:ed */ 613e1d5b659SRichard Röjfors i2c->tx_pos = msg->len; 614e1d5b659SRichard Röjfors } 615e1d5b659SRichard Röjfors 616e1d5b659SRichard Röjfors static void xiic_start_send(struct xiic_i2c *i2c) 617e1d5b659SRichard Röjfors { 618e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->tx_msg; 619e1d5b659SRichard Röjfors 620f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 621f1e9f89aSKedareswara rao Appana __func__, msg, msg->len); 622f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 623f1e9f89aSKedareswara rao Appana __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 624e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 625e1d5b659SRichard Röjfors 626e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) { 627e1d5b659SRichard Röjfors /* write the address */ 62830a64757SPeter Rosin u16 data = i2c_8bit_addr_from_msg(msg) | 629e1d5b659SRichard Röjfors XIIC_TX_DYN_START_MASK; 630e1d5b659SRichard Röjfors if ((i2c->nmsgs == 1) && msg->len == 0) 631e1d5b659SRichard Röjfors /* no data and last message -> add STOP */ 632e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 633e1d5b659SRichard Röjfors 634e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 635e1d5b659SRichard Röjfors } 636e1d5b659SRichard Röjfors 637e1d5b659SRichard Röjfors /* Clear any pending Tx empty, Tx Error and then enable them. */ 638e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 639d12e4bbbSMarek Vasut XIIC_INTR_BNB_MASK | 640d12e4bbbSMarek Vasut ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? 641d12e4bbbSMarek Vasut XIIC_INTR_TX_HALF_MASK : 0)); 642d12e4bbbSMarek Vasut 643d12e4bbbSMarek Vasut xiic_fill_tx_fifo(i2c); 644e1d5b659SRichard Röjfors } 645e1d5b659SRichard Röjfors 646e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c) 647e1d5b659SRichard Röjfors { 648e1d5b659SRichard Röjfors int fifo_space = xiic_tx_fifo_space(i2c); 649b822039bSMichal Simek 650e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 651e1d5b659SRichard Röjfors __func__, i2c->tx_msg, fifo_space); 652e1d5b659SRichard Röjfors 653e1d5b659SRichard Röjfors if (!i2c->tx_msg) 654e1d5b659SRichard Röjfors return; 655e1d5b659SRichard Röjfors 656e1d5b659SRichard Röjfors i2c->rx_pos = 0; 657e1d5b659SRichard Röjfors i2c->tx_pos = 0; 658e1d5b659SRichard Röjfors i2c->state = STATE_START; 659e1d5b659SRichard Röjfors if (i2c->tx_msg->flags & I2C_M_RD) { 660e1d5b659SRichard Röjfors /* we dont date putting several reads in the FIFO */ 661e1d5b659SRichard Röjfors xiic_start_recv(i2c); 662e1d5b659SRichard Röjfors } else { 663e1d5b659SRichard Röjfors xiic_start_send(i2c); 664e1d5b659SRichard Röjfors } 665e1d5b659SRichard Röjfors } 666e1d5b659SRichard Röjfors 667c119e7d0SMarek Vasut static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) 668e1d5b659SRichard Röjfors { 669b4c119dbSShubhrajyoti Datta int ret; 670c119e7d0SMarek Vasut 67177c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 672b4c119dbSShubhrajyoti Datta 673c119e7d0SMarek Vasut ret = xiic_busy(i2c); 674c119e7d0SMarek Vasut if (ret) 675c119e7d0SMarek Vasut goto out; 676c119e7d0SMarek Vasut 677c119e7d0SMarek Vasut i2c->tx_msg = msgs; 678c119e7d0SMarek Vasut i2c->rx_msg = NULL; 679c119e7d0SMarek Vasut i2c->nmsgs = num; 680fdacc3c7SMarek Vasut init_completion(&i2c->completion); 681c119e7d0SMarek Vasut 682b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c); 683b4c119dbSShubhrajyoti Datta if (!ret) 684e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 685b4c119dbSShubhrajyoti Datta 686c119e7d0SMarek Vasut out: 68777c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 688b4c119dbSShubhrajyoti Datta 689b4c119dbSShubhrajyoti Datta return ret; 690e1d5b659SRichard Röjfors } 691e1d5b659SRichard Röjfors 692e1d5b659SRichard Röjfors static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 693e1d5b659SRichard Röjfors { 694e1d5b659SRichard Röjfors struct xiic_i2c *i2c = i2c_get_adapdata(adap); 695e1d5b659SRichard Röjfors int err; 696e1d5b659SRichard Röjfors 697e1d5b659SRichard Röjfors dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 698e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 699e1d5b659SRichard Röjfors 700a85c5c7aSQinglang Miao err = pm_runtime_resume_and_get(i2c->dev); 70136ecbcabSShubhrajyoti Datta if (err < 0) 70236ecbcabSShubhrajyoti Datta return err; 70336ecbcabSShubhrajyoti Datta 704c119e7d0SMarek Vasut err = xiic_start_xfer(i2c, msgs, num); 705b4c119dbSShubhrajyoti Datta if (err < 0) { 706b4c119dbSShubhrajyoti Datta dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 707fdacc3c7SMarek Vasut return err; 708b4c119dbSShubhrajyoti Datta } 709e1d5b659SRichard Röjfors 710fdacc3c7SMarek Vasut err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); 711c119e7d0SMarek Vasut mutex_lock(&i2c->lock); 712fdacc3c7SMarek Vasut if (err == 0) { /* Timeout */ 713e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 714e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 715e1d5b659SRichard Röjfors i2c->nmsgs = 0; 71636ecbcabSShubhrajyoti Datta err = -ETIMEDOUT; 717fdacc3c7SMarek Vasut } else if (err < 0) { /* Completion error */ 718fdacc3c7SMarek Vasut i2c->tx_msg = NULL; 719fdacc3c7SMarek Vasut i2c->rx_msg = NULL; 720fdacc3c7SMarek Vasut i2c->nmsgs = 0; 721fdacc3c7SMarek Vasut } else { 722fdacc3c7SMarek Vasut err = (i2c->state == STATE_DONE) ? num : -EIO; 723e1d5b659SRichard Röjfors } 724c119e7d0SMarek Vasut mutex_unlock(&i2c->lock); 72536ecbcabSShubhrajyoti Datta pm_runtime_mark_last_busy(i2c->dev); 72636ecbcabSShubhrajyoti Datta pm_runtime_put_autosuspend(i2c->dev); 72736ecbcabSShubhrajyoti Datta return err; 728e1d5b659SRichard Röjfors } 729e1d5b659SRichard Röjfors 730e1d5b659SRichard Röjfors static u32 xiic_func(struct i2c_adapter *adap) 731e1d5b659SRichard Röjfors { 732e1d5b659SRichard Röjfors return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 733e1d5b659SRichard Röjfors } 734e1d5b659SRichard Röjfors 735e1d5b659SRichard Röjfors static const struct i2c_algorithm xiic_algorithm = { 736e1d5b659SRichard Röjfors .master_xfer = xiic_xfer, 737e1d5b659SRichard Röjfors .functionality = xiic_func, 738e1d5b659SRichard Röjfors }; 739e1d5b659SRichard Röjfors 74049b80958SRobert Hancock static const struct i2c_adapter_quirks xiic_quirks = { 74149b80958SRobert Hancock .max_read_len = 255, 74249b80958SRobert Hancock }; 74349b80958SRobert Hancock 744329430ccSBhumika Goyal static const struct i2c_adapter xiic_adapter = { 745e1d5b659SRichard Röjfors .owner = THIS_MODULE, 7464db5beedSWolfram Sang .class = I2C_CLASS_DEPRECATED, 747e1d5b659SRichard Röjfors .algo = &xiic_algorithm, 74849b80958SRobert Hancock .quirks = &xiic_quirks, 749e1d5b659SRichard Röjfors }; 750e1d5b659SRichard Röjfors 7510b255e92SBill Pemberton static int xiic_i2c_probe(struct platform_device *pdev) 752e1d5b659SRichard Röjfors { 753e1d5b659SRichard Röjfors struct xiic_i2c *i2c; 754e1d5b659SRichard Röjfors struct xiic_i2c_platform_data *pdata; 755e1d5b659SRichard Röjfors struct resource *res; 756e1d5b659SRichard Röjfors int ret, irq; 757e1d5b659SRichard Röjfors u8 i; 75848ef3ca9SThomas Gessler u32 sr; 759e1d5b659SRichard Röjfors 760168e722dSKedareswara rao Appana i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 761e1d5b659SRichard Röjfors if (!i2c) 762e1d5b659SRichard Röjfors return -ENOMEM; 763e1d5b659SRichard Röjfors 764168e722dSKedareswara rao Appana res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 765168e722dSKedareswara rao Appana i2c->base = devm_ioremap_resource(&pdev->dev, res); 766168e722dSKedareswara rao Appana if (IS_ERR(i2c->base)) 767168e722dSKedareswara rao Appana return PTR_ERR(i2c->base); 768e1d5b659SRichard Röjfors 769168e722dSKedareswara rao Appana irq = platform_get_irq(pdev, 0); 770168e722dSKedareswara rao Appana if (irq < 0) 771168e722dSKedareswara rao Appana return irq; 772168e722dSKedareswara rao Appana 773168e722dSKedareswara rao Appana pdata = dev_get_platdata(&pdev->dev); 774e1d5b659SRichard Röjfors 775e1d5b659SRichard Röjfors /* hook up driver to tree */ 776e1d5b659SRichard Röjfors platform_set_drvdata(pdev, i2c); 777e1d5b659SRichard Röjfors i2c->adap = xiic_adapter; 778e1d5b659SRichard Röjfors i2c_set_adapdata(&i2c->adap, i2c); 779e1d5b659SRichard Röjfors i2c->adap.dev.parent = &pdev->dev; 7803ac0b337SLars-Peter Clausen i2c->adap.dev.of_node = pdev->dev.of_node; 7811d366c2fSRobert Hancock snprintf(i2c->adap.name, sizeof(i2c->adap.name), 7821d366c2fSRobert Hancock DRIVER_NAME " %s", pdev->name); 783e1d5b659SRichard Röjfors 78477c68019SLars-Peter Clausen mutex_init(&i2c->lock); 785168e722dSKedareswara rao Appana 78636ecbcabSShubhrajyoti Datta i2c->clk = devm_clk_get(&pdev->dev, NULL); 7879dbba3f8SKrzysztof Kozlowski if (IS_ERR(i2c->clk)) 7889dbba3f8SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 7899dbba3f8SKrzysztof Kozlowski "input clock not found.\n"); 7909dbba3f8SKrzysztof Kozlowski 79136ecbcabSShubhrajyoti Datta ret = clk_prepare_enable(i2c->clk); 79236ecbcabSShubhrajyoti Datta if (ret) { 79336ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "Unable to enable clock.\n"); 79436ecbcabSShubhrajyoti Datta return ret; 79536ecbcabSShubhrajyoti Datta } 79636ecbcabSShubhrajyoti Datta i2c->dev = &pdev->dev; 79736ecbcabSShubhrajyoti Datta pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 79836ecbcabSShubhrajyoti Datta pm_runtime_use_autosuspend(i2c->dev); 79936ecbcabSShubhrajyoti Datta pm_runtime_set_active(i2c->dev); 80010b17004SShubhrajyoti Datta pm_runtime_enable(i2c->dev); 801861dcffeSMarek Vasut ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 802fcc2fac6SShubhrajyoti Datta xiic_process, IRQF_ONESHOT, 803fcc2fac6SShubhrajyoti Datta pdev->name, i2c); 804fcc2fac6SShubhrajyoti Datta 805168e722dSKedareswara rao Appana if (ret < 0) { 806e1d5b659SRichard Röjfors dev_err(&pdev->dev, "Cannot claim IRQ\n"); 80736ecbcabSShubhrajyoti Datta goto err_clk_dis; 808e1d5b659SRichard Röjfors } 809e1d5b659SRichard Röjfors 8109e3b184bSJaakko Laine i2c->singlemaster = 8119e3b184bSJaakko Laine of_property_read_bool(pdev->dev.of_node, "single-master"); 8129e3b184bSJaakko Laine 81348ef3ca9SThomas Gessler /* 81448ef3ca9SThomas Gessler * Detect endianness 81548ef3ca9SThomas Gessler * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 81648ef3ca9SThomas Gessler * set, assume that the endianness was wrong and swap. 81748ef3ca9SThomas Gessler */ 81848ef3ca9SThomas Gessler i2c->endianness = LITTLE; 81948ef3ca9SThomas Gessler xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 82048ef3ca9SThomas Gessler /* Reset is cleared in xiic_reinit */ 82148ef3ca9SThomas Gessler sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 82248ef3ca9SThomas Gessler if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 82348ef3ca9SThomas Gessler i2c->endianness = BIG; 82448ef3ca9SThomas Gessler 825b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c); 826b4c119dbSShubhrajyoti Datta if (ret < 0) { 827b4c119dbSShubhrajyoti Datta dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 828b4c119dbSShubhrajyoti Datta goto err_clk_dis; 829b4c119dbSShubhrajyoti Datta } 830617bdcbcSMichal Simek 831e1d5b659SRichard Röjfors /* add i2c adapter to i2c tree */ 832e1d5b659SRichard Röjfors ret = i2c_add_adapter(&i2c->adap); 833e1d5b659SRichard Röjfors if (ret) { 834168e722dSKedareswara rao Appana xiic_deinit(i2c); 83536ecbcabSShubhrajyoti Datta goto err_clk_dis; 836e1d5b659SRichard Röjfors } 837e1d5b659SRichard Röjfors 8383ac0b337SLars-Peter Clausen if (pdata) { 839e1d5b659SRichard Röjfors /* add in known devices to the bus */ 840e1d5b659SRichard Röjfors for (i = 0; i < pdata->num_devices; i++) 841bf255befSWolfram Sang i2c_new_client_device(&i2c->adap, pdata->devices + i); 8423ac0b337SLars-Peter Clausen } 8433ac0b337SLars-Peter Clausen 844e1d5b659SRichard Röjfors return 0; 84536ecbcabSShubhrajyoti Datta 84636ecbcabSShubhrajyoti Datta err_clk_dis: 84736ecbcabSShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 84836ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 84936ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 85036ecbcabSShubhrajyoti Datta return ret; 851e1d5b659SRichard Röjfors } 852e1d5b659SRichard Röjfors 8530b255e92SBill Pemberton static int xiic_i2c_remove(struct platform_device *pdev) 854e1d5b659SRichard Röjfors { 855e1d5b659SRichard Röjfors struct xiic_i2c *i2c = platform_get_drvdata(pdev); 85636ecbcabSShubhrajyoti Datta int ret; 857e1d5b659SRichard Röjfors 858e1d5b659SRichard Röjfors /* remove adapter & data */ 859e1d5b659SRichard Röjfors i2c_del_adapter(&i2c->adap); 860e1d5b659SRichard Röjfors 861a85c5c7aSQinglang Miao ret = pm_runtime_resume_and_get(i2c->dev); 86210b17004SShubhrajyoti Datta if (ret < 0) 86336ecbcabSShubhrajyoti Datta return ret; 86410b17004SShubhrajyoti Datta 865e1d5b659SRichard Röjfors xiic_deinit(i2c); 86610b17004SShubhrajyoti Datta pm_runtime_put_sync(i2c->dev); 86736ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 86836ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 86910b17004SShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 87010b17004SShubhrajyoti Datta pm_runtime_dont_use_autosuspend(&pdev->dev); 871e1d5b659SRichard Röjfors 872e1d5b659SRichard Röjfors return 0; 873e1d5b659SRichard Röjfors } 874e1d5b659SRichard Röjfors 8753ac0b337SLars-Peter Clausen #if defined(CONFIG_OF) 8760b255e92SBill Pemberton static const struct of_device_id xiic_of_match[] = { 8773ac0b337SLars-Peter Clausen { .compatible = "xlnx,xps-iic-2.00.a", }, 8783ac0b337SLars-Peter Clausen {}, 8793ac0b337SLars-Peter Clausen }; 8803ac0b337SLars-Peter Clausen MODULE_DEVICE_TABLE(of, xiic_of_match); 8813ac0b337SLars-Peter Clausen #endif 8823ac0b337SLars-Peter Clausen 88374d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 88436ecbcabSShubhrajyoti Datta { 8859242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev); 88636ecbcabSShubhrajyoti Datta 88736ecbcabSShubhrajyoti Datta clk_disable(i2c->clk); 88836ecbcabSShubhrajyoti Datta 88936ecbcabSShubhrajyoti Datta return 0; 89036ecbcabSShubhrajyoti Datta } 89136ecbcabSShubhrajyoti Datta 89274d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 89336ecbcabSShubhrajyoti Datta { 8949242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev); 89536ecbcabSShubhrajyoti Datta int ret; 89636ecbcabSShubhrajyoti Datta 89736ecbcabSShubhrajyoti Datta ret = clk_enable(i2c->clk); 89836ecbcabSShubhrajyoti Datta if (ret) { 89936ecbcabSShubhrajyoti Datta dev_err(dev, "Cannot enable clock.\n"); 90036ecbcabSShubhrajyoti Datta return ret; 90136ecbcabSShubhrajyoti Datta } 90236ecbcabSShubhrajyoti Datta 90336ecbcabSShubhrajyoti Datta return 0; 90436ecbcabSShubhrajyoti Datta } 90536ecbcabSShubhrajyoti Datta 90636ecbcabSShubhrajyoti Datta static const struct dev_pm_ops xiic_dev_pm_ops = { 90774d23319SMoritz Fischer SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 90874d23319SMoritz Fischer xiic_i2c_runtime_resume, NULL) 90936ecbcabSShubhrajyoti Datta }; 910b822039bSMichal Simek 911e1d5b659SRichard Röjfors static struct platform_driver xiic_i2c_driver = { 912e1d5b659SRichard Röjfors .probe = xiic_i2c_probe, 9130b255e92SBill Pemberton .remove = xiic_i2c_remove, 914e1d5b659SRichard Röjfors .driver = { 915e1d5b659SRichard Röjfors .name = DRIVER_NAME, 9163ac0b337SLars-Peter Clausen .of_match_table = of_match_ptr(xiic_of_match), 91736ecbcabSShubhrajyoti Datta .pm = &xiic_dev_pm_ops, 918e1d5b659SRichard Röjfors }, 919e1d5b659SRichard Röjfors }; 920e1d5b659SRichard Röjfors 921a3664b51SAxel Lin module_platform_driver(xiic_i2c_driver); 922e1d5b659SRichard Röjfors 923*b8caf0a0SMartin Tůma MODULE_ALIAS("platform:" DRIVER_NAME); 924e1d5b659SRichard Röjfors MODULE_AUTHOR("info@mocean-labs.com"); 925e1d5b659SRichard Röjfors MODULE_DESCRIPTION("Xilinx I2C bus driver"); 926e1d5b659SRichard Röjfors MODULE_LICENSE("GPL v2"); 927