11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e1d5b659SRichard Röjfors /* 3e1d5b659SRichard Röjfors * i2c-xiic.c 4e1d5b659SRichard Röjfors * Copyright (c) 2002-2007 Xilinx Inc. 5e1d5b659SRichard Röjfors * Copyright (c) 2009-2010 Intel Corporation 6e1d5b659SRichard Röjfors * 7e1d5b659SRichard Röjfors * This code was implemented by Mocean Laboratories AB when porting linux 8e1d5b659SRichard Röjfors * to the automotive development board Russellville. The copyright holder 9e1d5b659SRichard Röjfors * as seen in the header is Intel corporation. 10e1d5b659SRichard Röjfors * Mocean Laboratories forked off the GNU/Linux platform work into a 1125985edcSLucas De Marchi * separate company called Pelagicore AB, which committed the code to the 12e1d5b659SRichard Röjfors * kernel. 13e1d5b659SRichard Röjfors */ 14e1d5b659SRichard Röjfors 15e1d5b659SRichard Röjfors /* Supports: 16e1d5b659SRichard Röjfors * Xilinx IIC 17e1d5b659SRichard Röjfors */ 18e1d5b659SRichard Röjfors #include <linux/kernel.h> 19e1d5b659SRichard Röjfors #include <linux/module.h> 20e1d5b659SRichard Röjfors #include <linux/errno.h> 21168e722dSKedareswara rao Appana #include <linux/err.h> 2202ca6c40SRandy Dunlap #include <linux/delay.h> 23e1d5b659SRichard Röjfors #include <linux/platform_device.h> 24e1d5b659SRichard Röjfors #include <linux/i2c.h> 25e1d5b659SRichard Röjfors #include <linux/interrupt.h> 26e1d5b659SRichard Röjfors #include <linux/wait.h> 277072b75cSWolfram Sang #include <linux/platform_data/i2c-xiic.h> 28e1d5b659SRichard Röjfors #include <linux/io.h> 295a0e3ad6STejun Heo #include <linux/slab.h> 304edd65e6SSachin Kamat #include <linux/of.h> 3136ecbcabSShubhrajyoti Datta #include <linux/clk.h> 3236ecbcabSShubhrajyoti Datta #include <linux/pm_runtime.h> 33e1d5b659SRichard Röjfors 34e1d5b659SRichard Röjfors #define DRIVER_NAME "xiic-i2c" 35e1d5b659SRichard Röjfors 36e1d5b659SRichard Röjfors enum xilinx_i2c_state { 37e1d5b659SRichard Röjfors STATE_DONE, 38e1d5b659SRichard Röjfors STATE_ERROR, 39e1d5b659SRichard Röjfors STATE_START 40e1d5b659SRichard Röjfors }; 41e1d5b659SRichard Röjfors 4248ef3ca9SThomas Gessler enum xiic_endian { 4348ef3ca9SThomas Gessler LITTLE, 4448ef3ca9SThomas Gessler BIG 4548ef3ca9SThomas Gessler }; 4648ef3ca9SThomas Gessler 47e1d5b659SRichard Röjfors /** 48e1d5b659SRichard Röjfors * struct xiic_i2c - Internal representation of the XIIC I2C bus 49bcc156e2SShubhrajyoti Datta * @dev: Pointer to device structure 50e1d5b659SRichard Röjfors * @base: Memory base of the HW registers 51e1d5b659SRichard Röjfors * @wait: Wait queue for callers 52e1d5b659SRichard Röjfors * @adap: Kernel adapter representation 53e1d5b659SRichard Röjfors * @tx_msg: Messages from above to be sent 54e1d5b659SRichard Röjfors * @lock: Mutual exclusion 55e1d5b659SRichard Röjfors * @tx_pos: Current pos in TX message 56e1d5b659SRichard Röjfors * @nmsgs: Number of messages in tx_msg 57e1d5b659SRichard Röjfors * @rx_msg: Current RX message 58e1d5b659SRichard Röjfors * @rx_pos: Position within current RX message 59bea6ff02SShubhrajyoti Datta * @endianness: big/little-endian byte order 60bcc156e2SShubhrajyoti Datta * @clk: Pointer to AXI4-lite input clock 619106e45cSJaakko Laine * @state: See STATE_ 629e3b184bSJaakko Laine * @singlemaster: Indicates bus is single master 63e1d5b659SRichard Röjfors */ 64e1d5b659SRichard Röjfors struct xiic_i2c { 6536ecbcabSShubhrajyoti Datta struct device *dev; 66e1d5b659SRichard Röjfors void __iomem *base; 67e1d5b659SRichard Röjfors wait_queue_head_t wait; 68e1d5b659SRichard Röjfors struct i2c_adapter adap; 69e1d5b659SRichard Röjfors struct i2c_msg *tx_msg; 7077c68019SLars-Peter Clausen struct mutex lock; 71e1d5b659SRichard Röjfors unsigned int tx_pos; 72e1d5b659SRichard Röjfors unsigned int nmsgs; 73e1d5b659SRichard Röjfors struct i2c_msg *rx_msg; 74e1d5b659SRichard Röjfors int rx_pos; 7548ef3ca9SThomas Gessler enum xiic_endian endianness; 7636ecbcabSShubhrajyoti Datta struct clk *clk; 779106e45cSJaakko Laine enum xilinx_i2c_state state; 789e3b184bSJaakko Laine bool singlemaster; 79e1d5b659SRichard Röjfors }; 80e1d5b659SRichard Röjfors 81e1d5b659SRichard Röjfors 82e1d5b659SRichard Röjfors #define XIIC_MSB_OFFSET 0 83e1d5b659SRichard Röjfors #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 84e1d5b659SRichard Röjfors 85e1d5b659SRichard Röjfors /* 86e1d5b659SRichard Röjfors * Register offsets in bytes from RegisterBase. Three is added to the 87e1d5b659SRichard Röjfors * base offset to access LSB (IBM style) of the word 88e1d5b659SRichard Röjfors */ 89e1d5b659SRichard Röjfors #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 90e1d5b659SRichard Röjfors #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 91e1d5b659SRichard Röjfors #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 92e1d5b659SRichard Röjfors #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 93e1d5b659SRichard Röjfors #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 94e1d5b659SRichard Röjfors #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 95e1d5b659SRichard Röjfors #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 96e1d5b659SRichard Röjfors #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 97e1d5b659SRichard Röjfors #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 98e1d5b659SRichard Röjfors #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 99e1d5b659SRichard Röjfors 100e1d5b659SRichard Röjfors /* Control Register masks */ 101e1d5b659SRichard Röjfors #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 102e1d5b659SRichard Röjfors #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 103e1d5b659SRichard Röjfors #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 104e1d5b659SRichard Röjfors #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 105e1d5b659SRichard Röjfors #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 106e1d5b659SRichard Röjfors #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 107e1d5b659SRichard Röjfors #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 108e1d5b659SRichard Röjfors 109e1d5b659SRichard Röjfors /* Status Register masks */ 110e1d5b659SRichard Röjfors #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 111e1d5b659SRichard Röjfors #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 112e1d5b659SRichard Röjfors #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 113e1d5b659SRichard Röjfors #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 114e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 115e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 116e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 117e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 118e1d5b659SRichard Röjfors 119e1d5b659SRichard Röjfors /* Interrupt Status Register masks Interrupt occurs when... */ 120e1d5b659SRichard Röjfors #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 121e1d5b659SRichard Röjfors #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 122e1d5b659SRichard Röjfors #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 123e1d5b659SRichard Röjfors #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 124e1d5b659SRichard Röjfors #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 125e1d5b659SRichard Röjfors #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 126e1d5b659SRichard Röjfors #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 127e1d5b659SRichard Röjfors #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 128e1d5b659SRichard Röjfors 129e1d5b659SRichard Röjfors /* The following constants specify the depth of the FIFOs */ 130e1d5b659SRichard Röjfors #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 131e1d5b659SRichard Röjfors #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 132e1d5b659SRichard Röjfors 133e1d5b659SRichard Röjfors /* The following constants specify groups of interrupts that are typically 134e1d5b659SRichard Röjfors * enabled or disables at the same time 135e1d5b659SRichard Röjfors */ 136e1d5b659SRichard Röjfors #define XIIC_TX_INTERRUPTS \ 137e1d5b659SRichard Röjfors (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 138e1d5b659SRichard Röjfors 139e1d5b659SRichard Röjfors #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 140e1d5b659SRichard Röjfors 141e1d5b659SRichard Röjfors /* 142e1d5b659SRichard Röjfors * Tx Fifo upper bit masks. 143e1d5b659SRichard Röjfors */ 144e1d5b659SRichard Röjfors #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 145e1d5b659SRichard Röjfors #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 146e1d5b659SRichard Röjfors 147e1d5b659SRichard Röjfors /* 148e1d5b659SRichard Röjfors * The following constants define the register offsets for the Interrupt 149e1d5b659SRichard Röjfors * registers. There are some holes in the memory map for reserved addresses 150e1d5b659SRichard Röjfors * to allow other registers to be added and still match the memory map of the 151e1d5b659SRichard Röjfors * interrupt controller registers 152e1d5b659SRichard Röjfors */ 153e1d5b659SRichard Röjfors #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 154e1d5b659SRichard Röjfors #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 155e1d5b659SRichard Röjfors #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 156e1d5b659SRichard Röjfors #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 157e1d5b659SRichard Röjfors 158e1d5b659SRichard Röjfors #define XIIC_RESET_MASK 0xAUL 159e1d5b659SRichard Röjfors 16036ecbcabSShubhrajyoti Datta #define XIIC_PM_TIMEOUT 1000 /* ms */ 161b4c119dbSShubhrajyoti Datta /* timeout waiting for the controller to respond */ 162b4c119dbSShubhrajyoti Datta #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 163e1d5b659SRichard Röjfors /* 164e1d5b659SRichard Röjfors * The following constant is used for the device global interrupt enable 165e1d5b659SRichard Röjfors * register, to enable all interrupts for the device, this is the only bit 166e1d5b659SRichard Röjfors * in the register 167e1d5b659SRichard Röjfors */ 168e1d5b659SRichard Röjfors #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 169e1d5b659SRichard Röjfors 170e1d5b659SRichard Röjfors #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 171e1d5b659SRichard Röjfors #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 172e1d5b659SRichard Röjfors 173b4c119dbSShubhrajyoti Datta static int xiic_start_xfer(struct xiic_i2c *i2c); 174e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c); 175e1d5b659SRichard Röjfors 17648ef3ca9SThomas Gessler /* 17748ef3ca9SThomas Gessler * For the register read and write functions, a little-endian and big-endian 17848ef3ca9SThomas Gessler * version are necessary. Endianness is detected during the probe function. 17948ef3ca9SThomas Gessler * Only the least significant byte [doublet] of the register are ever 18048ef3ca9SThomas Gessler * accessed. This requires an offset of 3 [2] from the base address for 18148ef3ca9SThomas Gessler * big-endian systems. 18248ef3ca9SThomas Gessler */ 18348ef3ca9SThomas Gessler 184e1d5b659SRichard Röjfors static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 185e1d5b659SRichard Röjfors { 18648ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 187e1d5b659SRichard Röjfors iowrite8(value, i2c->base + reg); 18848ef3ca9SThomas Gessler else 18948ef3ca9SThomas Gessler iowrite8(value, i2c->base + reg + 3); 190e1d5b659SRichard Röjfors } 191e1d5b659SRichard Röjfors 192e1d5b659SRichard Röjfors static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 193e1d5b659SRichard Röjfors { 19448ef3ca9SThomas Gessler u8 ret; 19548ef3ca9SThomas Gessler 19648ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 19748ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg); 19848ef3ca9SThomas Gessler else 19948ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg + 3); 20048ef3ca9SThomas Gessler return ret; 201e1d5b659SRichard Röjfors } 202e1d5b659SRichard Röjfors 203e1d5b659SRichard Röjfors static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 204e1d5b659SRichard Röjfors { 20548ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 206e1d5b659SRichard Röjfors iowrite16(value, i2c->base + reg); 20748ef3ca9SThomas Gessler else 20848ef3ca9SThomas Gessler iowrite16be(value, i2c->base + reg + 2); 209e1d5b659SRichard Röjfors } 210e1d5b659SRichard Röjfors 211e1d5b659SRichard Röjfors static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 212e1d5b659SRichard Röjfors { 21348ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 214e1d5b659SRichard Röjfors iowrite32(value, i2c->base + reg); 21548ef3ca9SThomas Gessler else 21648ef3ca9SThomas Gessler iowrite32be(value, i2c->base + reg); 217e1d5b659SRichard Röjfors } 218e1d5b659SRichard Röjfors 219e1d5b659SRichard Röjfors static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 220e1d5b659SRichard Röjfors { 22148ef3ca9SThomas Gessler u32 ret; 22248ef3ca9SThomas Gessler 22348ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 22448ef3ca9SThomas Gessler ret = ioread32(i2c->base + reg); 22548ef3ca9SThomas Gessler else 22648ef3ca9SThomas Gessler ret = ioread32be(i2c->base + reg); 22748ef3ca9SThomas Gessler return ret; 228e1d5b659SRichard Röjfors } 229e1d5b659SRichard Röjfors 230e1d5b659SRichard Röjfors static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 231e1d5b659SRichard Röjfors { 232e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 233e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 234e1d5b659SRichard Röjfors } 235e1d5b659SRichard Röjfors 236e1d5b659SRichard Röjfors static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 237e1d5b659SRichard Röjfors { 238e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 239e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 240e1d5b659SRichard Röjfors } 241e1d5b659SRichard Röjfors 242e1d5b659SRichard Röjfors static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 243e1d5b659SRichard Röjfors { 244e1d5b659SRichard Röjfors u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 245e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 246e1d5b659SRichard Röjfors } 247e1d5b659SRichard Röjfors 248e1d5b659SRichard Röjfors static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 249e1d5b659SRichard Röjfors { 250e1d5b659SRichard Röjfors xiic_irq_clr(i2c, mask); 251e1d5b659SRichard Röjfors xiic_irq_en(i2c, mask); 252e1d5b659SRichard Röjfors } 253e1d5b659SRichard Röjfors 254b4c119dbSShubhrajyoti Datta static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 255e1d5b659SRichard Röjfors { 256e1d5b659SRichard Röjfors u8 sr; 257b4c119dbSShubhrajyoti Datta unsigned long timeout; 258b4c119dbSShubhrajyoti Datta 259b4c119dbSShubhrajyoti Datta timeout = jiffies + XIIC_I2C_TIMEOUT; 260e1d5b659SRichard Röjfors for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 261e1d5b659SRichard Röjfors !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 262b4c119dbSShubhrajyoti Datta sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 263e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 264b4c119dbSShubhrajyoti Datta if (time_after(jiffies, timeout)) { 265b4c119dbSShubhrajyoti Datta dev_err(i2c->dev, "Failed to clear rx fifo\n"); 266b4c119dbSShubhrajyoti Datta return -ETIMEDOUT; 267b4c119dbSShubhrajyoti Datta } 268e1d5b659SRichard Röjfors } 269e1d5b659SRichard Röjfors 270b4c119dbSShubhrajyoti Datta return 0; 271b4c119dbSShubhrajyoti Datta } 272b4c119dbSShubhrajyoti Datta 273b4c119dbSShubhrajyoti Datta static int xiic_reinit(struct xiic_i2c *i2c) 274e1d5b659SRichard Röjfors { 275b4c119dbSShubhrajyoti Datta int ret; 276b4c119dbSShubhrajyoti Datta 277e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 278e1d5b659SRichard Röjfors 279e1d5b659SRichard Röjfors /* Set receive Fifo depth to maximum (zero based). */ 280e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 281e1d5b659SRichard Röjfors 282e1d5b659SRichard Röjfors /* Reset Tx Fifo. */ 283e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 284e1d5b659SRichard Röjfors 285e1d5b659SRichard Röjfors /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 286e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 287e1d5b659SRichard Röjfors 288e1d5b659SRichard Röjfors /* make sure RX fifo is empty */ 289b4c119dbSShubhrajyoti Datta ret = xiic_clear_rx_fifo(i2c); 290b4c119dbSShubhrajyoti Datta if (ret) 291b4c119dbSShubhrajyoti Datta return ret; 292e1d5b659SRichard Röjfors 293e1d5b659SRichard Röjfors /* Enable interrupts */ 294e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 295e1d5b659SRichard Röjfors 296542e2a9bSShubhrajyoti Datta xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 297b4c119dbSShubhrajyoti Datta 298b4c119dbSShubhrajyoti Datta return 0; 299e1d5b659SRichard Röjfors } 300e1d5b659SRichard Röjfors 301e1d5b659SRichard Röjfors static void xiic_deinit(struct xiic_i2c *i2c) 302e1d5b659SRichard Röjfors { 303e1d5b659SRichard Röjfors u8 cr; 304e1d5b659SRichard Röjfors 305e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 306e1d5b659SRichard Röjfors 307e1d5b659SRichard Röjfors /* Disable IIC Device. */ 308e1d5b659SRichard Röjfors cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 309e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 310e1d5b659SRichard Röjfors } 311e1d5b659SRichard Röjfors 312e1d5b659SRichard Röjfors static void xiic_read_rx(struct xiic_i2c *i2c) 313e1d5b659SRichard Röjfors { 314e1d5b659SRichard Röjfors u8 bytes_in_fifo; 315e1d5b659SRichard Röjfors int i; 316e1d5b659SRichard Röjfors 317e1d5b659SRichard Röjfors bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 318e1d5b659SRichard Röjfors 319f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, 320f1e9f89aSKedareswara rao Appana "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 321e1d5b659SRichard Röjfors __func__, bytes_in_fifo, xiic_rx_space(i2c), 322e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 323e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 324e1d5b659SRichard Röjfors 325e1d5b659SRichard Röjfors if (bytes_in_fifo > xiic_rx_space(i2c)) 326e1d5b659SRichard Röjfors bytes_in_fifo = xiic_rx_space(i2c); 327e1d5b659SRichard Röjfors 328e1d5b659SRichard Röjfors for (i = 0; i < bytes_in_fifo; i++) 329e1d5b659SRichard Röjfors i2c->rx_msg->buf[i2c->rx_pos++] = 330e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 331e1d5b659SRichard Röjfors 332e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 333e1d5b659SRichard Röjfors (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 334e1d5b659SRichard Röjfors IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 335e1d5b659SRichard Röjfors } 336e1d5b659SRichard Röjfors 337e1d5b659SRichard Röjfors static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 338e1d5b659SRichard Röjfors { 339e1d5b659SRichard Röjfors /* return the actual space left in the FIFO */ 340e1d5b659SRichard Röjfors return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 341e1d5b659SRichard Röjfors } 342e1d5b659SRichard Röjfors 343e1d5b659SRichard Röjfors static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 344e1d5b659SRichard Röjfors { 345e1d5b659SRichard Röjfors u8 fifo_space = xiic_tx_fifo_space(i2c); 346e1d5b659SRichard Röjfors int len = xiic_tx_space(i2c); 347e1d5b659SRichard Röjfors 348e1d5b659SRichard Röjfors len = (len > fifo_space) ? fifo_space : len; 349e1d5b659SRichard Röjfors 350e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 351e1d5b659SRichard Röjfors __func__, len, fifo_space); 352e1d5b659SRichard Röjfors 353e1d5b659SRichard Röjfors while (len--) { 354e1d5b659SRichard Röjfors u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 355e1d5b659SRichard Röjfors if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 356e1d5b659SRichard Röjfors /* last message in transfer -> STOP */ 357e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 358e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 359c39e8e43SSteven A. Falco } 360e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 361e1d5b659SRichard Röjfors } 362e1d5b659SRichard Röjfors } 363e1d5b659SRichard Röjfors 364e1d5b659SRichard Röjfors static void xiic_wakeup(struct xiic_i2c *i2c, int code) 365e1d5b659SRichard Röjfors { 366e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 367e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 368e1d5b659SRichard Röjfors i2c->nmsgs = 0; 369e1d5b659SRichard Röjfors i2c->state = code; 370e1d5b659SRichard Röjfors wake_up(&i2c->wait); 371e1d5b659SRichard Röjfors } 372e1d5b659SRichard Röjfors 373fcc2fac6SShubhrajyoti Datta static irqreturn_t xiic_process(int irq, void *dev_id) 374e1d5b659SRichard Röjfors { 375fcc2fac6SShubhrajyoti Datta struct xiic_i2c *i2c = dev_id; 376e1d5b659SRichard Röjfors u32 pend, isr, ier; 377e1d5b659SRichard Röjfors u32 clr = 0; 378e1d5b659SRichard Röjfors 379e1d5b659SRichard Röjfors /* Get the interrupt Status from the IPIF. There is no clearing of 380e1d5b659SRichard Röjfors * interrupts in the IPIF. Interrupts must be cleared at the source. 381e1d5b659SRichard Röjfors * To find which interrupts are pending; AND interrupts pending with 382e1d5b659SRichard Röjfors * interrupts masked. 383e1d5b659SRichard Röjfors */ 38477c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 385e1d5b659SRichard Röjfors isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 386e1d5b659SRichard Röjfors ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 387e1d5b659SRichard Röjfors pend = isr & ier; 388e1d5b659SRichard Röjfors 389f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 390f1e9f89aSKedareswara rao Appana __func__, ier, isr, pend); 391f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 392f1e9f89aSKedareswara rao Appana __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 393e1d5b659SRichard Röjfors i2c->tx_msg, i2c->nmsgs); 394e1d5b659SRichard Röjfors 395e1d5b659SRichard Röjfors 396e1d5b659SRichard Röjfors /* Service requesting interrupt */ 397e1d5b659SRichard Röjfors if ((pend & XIIC_INTR_ARB_LOST_MASK) || 398e1d5b659SRichard Röjfors ((pend & XIIC_INTR_TX_ERROR_MASK) && 399e1d5b659SRichard Röjfors !(pend & XIIC_INTR_RX_FULL_MASK))) { 400e1d5b659SRichard Röjfors /* bus arbritration lost, or... 401e1d5b659SRichard Röjfors * Transmit error _OR_ RX completed 402e1d5b659SRichard Röjfors * if this happens when RX_FULL is not set 403e1d5b659SRichard Röjfors * this is probably a TX error 404e1d5b659SRichard Röjfors */ 405e1d5b659SRichard Röjfors 406e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 407e1d5b659SRichard Röjfors 408e1d5b659SRichard Röjfors /* dynamic mode seem to suffer from problems if we just flushes 409e1d5b659SRichard Röjfors * fifos and the next message is a TX with len 0 (only addr) 410e1d5b659SRichard Röjfors * reset the IP instead of just flush fifos 411e1d5b659SRichard Röjfors */ 412e1d5b659SRichard Röjfors xiic_reinit(i2c); 413e1d5b659SRichard Röjfors 4146b0c8dc3SShubhrajyoti Datta if (i2c->rx_msg) 4156b0c8dc3SShubhrajyoti Datta xiic_wakeup(i2c, STATE_ERROR); 416e1d5b659SRichard Röjfors if (i2c->tx_msg) 417e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_ERROR); 4187f9906bdSShubhrajyoti Datta } 4197f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_RX_FULL_MASK) { 420e1d5b659SRichard Röjfors /* Receive register/FIFO is full */ 421e1d5b659SRichard Röjfors 4227f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_RX_FULL_MASK; 423e1d5b659SRichard Röjfors if (!i2c->rx_msg) { 424e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 4251ee7cdbfSColin Ian King "%s unexpected RX IRQ\n", __func__); 426e1d5b659SRichard Röjfors xiic_clear_rx_fifo(i2c); 427e1d5b659SRichard Röjfors goto out; 428e1d5b659SRichard Röjfors } 429e1d5b659SRichard Röjfors 430e1d5b659SRichard Röjfors xiic_read_rx(i2c); 431e1d5b659SRichard Röjfors if (xiic_rx_space(i2c) == 0) { 432e1d5b659SRichard Röjfors /* this is the last part of the message */ 433e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 434e1d5b659SRichard Röjfors 435e1d5b659SRichard Röjfors /* also clear TX error if there (RX complete) */ 436e1d5b659SRichard Röjfors clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 437e1d5b659SRichard Röjfors 438e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 439e1d5b659SRichard Röjfors "%s end of message, nmsgs: %d\n", 440e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 441e1d5b659SRichard Röjfors 442e1d5b659SRichard Röjfors /* send next message if this wasn't the last, 443e1d5b659SRichard Röjfors * otherwise the transfer will be finialise when 444e1d5b659SRichard Röjfors * receiving the bus not busy interrupt 445e1d5b659SRichard Röjfors */ 446e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 447e1d5b659SRichard Röjfors i2c->nmsgs--; 448e1d5b659SRichard Röjfors i2c->tx_msg++; 449e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 450e1d5b659SRichard Röjfors "%s will start next...\n", __func__); 451e1d5b659SRichard Röjfors 452e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 453e1d5b659SRichard Röjfors } 454e1d5b659SRichard Röjfors } 4557f9906bdSShubhrajyoti Datta } 4567f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_BNB_MASK) { 457e1d5b659SRichard Röjfors /* IIC bus has transitioned to not busy */ 4587f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_BNB_MASK; 459e1d5b659SRichard Röjfors 460e1d5b659SRichard Röjfors /* The bus is not busy, disable BusNotBusy interrupt */ 461e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 462e1d5b659SRichard Röjfors 463e1d5b659SRichard Röjfors if (!i2c->tx_msg) 464e1d5b659SRichard Röjfors goto out; 465e1d5b659SRichard Röjfors 466e1d5b659SRichard Röjfors if ((i2c->nmsgs == 1) && !i2c->rx_msg && 467e1d5b659SRichard Röjfors xiic_tx_space(i2c) == 0) 468e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_DONE); 469e1d5b659SRichard Röjfors else 470e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_ERROR); 4717f9906bdSShubhrajyoti Datta } 4727f9906bdSShubhrajyoti Datta if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 473d36b6910SAl Viro /* Transmit register/FIFO is empty or ½ empty */ 474e1d5b659SRichard Röjfors 4757f9906bdSShubhrajyoti Datta clr |= (pend & 4767f9906bdSShubhrajyoti Datta (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 477e1d5b659SRichard Röjfors 478e1d5b659SRichard Röjfors if (!i2c->tx_msg) { 479e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 4801ee7cdbfSColin Ian King "%s unexpected TX IRQ\n", __func__); 481e1d5b659SRichard Röjfors goto out; 482e1d5b659SRichard Röjfors } 483e1d5b659SRichard Röjfors 484e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c); 485e1d5b659SRichard Röjfors 486e1d5b659SRichard Röjfors /* current message sent and there is space in the fifo */ 487e1d5b659SRichard Röjfors if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 488e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 489e1d5b659SRichard Röjfors "%s end of message sent, nmsgs: %d\n", 490e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 491e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 492e1d5b659SRichard Röjfors i2c->nmsgs--; 493e1d5b659SRichard Röjfors i2c->tx_msg++; 494e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 495e1d5b659SRichard Röjfors } else { 496e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 497e1d5b659SRichard Röjfors 498e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 499e1d5b659SRichard Röjfors "%s Got TX IRQ but no more to do...\n", 500e1d5b659SRichard Röjfors __func__); 501e1d5b659SRichard Röjfors } 502e1d5b659SRichard Röjfors } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 503e1d5b659SRichard Röjfors /* current frame is sent and is last, 504e1d5b659SRichard Röjfors * make sure to disable tx half 505e1d5b659SRichard Röjfors */ 506e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 507e1d5b659SRichard Röjfors } 508e1d5b659SRichard Röjfors out: 509e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 510e1d5b659SRichard Röjfors 511e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 51277c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 513fcc2fac6SShubhrajyoti Datta return IRQ_HANDLED; 514e1d5b659SRichard Röjfors } 515e1d5b659SRichard Röjfors 516e1d5b659SRichard Röjfors static int xiic_bus_busy(struct xiic_i2c *i2c) 517e1d5b659SRichard Röjfors { 518e1d5b659SRichard Röjfors u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 519e1d5b659SRichard Röjfors 520e1d5b659SRichard Röjfors return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 521e1d5b659SRichard Röjfors } 522e1d5b659SRichard Röjfors 523e1d5b659SRichard Röjfors static int xiic_busy(struct xiic_i2c *i2c) 524e1d5b659SRichard Röjfors { 525e1d5b659SRichard Röjfors int tries = 3; 526e1d5b659SRichard Röjfors int err; 527e1d5b659SRichard Röjfors 528e1d5b659SRichard Röjfors if (i2c->tx_msg) 529e1d5b659SRichard Röjfors return -EBUSY; 530e1d5b659SRichard Röjfors 5319e3b184bSJaakko Laine /* In single master mode bus can only be busy, when in use by this 5329e3b184bSJaakko Laine * driver. If the register indicates bus being busy for some reason we 5339e3b184bSJaakko Laine * should ignore it, since bus will never be released and i2c will be 5349e3b184bSJaakko Laine * stuck forever. 5359e3b184bSJaakko Laine */ 5369e3b184bSJaakko Laine if (i2c->singlemaster) { 5379e3b184bSJaakko Laine return 0; 5389e3b184bSJaakko Laine } 5399e3b184bSJaakko Laine 540e1d5b659SRichard Röjfors /* for instance if previous transfer was terminated due to TX error 541e1d5b659SRichard Röjfors * it might be that the bus is on it's way to become available 542e1d5b659SRichard Röjfors * give it at most 3 ms to wake 543e1d5b659SRichard Röjfors */ 544e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 545e1d5b659SRichard Röjfors while (err && tries--) { 546b33aa252SShubhrajyoti Datta msleep(1); 547e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 548e1d5b659SRichard Röjfors } 549e1d5b659SRichard Röjfors 550e1d5b659SRichard Röjfors return err; 551e1d5b659SRichard Röjfors } 552e1d5b659SRichard Röjfors 553e1d5b659SRichard Röjfors static void xiic_start_recv(struct xiic_i2c *i2c) 554e1d5b659SRichard Röjfors { 555e1d5b659SRichard Röjfors u8 rx_watermark; 556e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 557ae7304c3SShubhrajyoti Datta unsigned long flags; 558e1d5b659SRichard Röjfors 559e1d5b659SRichard Röjfors /* Clear and enable Rx full interrupt. */ 560e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 561e1d5b659SRichard Röjfors 562e1d5b659SRichard Röjfors /* we want to get all but last byte, because the TX_ERROR IRQ is used 563e1d5b659SRichard Röjfors * to inidicate error ACK on the address, and negative ack on the last 564e1d5b659SRichard Röjfors * received byte, so to not mix them receive all but last. 565e1d5b659SRichard Röjfors * In the case where there is only one byte to receive 566e1d5b659SRichard Röjfors * we can check if ERROR and RX full is set at the same time 567e1d5b659SRichard Röjfors */ 568e1d5b659SRichard Röjfors rx_watermark = msg->len; 569e1d5b659SRichard Röjfors if (rx_watermark > IIC_RX_FIFO_DEPTH) 570e1d5b659SRichard Röjfors rx_watermark = IIC_RX_FIFO_DEPTH; 571e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 572e1d5b659SRichard Röjfors 573ae7304c3SShubhrajyoti Datta local_irq_save(flags); 574e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) 575e1d5b659SRichard Röjfors /* write the address */ 576e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 57730a64757SPeter Rosin i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); 578e1d5b659SRichard Röjfors 579e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 580e1d5b659SRichard Röjfors 581e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 582e1d5b659SRichard Röjfors msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 583ae7304c3SShubhrajyoti Datta local_irq_restore(flags); 584ae7304c3SShubhrajyoti Datta 585e1d5b659SRichard Röjfors if (i2c->nmsgs == 1) 586e1d5b659SRichard Röjfors /* very last, enable bus not busy as well */ 587e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 588e1d5b659SRichard Röjfors 589e1d5b659SRichard Röjfors /* the message is tx:ed */ 590e1d5b659SRichard Röjfors i2c->tx_pos = msg->len; 591e1d5b659SRichard Röjfors } 592e1d5b659SRichard Röjfors 593e1d5b659SRichard Röjfors static void xiic_start_send(struct xiic_i2c *i2c) 594e1d5b659SRichard Röjfors { 595e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->tx_msg; 596e1d5b659SRichard Röjfors 597e1d5b659SRichard Röjfors xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); 598e1d5b659SRichard Röjfors 599f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 600f1e9f89aSKedareswara rao Appana __func__, msg, msg->len); 601f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 602f1e9f89aSKedareswara rao Appana __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 603e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 604e1d5b659SRichard Röjfors 605e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) { 606e1d5b659SRichard Röjfors /* write the address */ 60730a64757SPeter Rosin u16 data = i2c_8bit_addr_from_msg(msg) | 608e1d5b659SRichard Röjfors XIIC_TX_DYN_START_MASK; 609e1d5b659SRichard Röjfors if ((i2c->nmsgs == 1) && msg->len == 0) 610e1d5b659SRichard Röjfors /* no data and last message -> add STOP */ 611e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 612e1d5b659SRichard Röjfors 613e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 614e1d5b659SRichard Röjfors } 615e1d5b659SRichard Röjfors 616e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c); 617e1d5b659SRichard Röjfors 618e1d5b659SRichard Röjfors /* Clear any pending Tx empty, Tx Error and then enable them. */ 619e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 620e1d5b659SRichard Röjfors XIIC_INTR_BNB_MASK); 621e1d5b659SRichard Röjfors } 622e1d5b659SRichard Röjfors 623e1d5b659SRichard Röjfors static irqreturn_t xiic_isr(int irq, void *dev_id) 624e1d5b659SRichard Röjfors { 625e1d5b659SRichard Röjfors struct xiic_i2c *i2c = dev_id; 626fcc2fac6SShubhrajyoti Datta u32 pend, isr, ier; 627fcc2fac6SShubhrajyoti Datta irqreturn_t ret = IRQ_NONE; 628fcc2fac6SShubhrajyoti Datta /* Do not processes a devices interrupts if the device has no 629fcc2fac6SShubhrajyoti Datta * interrupts pending 630fcc2fac6SShubhrajyoti Datta */ 631e1d5b659SRichard Röjfors 632e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); 633e1d5b659SRichard Röjfors 634fcc2fac6SShubhrajyoti Datta isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 635fcc2fac6SShubhrajyoti Datta ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 636fcc2fac6SShubhrajyoti Datta pend = isr & ier; 637fcc2fac6SShubhrajyoti Datta if (pend) 638fcc2fac6SShubhrajyoti Datta ret = IRQ_WAKE_THREAD; 639e1d5b659SRichard Röjfors 640fcc2fac6SShubhrajyoti Datta return ret; 641e1d5b659SRichard Röjfors } 642e1d5b659SRichard Röjfors 643e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c) 644e1d5b659SRichard Röjfors { 645e1d5b659SRichard Röjfors int first = 1; 646e1d5b659SRichard Röjfors int fifo_space = xiic_tx_fifo_space(i2c); 647e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 648e1d5b659SRichard Röjfors __func__, i2c->tx_msg, fifo_space); 649e1d5b659SRichard Röjfors 650e1d5b659SRichard Röjfors if (!i2c->tx_msg) 651e1d5b659SRichard Röjfors return; 652e1d5b659SRichard Röjfors 653e1d5b659SRichard Röjfors i2c->rx_pos = 0; 654e1d5b659SRichard Röjfors i2c->tx_pos = 0; 655e1d5b659SRichard Röjfors i2c->state = STATE_START; 656e1d5b659SRichard Röjfors while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { 657e1d5b659SRichard Röjfors if (!first) { 658e1d5b659SRichard Röjfors i2c->nmsgs--; 659e1d5b659SRichard Röjfors i2c->tx_msg++; 660e1d5b659SRichard Röjfors i2c->tx_pos = 0; 661e1d5b659SRichard Röjfors } else 662e1d5b659SRichard Röjfors first = 0; 663e1d5b659SRichard Röjfors 664e1d5b659SRichard Röjfors if (i2c->tx_msg->flags & I2C_M_RD) { 665e1d5b659SRichard Röjfors /* we dont date putting several reads in the FIFO */ 666e1d5b659SRichard Röjfors xiic_start_recv(i2c); 667e1d5b659SRichard Röjfors return; 668e1d5b659SRichard Röjfors } else { 669e1d5b659SRichard Röjfors xiic_start_send(i2c); 670e1d5b659SRichard Röjfors if (xiic_tx_space(i2c) != 0) { 671e1d5b659SRichard Röjfors /* the message could not be completely sent */ 672e1d5b659SRichard Röjfors break; 673e1d5b659SRichard Röjfors } 674e1d5b659SRichard Röjfors } 675e1d5b659SRichard Röjfors 676e1d5b659SRichard Röjfors fifo_space = xiic_tx_fifo_space(i2c); 677e1d5b659SRichard Röjfors } 678e1d5b659SRichard Röjfors 679e1d5b659SRichard Röjfors /* there are more messages or the current one could not be completely 680e1d5b659SRichard Röjfors * put into the FIFO, also enable the half empty interrupt 681e1d5b659SRichard Röjfors */ 682e1d5b659SRichard Röjfors if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) 683e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); 684e1d5b659SRichard Röjfors 685e1d5b659SRichard Röjfors } 686e1d5b659SRichard Röjfors 687b4c119dbSShubhrajyoti Datta static int xiic_start_xfer(struct xiic_i2c *i2c) 688e1d5b659SRichard Röjfors { 689b4c119dbSShubhrajyoti Datta int ret; 69077c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 691b4c119dbSShubhrajyoti Datta 692b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c); 693b4c119dbSShubhrajyoti Datta if (!ret) 694e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 695b4c119dbSShubhrajyoti Datta 69677c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 697b4c119dbSShubhrajyoti Datta 698b4c119dbSShubhrajyoti Datta return ret; 699e1d5b659SRichard Röjfors } 700e1d5b659SRichard Röjfors 701e1d5b659SRichard Röjfors static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 702e1d5b659SRichard Röjfors { 703e1d5b659SRichard Röjfors struct xiic_i2c *i2c = i2c_get_adapdata(adap); 704e1d5b659SRichard Röjfors int err; 705e1d5b659SRichard Röjfors 706e1d5b659SRichard Röjfors dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 707e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 708e1d5b659SRichard Röjfors 709*a85c5c7aSQinglang Miao err = pm_runtime_resume_and_get(i2c->dev); 71036ecbcabSShubhrajyoti Datta if (err < 0) 71136ecbcabSShubhrajyoti Datta return err; 71236ecbcabSShubhrajyoti Datta 713e1d5b659SRichard Röjfors err = xiic_busy(i2c); 714e1d5b659SRichard Röjfors if (err) 71536ecbcabSShubhrajyoti Datta goto out; 716e1d5b659SRichard Röjfors 717e1d5b659SRichard Röjfors i2c->tx_msg = msgs; 718e1d5b659SRichard Röjfors i2c->nmsgs = num; 719e1d5b659SRichard Röjfors 720b4c119dbSShubhrajyoti Datta err = xiic_start_xfer(i2c); 721b4c119dbSShubhrajyoti Datta if (err < 0) { 722b4c119dbSShubhrajyoti Datta dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 723b4c119dbSShubhrajyoti Datta goto out; 724b4c119dbSShubhrajyoti Datta } 725e1d5b659SRichard Röjfors 726e1d5b659SRichard Röjfors if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 72736ecbcabSShubhrajyoti Datta (i2c->state == STATE_DONE), HZ)) { 72836ecbcabSShubhrajyoti Datta err = (i2c->state == STATE_DONE) ? num : -EIO; 72936ecbcabSShubhrajyoti Datta goto out; 73036ecbcabSShubhrajyoti Datta } else { 731e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 732e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 733e1d5b659SRichard Röjfors i2c->nmsgs = 0; 73436ecbcabSShubhrajyoti Datta err = -ETIMEDOUT; 73536ecbcabSShubhrajyoti Datta goto out; 736e1d5b659SRichard Röjfors } 73736ecbcabSShubhrajyoti Datta out: 73836ecbcabSShubhrajyoti Datta pm_runtime_mark_last_busy(i2c->dev); 73936ecbcabSShubhrajyoti Datta pm_runtime_put_autosuspend(i2c->dev); 74036ecbcabSShubhrajyoti Datta return err; 741e1d5b659SRichard Röjfors } 742e1d5b659SRichard Röjfors 743e1d5b659SRichard Röjfors static u32 xiic_func(struct i2c_adapter *adap) 744e1d5b659SRichard Röjfors { 745e1d5b659SRichard Röjfors return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 746e1d5b659SRichard Röjfors } 747e1d5b659SRichard Röjfors 748e1d5b659SRichard Röjfors static const struct i2c_algorithm xiic_algorithm = { 749e1d5b659SRichard Röjfors .master_xfer = xiic_xfer, 750e1d5b659SRichard Röjfors .functionality = xiic_func, 751e1d5b659SRichard Röjfors }; 752e1d5b659SRichard Röjfors 75349b80958SRobert Hancock static const struct i2c_adapter_quirks xiic_quirks = { 75449b80958SRobert Hancock .max_read_len = 255, 75549b80958SRobert Hancock }; 75649b80958SRobert Hancock 757329430ccSBhumika Goyal static const struct i2c_adapter xiic_adapter = { 758e1d5b659SRichard Röjfors .owner = THIS_MODULE, 759e1d5b659SRichard Röjfors .name = DRIVER_NAME, 7604db5beedSWolfram Sang .class = I2C_CLASS_DEPRECATED, 761e1d5b659SRichard Röjfors .algo = &xiic_algorithm, 76249b80958SRobert Hancock .quirks = &xiic_quirks, 763e1d5b659SRichard Röjfors }; 764e1d5b659SRichard Röjfors 765e1d5b659SRichard Röjfors 7660b255e92SBill Pemberton static int xiic_i2c_probe(struct platform_device *pdev) 767e1d5b659SRichard Röjfors { 768e1d5b659SRichard Röjfors struct xiic_i2c *i2c; 769e1d5b659SRichard Röjfors struct xiic_i2c_platform_data *pdata; 770e1d5b659SRichard Röjfors struct resource *res; 771e1d5b659SRichard Röjfors int ret, irq; 772e1d5b659SRichard Röjfors u8 i; 77348ef3ca9SThomas Gessler u32 sr; 774e1d5b659SRichard Röjfors 775168e722dSKedareswara rao Appana i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 776e1d5b659SRichard Röjfors if (!i2c) 777e1d5b659SRichard Röjfors return -ENOMEM; 778e1d5b659SRichard Röjfors 779168e722dSKedareswara rao Appana res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 780168e722dSKedareswara rao Appana i2c->base = devm_ioremap_resource(&pdev->dev, res); 781168e722dSKedareswara rao Appana if (IS_ERR(i2c->base)) 782168e722dSKedareswara rao Appana return PTR_ERR(i2c->base); 783e1d5b659SRichard Röjfors 784168e722dSKedareswara rao Appana irq = platform_get_irq(pdev, 0); 785168e722dSKedareswara rao Appana if (irq < 0) 786168e722dSKedareswara rao Appana return irq; 787168e722dSKedareswara rao Appana 788168e722dSKedareswara rao Appana pdata = dev_get_platdata(&pdev->dev); 789e1d5b659SRichard Röjfors 790e1d5b659SRichard Röjfors /* hook up driver to tree */ 791e1d5b659SRichard Röjfors platform_set_drvdata(pdev, i2c); 792e1d5b659SRichard Röjfors i2c->adap = xiic_adapter; 793e1d5b659SRichard Röjfors i2c_set_adapdata(&i2c->adap, i2c); 794e1d5b659SRichard Röjfors i2c->adap.dev.parent = &pdev->dev; 7953ac0b337SLars-Peter Clausen i2c->adap.dev.of_node = pdev->dev.of_node; 796e1d5b659SRichard Röjfors 79777c68019SLars-Peter Clausen mutex_init(&i2c->lock); 798e1d5b659SRichard Röjfors init_waitqueue_head(&i2c->wait); 799168e722dSKedareswara rao Appana 80036ecbcabSShubhrajyoti Datta i2c->clk = devm_clk_get(&pdev->dev, NULL); 80136ecbcabSShubhrajyoti Datta if (IS_ERR(i2c->clk)) { 802c9d05968SVenkatesh Yadav Abbarapu if (PTR_ERR(i2c->clk) != -EPROBE_DEFER) 80336ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "input clock not found.\n"); 80436ecbcabSShubhrajyoti Datta return PTR_ERR(i2c->clk); 80536ecbcabSShubhrajyoti Datta } 80636ecbcabSShubhrajyoti Datta ret = clk_prepare_enable(i2c->clk); 80736ecbcabSShubhrajyoti Datta if (ret) { 80836ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "Unable to enable clock.\n"); 80936ecbcabSShubhrajyoti Datta return ret; 81036ecbcabSShubhrajyoti Datta } 81136ecbcabSShubhrajyoti Datta i2c->dev = &pdev->dev; 81236ecbcabSShubhrajyoti Datta pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 81336ecbcabSShubhrajyoti Datta pm_runtime_use_autosuspend(i2c->dev); 81436ecbcabSShubhrajyoti Datta pm_runtime_set_active(i2c->dev); 81510b17004SShubhrajyoti Datta pm_runtime_enable(i2c->dev); 816fcc2fac6SShubhrajyoti Datta ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr, 817fcc2fac6SShubhrajyoti Datta xiic_process, IRQF_ONESHOT, 818fcc2fac6SShubhrajyoti Datta pdev->name, i2c); 819fcc2fac6SShubhrajyoti Datta 820168e722dSKedareswara rao Appana if (ret < 0) { 821e1d5b659SRichard Röjfors dev_err(&pdev->dev, "Cannot claim IRQ\n"); 82236ecbcabSShubhrajyoti Datta goto err_clk_dis; 823e1d5b659SRichard Röjfors } 824e1d5b659SRichard Röjfors 8259e3b184bSJaakko Laine i2c->singlemaster = 8269e3b184bSJaakko Laine of_property_read_bool(pdev->dev.of_node, "single-master"); 8279e3b184bSJaakko Laine 82848ef3ca9SThomas Gessler /* 82948ef3ca9SThomas Gessler * Detect endianness 83048ef3ca9SThomas Gessler * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 83148ef3ca9SThomas Gessler * set, assume that the endianness was wrong and swap. 83248ef3ca9SThomas Gessler */ 83348ef3ca9SThomas Gessler i2c->endianness = LITTLE; 83448ef3ca9SThomas Gessler xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 83548ef3ca9SThomas Gessler /* Reset is cleared in xiic_reinit */ 83648ef3ca9SThomas Gessler sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 83748ef3ca9SThomas Gessler if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 83848ef3ca9SThomas Gessler i2c->endianness = BIG; 83948ef3ca9SThomas Gessler 840b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c); 841b4c119dbSShubhrajyoti Datta if (ret < 0) { 842b4c119dbSShubhrajyoti Datta dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 843b4c119dbSShubhrajyoti Datta goto err_clk_dis; 844b4c119dbSShubhrajyoti Datta } 845617bdcbcSMichal Simek 846e1d5b659SRichard Röjfors /* add i2c adapter to i2c tree */ 847e1d5b659SRichard Röjfors ret = i2c_add_adapter(&i2c->adap); 848e1d5b659SRichard Röjfors if (ret) { 849168e722dSKedareswara rao Appana xiic_deinit(i2c); 85036ecbcabSShubhrajyoti Datta goto err_clk_dis; 851e1d5b659SRichard Röjfors } 852e1d5b659SRichard Röjfors 8533ac0b337SLars-Peter Clausen if (pdata) { 854e1d5b659SRichard Röjfors /* add in known devices to the bus */ 855e1d5b659SRichard Röjfors for (i = 0; i < pdata->num_devices; i++) 856bf255befSWolfram Sang i2c_new_client_device(&i2c->adap, pdata->devices + i); 8573ac0b337SLars-Peter Clausen } 8583ac0b337SLars-Peter Clausen 859e1d5b659SRichard Röjfors return 0; 86036ecbcabSShubhrajyoti Datta 86136ecbcabSShubhrajyoti Datta err_clk_dis: 86236ecbcabSShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 86336ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 86436ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 86536ecbcabSShubhrajyoti Datta return ret; 866e1d5b659SRichard Röjfors } 867e1d5b659SRichard Röjfors 8680b255e92SBill Pemberton static int xiic_i2c_remove(struct platform_device *pdev) 869e1d5b659SRichard Röjfors { 870e1d5b659SRichard Röjfors struct xiic_i2c *i2c = platform_get_drvdata(pdev); 87136ecbcabSShubhrajyoti Datta int ret; 872e1d5b659SRichard Röjfors 873e1d5b659SRichard Röjfors /* remove adapter & data */ 874e1d5b659SRichard Röjfors i2c_del_adapter(&i2c->adap); 875e1d5b659SRichard Röjfors 876*a85c5c7aSQinglang Miao ret = pm_runtime_resume_and_get(i2c->dev); 87710b17004SShubhrajyoti Datta if (ret < 0) 87836ecbcabSShubhrajyoti Datta return ret; 87910b17004SShubhrajyoti Datta 880e1d5b659SRichard Röjfors xiic_deinit(i2c); 88110b17004SShubhrajyoti Datta pm_runtime_put_sync(i2c->dev); 88236ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 88336ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 88410b17004SShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 88510b17004SShubhrajyoti Datta pm_runtime_dont_use_autosuspend(&pdev->dev); 886e1d5b659SRichard Röjfors 887e1d5b659SRichard Röjfors return 0; 888e1d5b659SRichard Röjfors } 889e1d5b659SRichard Röjfors 8903ac0b337SLars-Peter Clausen #if defined(CONFIG_OF) 8910b255e92SBill Pemberton static const struct of_device_id xiic_of_match[] = { 8923ac0b337SLars-Peter Clausen { .compatible = "xlnx,xps-iic-2.00.a", }, 8933ac0b337SLars-Peter Clausen {}, 8943ac0b337SLars-Peter Clausen }; 8953ac0b337SLars-Peter Clausen MODULE_DEVICE_TABLE(of, xiic_of_match); 8963ac0b337SLars-Peter Clausen #endif 8973ac0b337SLars-Peter Clausen 89874d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 89936ecbcabSShubhrajyoti Datta { 9009242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev); 90136ecbcabSShubhrajyoti Datta 90236ecbcabSShubhrajyoti Datta clk_disable(i2c->clk); 90336ecbcabSShubhrajyoti Datta 90436ecbcabSShubhrajyoti Datta return 0; 90536ecbcabSShubhrajyoti Datta } 90636ecbcabSShubhrajyoti Datta 90774d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 90836ecbcabSShubhrajyoti Datta { 9099242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev); 91036ecbcabSShubhrajyoti Datta int ret; 91136ecbcabSShubhrajyoti Datta 91236ecbcabSShubhrajyoti Datta ret = clk_enable(i2c->clk); 91336ecbcabSShubhrajyoti Datta if (ret) { 91436ecbcabSShubhrajyoti Datta dev_err(dev, "Cannot enable clock.\n"); 91536ecbcabSShubhrajyoti Datta return ret; 91636ecbcabSShubhrajyoti Datta } 91736ecbcabSShubhrajyoti Datta 91836ecbcabSShubhrajyoti Datta return 0; 91936ecbcabSShubhrajyoti Datta } 92036ecbcabSShubhrajyoti Datta 92136ecbcabSShubhrajyoti Datta static const struct dev_pm_ops xiic_dev_pm_ops = { 92274d23319SMoritz Fischer SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 92374d23319SMoritz Fischer xiic_i2c_runtime_resume, NULL) 92436ecbcabSShubhrajyoti Datta }; 925e1d5b659SRichard Röjfors static struct platform_driver xiic_i2c_driver = { 926e1d5b659SRichard Röjfors .probe = xiic_i2c_probe, 9270b255e92SBill Pemberton .remove = xiic_i2c_remove, 928e1d5b659SRichard Röjfors .driver = { 929e1d5b659SRichard Röjfors .name = DRIVER_NAME, 9303ac0b337SLars-Peter Clausen .of_match_table = of_match_ptr(xiic_of_match), 93136ecbcabSShubhrajyoti Datta .pm = &xiic_dev_pm_ops, 932e1d5b659SRichard Röjfors }, 933e1d5b659SRichard Röjfors }; 934e1d5b659SRichard Röjfors 935a3664b51SAxel Lin module_platform_driver(xiic_i2c_driver); 936e1d5b659SRichard Röjfors 937e1d5b659SRichard Röjfors MODULE_AUTHOR("info@mocean-labs.com"); 938e1d5b659SRichard Röjfors MODULE_DESCRIPTION("Xilinx I2C bus driver"); 939e1d5b659SRichard Röjfors MODULE_LICENSE("GPL v2"); 940a3664b51SAxel Lin MODULE_ALIAS("platform:"DRIVER_NAME); 941