11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e1d5b659SRichard Röjfors /* 3e1d5b659SRichard Röjfors * i2c-xiic.c 4e1d5b659SRichard Röjfors * Copyright (c) 2002-2007 Xilinx Inc. 5e1d5b659SRichard Röjfors * Copyright (c) 2009-2010 Intel Corporation 6e1d5b659SRichard Röjfors * 7e1d5b659SRichard Röjfors * This code was implemented by Mocean Laboratories AB when porting linux 8e1d5b659SRichard Röjfors * to the automotive development board Russellville. The copyright holder 9e1d5b659SRichard Röjfors * as seen in the header is Intel corporation. 10e1d5b659SRichard Röjfors * Mocean Laboratories forked off the GNU/Linux platform work into a 1125985edcSLucas De Marchi * separate company called Pelagicore AB, which committed the code to the 12e1d5b659SRichard Röjfors * kernel. 13e1d5b659SRichard Röjfors */ 14e1d5b659SRichard Röjfors 15e1d5b659SRichard Röjfors /* Supports: 16e1d5b659SRichard Röjfors * Xilinx IIC 17e1d5b659SRichard Röjfors */ 18e1d5b659SRichard Röjfors #include <linux/kernel.h> 19e1d5b659SRichard Röjfors #include <linux/module.h> 20e1d5b659SRichard Röjfors #include <linux/errno.h> 21168e722dSKedareswara rao Appana #include <linux/err.h> 2202ca6c40SRandy Dunlap #include <linux/delay.h> 23e1d5b659SRichard Röjfors #include <linux/platform_device.h> 24e1d5b659SRichard Röjfors #include <linux/i2c.h> 25e1d5b659SRichard Röjfors #include <linux/interrupt.h> 26e1d5b659SRichard Röjfors #include <linux/wait.h> 277072b75cSWolfram Sang #include <linux/platform_data/i2c-xiic.h> 28e1d5b659SRichard Röjfors #include <linux/io.h> 295a0e3ad6STejun Heo #include <linux/slab.h> 304edd65e6SSachin Kamat #include <linux/of.h> 3136ecbcabSShubhrajyoti Datta #include <linux/clk.h> 3236ecbcabSShubhrajyoti Datta #include <linux/pm_runtime.h> 33e1d5b659SRichard Röjfors 34e1d5b659SRichard Röjfors #define DRIVER_NAME "xiic-i2c" 35e1d5b659SRichard Röjfors 36e1d5b659SRichard Röjfors enum xilinx_i2c_state { 37e1d5b659SRichard Röjfors STATE_DONE, 38e1d5b659SRichard Röjfors STATE_ERROR, 39e1d5b659SRichard Röjfors STATE_START 40e1d5b659SRichard Röjfors }; 41e1d5b659SRichard Röjfors 4248ef3ca9SThomas Gessler enum xiic_endian { 4348ef3ca9SThomas Gessler LITTLE, 4448ef3ca9SThomas Gessler BIG 4548ef3ca9SThomas Gessler }; 4648ef3ca9SThomas Gessler 47e1d5b659SRichard Röjfors /** 48e1d5b659SRichard Röjfors * struct xiic_i2c - Internal representation of the XIIC I2C bus 49bcc156e2SShubhrajyoti Datta * @dev: Pointer to device structure 50e1d5b659SRichard Röjfors * @base: Memory base of the HW registers 51e1d5b659SRichard Röjfors * @wait: Wait queue for callers 52e1d5b659SRichard Röjfors * @adap: Kernel adapter representation 53e1d5b659SRichard Röjfors * @tx_msg: Messages from above to be sent 54e1d5b659SRichard Röjfors * @lock: Mutual exclusion 55e1d5b659SRichard Röjfors * @tx_pos: Current pos in TX message 56e1d5b659SRichard Röjfors * @nmsgs: Number of messages in tx_msg 57e1d5b659SRichard Röjfors * @rx_msg: Current RX message 58e1d5b659SRichard Röjfors * @rx_pos: Position within current RX message 59bea6ff02SShubhrajyoti Datta * @endianness: big/little-endian byte order 60bcc156e2SShubhrajyoti Datta * @clk: Pointer to AXI4-lite input clock 619106e45cSJaakko Laine * @state: See STATE_ 62e1d5b659SRichard Röjfors */ 63e1d5b659SRichard Röjfors struct xiic_i2c { 6436ecbcabSShubhrajyoti Datta struct device *dev; 65e1d5b659SRichard Röjfors void __iomem *base; 66e1d5b659SRichard Röjfors wait_queue_head_t wait; 67e1d5b659SRichard Röjfors struct i2c_adapter adap; 68e1d5b659SRichard Röjfors struct i2c_msg *tx_msg; 6977c68019SLars-Peter Clausen struct mutex lock; 70e1d5b659SRichard Röjfors unsigned int tx_pos; 71e1d5b659SRichard Röjfors unsigned int nmsgs; 72e1d5b659SRichard Röjfors struct i2c_msg *rx_msg; 73e1d5b659SRichard Röjfors int rx_pos; 7448ef3ca9SThomas Gessler enum xiic_endian endianness; 7536ecbcabSShubhrajyoti Datta struct clk *clk; 769106e45cSJaakko Laine enum xilinx_i2c_state state; 77e1d5b659SRichard Röjfors }; 78e1d5b659SRichard Röjfors 79e1d5b659SRichard Röjfors 80e1d5b659SRichard Röjfors #define XIIC_MSB_OFFSET 0 81e1d5b659SRichard Röjfors #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 82e1d5b659SRichard Röjfors 83e1d5b659SRichard Röjfors /* 84e1d5b659SRichard Röjfors * Register offsets in bytes from RegisterBase. Three is added to the 85e1d5b659SRichard Röjfors * base offset to access LSB (IBM style) of the word 86e1d5b659SRichard Röjfors */ 87e1d5b659SRichard Röjfors #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 88e1d5b659SRichard Röjfors #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 89e1d5b659SRichard Röjfors #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 90e1d5b659SRichard Röjfors #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 91e1d5b659SRichard Röjfors #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 92e1d5b659SRichard Röjfors #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 93e1d5b659SRichard Röjfors #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 94e1d5b659SRichard Röjfors #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 95e1d5b659SRichard Röjfors #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 96e1d5b659SRichard Röjfors #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 97e1d5b659SRichard Röjfors 98e1d5b659SRichard Röjfors /* Control Register masks */ 99e1d5b659SRichard Röjfors #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 100e1d5b659SRichard Röjfors #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 101e1d5b659SRichard Röjfors #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 102e1d5b659SRichard Röjfors #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 103e1d5b659SRichard Röjfors #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 104e1d5b659SRichard Röjfors #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 105e1d5b659SRichard Röjfors #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 106e1d5b659SRichard Röjfors 107e1d5b659SRichard Röjfors /* Status Register masks */ 108e1d5b659SRichard Röjfors #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 109e1d5b659SRichard Röjfors #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 110e1d5b659SRichard Röjfors #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 111e1d5b659SRichard Röjfors #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 112e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 113e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 114e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 115e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 116e1d5b659SRichard Röjfors 117e1d5b659SRichard Röjfors /* Interrupt Status Register masks Interrupt occurs when... */ 118e1d5b659SRichard Röjfors #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 119e1d5b659SRichard Röjfors #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 120e1d5b659SRichard Röjfors #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 121e1d5b659SRichard Röjfors #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 122e1d5b659SRichard Röjfors #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 123e1d5b659SRichard Röjfors #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 124e1d5b659SRichard Röjfors #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 125e1d5b659SRichard Röjfors #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 126e1d5b659SRichard Röjfors 127e1d5b659SRichard Röjfors /* The following constants specify the depth of the FIFOs */ 128e1d5b659SRichard Röjfors #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 129e1d5b659SRichard Röjfors #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 130e1d5b659SRichard Röjfors 131e1d5b659SRichard Röjfors /* The following constants specify groups of interrupts that are typically 132e1d5b659SRichard Röjfors * enabled or disables at the same time 133e1d5b659SRichard Röjfors */ 134e1d5b659SRichard Röjfors #define XIIC_TX_INTERRUPTS \ 135e1d5b659SRichard Röjfors (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 136e1d5b659SRichard Röjfors 137e1d5b659SRichard Röjfors #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 138e1d5b659SRichard Röjfors 139e1d5b659SRichard Röjfors /* 140e1d5b659SRichard Röjfors * Tx Fifo upper bit masks. 141e1d5b659SRichard Röjfors */ 142e1d5b659SRichard Röjfors #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 143e1d5b659SRichard Röjfors #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 144e1d5b659SRichard Röjfors 145e1d5b659SRichard Röjfors /* 146e1d5b659SRichard Röjfors * The following constants define the register offsets for the Interrupt 147e1d5b659SRichard Röjfors * registers. There are some holes in the memory map for reserved addresses 148e1d5b659SRichard Röjfors * to allow other registers to be added and still match the memory map of the 149e1d5b659SRichard Röjfors * interrupt controller registers 150e1d5b659SRichard Röjfors */ 151e1d5b659SRichard Röjfors #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 152e1d5b659SRichard Röjfors #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 153e1d5b659SRichard Röjfors #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 154e1d5b659SRichard Röjfors #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 155e1d5b659SRichard Röjfors 156e1d5b659SRichard Röjfors #define XIIC_RESET_MASK 0xAUL 157e1d5b659SRichard Röjfors 15836ecbcabSShubhrajyoti Datta #define XIIC_PM_TIMEOUT 1000 /* ms */ 159b4c119dbSShubhrajyoti Datta /* timeout waiting for the controller to respond */ 160b4c119dbSShubhrajyoti Datta #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 161e1d5b659SRichard Röjfors /* 162e1d5b659SRichard Röjfors * The following constant is used for the device global interrupt enable 163e1d5b659SRichard Röjfors * register, to enable all interrupts for the device, this is the only bit 164e1d5b659SRichard Röjfors * in the register 165e1d5b659SRichard Röjfors */ 166e1d5b659SRichard Röjfors #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 167e1d5b659SRichard Röjfors 168e1d5b659SRichard Röjfors #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 169e1d5b659SRichard Röjfors #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 170e1d5b659SRichard Röjfors 171b4c119dbSShubhrajyoti Datta static int xiic_start_xfer(struct xiic_i2c *i2c); 172e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c); 173e1d5b659SRichard Röjfors 17448ef3ca9SThomas Gessler /* 17548ef3ca9SThomas Gessler * For the register read and write functions, a little-endian and big-endian 17648ef3ca9SThomas Gessler * version are necessary. Endianness is detected during the probe function. 17748ef3ca9SThomas Gessler * Only the least significant byte [doublet] of the register are ever 17848ef3ca9SThomas Gessler * accessed. This requires an offset of 3 [2] from the base address for 17948ef3ca9SThomas Gessler * big-endian systems. 18048ef3ca9SThomas Gessler */ 18148ef3ca9SThomas Gessler 182e1d5b659SRichard Röjfors static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 183e1d5b659SRichard Röjfors { 18448ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 185e1d5b659SRichard Röjfors iowrite8(value, i2c->base + reg); 18648ef3ca9SThomas Gessler else 18748ef3ca9SThomas Gessler iowrite8(value, i2c->base + reg + 3); 188e1d5b659SRichard Röjfors } 189e1d5b659SRichard Röjfors 190e1d5b659SRichard Röjfors static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 191e1d5b659SRichard Röjfors { 19248ef3ca9SThomas Gessler u8 ret; 19348ef3ca9SThomas Gessler 19448ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 19548ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg); 19648ef3ca9SThomas Gessler else 19748ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg + 3); 19848ef3ca9SThomas Gessler return ret; 199e1d5b659SRichard Röjfors } 200e1d5b659SRichard Röjfors 201e1d5b659SRichard Röjfors static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 202e1d5b659SRichard Röjfors { 20348ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 204e1d5b659SRichard Röjfors iowrite16(value, i2c->base + reg); 20548ef3ca9SThomas Gessler else 20648ef3ca9SThomas Gessler iowrite16be(value, i2c->base + reg + 2); 207e1d5b659SRichard Röjfors } 208e1d5b659SRichard Röjfors 209e1d5b659SRichard Röjfors static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 210e1d5b659SRichard Röjfors { 21148ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 212e1d5b659SRichard Röjfors iowrite32(value, i2c->base + reg); 21348ef3ca9SThomas Gessler else 21448ef3ca9SThomas Gessler iowrite32be(value, i2c->base + reg); 215e1d5b659SRichard Röjfors } 216e1d5b659SRichard Röjfors 217e1d5b659SRichard Röjfors static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 218e1d5b659SRichard Röjfors { 21948ef3ca9SThomas Gessler u32 ret; 22048ef3ca9SThomas Gessler 22148ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 22248ef3ca9SThomas Gessler ret = ioread32(i2c->base + reg); 22348ef3ca9SThomas Gessler else 22448ef3ca9SThomas Gessler ret = ioread32be(i2c->base + reg); 22548ef3ca9SThomas Gessler return ret; 226e1d5b659SRichard Röjfors } 227e1d5b659SRichard Röjfors 228e1d5b659SRichard Röjfors static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 229e1d5b659SRichard Röjfors { 230e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 231e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 232e1d5b659SRichard Röjfors } 233e1d5b659SRichard Röjfors 234e1d5b659SRichard Röjfors static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 235e1d5b659SRichard Röjfors { 236e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 237e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 238e1d5b659SRichard Röjfors } 239e1d5b659SRichard Röjfors 240e1d5b659SRichard Röjfors static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 241e1d5b659SRichard Röjfors { 242e1d5b659SRichard Röjfors u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 243e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 244e1d5b659SRichard Röjfors } 245e1d5b659SRichard Röjfors 246e1d5b659SRichard Röjfors static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 247e1d5b659SRichard Röjfors { 248e1d5b659SRichard Röjfors xiic_irq_clr(i2c, mask); 249e1d5b659SRichard Röjfors xiic_irq_en(i2c, mask); 250e1d5b659SRichard Röjfors } 251e1d5b659SRichard Röjfors 252b4c119dbSShubhrajyoti Datta static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 253e1d5b659SRichard Röjfors { 254e1d5b659SRichard Röjfors u8 sr; 255b4c119dbSShubhrajyoti Datta unsigned long timeout; 256b4c119dbSShubhrajyoti Datta 257b4c119dbSShubhrajyoti Datta timeout = jiffies + XIIC_I2C_TIMEOUT; 258e1d5b659SRichard Röjfors for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 259e1d5b659SRichard Röjfors !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 260b4c119dbSShubhrajyoti Datta sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 261e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 262b4c119dbSShubhrajyoti Datta if (time_after(jiffies, timeout)) { 263b4c119dbSShubhrajyoti Datta dev_err(i2c->dev, "Failed to clear rx fifo\n"); 264b4c119dbSShubhrajyoti Datta return -ETIMEDOUT; 265b4c119dbSShubhrajyoti Datta } 266e1d5b659SRichard Röjfors } 267e1d5b659SRichard Röjfors 268b4c119dbSShubhrajyoti Datta return 0; 269b4c119dbSShubhrajyoti Datta } 270b4c119dbSShubhrajyoti Datta 271b4c119dbSShubhrajyoti Datta static int xiic_reinit(struct xiic_i2c *i2c) 272e1d5b659SRichard Röjfors { 273b4c119dbSShubhrajyoti Datta int ret; 274b4c119dbSShubhrajyoti Datta 275e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 276e1d5b659SRichard Röjfors 277e1d5b659SRichard Röjfors /* Set receive Fifo depth to maximum (zero based). */ 278e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 279e1d5b659SRichard Röjfors 280e1d5b659SRichard Röjfors /* Reset Tx Fifo. */ 281e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 282e1d5b659SRichard Röjfors 283e1d5b659SRichard Röjfors /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 284e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 285e1d5b659SRichard Röjfors 286e1d5b659SRichard Röjfors /* make sure RX fifo is empty */ 287b4c119dbSShubhrajyoti Datta ret = xiic_clear_rx_fifo(i2c); 288b4c119dbSShubhrajyoti Datta if (ret) 289b4c119dbSShubhrajyoti Datta return ret; 290e1d5b659SRichard Röjfors 291e1d5b659SRichard Röjfors /* Enable interrupts */ 292e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 293e1d5b659SRichard Röjfors 294542e2a9bSShubhrajyoti Datta xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 295b4c119dbSShubhrajyoti Datta 296b4c119dbSShubhrajyoti Datta return 0; 297e1d5b659SRichard Röjfors } 298e1d5b659SRichard Röjfors 299e1d5b659SRichard Röjfors static void xiic_deinit(struct xiic_i2c *i2c) 300e1d5b659SRichard Röjfors { 301e1d5b659SRichard Röjfors u8 cr; 302e1d5b659SRichard Röjfors 303e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 304e1d5b659SRichard Röjfors 305e1d5b659SRichard Röjfors /* Disable IIC Device. */ 306e1d5b659SRichard Röjfors cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 307e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 308e1d5b659SRichard Röjfors } 309e1d5b659SRichard Röjfors 310e1d5b659SRichard Röjfors static void xiic_read_rx(struct xiic_i2c *i2c) 311e1d5b659SRichard Röjfors { 312e1d5b659SRichard Röjfors u8 bytes_in_fifo; 313e1d5b659SRichard Röjfors int i; 314e1d5b659SRichard Röjfors 315e1d5b659SRichard Röjfors bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 316e1d5b659SRichard Röjfors 317f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, 318f1e9f89aSKedareswara rao Appana "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 319e1d5b659SRichard Röjfors __func__, bytes_in_fifo, xiic_rx_space(i2c), 320e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 321e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 322e1d5b659SRichard Röjfors 323e1d5b659SRichard Röjfors if (bytes_in_fifo > xiic_rx_space(i2c)) 324e1d5b659SRichard Röjfors bytes_in_fifo = xiic_rx_space(i2c); 325e1d5b659SRichard Röjfors 326e1d5b659SRichard Röjfors for (i = 0; i < bytes_in_fifo; i++) 327e1d5b659SRichard Röjfors i2c->rx_msg->buf[i2c->rx_pos++] = 328e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 329e1d5b659SRichard Röjfors 330e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 331e1d5b659SRichard Röjfors (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 332e1d5b659SRichard Röjfors IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 333e1d5b659SRichard Röjfors } 334e1d5b659SRichard Röjfors 335e1d5b659SRichard Röjfors static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 336e1d5b659SRichard Röjfors { 337e1d5b659SRichard Röjfors /* return the actual space left in the FIFO */ 338e1d5b659SRichard Röjfors return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 339e1d5b659SRichard Röjfors } 340e1d5b659SRichard Röjfors 341e1d5b659SRichard Röjfors static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 342e1d5b659SRichard Röjfors { 343e1d5b659SRichard Röjfors u8 fifo_space = xiic_tx_fifo_space(i2c); 344e1d5b659SRichard Röjfors int len = xiic_tx_space(i2c); 345e1d5b659SRichard Röjfors 346e1d5b659SRichard Röjfors len = (len > fifo_space) ? fifo_space : len; 347e1d5b659SRichard Röjfors 348e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 349e1d5b659SRichard Röjfors __func__, len, fifo_space); 350e1d5b659SRichard Röjfors 351e1d5b659SRichard Röjfors while (len--) { 352e1d5b659SRichard Röjfors u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 353e1d5b659SRichard Röjfors if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 354e1d5b659SRichard Röjfors /* last message in transfer -> STOP */ 355e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 356e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 357c39e8e43SSteven A. Falco } 358e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 359e1d5b659SRichard Röjfors } 360e1d5b659SRichard Röjfors } 361e1d5b659SRichard Röjfors 362e1d5b659SRichard Röjfors static void xiic_wakeup(struct xiic_i2c *i2c, int code) 363e1d5b659SRichard Röjfors { 364e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 365e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 366e1d5b659SRichard Röjfors i2c->nmsgs = 0; 367e1d5b659SRichard Röjfors i2c->state = code; 368e1d5b659SRichard Röjfors wake_up(&i2c->wait); 369e1d5b659SRichard Röjfors } 370e1d5b659SRichard Röjfors 371fcc2fac6SShubhrajyoti Datta static irqreturn_t xiic_process(int irq, void *dev_id) 372e1d5b659SRichard Röjfors { 373fcc2fac6SShubhrajyoti Datta struct xiic_i2c *i2c = dev_id; 374e1d5b659SRichard Röjfors u32 pend, isr, ier; 375e1d5b659SRichard Röjfors u32 clr = 0; 376e1d5b659SRichard Röjfors 377e1d5b659SRichard Röjfors /* Get the interrupt Status from the IPIF. There is no clearing of 378e1d5b659SRichard Röjfors * interrupts in the IPIF. Interrupts must be cleared at the source. 379e1d5b659SRichard Röjfors * To find which interrupts are pending; AND interrupts pending with 380e1d5b659SRichard Röjfors * interrupts masked. 381e1d5b659SRichard Röjfors */ 38277c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 383e1d5b659SRichard Röjfors isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 384e1d5b659SRichard Röjfors ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 385e1d5b659SRichard Röjfors pend = isr & ier; 386e1d5b659SRichard Röjfors 387f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 388f1e9f89aSKedareswara rao Appana __func__, ier, isr, pend); 389f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 390f1e9f89aSKedareswara rao Appana __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 391e1d5b659SRichard Röjfors i2c->tx_msg, i2c->nmsgs); 392e1d5b659SRichard Röjfors 393e1d5b659SRichard Röjfors 394e1d5b659SRichard Röjfors /* Service requesting interrupt */ 395e1d5b659SRichard Röjfors if ((pend & XIIC_INTR_ARB_LOST_MASK) || 396e1d5b659SRichard Röjfors ((pend & XIIC_INTR_TX_ERROR_MASK) && 397e1d5b659SRichard Röjfors !(pend & XIIC_INTR_RX_FULL_MASK))) { 398e1d5b659SRichard Röjfors /* bus arbritration lost, or... 399e1d5b659SRichard Röjfors * Transmit error _OR_ RX completed 400e1d5b659SRichard Röjfors * if this happens when RX_FULL is not set 401e1d5b659SRichard Röjfors * this is probably a TX error 402e1d5b659SRichard Röjfors */ 403e1d5b659SRichard Röjfors 404e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 405e1d5b659SRichard Röjfors 406e1d5b659SRichard Röjfors /* dynamic mode seem to suffer from problems if we just flushes 407e1d5b659SRichard Röjfors * fifos and the next message is a TX with len 0 (only addr) 408e1d5b659SRichard Röjfors * reset the IP instead of just flush fifos 409e1d5b659SRichard Röjfors */ 410e1d5b659SRichard Röjfors xiic_reinit(i2c); 411e1d5b659SRichard Röjfors 4126b0c8dc3SShubhrajyoti Datta if (i2c->rx_msg) 4136b0c8dc3SShubhrajyoti Datta xiic_wakeup(i2c, STATE_ERROR); 414e1d5b659SRichard Röjfors if (i2c->tx_msg) 415e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_ERROR); 4167f9906bdSShubhrajyoti Datta } 4177f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_RX_FULL_MASK) { 418e1d5b659SRichard Röjfors /* Receive register/FIFO is full */ 419e1d5b659SRichard Röjfors 4207f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_RX_FULL_MASK; 421e1d5b659SRichard Röjfors if (!i2c->rx_msg) { 422e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 4231ee7cdbfSColin Ian King "%s unexpected RX IRQ\n", __func__); 424e1d5b659SRichard Röjfors xiic_clear_rx_fifo(i2c); 425e1d5b659SRichard Röjfors goto out; 426e1d5b659SRichard Röjfors } 427e1d5b659SRichard Röjfors 428e1d5b659SRichard Röjfors xiic_read_rx(i2c); 429e1d5b659SRichard Röjfors if (xiic_rx_space(i2c) == 0) { 430e1d5b659SRichard Röjfors /* this is the last part of the message */ 431e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 432e1d5b659SRichard Röjfors 433e1d5b659SRichard Röjfors /* also clear TX error if there (RX complete) */ 434e1d5b659SRichard Röjfors clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 435e1d5b659SRichard Röjfors 436e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 437e1d5b659SRichard Röjfors "%s end of message, nmsgs: %d\n", 438e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 439e1d5b659SRichard Röjfors 440e1d5b659SRichard Röjfors /* send next message if this wasn't the last, 441e1d5b659SRichard Röjfors * otherwise the transfer will be finialise when 442e1d5b659SRichard Röjfors * receiving the bus not busy interrupt 443e1d5b659SRichard Röjfors */ 444e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 445e1d5b659SRichard Röjfors i2c->nmsgs--; 446e1d5b659SRichard Röjfors i2c->tx_msg++; 447e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 448e1d5b659SRichard Röjfors "%s will start next...\n", __func__); 449e1d5b659SRichard Röjfors 450e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 451e1d5b659SRichard Röjfors } 452e1d5b659SRichard Röjfors } 4537f9906bdSShubhrajyoti Datta } 4547f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_BNB_MASK) { 455e1d5b659SRichard Röjfors /* IIC bus has transitioned to not busy */ 4567f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_BNB_MASK; 457e1d5b659SRichard Röjfors 458e1d5b659SRichard Röjfors /* The bus is not busy, disable BusNotBusy interrupt */ 459e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 460e1d5b659SRichard Röjfors 461e1d5b659SRichard Röjfors if (!i2c->tx_msg) 462e1d5b659SRichard Röjfors goto out; 463e1d5b659SRichard Röjfors 464e1d5b659SRichard Röjfors if ((i2c->nmsgs == 1) && !i2c->rx_msg && 465e1d5b659SRichard Röjfors xiic_tx_space(i2c) == 0) 466e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_DONE); 467e1d5b659SRichard Röjfors else 468e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_ERROR); 4697f9906bdSShubhrajyoti Datta } 4707f9906bdSShubhrajyoti Datta if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 471d36b6910SAl Viro /* Transmit register/FIFO is empty or ½ empty */ 472e1d5b659SRichard Röjfors 4737f9906bdSShubhrajyoti Datta clr |= (pend & 4747f9906bdSShubhrajyoti Datta (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 475e1d5b659SRichard Röjfors 476e1d5b659SRichard Röjfors if (!i2c->tx_msg) { 477e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 4781ee7cdbfSColin Ian King "%s unexpected TX IRQ\n", __func__); 479e1d5b659SRichard Röjfors goto out; 480e1d5b659SRichard Röjfors } 481e1d5b659SRichard Röjfors 482e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c); 483e1d5b659SRichard Röjfors 484e1d5b659SRichard Röjfors /* current message sent and there is space in the fifo */ 485e1d5b659SRichard Röjfors if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 486e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 487e1d5b659SRichard Röjfors "%s end of message sent, nmsgs: %d\n", 488e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 489e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 490e1d5b659SRichard Röjfors i2c->nmsgs--; 491e1d5b659SRichard Röjfors i2c->tx_msg++; 492e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 493e1d5b659SRichard Röjfors } else { 494e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 495e1d5b659SRichard Röjfors 496e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 497e1d5b659SRichard Röjfors "%s Got TX IRQ but no more to do...\n", 498e1d5b659SRichard Röjfors __func__); 499e1d5b659SRichard Röjfors } 500e1d5b659SRichard Röjfors } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 501e1d5b659SRichard Röjfors /* current frame is sent and is last, 502e1d5b659SRichard Röjfors * make sure to disable tx half 503e1d5b659SRichard Röjfors */ 504e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 505e1d5b659SRichard Röjfors } 506e1d5b659SRichard Röjfors out: 507e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 508e1d5b659SRichard Röjfors 509e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 51077c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 511fcc2fac6SShubhrajyoti Datta return IRQ_HANDLED; 512e1d5b659SRichard Röjfors } 513e1d5b659SRichard Röjfors 514e1d5b659SRichard Röjfors static int xiic_bus_busy(struct xiic_i2c *i2c) 515e1d5b659SRichard Röjfors { 516e1d5b659SRichard Röjfors u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 517e1d5b659SRichard Röjfors 518e1d5b659SRichard Röjfors return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 519e1d5b659SRichard Röjfors } 520e1d5b659SRichard Röjfors 521e1d5b659SRichard Röjfors static int xiic_busy(struct xiic_i2c *i2c) 522e1d5b659SRichard Röjfors { 523e1d5b659SRichard Röjfors int tries = 3; 524e1d5b659SRichard Röjfors int err; 525e1d5b659SRichard Röjfors 526e1d5b659SRichard Röjfors if (i2c->tx_msg) 527e1d5b659SRichard Röjfors return -EBUSY; 528e1d5b659SRichard Röjfors 529e1d5b659SRichard Röjfors /* for instance if previous transfer was terminated due to TX error 530e1d5b659SRichard Röjfors * it might be that the bus is on it's way to become available 531e1d5b659SRichard Röjfors * give it at most 3 ms to wake 532e1d5b659SRichard Röjfors */ 533e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 534e1d5b659SRichard Röjfors while (err && tries--) { 535b33aa252SShubhrajyoti Datta msleep(1); 536e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 537e1d5b659SRichard Röjfors } 538e1d5b659SRichard Röjfors 539e1d5b659SRichard Röjfors return err; 540e1d5b659SRichard Röjfors } 541e1d5b659SRichard Röjfors 542e1d5b659SRichard Röjfors static void xiic_start_recv(struct xiic_i2c *i2c) 543e1d5b659SRichard Röjfors { 544e1d5b659SRichard Röjfors u8 rx_watermark; 545e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 546ae7304c3SShubhrajyoti Datta unsigned long flags; 547e1d5b659SRichard Röjfors 548e1d5b659SRichard Röjfors /* Clear and enable Rx full interrupt. */ 549e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 550e1d5b659SRichard Röjfors 551e1d5b659SRichard Röjfors /* we want to get all but last byte, because the TX_ERROR IRQ is used 552e1d5b659SRichard Röjfors * to inidicate error ACK on the address, and negative ack on the last 553e1d5b659SRichard Röjfors * received byte, so to not mix them receive all but last. 554e1d5b659SRichard Röjfors * In the case where there is only one byte to receive 555e1d5b659SRichard Röjfors * we can check if ERROR and RX full is set at the same time 556e1d5b659SRichard Röjfors */ 557e1d5b659SRichard Röjfors rx_watermark = msg->len; 558e1d5b659SRichard Röjfors if (rx_watermark > IIC_RX_FIFO_DEPTH) 559e1d5b659SRichard Röjfors rx_watermark = IIC_RX_FIFO_DEPTH; 560e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 561e1d5b659SRichard Röjfors 562ae7304c3SShubhrajyoti Datta local_irq_save(flags); 563e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) 564e1d5b659SRichard Röjfors /* write the address */ 565e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 56630a64757SPeter Rosin i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); 567e1d5b659SRichard Röjfors 568e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 569e1d5b659SRichard Röjfors 570e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 571e1d5b659SRichard Röjfors msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 572ae7304c3SShubhrajyoti Datta local_irq_restore(flags); 573ae7304c3SShubhrajyoti Datta 574e1d5b659SRichard Röjfors if (i2c->nmsgs == 1) 575e1d5b659SRichard Röjfors /* very last, enable bus not busy as well */ 576e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 577e1d5b659SRichard Röjfors 578e1d5b659SRichard Röjfors /* the message is tx:ed */ 579e1d5b659SRichard Röjfors i2c->tx_pos = msg->len; 580e1d5b659SRichard Röjfors } 581e1d5b659SRichard Röjfors 582e1d5b659SRichard Röjfors static void xiic_start_send(struct xiic_i2c *i2c) 583e1d5b659SRichard Röjfors { 584e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->tx_msg; 585e1d5b659SRichard Röjfors 586e1d5b659SRichard Röjfors xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); 587e1d5b659SRichard Röjfors 588f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 589f1e9f89aSKedareswara rao Appana __func__, msg, msg->len); 590f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 591f1e9f89aSKedareswara rao Appana __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 592e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 593e1d5b659SRichard Röjfors 594e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) { 595e1d5b659SRichard Röjfors /* write the address */ 59630a64757SPeter Rosin u16 data = i2c_8bit_addr_from_msg(msg) | 597e1d5b659SRichard Röjfors XIIC_TX_DYN_START_MASK; 598e1d5b659SRichard Röjfors if ((i2c->nmsgs == 1) && msg->len == 0) 599e1d5b659SRichard Röjfors /* no data and last message -> add STOP */ 600e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 601e1d5b659SRichard Röjfors 602e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 603e1d5b659SRichard Röjfors } 604e1d5b659SRichard Röjfors 605e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c); 606e1d5b659SRichard Röjfors 607e1d5b659SRichard Röjfors /* Clear any pending Tx empty, Tx Error and then enable them. */ 608e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 609e1d5b659SRichard Röjfors XIIC_INTR_BNB_MASK); 610e1d5b659SRichard Röjfors } 611e1d5b659SRichard Röjfors 612e1d5b659SRichard Röjfors static irqreturn_t xiic_isr(int irq, void *dev_id) 613e1d5b659SRichard Röjfors { 614e1d5b659SRichard Röjfors struct xiic_i2c *i2c = dev_id; 615fcc2fac6SShubhrajyoti Datta u32 pend, isr, ier; 616fcc2fac6SShubhrajyoti Datta irqreturn_t ret = IRQ_NONE; 617fcc2fac6SShubhrajyoti Datta /* Do not processes a devices interrupts if the device has no 618fcc2fac6SShubhrajyoti Datta * interrupts pending 619fcc2fac6SShubhrajyoti Datta */ 620e1d5b659SRichard Röjfors 621e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); 622e1d5b659SRichard Röjfors 623fcc2fac6SShubhrajyoti Datta isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 624fcc2fac6SShubhrajyoti Datta ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 625fcc2fac6SShubhrajyoti Datta pend = isr & ier; 626fcc2fac6SShubhrajyoti Datta if (pend) 627fcc2fac6SShubhrajyoti Datta ret = IRQ_WAKE_THREAD; 628e1d5b659SRichard Röjfors 629fcc2fac6SShubhrajyoti Datta return ret; 630e1d5b659SRichard Röjfors } 631e1d5b659SRichard Röjfors 632e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c) 633e1d5b659SRichard Röjfors { 634e1d5b659SRichard Röjfors int first = 1; 635e1d5b659SRichard Röjfors int fifo_space = xiic_tx_fifo_space(i2c); 636e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 637e1d5b659SRichard Röjfors __func__, i2c->tx_msg, fifo_space); 638e1d5b659SRichard Röjfors 639e1d5b659SRichard Röjfors if (!i2c->tx_msg) 640e1d5b659SRichard Röjfors return; 641e1d5b659SRichard Röjfors 642e1d5b659SRichard Röjfors i2c->rx_pos = 0; 643e1d5b659SRichard Röjfors i2c->tx_pos = 0; 644e1d5b659SRichard Röjfors i2c->state = STATE_START; 645e1d5b659SRichard Röjfors while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { 646e1d5b659SRichard Röjfors if (!first) { 647e1d5b659SRichard Röjfors i2c->nmsgs--; 648e1d5b659SRichard Röjfors i2c->tx_msg++; 649e1d5b659SRichard Röjfors i2c->tx_pos = 0; 650e1d5b659SRichard Röjfors } else 651e1d5b659SRichard Röjfors first = 0; 652e1d5b659SRichard Röjfors 653e1d5b659SRichard Röjfors if (i2c->tx_msg->flags & I2C_M_RD) { 654e1d5b659SRichard Röjfors /* we dont date putting several reads in the FIFO */ 655e1d5b659SRichard Röjfors xiic_start_recv(i2c); 656e1d5b659SRichard Röjfors return; 657e1d5b659SRichard Röjfors } else { 658e1d5b659SRichard Röjfors xiic_start_send(i2c); 659e1d5b659SRichard Röjfors if (xiic_tx_space(i2c) != 0) { 660e1d5b659SRichard Röjfors /* the message could not be completely sent */ 661e1d5b659SRichard Röjfors break; 662e1d5b659SRichard Röjfors } 663e1d5b659SRichard Röjfors } 664e1d5b659SRichard Röjfors 665e1d5b659SRichard Röjfors fifo_space = xiic_tx_fifo_space(i2c); 666e1d5b659SRichard Röjfors } 667e1d5b659SRichard Röjfors 668e1d5b659SRichard Röjfors /* there are more messages or the current one could not be completely 669e1d5b659SRichard Röjfors * put into the FIFO, also enable the half empty interrupt 670e1d5b659SRichard Röjfors */ 671e1d5b659SRichard Röjfors if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) 672e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); 673e1d5b659SRichard Röjfors 674e1d5b659SRichard Röjfors } 675e1d5b659SRichard Röjfors 676b4c119dbSShubhrajyoti Datta static int xiic_start_xfer(struct xiic_i2c *i2c) 677e1d5b659SRichard Röjfors { 678b4c119dbSShubhrajyoti Datta int ret; 67977c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 680b4c119dbSShubhrajyoti Datta 681b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c); 682b4c119dbSShubhrajyoti Datta if (!ret) 683e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 684b4c119dbSShubhrajyoti Datta 68577c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 686b4c119dbSShubhrajyoti Datta 687b4c119dbSShubhrajyoti Datta return ret; 688e1d5b659SRichard Röjfors } 689e1d5b659SRichard Röjfors 690e1d5b659SRichard Röjfors static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 691e1d5b659SRichard Röjfors { 692e1d5b659SRichard Röjfors struct xiic_i2c *i2c = i2c_get_adapdata(adap); 693e1d5b659SRichard Röjfors int err; 694e1d5b659SRichard Röjfors 695e1d5b659SRichard Röjfors dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 696e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 697e1d5b659SRichard Röjfors 69836ecbcabSShubhrajyoti Datta err = pm_runtime_get_sync(i2c->dev); 69936ecbcabSShubhrajyoti Datta if (err < 0) 70036ecbcabSShubhrajyoti Datta return err; 70136ecbcabSShubhrajyoti Datta 702e1d5b659SRichard Röjfors err = xiic_busy(i2c); 703e1d5b659SRichard Röjfors if (err) 70436ecbcabSShubhrajyoti Datta goto out; 705e1d5b659SRichard Röjfors 706e1d5b659SRichard Röjfors i2c->tx_msg = msgs; 707e1d5b659SRichard Röjfors i2c->nmsgs = num; 708e1d5b659SRichard Röjfors 709b4c119dbSShubhrajyoti Datta err = xiic_start_xfer(i2c); 710b4c119dbSShubhrajyoti Datta if (err < 0) { 711b4c119dbSShubhrajyoti Datta dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 712b4c119dbSShubhrajyoti Datta goto out; 713b4c119dbSShubhrajyoti Datta } 714e1d5b659SRichard Röjfors 715e1d5b659SRichard Röjfors if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 71636ecbcabSShubhrajyoti Datta (i2c->state == STATE_DONE), HZ)) { 71736ecbcabSShubhrajyoti Datta err = (i2c->state == STATE_DONE) ? num : -EIO; 71836ecbcabSShubhrajyoti Datta goto out; 71936ecbcabSShubhrajyoti Datta } else { 720e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 721e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 722e1d5b659SRichard Röjfors i2c->nmsgs = 0; 72336ecbcabSShubhrajyoti Datta err = -ETIMEDOUT; 72436ecbcabSShubhrajyoti Datta goto out; 725e1d5b659SRichard Röjfors } 72636ecbcabSShubhrajyoti Datta out: 72736ecbcabSShubhrajyoti Datta pm_runtime_mark_last_busy(i2c->dev); 72836ecbcabSShubhrajyoti Datta pm_runtime_put_autosuspend(i2c->dev); 72936ecbcabSShubhrajyoti Datta return err; 730e1d5b659SRichard Röjfors } 731e1d5b659SRichard Röjfors 732e1d5b659SRichard Röjfors static u32 xiic_func(struct i2c_adapter *adap) 733e1d5b659SRichard Röjfors { 734e1d5b659SRichard Röjfors return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 735e1d5b659SRichard Röjfors } 736e1d5b659SRichard Röjfors 737e1d5b659SRichard Röjfors static const struct i2c_algorithm xiic_algorithm = { 738e1d5b659SRichard Röjfors .master_xfer = xiic_xfer, 739e1d5b659SRichard Röjfors .functionality = xiic_func, 740e1d5b659SRichard Röjfors }; 741e1d5b659SRichard Röjfors 74249b80958SRobert Hancock static const struct i2c_adapter_quirks xiic_quirks = { 74349b80958SRobert Hancock .max_read_len = 255, 74449b80958SRobert Hancock }; 74549b80958SRobert Hancock 746329430ccSBhumika Goyal static const struct i2c_adapter xiic_adapter = { 747e1d5b659SRichard Röjfors .owner = THIS_MODULE, 748e1d5b659SRichard Röjfors .name = DRIVER_NAME, 7494db5beedSWolfram Sang .class = I2C_CLASS_DEPRECATED, 750e1d5b659SRichard Röjfors .algo = &xiic_algorithm, 75149b80958SRobert Hancock .quirks = &xiic_quirks, 752e1d5b659SRichard Röjfors }; 753e1d5b659SRichard Röjfors 754e1d5b659SRichard Röjfors 7550b255e92SBill Pemberton static int xiic_i2c_probe(struct platform_device *pdev) 756e1d5b659SRichard Röjfors { 757e1d5b659SRichard Röjfors struct xiic_i2c *i2c; 758e1d5b659SRichard Röjfors struct xiic_i2c_platform_data *pdata; 759e1d5b659SRichard Röjfors struct resource *res; 760e1d5b659SRichard Röjfors int ret, irq; 761e1d5b659SRichard Röjfors u8 i; 76248ef3ca9SThomas Gessler u32 sr; 763e1d5b659SRichard Röjfors 764168e722dSKedareswara rao Appana i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 765e1d5b659SRichard Röjfors if (!i2c) 766e1d5b659SRichard Röjfors return -ENOMEM; 767e1d5b659SRichard Röjfors 768168e722dSKedareswara rao Appana res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 769168e722dSKedareswara rao Appana i2c->base = devm_ioremap_resource(&pdev->dev, res); 770168e722dSKedareswara rao Appana if (IS_ERR(i2c->base)) 771168e722dSKedareswara rao Appana return PTR_ERR(i2c->base); 772e1d5b659SRichard Röjfors 773168e722dSKedareswara rao Appana irq = platform_get_irq(pdev, 0); 774168e722dSKedareswara rao Appana if (irq < 0) 775168e722dSKedareswara rao Appana return irq; 776168e722dSKedareswara rao Appana 777168e722dSKedareswara rao Appana pdata = dev_get_platdata(&pdev->dev); 778e1d5b659SRichard Röjfors 779e1d5b659SRichard Röjfors /* hook up driver to tree */ 780e1d5b659SRichard Röjfors platform_set_drvdata(pdev, i2c); 781e1d5b659SRichard Röjfors i2c->adap = xiic_adapter; 782e1d5b659SRichard Röjfors i2c_set_adapdata(&i2c->adap, i2c); 783e1d5b659SRichard Röjfors i2c->adap.dev.parent = &pdev->dev; 7843ac0b337SLars-Peter Clausen i2c->adap.dev.of_node = pdev->dev.of_node; 785e1d5b659SRichard Röjfors 78677c68019SLars-Peter Clausen mutex_init(&i2c->lock); 787e1d5b659SRichard Röjfors init_waitqueue_head(&i2c->wait); 788168e722dSKedareswara rao Appana 78936ecbcabSShubhrajyoti Datta i2c->clk = devm_clk_get(&pdev->dev, NULL); 79036ecbcabSShubhrajyoti Datta if (IS_ERR(i2c->clk)) { 791c9d05968SVenkatesh Yadav Abbarapu if (PTR_ERR(i2c->clk) != -EPROBE_DEFER) 79236ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "input clock not found.\n"); 79336ecbcabSShubhrajyoti Datta return PTR_ERR(i2c->clk); 79436ecbcabSShubhrajyoti Datta } 79536ecbcabSShubhrajyoti Datta ret = clk_prepare_enable(i2c->clk); 79636ecbcabSShubhrajyoti Datta if (ret) { 79736ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "Unable to enable clock.\n"); 79836ecbcabSShubhrajyoti Datta return ret; 79936ecbcabSShubhrajyoti Datta } 80036ecbcabSShubhrajyoti Datta i2c->dev = &pdev->dev; 80136ecbcabSShubhrajyoti Datta pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 80236ecbcabSShubhrajyoti Datta pm_runtime_use_autosuspend(i2c->dev); 80336ecbcabSShubhrajyoti Datta pm_runtime_set_active(i2c->dev); 80410b17004SShubhrajyoti Datta pm_runtime_enable(i2c->dev); 805fcc2fac6SShubhrajyoti Datta ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr, 806fcc2fac6SShubhrajyoti Datta xiic_process, IRQF_ONESHOT, 807fcc2fac6SShubhrajyoti Datta pdev->name, i2c); 808fcc2fac6SShubhrajyoti Datta 809168e722dSKedareswara rao Appana if (ret < 0) { 810e1d5b659SRichard Röjfors dev_err(&pdev->dev, "Cannot claim IRQ\n"); 81136ecbcabSShubhrajyoti Datta goto err_clk_dis; 812e1d5b659SRichard Röjfors } 813e1d5b659SRichard Röjfors 81448ef3ca9SThomas Gessler /* 81548ef3ca9SThomas Gessler * Detect endianness 81648ef3ca9SThomas Gessler * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 81748ef3ca9SThomas Gessler * set, assume that the endianness was wrong and swap. 81848ef3ca9SThomas Gessler */ 81948ef3ca9SThomas Gessler i2c->endianness = LITTLE; 82048ef3ca9SThomas Gessler xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 82148ef3ca9SThomas Gessler /* Reset is cleared in xiic_reinit */ 82248ef3ca9SThomas Gessler sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 82348ef3ca9SThomas Gessler if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 82448ef3ca9SThomas Gessler i2c->endianness = BIG; 82548ef3ca9SThomas Gessler 826b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c); 827b4c119dbSShubhrajyoti Datta if (ret < 0) { 828b4c119dbSShubhrajyoti Datta dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 829b4c119dbSShubhrajyoti Datta goto err_clk_dis; 830b4c119dbSShubhrajyoti Datta } 831617bdcbcSMichal Simek 832e1d5b659SRichard Röjfors /* add i2c adapter to i2c tree */ 833e1d5b659SRichard Röjfors ret = i2c_add_adapter(&i2c->adap); 834e1d5b659SRichard Röjfors if (ret) { 835168e722dSKedareswara rao Appana xiic_deinit(i2c); 83636ecbcabSShubhrajyoti Datta goto err_clk_dis; 837e1d5b659SRichard Röjfors } 838e1d5b659SRichard Röjfors 8393ac0b337SLars-Peter Clausen if (pdata) { 840e1d5b659SRichard Röjfors /* add in known devices to the bus */ 841e1d5b659SRichard Röjfors for (i = 0; i < pdata->num_devices; i++) 842bf255befSWolfram Sang i2c_new_client_device(&i2c->adap, pdata->devices + i); 8433ac0b337SLars-Peter Clausen } 8443ac0b337SLars-Peter Clausen 845e1d5b659SRichard Röjfors return 0; 84636ecbcabSShubhrajyoti Datta 84736ecbcabSShubhrajyoti Datta err_clk_dis: 84836ecbcabSShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 84936ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 85036ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 85136ecbcabSShubhrajyoti Datta return ret; 852e1d5b659SRichard Röjfors } 853e1d5b659SRichard Röjfors 8540b255e92SBill Pemberton static int xiic_i2c_remove(struct platform_device *pdev) 855e1d5b659SRichard Röjfors { 856e1d5b659SRichard Röjfors struct xiic_i2c *i2c = platform_get_drvdata(pdev); 85736ecbcabSShubhrajyoti Datta int ret; 858e1d5b659SRichard Röjfors 859e1d5b659SRichard Röjfors /* remove adapter & data */ 860e1d5b659SRichard Röjfors i2c_del_adapter(&i2c->adap); 861e1d5b659SRichard Röjfors 86210b17004SShubhrajyoti Datta ret = pm_runtime_get_sync(i2c->dev); 86310b17004SShubhrajyoti Datta if (ret < 0) 86436ecbcabSShubhrajyoti Datta return ret; 86510b17004SShubhrajyoti Datta 866e1d5b659SRichard Röjfors xiic_deinit(i2c); 86710b17004SShubhrajyoti Datta pm_runtime_put_sync(i2c->dev); 86836ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 86936ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 87010b17004SShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 87110b17004SShubhrajyoti Datta pm_runtime_dont_use_autosuspend(&pdev->dev); 872e1d5b659SRichard Röjfors 873e1d5b659SRichard Röjfors return 0; 874e1d5b659SRichard Röjfors } 875e1d5b659SRichard Röjfors 8763ac0b337SLars-Peter Clausen #if defined(CONFIG_OF) 8770b255e92SBill Pemberton static const struct of_device_id xiic_of_match[] = { 8783ac0b337SLars-Peter Clausen { .compatible = "xlnx,xps-iic-2.00.a", }, 8793ac0b337SLars-Peter Clausen {}, 8803ac0b337SLars-Peter Clausen }; 8813ac0b337SLars-Peter Clausen MODULE_DEVICE_TABLE(of, xiic_of_match); 8823ac0b337SLars-Peter Clausen #endif 8833ac0b337SLars-Peter Clausen 88474d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 88536ecbcabSShubhrajyoti Datta { 8869242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev); 88736ecbcabSShubhrajyoti Datta 88836ecbcabSShubhrajyoti Datta clk_disable(i2c->clk); 88936ecbcabSShubhrajyoti Datta 89036ecbcabSShubhrajyoti Datta return 0; 89136ecbcabSShubhrajyoti Datta } 89236ecbcabSShubhrajyoti Datta 89374d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 89436ecbcabSShubhrajyoti Datta { 8959242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev); 89636ecbcabSShubhrajyoti Datta int ret; 89736ecbcabSShubhrajyoti Datta 89836ecbcabSShubhrajyoti Datta ret = clk_enable(i2c->clk); 89936ecbcabSShubhrajyoti Datta if (ret) { 90036ecbcabSShubhrajyoti Datta dev_err(dev, "Cannot enable clock.\n"); 90136ecbcabSShubhrajyoti Datta return ret; 90236ecbcabSShubhrajyoti Datta } 90336ecbcabSShubhrajyoti Datta 90436ecbcabSShubhrajyoti Datta return 0; 90536ecbcabSShubhrajyoti Datta } 90636ecbcabSShubhrajyoti Datta 90736ecbcabSShubhrajyoti Datta static const struct dev_pm_ops xiic_dev_pm_ops = { 90874d23319SMoritz Fischer SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 90974d23319SMoritz Fischer xiic_i2c_runtime_resume, NULL) 91036ecbcabSShubhrajyoti Datta }; 911e1d5b659SRichard Röjfors static struct platform_driver xiic_i2c_driver = { 912e1d5b659SRichard Röjfors .probe = xiic_i2c_probe, 9130b255e92SBill Pemberton .remove = xiic_i2c_remove, 914e1d5b659SRichard Röjfors .driver = { 915e1d5b659SRichard Röjfors .name = DRIVER_NAME, 9163ac0b337SLars-Peter Clausen .of_match_table = of_match_ptr(xiic_of_match), 91736ecbcabSShubhrajyoti Datta .pm = &xiic_dev_pm_ops, 918e1d5b659SRichard Röjfors }, 919e1d5b659SRichard Röjfors }; 920e1d5b659SRichard Röjfors 921a3664b51SAxel Lin module_platform_driver(xiic_i2c_driver); 922e1d5b659SRichard Röjfors 923e1d5b659SRichard Röjfors MODULE_AUTHOR("info@mocean-labs.com"); 924e1d5b659SRichard Röjfors MODULE_DESCRIPTION("Xilinx I2C bus driver"); 925e1d5b659SRichard Röjfors MODULE_LICENSE("GPL v2"); 926a3664b51SAxel Lin MODULE_ALIAS("platform:"DRIVER_NAME); 927