11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2e1d5b659SRichard Röjfors /* 3e1d5b659SRichard Röjfors * i2c-xiic.c 4e1d5b659SRichard Röjfors * Copyright (c) 2002-2007 Xilinx Inc. 5e1d5b659SRichard Röjfors * Copyright (c) 2009-2010 Intel Corporation 6e1d5b659SRichard Röjfors * 7e1d5b659SRichard Röjfors * This code was implemented by Mocean Laboratories AB when porting linux 8e1d5b659SRichard Röjfors * to the automotive development board Russellville. The copyright holder 9e1d5b659SRichard Röjfors * as seen in the header is Intel corporation. 10e1d5b659SRichard Röjfors * Mocean Laboratories forked off the GNU/Linux platform work into a 1125985edcSLucas De Marchi * separate company called Pelagicore AB, which committed the code to the 12e1d5b659SRichard Röjfors * kernel. 13e1d5b659SRichard Röjfors */ 14e1d5b659SRichard Röjfors 15e1d5b659SRichard Röjfors /* Supports: 16e1d5b659SRichard Röjfors * Xilinx IIC 17e1d5b659SRichard Röjfors */ 18e1d5b659SRichard Röjfors #include <linux/kernel.h> 19e1d5b659SRichard Röjfors #include <linux/module.h> 20e1d5b659SRichard Röjfors #include <linux/errno.h> 21168e722dSKedareswara rao Appana #include <linux/err.h> 2202ca6c40SRandy Dunlap #include <linux/delay.h> 23e1d5b659SRichard Röjfors #include <linux/platform_device.h> 24e1d5b659SRichard Röjfors #include <linux/i2c.h> 25e1d5b659SRichard Röjfors #include <linux/interrupt.h> 26fdacc3c7SMarek Vasut #include <linux/completion.h> 277072b75cSWolfram Sang #include <linux/platform_data/i2c-xiic.h> 28e1d5b659SRichard Röjfors #include <linux/io.h> 295a0e3ad6STejun Heo #include <linux/slab.h> 304edd65e6SSachin Kamat #include <linux/of.h> 3136ecbcabSShubhrajyoti Datta #include <linux/clk.h> 3236ecbcabSShubhrajyoti Datta #include <linux/pm_runtime.h> 33e1d5b659SRichard Röjfors 34e1d5b659SRichard Röjfors #define DRIVER_NAME "xiic-i2c" 35e1d5b659SRichard Röjfors 36e1d5b659SRichard Röjfors enum xilinx_i2c_state { 37e1d5b659SRichard Röjfors STATE_DONE, 38e1d5b659SRichard Röjfors STATE_ERROR, 39e1d5b659SRichard Röjfors STATE_START 40e1d5b659SRichard Röjfors }; 41e1d5b659SRichard Röjfors 4248ef3ca9SThomas Gessler enum xiic_endian { 4348ef3ca9SThomas Gessler LITTLE, 4448ef3ca9SThomas Gessler BIG 4548ef3ca9SThomas Gessler }; 4648ef3ca9SThomas Gessler 47e1d5b659SRichard Röjfors /** 48e1d5b659SRichard Röjfors * struct xiic_i2c - Internal representation of the XIIC I2C bus 49bcc156e2SShubhrajyoti Datta * @dev: Pointer to device structure 50e1d5b659SRichard Röjfors * @base: Memory base of the HW registers 51fdacc3c7SMarek Vasut * @completion: Completion for callers 52e1d5b659SRichard Röjfors * @adap: Kernel adapter representation 53e1d5b659SRichard Röjfors * @tx_msg: Messages from above to be sent 54e1d5b659SRichard Röjfors * @lock: Mutual exclusion 55e1d5b659SRichard Röjfors * @tx_pos: Current pos in TX message 56e1d5b659SRichard Röjfors * @nmsgs: Number of messages in tx_msg 57e1d5b659SRichard Röjfors * @rx_msg: Current RX message 58e1d5b659SRichard Röjfors * @rx_pos: Position within current RX message 59bea6ff02SShubhrajyoti Datta * @endianness: big/little-endian byte order 60bcc156e2SShubhrajyoti Datta * @clk: Pointer to AXI4-lite input clock 619106e45cSJaakko Laine * @state: See STATE_ 629e3b184bSJaakko Laine * @singlemaster: Indicates bus is single master 63e1d5b659SRichard Röjfors */ 64e1d5b659SRichard Röjfors struct xiic_i2c { 6536ecbcabSShubhrajyoti Datta struct device *dev; 66e1d5b659SRichard Röjfors void __iomem *base; 67fdacc3c7SMarek Vasut struct completion completion; 68e1d5b659SRichard Röjfors struct i2c_adapter adap; 69e1d5b659SRichard Röjfors struct i2c_msg *tx_msg; 7077c68019SLars-Peter Clausen struct mutex lock; 71e1d5b659SRichard Röjfors unsigned int tx_pos; 72e1d5b659SRichard Röjfors unsigned int nmsgs; 73e1d5b659SRichard Röjfors struct i2c_msg *rx_msg; 74e1d5b659SRichard Röjfors int rx_pos; 7548ef3ca9SThomas Gessler enum xiic_endian endianness; 7636ecbcabSShubhrajyoti Datta struct clk *clk; 779106e45cSJaakko Laine enum xilinx_i2c_state state; 789e3b184bSJaakko Laine bool singlemaster; 79e1d5b659SRichard Röjfors }; 80e1d5b659SRichard Röjfors 81e1d5b659SRichard Röjfors 82e1d5b659SRichard Röjfors #define XIIC_MSB_OFFSET 0 83e1d5b659SRichard Röjfors #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 84e1d5b659SRichard Röjfors 85e1d5b659SRichard Röjfors /* 86e1d5b659SRichard Röjfors * Register offsets in bytes from RegisterBase. Three is added to the 87e1d5b659SRichard Röjfors * base offset to access LSB (IBM style) of the word 88e1d5b659SRichard Röjfors */ 89e1d5b659SRichard Röjfors #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 90e1d5b659SRichard Röjfors #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 91e1d5b659SRichard Röjfors #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 92e1d5b659SRichard Röjfors #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 93e1d5b659SRichard Röjfors #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 94e1d5b659SRichard Röjfors #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 95e1d5b659SRichard Röjfors #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 96e1d5b659SRichard Röjfors #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 97e1d5b659SRichard Röjfors #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 98e1d5b659SRichard Röjfors #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 99e1d5b659SRichard Röjfors 100e1d5b659SRichard Röjfors /* Control Register masks */ 101e1d5b659SRichard Röjfors #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 102e1d5b659SRichard Röjfors #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 103e1d5b659SRichard Röjfors #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 104e1d5b659SRichard Röjfors #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 105e1d5b659SRichard Röjfors #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 106e1d5b659SRichard Röjfors #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 107e1d5b659SRichard Röjfors #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 108e1d5b659SRichard Röjfors 109e1d5b659SRichard Röjfors /* Status Register masks */ 110e1d5b659SRichard Röjfors #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 111e1d5b659SRichard Röjfors #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 112e1d5b659SRichard Röjfors #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 113e1d5b659SRichard Röjfors #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 114e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 115e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 116e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 117e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 118e1d5b659SRichard Röjfors 119e1d5b659SRichard Röjfors /* Interrupt Status Register masks Interrupt occurs when... */ 120e1d5b659SRichard Röjfors #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 121e1d5b659SRichard Röjfors #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 122e1d5b659SRichard Röjfors #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 123e1d5b659SRichard Röjfors #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 124e1d5b659SRichard Röjfors #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 125e1d5b659SRichard Röjfors #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 126e1d5b659SRichard Röjfors #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 127e1d5b659SRichard Röjfors #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 128e1d5b659SRichard Röjfors 129e1d5b659SRichard Röjfors /* The following constants specify the depth of the FIFOs */ 130e1d5b659SRichard Röjfors #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 131e1d5b659SRichard Röjfors #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 132e1d5b659SRichard Röjfors 133e1d5b659SRichard Röjfors /* The following constants specify groups of interrupts that are typically 134e1d5b659SRichard Röjfors * enabled or disables at the same time 135e1d5b659SRichard Röjfors */ 136e1d5b659SRichard Röjfors #define XIIC_TX_INTERRUPTS \ 137e1d5b659SRichard Röjfors (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 138e1d5b659SRichard Röjfors 139e1d5b659SRichard Röjfors #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 140e1d5b659SRichard Röjfors 141e1d5b659SRichard Röjfors /* 142e1d5b659SRichard Röjfors * Tx Fifo upper bit masks. 143e1d5b659SRichard Röjfors */ 144e1d5b659SRichard Röjfors #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 145e1d5b659SRichard Röjfors #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 146e1d5b659SRichard Röjfors 147e1d5b659SRichard Röjfors /* 148e1d5b659SRichard Röjfors * The following constants define the register offsets for the Interrupt 149e1d5b659SRichard Röjfors * registers. There are some holes in the memory map for reserved addresses 150e1d5b659SRichard Röjfors * to allow other registers to be added and still match the memory map of the 151e1d5b659SRichard Röjfors * interrupt controller registers 152e1d5b659SRichard Röjfors */ 153e1d5b659SRichard Röjfors #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 154e1d5b659SRichard Röjfors #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 155e1d5b659SRichard Röjfors #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 156e1d5b659SRichard Röjfors #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 157e1d5b659SRichard Röjfors 158e1d5b659SRichard Röjfors #define XIIC_RESET_MASK 0xAUL 159e1d5b659SRichard Röjfors 16036ecbcabSShubhrajyoti Datta #define XIIC_PM_TIMEOUT 1000 /* ms */ 161b4c119dbSShubhrajyoti Datta /* timeout waiting for the controller to respond */ 162b4c119dbSShubhrajyoti Datta #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 163fdacc3c7SMarek Vasut /* timeout waiting for the controller finish transfers */ 164fdacc3c7SMarek Vasut #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 165fdacc3c7SMarek Vasut 166e1d5b659SRichard Röjfors /* 167e1d5b659SRichard Röjfors * The following constant is used for the device global interrupt enable 168e1d5b659SRichard Röjfors * register, to enable all interrupts for the device, this is the only bit 169e1d5b659SRichard Röjfors * in the register 170e1d5b659SRichard Röjfors */ 171e1d5b659SRichard Röjfors #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 172e1d5b659SRichard Röjfors 173e1d5b659SRichard Röjfors #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 174e1d5b659SRichard Röjfors #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 175e1d5b659SRichard Röjfors 176c119e7d0SMarek Vasut static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 177e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c); 178e1d5b659SRichard Röjfors 17948ef3ca9SThomas Gessler /* 18048ef3ca9SThomas Gessler * For the register read and write functions, a little-endian and big-endian 18148ef3ca9SThomas Gessler * version are necessary. Endianness is detected during the probe function. 18248ef3ca9SThomas Gessler * Only the least significant byte [doublet] of the register are ever 18348ef3ca9SThomas Gessler * accessed. This requires an offset of 3 [2] from the base address for 18448ef3ca9SThomas Gessler * big-endian systems. 18548ef3ca9SThomas Gessler */ 18648ef3ca9SThomas Gessler 187e1d5b659SRichard Röjfors static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 188e1d5b659SRichard Röjfors { 18948ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 190e1d5b659SRichard Röjfors iowrite8(value, i2c->base + reg); 19148ef3ca9SThomas Gessler else 19248ef3ca9SThomas Gessler iowrite8(value, i2c->base + reg + 3); 193e1d5b659SRichard Röjfors } 194e1d5b659SRichard Röjfors 195e1d5b659SRichard Röjfors static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 196e1d5b659SRichard Röjfors { 19748ef3ca9SThomas Gessler u8 ret; 19848ef3ca9SThomas Gessler 19948ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 20048ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg); 20148ef3ca9SThomas Gessler else 20248ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg + 3); 20348ef3ca9SThomas Gessler return ret; 204e1d5b659SRichard Röjfors } 205e1d5b659SRichard Röjfors 206e1d5b659SRichard Röjfors static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 207e1d5b659SRichard Röjfors { 20848ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 209e1d5b659SRichard Röjfors iowrite16(value, i2c->base + reg); 21048ef3ca9SThomas Gessler else 21148ef3ca9SThomas Gessler iowrite16be(value, i2c->base + reg + 2); 212e1d5b659SRichard Röjfors } 213e1d5b659SRichard Röjfors 214e1d5b659SRichard Röjfors static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 215e1d5b659SRichard Röjfors { 21648ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 217e1d5b659SRichard Röjfors iowrite32(value, i2c->base + reg); 21848ef3ca9SThomas Gessler else 21948ef3ca9SThomas Gessler iowrite32be(value, i2c->base + reg); 220e1d5b659SRichard Röjfors } 221e1d5b659SRichard Röjfors 222e1d5b659SRichard Röjfors static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 223e1d5b659SRichard Röjfors { 22448ef3ca9SThomas Gessler u32 ret; 22548ef3ca9SThomas Gessler 22648ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 22748ef3ca9SThomas Gessler ret = ioread32(i2c->base + reg); 22848ef3ca9SThomas Gessler else 22948ef3ca9SThomas Gessler ret = ioread32be(i2c->base + reg); 23048ef3ca9SThomas Gessler return ret; 231e1d5b659SRichard Röjfors } 232e1d5b659SRichard Röjfors 233e1d5b659SRichard Röjfors static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 234e1d5b659SRichard Röjfors { 235e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 236e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 237e1d5b659SRichard Röjfors } 238e1d5b659SRichard Röjfors 239e1d5b659SRichard Röjfors static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 240e1d5b659SRichard Röjfors { 241e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 242e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 243e1d5b659SRichard Röjfors } 244e1d5b659SRichard Röjfors 245e1d5b659SRichard Röjfors static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 246e1d5b659SRichard Röjfors { 247e1d5b659SRichard Röjfors u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 248e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 249e1d5b659SRichard Röjfors } 250e1d5b659SRichard Röjfors 251e1d5b659SRichard Röjfors static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 252e1d5b659SRichard Röjfors { 253e1d5b659SRichard Röjfors xiic_irq_clr(i2c, mask); 254e1d5b659SRichard Röjfors xiic_irq_en(i2c, mask); 255e1d5b659SRichard Röjfors } 256e1d5b659SRichard Röjfors 257b4c119dbSShubhrajyoti Datta static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 258e1d5b659SRichard Röjfors { 259e1d5b659SRichard Röjfors u8 sr; 260b4c119dbSShubhrajyoti Datta unsigned long timeout; 261b4c119dbSShubhrajyoti Datta 262b4c119dbSShubhrajyoti Datta timeout = jiffies + XIIC_I2C_TIMEOUT; 263e1d5b659SRichard Röjfors for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 264e1d5b659SRichard Röjfors !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 265b4c119dbSShubhrajyoti Datta sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 266e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 267b4c119dbSShubhrajyoti Datta if (time_after(jiffies, timeout)) { 268b4c119dbSShubhrajyoti Datta dev_err(i2c->dev, "Failed to clear rx fifo\n"); 269b4c119dbSShubhrajyoti Datta return -ETIMEDOUT; 270b4c119dbSShubhrajyoti Datta } 271e1d5b659SRichard Röjfors } 272e1d5b659SRichard Röjfors 273b4c119dbSShubhrajyoti Datta return 0; 274b4c119dbSShubhrajyoti Datta } 275b4c119dbSShubhrajyoti Datta 276b4c119dbSShubhrajyoti Datta static int xiic_reinit(struct xiic_i2c *i2c) 277e1d5b659SRichard Röjfors { 278b4c119dbSShubhrajyoti Datta int ret; 279b4c119dbSShubhrajyoti Datta 280e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 281e1d5b659SRichard Röjfors 282e1d5b659SRichard Röjfors /* Set receive Fifo depth to maximum (zero based). */ 283e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 284e1d5b659SRichard Röjfors 285e1d5b659SRichard Röjfors /* Reset Tx Fifo. */ 286e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 287e1d5b659SRichard Röjfors 288e1d5b659SRichard Röjfors /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 289e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 290e1d5b659SRichard Röjfors 291e1d5b659SRichard Röjfors /* make sure RX fifo is empty */ 292b4c119dbSShubhrajyoti Datta ret = xiic_clear_rx_fifo(i2c); 293b4c119dbSShubhrajyoti Datta if (ret) 294b4c119dbSShubhrajyoti Datta return ret; 295e1d5b659SRichard Röjfors 296e1d5b659SRichard Röjfors /* Enable interrupts */ 297e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 298e1d5b659SRichard Röjfors 299542e2a9bSShubhrajyoti Datta xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 300b4c119dbSShubhrajyoti Datta 301b4c119dbSShubhrajyoti Datta return 0; 302e1d5b659SRichard Röjfors } 303e1d5b659SRichard Röjfors 304e1d5b659SRichard Röjfors static void xiic_deinit(struct xiic_i2c *i2c) 305e1d5b659SRichard Röjfors { 306e1d5b659SRichard Röjfors u8 cr; 307e1d5b659SRichard Röjfors 308e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 309e1d5b659SRichard Röjfors 310e1d5b659SRichard Röjfors /* Disable IIC Device. */ 311e1d5b659SRichard Röjfors cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 312e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 313e1d5b659SRichard Röjfors } 314e1d5b659SRichard Röjfors 315e1d5b659SRichard Röjfors static void xiic_read_rx(struct xiic_i2c *i2c) 316e1d5b659SRichard Röjfors { 317e1d5b659SRichard Röjfors u8 bytes_in_fifo; 318e1d5b659SRichard Röjfors int i; 319e1d5b659SRichard Röjfors 320e1d5b659SRichard Röjfors bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 321e1d5b659SRichard Röjfors 322f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, 323f1e9f89aSKedareswara rao Appana "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 324e1d5b659SRichard Röjfors __func__, bytes_in_fifo, xiic_rx_space(i2c), 325e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 326e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 327e1d5b659SRichard Röjfors 328e1d5b659SRichard Röjfors if (bytes_in_fifo > xiic_rx_space(i2c)) 329e1d5b659SRichard Röjfors bytes_in_fifo = xiic_rx_space(i2c); 330e1d5b659SRichard Röjfors 331e1d5b659SRichard Röjfors for (i = 0; i < bytes_in_fifo; i++) 332e1d5b659SRichard Röjfors i2c->rx_msg->buf[i2c->rx_pos++] = 333e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 334e1d5b659SRichard Röjfors 335e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 336e1d5b659SRichard Röjfors (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 337e1d5b659SRichard Röjfors IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 338e1d5b659SRichard Röjfors } 339e1d5b659SRichard Röjfors 340e1d5b659SRichard Röjfors static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 341e1d5b659SRichard Röjfors { 342e1d5b659SRichard Röjfors /* return the actual space left in the FIFO */ 343e1d5b659SRichard Röjfors return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 344e1d5b659SRichard Röjfors } 345e1d5b659SRichard Röjfors 346e1d5b659SRichard Röjfors static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 347e1d5b659SRichard Röjfors { 348e1d5b659SRichard Röjfors u8 fifo_space = xiic_tx_fifo_space(i2c); 349e1d5b659SRichard Röjfors int len = xiic_tx_space(i2c); 350e1d5b659SRichard Röjfors 351e1d5b659SRichard Röjfors len = (len > fifo_space) ? fifo_space : len; 352e1d5b659SRichard Röjfors 353e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 354e1d5b659SRichard Röjfors __func__, len, fifo_space); 355e1d5b659SRichard Röjfors 356e1d5b659SRichard Röjfors while (len--) { 357e1d5b659SRichard Röjfors u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 358e1d5b659SRichard Röjfors if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 359e1d5b659SRichard Röjfors /* last message in transfer -> STOP */ 360e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 361e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 362c39e8e43SSteven A. Falco } 363e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 364e1d5b659SRichard Röjfors } 365e1d5b659SRichard Röjfors } 366e1d5b659SRichard Röjfors 367e1d5b659SRichard Röjfors static void xiic_wakeup(struct xiic_i2c *i2c, int code) 368e1d5b659SRichard Röjfors { 369e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 370e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 371e1d5b659SRichard Röjfors i2c->nmsgs = 0; 372e1d5b659SRichard Röjfors i2c->state = code; 373fdacc3c7SMarek Vasut complete(&i2c->completion); 374e1d5b659SRichard Röjfors } 375e1d5b659SRichard Röjfors 376fcc2fac6SShubhrajyoti Datta static irqreturn_t xiic_process(int irq, void *dev_id) 377e1d5b659SRichard Röjfors { 378fcc2fac6SShubhrajyoti Datta struct xiic_i2c *i2c = dev_id; 379e1d5b659SRichard Röjfors u32 pend, isr, ier; 380e1d5b659SRichard Röjfors u32 clr = 0; 381743e227aSMarek Vasut int xfer_more = 0; 382743e227aSMarek Vasut int wakeup_req = 0; 383743e227aSMarek Vasut int wakeup_code = 0; 384*8fa9c938SShubhrajyoti Datta int ret; 385e1d5b659SRichard Röjfors 386e1d5b659SRichard Röjfors /* Get the interrupt Status from the IPIF. There is no clearing of 387e1d5b659SRichard Röjfors * interrupts in the IPIF. Interrupts must be cleared at the source. 388e1d5b659SRichard Röjfors * To find which interrupts are pending; AND interrupts pending with 389e1d5b659SRichard Röjfors * interrupts masked. 390e1d5b659SRichard Röjfors */ 39177c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 392e1d5b659SRichard Röjfors isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 393e1d5b659SRichard Röjfors ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 394e1d5b659SRichard Röjfors pend = isr & ier; 395e1d5b659SRichard Röjfors 396f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 397f1e9f89aSKedareswara rao Appana __func__, ier, isr, pend); 398f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 399f1e9f89aSKedareswara rao Appana __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 400e1d5b659SRichard Röjfors i2c->tx_msg, i2c->nmsgs); 401e1d5b659SRichard Röjfors 402e1d5b659SRichard Röjfors 403e1d5b659SRichard Röjfors /* Service requesting interrupt */ 404e1d5b659SRichard Röjfors if ((pend & XIIC_INTR_ARB_LOST_MASK) || 405e1d5b659SRichard Röjfors ((pend & XIIC_INTR_TX_ERROR_MASK) && 406e1d5b659SRichard Röjfors !(pend & XIIC_INTR_RX_FULL_MASK))) { 407e1d5b659SRichard Röjfors /* bus arbritration lost, or... 408e1d5b659SRichard Röjfors * Transmit error _OR_ RX completed 409e1d5b659SRichard Röjfors * if this happens when RX_FULL is not set 410e1d5b659SRichard Röjfors * this is probably a TX error 411e1d5b659SRichard Röjfors */ 412e1d5b659SRichard Röjfors 413e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 414e1d5b659SRichard Röjfors 415e1d5b659SRichard Röjfors /* dynamic mode seem to suffer from problems if we just flushes 416e1d5b659SRichard Röjfors * fifos and the next message is a TX with len 0 (only addr) 417e1d5b659SRichard Röjfors * reset the IP instead of just flush fifos 418e1d5b659SRichard Röjfors */ 419*8fa9c938SShubhrajyoti Datta ret = xiic_reinit(i2c); 420*8fa9c938SShubhrajyoti Datta if (!ret) 421*8fa9c938SShubhrajyoti Datta dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); 422e1d5b659SRichard Röjfors 423743e227aSMarek Vasut if (i2c->rx_msg) { 424743e227aSMarek Vasut wakeup_req = 1; 425743e227aSMarek Vasut wakeup_code = STATE_ERROR; 426743e227aSMarek Vasut } 427743e227aSMarek Vasut if (i2c->tx_msg) { 428743e227aSMarek Vasut wakeup_req = 1; 429743e227aSMarek Vasut wakeup_code = STATE_ERROR; 430743e227aSMarek Vasut } 4317f9906bdSShubhrajyoti Datta } 4327f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_RX_FULL_MASK) { 433e1d5b659SRichard Röjfors /* Receive register/FIFO is full */ 434e1d5b659SRichard Röjfors 4357f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_RX_FULL_MASK; 436e1d5b659SRichard Röjfors if (!i2c->rx_msg) { 437e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 4381ee7cdbfSColin Ian King "%s unexpected RX IRQ\n", __func__); 439e1d5b659SRichard Röjfors xiic_clear_rx_fifo(i2c); 440e1d5b659SRichard Röjfors goto out; 441e1d5b659SRichard Röjfors } 442e1d5b659SRichard Röjfors 443e1d5b659SRichard Röjfors xiic_read_rx(i2c); 444e1d5b659SRichard Röjfors if (xiic_rx_space(i2c) == 0) { 445e1d5b659SRichard Röjfors /* this is the last part of the message */ 446e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 447e1d5b659SRichard Röjfors 448e1d5b659SRichard Röjfors /* also clear TX error if there (RX complete) */ 449e1d5b659SRichard Röjfors clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 450e1d5b659SRichard Röjfors 451e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 452e1d5b659SRichard Röjfors "%s end of message, nmsgs: %d\n", 453e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 454e1d5b659SRichard Röjfors 455e1d5b659SRichard Röjfors /* send next message if this wasn't the last, 456e1d5b659SRichard Röjfors * otherwise the transfer will be finialise when 457e1d5b659SRichard Röjfors * receiving the bus not busy interrupt 458e1d5b659SRichard Röjfors */ 459e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 460e1d5b659SRichard Röjfors i2c->nmsgs--; 461e1d5b659SRichard Röjfors i2c->tx_msg++; 462e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 463e1d5b659SRichard Röjfors "%s will start next...\n", __func__); 464743e227aSMarek Vasut xfer_more = 1; 465e1d5b659SRichard Röjfors } 466e1d5b659SRichard Röjfors } 4677f9906bdSShubhrajyoti Datta } 4687f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_BNB_MASK) { 469e1d5b659SRichard Röjfors /* IIC bus has transitioned to not busy */ 4707f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_BNB_MASK; 471e1d5b659SRichard Röjfors 472e1d5b659SRichard Röjfors /* The bus is not busy, disable BusNotBusy interrupt */ 473e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 474e1d5b659SRichard Röjfors 475e1d5b659SRichard Röjfors if (!i2c->tx_msg) 476e1d5b659SRichard Röjfors goto out; 477e1d5b659SRichard Röjfors 478743e227aSMarek Vasut wakeup_req = 1; 479743e227aSMarek Vasut 480743e227aSMarek Vasut if (i2c->nmsgs == 1 && !i2c->rx_msg && 481e1d5b659SRichard Röjfors xiic_tx_space(i2c) == 0) 482743e227aSMarek Vasut wakeup_code = STATE_DONE; 483e1d5b659SRichard Röjfors else 484743e227aSMarek Vasut wakeup_code = STATE_ERROR; 4857f9906bdSShubhrajyoti Datta } 4867f9906bdSShubhrajyoti Datta if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 487d36b6910SAl Viro /* Transmit register/FIFO is empty or ½ empty */ 488e1d5b659SRichard Röjfors 4897f9906bdSShubhrajyoti Datta clr |= (pend & 4907f9906bdSShubhrajyoti Datta (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 491e1d5b659SRichard Röjfors 492e1d5b659SRichard Röjfors if (!i2c->tx_msg) { 493e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 4941ee7cdbfSColin Ian King "%s unexpected TX IRQ\n", __func__); 495e1d5b659SRichard Röjfors goto out; 496e1d5b659SRichard Röjfors } 497e1d5b659SRichard Röjfors 498e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c); 499e1d5b659SRichard Röjfors 500e1d5b659SRichard Röjfors /* current message sent and there is space in the fifo */ 501e1d5b659SRichard Röjfors if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 502e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 503e1d5b659SRichard Röjfors "%s end of message sent, nmsgs: %d\n", 504e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 505e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 506e1d5b659SRichard Röjfors i2c->nmsgs--; 507e1d5b659SRichard Röjfors i2c->tx_msg++; 508743e227aSMarek Vasut xfer_more = 1; 509e1d5b659SRichard Röjfors } else { 510e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 511e1d5b659SRichard Röjfors 512e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 513e1d5b659SRichard Röjfors "%s Got TX IRQ but no more to do...\n", 514e1d5b659SRichard Röjfors __func__); 515e1d5b659SRichard Röjfors } 516e1d5b659SRichard Röjfors } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 517e1d5b659SRichard Röjfors /* current frame is sent and is last, 518e1d5b659SRichard Röjfors * make sure to disable tx half 519e1d5b659SRichard Röjfors */ 520e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 521e1d5b659SRichard Röjfors } 522e1d5b659SRichard Röjfors out: 523e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 524e1d5b659SRichard Röjfors 525e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 526743e227aSMarek Vasut if (xfer_more) 527743e227aSMarek Vasut __xiic_start_xfer(i2c); 528743e227aSMarek Vasut if (wakeup_req) 529743e227aSMarek Vasut xiic_wakeup(i2c, wakeup_code); 530743e227aSMarek Vasut 531743e227aSMarek Vasut WARN_ON(xfer_more && wakeup_req); 532743e227aSMarek Vasut 53377c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 534fcc2fac6SShubhrajyoti Datta return IRQ_HANDLED; 535e1d5b659SRichard Röjfors } 536e1d5b659SRichard Röjfors 537e1d5b659SRichard Röjfors static int xiic_bus_busy(struct xiic_i2c *i2c) 538e1d5b659SRichard Röjfors { 539e1d5b659SRichard Röjfors u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 540e1d5b659SRichard Röjfors 541e1d5b659SRichard Röjfors return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 542e1d5b659SRichard Röjfors } 543e1d5b659SRichard Röjfors 544e1d5b659SRichard Röjfors static int xiic_busy(struct xiic_i2c *i2c) 545e1d5b659SRichard Röjfors { 546e1d5b659SRichard Röjfors int tries = 3; 547e1d5b659SRichard Röjfors int err; 548e1d5b659SRichard Röjfors 549294b29f1SMarek Vasut if (i2c->tx_msg || i2c->rx_msg) 550e1d5b659SRichard Röjfors return -EBUSY; 551e1d5b659SRichard Röjfors 5529e3b184bSJaakko Laine /* In single master mode bus can only be busy, when in use by this 5539e3b184bSJaakko Laine * driver. If the register indicates bus being busy for some reason we 5549e3b184bSJaakko Laine * should ignore it, since bus will never be released and i2c will be 5559e3b184bSJaakko Laine * stuck forever. 5569e3b184bSJaakko Laine */ 5579e3b184bSJaakko Laine if (i2c->singlemaster) { 5589e3b184bSJaakko Laine return 0; 5599e3b184bSJaakko Laine } 5609e3b184bSJaakko Laine 561e1d5b659SRichard Röjfors /* for instance if previous transfer was terminated due to TX error 562e1d5b659SRichard Röjfors * it might be that the bus is on it's way to become available 563e1d5b659SRichard Röjfors * give it at most 3 ms to wake 564e1d5b659SRichard Röjfors */ 565e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 566e1d5b659SRichard Röjfors while (err && tries--) { 567b33aa252SShubhrajyoti Datta msleep(1); 568e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 569e1d5b659SRichard Röjfors } 570e1d5b659SRichard Röjfors 571e1d5b659SRichard Röjfors return err; 572e1d5b659SRichard Röjfors } 573e1d5b659SRichard Röjfors 574e1d5b659SRichard Röjfors static void xiic_start_recv(struct xiic_i2c *i2c) 575e1d5b659SRichard Röjfors { 576e1d5b659SRichard Röjfors u8 rx_watermark; 577e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 578e1d5b659SRichard Röjfors 579e1d5b659SRichard Röjfors /* Clear and enable Rx full interrupt. */ 580e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 581e1d5b659SRichard Röjfors 582e1d5b659SRichard Röjfors /* we want to get all but last byte, because the TX_ERROR IRQ is used 583e1d5b659SRichard Röjfors * to inidicate error ACK on the address, and negative ack on the last 584e1d5b659SRichard Röjfors * received byte, so to not mix them receive all but last. 585e1d5b659SRichard Röjfors * In the case where there is only one byte to receive 586e1d5b659SRichard Röjfors * we can check if ERROR and RX full is set at the same time 587e1d5b659SRichard Röjfors */ 588e1d5b659SRichard Röjfors rx_watermark = msg->len; 589e1d5b659SRichard Röjfors if (rx_watermark > IIC_RX_FIFO_DEPTH) 590e1d5b659SRichard Röjfors rx_watermark = IIC_RX_FIFO_DEPTH; 591e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 592e1d5b659SRichard Röjfors 593e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) 594e1d5b659SRichard Röjfors /* write the address */ 595e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 59630a64757SPeter Rosin i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); 597e1d5b659SRichard Röjfors 598e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 599e1d5b659SRichard Röjfors 600e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 601e1d5b659SRichard Röjfors msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 602ae7304c3SShubhrajyoti Datta 603e1d5b659SRichard Röjfors if (i2c->nmsgs == 1) 604e1d5b659SRichard Röjfors /* very last, enable bus not busy as well */ 605e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 606e1d5b659SRichard Röjfors 607e1d5b659SRichard Röjfors /* the message is tx:ed */ 608e1d5b659SRichard Röjfors i2c->tx_pos = msg->len; 609e1d5b659SRichard Röjfors } 610e1d5b659SRichard Röjfors 611e1d5b659SRichard Röjfors static void xiic_start_send(struct xiic_i2c *i2c) 612e1d5b659SRichard Röjfors { 613e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->tx_msg; 614e1d5b659SRichard Röjfors 615f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 616f1e9f89aSKedareswara rao Appana __func__, msg, msg->len); 617f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 618f1e9f89aSKedareswara rao Appana __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 619e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 620e1d5b659SRichard Röjfors 621e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) { 622e1d5b659SRichard Röjfors /* write the address */ 62330a64757SPeter Rosin u16 data = i2c_8bit_addr_from_msg(msg) | 624e1d5b659SRichard Röjfors XIIC_TX_DYN_START_MASK; 625e1d5b659SRichard Röjfors if ((i2c->nmsgs == 1) && msg->len == 0) 626e1d5b659SRichard Röjfors /* no data and last message -> add STOP */ 627e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 628e1d5b659SRichard Röjfors 629e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 630e1d5b659SRichard Röjfors } 631e1d5b659SRichard Röjfors 632e1d5b659SRichard Röjfors /* Clear any pending Tx empty, Tx Error and then enable them. */ 633e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 634d12e4bbbSMarek Vasut XIIC_INTR_BNB_MASK | 635d12e4bbbSMarek Vasut ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? 636d12e4bbbSMarek Vasut XIIC_INTR_TX_HALF_MASK : 0)); 637d12e4bbbSMarek Vasut 638d12e4bbbSMarek Vasut xiic_fill_tx_fifo(i2c); 639e1d5b659SRichard Röjfors } 640e1d5b659SRichard Röjfors 641e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c) 642e1d5b659SRichard Röjfors { 643e1d5b659SRichard Röjfors int fifo_space = xiic_tx_fifo_space(i2c); 644e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 645e1d5b659SRichard Röjfors __func__, i2c->tx_msg, fifo_space); 646e1d5b659SRichard Röjfors 647e1d5b659SRichard Röjfors if (!i2c->tx_msg) 648e1d5b659SRichard Röjfors return; 649e1d5b659SRichard Röjfors 650e1d5b659SRichard Röjfors i2c->rx_pos = 0; 651e1d5b659SRichard Röjfors i2c->tx_pos = 0; 652e1d5b659SRichard Röjfors i2c->state = STATE_START; 653e1d5b659SRichard Röjfors if (i2c->tx_msg->flags & I2C_M_RD) { 654e1d5b659SRichard Röjfors /* we dont date putting several reads in the FIFO */ 655e1d5b659SRichard Röjfors xiic_start_recv(i2c); 656e1d5b659SRichard Röjfors } else { 657e1d5b659SRichard Röjfors xiic_start_send(i2c); 658e1d5b659SRichard Röjfors } 659e1d5b659SRichard Röjfors } 660e1d5b659SRichard Röjfors 661c119e7d0SMarek Vasut static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) 662e1d5b659SRichard Röjfors { 663b4c119dbSShubhrajyoti Datta int ret; 664c119e7d0SMarek Vasut 66577c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 666b4c119dbSShubhrajyoti Datta 667c119e7d0SMarek Vasut ret = xiic_busy(i2c); 668c119e7d0SMarek Vasut if (ret) 669c119e7d0SMarek Vasut goto out; 670c119e7d0SMarek Vasut 671c119e7d0SMarek Vasut i2c->tx_msg = msgs; 672c119e7d0SMarek Vasut i2c->rx_msg = NULL; 673c119e7d0SMarek Vasut i2c->nmsgs = num; 674fdacc3c7SMarek Vasut init_completion(&i2c->completion); 675c119e7d0SMarek Vasut 676b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c); 677b4c119dbSShubhrajyoti Datta if (!ret) 678e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 679b4c119dbSShubhrajyoti Datta 680c119e7d0SMarek Vasut out: 68177c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 682b4c119dbSShubhrajyoti Datta 683b4c119dbSShubhrajyoti Datta return ret; 684e1d5b659SRichard Röjfors } 685e1d5b659SRichard Röjfors 686e1d5b659SRichard Röjfors static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 687e1d5b659SRichard Röjfors { 688e1d5b659SRichard Röjfors struct xiic_i2c *i2c = i2c_get_adapdata(adap); 689e1d5b659SRichard Röjfors int err; 690e1d5b659SRichard Röjfors 691e1d5b659SRichard Röjfors dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 692e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 693e1d5b659SRichard Röjfors 694a85c5c7aSQinglang Miao err = pm_runtime_resume_and_get(i2c->dev); 69536ecbcabSShubhrajyoti Datta if (err < 0) 69636ecbcabSShubhrajyoti Datta return err; 69736ecbcabSShubhrajyoti Datta 698c119e7d0SMarek Vasut err = xiic_start_xfer(i2c, msgs, num); 699b4c119dbSShubhrajyoti Datta if (err < 0) { 700b4c119dbSShubhrajyoti Datta dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 701fdacc3c7SMarek Vasut return err; 702b4c119dbSShubhrajyoti Datta } 703e1d5b659SRichard Röjfors 704fdacc3c7SMarek Vasut err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); 705c119e7d0SMarek Vasut mutex_lock(&i2c->lock); 706fdacc3c7SMarek Vasut if (err == 0) { /* Timeout */ 707e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 708e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 709e1d5b659SRichard Röjfors i2c->nmsgs = 0; 71036ecbcabSShubhrajyoti Datta err = -ETIMEDOUT; 711fdacc3c7SMarek Vasut } else if (err < 0) { /* Completion error */ 712fdacc3c7SMarek Vasut i2c->tx_msg = NULL; 713fdacc3c7SMarek Vasut i2c->rx_msg = NULL; 714fdacc3c7SMarek Vasut i2c->nmsgs = 0; 715fdacc3c7SMarek Vasut } else { 716fdacc3c7SMarek Vasut err = (i2c->state == STATE_DONE) ? num : -EIO; 717e1d5b659SRichard Röjfors } 718c119e7d0SMarek Vasut mutex_unlock(&i2c->lock); 71936ecbcabSShubhrajyoti Datta pm_runtime_mark_last_busy(i2c->dev); 72036ecbcabSShubhrajyoti Datta pm_runtime_put_autosuspend(i2c->dev); 72136ecbcabSShubhrajyoti Datta return err; 722e1d5b659SRichard Röjfors } 723e1d5b659SRichard Röjfors 724e1d5b659SRichard Röjfors static u32 xiic_func(struct i2c_adapter *adap) 725e1d5b659SRichard Röjfors { 726e1d5b659SRichard Röjfors return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 727e1d5b659SRichard Röjfors } 728e1d5b659SRichard Röjfors 729e1d5b659SRichard Röjfors static const struct i2c_algorithm xiic_algorithm = { 730e1d5b659SRichard Röjfors .master_xfer = xiic_xfer, 731e1d5b659SRichard Röjfors .functionality = xiic_func, 732e1d5b659SRichard Röjfors }; 733e1d5b659SRichard Röjfors 73449b80958SRobert Hancock static const struct i2c_adapter_quirks xiic_quirks = { 73549b80958SRobert Hancock .max_read_len = 255, 73649b80958SRobert Hancock }; 73749b80958SRobert Hancock 738329430ccSBhumika Goyal static const struct i2c_adapter xiic_adapter = { 739e1d5b659SRichard Röjfors .owner = THIS_MODULE, 7404db5beedSWolfram Sang .class = I2C_CLASS_DEPRECATED, 741e1d5b659SRichard Röjfors .algo = &xiic_algorithm, 74249b80958SRobert Hancock .quirks = &xiic_quirks, 743e1d5b659SRichard Röjfors }; 744e1d5b659SRichard Röjfors 745e1d5b659SRichard Röjfors 7460b255e92SBill Pemberton static int xiic_i2c_probe(struct platform_device *pdev) 747e1d5b659SRichard Röjfors { 748e1d5b659SRichard Röjfors struct xiic_i2c *i2c; 749e1d5b659SRichard Röjfors struct xiic_i2c_platform_data *pdata; 750e1d5b659SRichard Röjfors struct resource *res; 751e1d5b659SRichard Röjfors int ret, irq; 752e1d5b659SRichard Röjfors u8 i; 75348ef3ca9SThomas Gessler u32 sr; 754e1d5b659SRichard Röjfors 755168e722dSKedareswara rao Appana i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 756e1d5b659SRichard Röjfors if (!i2c) 757e1d5b659SRichard Röjfors return -ENOMEM; 758e1d5b659SRichard Röjfors 759168e722dSKedareswara rao Appana res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 760168e722dSKedareswara rao Appana i2c->base = devm_ioremap_resource(&pdev->dev, res); 761168e722dSKedareswara rao Appana if (IS_ERR(i2c->base)) 762168e722dSKedareswara rao Appana return PTR_ERR(i2c->base); 763e1d5b659SRichard Röjfors 764168e722dSKedareswara rao Appana irq = platform_get_irq(pdev, 0); 765168e722dSKedareswara rao Appana if (irq < 0) 766168e722dSKedareswara rao Appana return irq; 767168e722dSKedareswara rao Appana 768168e722dSKedareswara rao Appana pdata = dev_get_platdata(&pdev->dev); 769e1d5b659SRichard Röjfors 770e1d5b659SRichard Röjfors /* hook up driver to tree */ 771e1d5b659SRichard Röjfors platform_set_drvdata(pdev, i2c); 772e1d5b659SRichard Röjfors i2c->adap = xiic_adapter; 773e1d5b659SRichard Röjfors i2c_set_adapdata(&i2c->adap, i2c); 774e1d5b659SRichard Röjfors i2c->adap.dev.parent = &pdev->dev; 7753ac0b337SLars-Peter Clausen i2c->adap.dev.of_node = pdev->dev.of_node; 7761d366c2fSRobert Hancock snprintf(i2c->adap.name, sizeof(i2c->adap.name), 7771d366c2fSRobert Hancock DRIVER_NAME " %s", pdev->name); 778e1d5b659SRichard Röjfors 77977c68019SLars-Peter Clausen mutex_init(&i2c->lock); 780168e722dSKedareswara rao Appana 78136ecbcabSShubhrajyoti Datta i2c->clk = devm_clk_get(&pdev->dev, NULL); 7829dbba3f8SKrzysztof Kozlowski if (IS_ERR(i2c->clk)) 7839dbba3f8SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 7849dbba3f8SKrzysztof Kozlowski "input clock not found.\n"); 7859dbba3f8SKrzysztof Kozlowski 78636ecbcabSShubhrajyoti Datta ret = clk_prepare_enable(i2c->clk); 78736ecbcabSShubhrajyoti Datta if (ret) { 78836ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "Unable to enable clock.\n"); 78936ecbcabSShubhrajyoti Datta return ret; 79036ecbcabSShubhrajyoti Datta } 79136ecbcabSShubhrajyoti Datta i2c->dev = &pdev->dev; 79236ecbcabSShubhrajyoti Datta pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 79336ecbcabSShubhrajyoti Datta pm_runtime_use_autosuspend(i2c->dev); 79436ecbcabSShubhrajyoti Datta pm_runtime_set_active(i2c->dev); 79510b17004SShubhrajyoti Datta pm_runtime_enable(i2c->dev); 796861dcffeSMarek Vasut ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 797fcc2fac6SShubhrajyoti Datta xiic_process, IRQF_ONESHOT, 798fcc2fac6SShubhrajyoti Datta pdev->name, i2c); 799fcc2fac6SShubhrajyoti Datta 800168e722dSKedareswara rao Appana if (ret < 0) { 801e1d5b659SRichard Röjfors dev_err(&pdev->dev, "Cannot claim IRQ\n"); 80236ecbcabSShubhrajyoti Datta goto err_clk_dis; 803e1d5b659SRichard Röjfors } 804e1d5b659SRichard Röjfors 8059e3b184bSJaakko Laine i2c->singlemaster = 8069e3b184bSJaakko Laine of_property_read_bool(pdev->dev.of_node, "single-master"); 8079e3b184bSJaakko Laine 80848ef3ca9SThomas Gessler /* 80948ef3ca9SThomas Gessler * Detect endianness 81048ef3ca9SThomas Gessler * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 81148ef3ca9SThomas Gessler * set, assume that the endianness was wrong and swap. 81248ef3ca9SThomas Gessler */ 81348ef3ca9SThomas Gessler i2c->endianness = LITTLE; 81448ef3ca9SThomas Gessler xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 81548ef3ca9SThomas Gessler /* Reset is cleared in xiic_reinit */ 81648ef3ca9SThomas Gessler sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 81748ef3ca9SThomas Gessler if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 81848ef3ca9SThomas Gessler i2c->endianness = BIG; 81948ef3ca9SThomas Gessler 820b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c); 821b4c119dbSShubhrajyoti Datta if (ret < 0) { 822b4c119dbSShubhrajyoti Datta dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 823b4c119dbSShubhrajyoti Datta goto err_clk_dis; 824b4c119dbSShubhrajyoti Datta } 825617bdcbcSMichal Simek 826e1d5b659SRichard Röjfors /* add i2c adapter to i2c tree */ 827e1d5b659SRichard Röjfors ret = i2c_add_adapter(&i2c->adap); 828e1d5b659SRichard Röjfors if (ret) { 829168e722dSKedareswara rao Appana xiic_deinit(i2c); 83036ecbcabSShubhrajyoti Datta goto err_clk_dis; 831e1d5b659SRichard Röjfors } 832e1d5b659SRichard Röjfors 8333ac0b337SLars-Peter Clausen if (pdata) { 834e1d5b659SRichard Röjfors /* add in known devices to the bus */ 835e1d5b659SRichard Röjfors for (i = 0; i < pdata->num_devices; i++) 836bf255befSWolfram Sang i2c_new_client_device(&i2c->adap, pdata->devices + i); 8373ac0b337SLars-Peter Clausen } 8383ac0b337SLars-Peter Clausen 839e1d5b659SRichard Röjfors return 0; 84036ecbcabSShubhrajyoti Datta 84136ecbcabSShubhrajyoti Datta err_clk_dis: 84236ecbcabSShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 84336ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 84436ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 84536ecbcabSShubhrajyoti Datta return ret; 846e1d5b659SRichard Röjfors } 847e1d5b659SRichard Röjfors 8480b255e92SBill Pemberton static int xiic_i2c_remove(struct platform_device *pdev) 849e1d5b659SRichard Röjfors { 850e1d5b659SRichard Röjfors struct xiic_i2c *i2c = platform_get_drvdata(pdev); 85136ecbcabSShubhrajyoti Datta int ret; 852e1d5b659SRichard Röjfors 853e1d5b659SRichard Röjfors /* remove adapter & data */ 854e1d5b659SRichard Röjfors i2c_del_adapter(&i2c->adap); 855e1d5b659SRichard Röjfors 856a85c5c7aSQinglang Miao ret = pm_runtime_resume_and_get(i2c->dev); 85710b17004SShubhrajyoti Datta if (ret < 0) 85836ecbcabSShubhrajyoti Datta return ret; 85910b17004SShubhrajyoti Datta 860e1d5b659SRichard Röjfors xiic_deinit(i2c); 86110b17004SShubhrajyoti Datta pm_runtime_put_sync(i2c->dev); 86236ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 86336ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 86410b17004SShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 86510b17004SShubhrajyoti Datta pm_runtime_dont_use_autosuspend(&pdev->dev); 866e1d5b659SRichard Röjfors 867e1d5b659SRichard Röjfors return 0; 868e1d5b659SRichard Röjfors } 869e1d5b659SRichard Röjfors 8703ac0b337SLars-Peter Clausen #if defined(CONFIG_OF) 8710b255e92SBill Pemberton static const struct of_device_id xiic_of_match[] = { 8723ac0b337SLars-Peter Clausen { .compatible = "xlnx,xps-iic-2.00.a", }, 8733ac0b337SLars-Peter Clausen {}, 8743ac0b337SLars-Peter Clausen }; 8753ac0b337SLars-Peter Clausen MODULE_DEVICE_TABLE(of, xiic_of_match); 8763ac0b337SLars-Peter Clausen #endif 8773ac0b337SLars-Peter Clausen 87874d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 87936ecbcabSShubhrajyoti Datta { 8809242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev); 88136ecbcabSShubhrajyoti Datta 88236ecbcabSShubhrajyoti Datta clk_disable(i2c->clk); 88336ecbcabSShubhrajyoti Datta 88436ecbcabSShubhrajyoti Datta return 0; 88536ecbcabSShubhrajyoti Datta } 88636ecbcabSShubhrajyoti Datta 88774d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 88836ecbcabSShubhrajyoti Datta { 8899242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev); 89036ecbcabSShubhrajyoti Datta int ret; 89136ecbcabSShubhrajyoti Datta 89236ecbcabSShubhrajyoti Datta ret = clk_enable(i2c->clk); 89336ecbcabSShubhrajyoti Datta if (ret) { 89436ecbcabSShubhrajyoti Datta dev_err(dev, "Cannot enable clock.\n"); 89536ecbcabSShubhrajyoti Datta return ret; 89636ecbcabSShubhrajyoti Datta } 89736ecbcabSShubhrajyoti Datta 89836ecbcabSShubhrajyoti Datta return 0; 89936ecbcabSShubhrajyoti Datta } 90036ecbcabSShubhrajyoti Datta 90136ecbcabSShubhrajyoti Datta static const struct dev_pm_ops xiic_dev_pm_ops = { 90274d23319SMoritz Fischer SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 90374d23319SMoritz Fischer xiic_i2c_runtime_resume, NULL) 90436ecbcabSShubhrajyoti Datta }; 905e1d5b659SRichard Röjfors static struct platform_driver xiic_i2c_driver = { 906e1d5b659SRichard Röjfors .probe = xiic_i2c_probe, 9070b255e92SBill Pemberton .remove = xiic_i2c_remove, 908e1d5b659SRichard Röjfors .driver = { 909e1d5b659SRichard Röjfors .name = DRIVER_NAME, 9103ac0b337SLars-Peter Clausen .of_match_table = of_match_ptr(xiic_of_match), 91136ecbcabSShubhrajyoti Datta .pm = &xiic_dev_pm_ops, 912e1d5b659SRichard Röjfors }, 913e1d5b659SRichard Röjfors }; 914e1d5b659SRichard Röjfors 915a3664b51SAxel Lin module_platform_driver(xiic_i2c_driver); 916e1d5b659SRichard Röjfors 917e1d5b659SRichard Röjfors MODULE_AUTHOR("info@mocean-labs.com"); 918e1d5b659SRichard Röjfors MODULE_DESCRIPTION("Xilinx I2C bus driver"); 919e1d5b659SRichard Röjfors MODULE_LICENSE("GPL v2"); 920a3664b51SAxel Lin MODULE_ALIAS("platform:"DRIVER_NAME); 921