1e1d5b659SRichard Röjfors /* 2e1d5b659SRichard Röjfors * i2c-xiic.c 3e1d5b659SRichard Röjfors * Copyright (c) 2002-2007 Xilinx Inc. 4e1d5b659SRichard Röjfors * Copyright (c) 2009-2010 Intel Corporation 5e1d5b659SRichard Röjfors * 6e1d5b659SRichard Röjfors * This program is free software; you can redistribute it and/or modify 7e1d5b659SRichard Röjfors * it under the terms of the GNU General Public License version 2 as 8e1d5b659SRichard Röjfors * published by the Free Software Foundation. 9e1d5b659SRichard Röjfors * 10e1d5b659SRichard Röjfors * This program is distributed in the hope that it will be useful, 11e1d5b659SRichard Röjfors * but WITHOUT ANY WARRANTY; without even the implied warranty of 12e1d5b659SRichard Röjfors * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13e1d5b659SRichard Röjfors * GNU General Public License for more details. 14e1d5b659SRichard Röjfors * 15e1d5b659SRichard Röjfors * 16e1d5b659SRichard Röjfors * This code was implemented by Mocean Laboratories AB when porting linux 17e1d5b659SRichard Röjfors * to the automotive development board Russellville. The copyright holder 18e1d5b659SRichard Röjfors * as seen in the header is Intel corporation. 19e1d5b659SRichard Röjfors * Mocean Laboratories forked off the GNU/Linux platform work into a 2025985edcSLucas De Marchi * separate company called Pelagicore AB, which committed the code to the 21e1d5b659SRichard Röjfors * kernel. 22e1d5b659SRichard Röjfors */ 23e1d5b659SRichard Röjfors 24e1d5b659SRichard Röjfors /* Supports: 25e1d5b659SRichard Röjfors * Xilinx IIC 26e1d5b659SRichard Röjfors */ 27e1d5b659SRichard Röjfors #include <linux/kernel.h> 28e1d5b659SRichard Röjfors #include <linux/module.h> 29e1d5b659SRichard Röjfors #include <linux/errno.h> 30168e722dSKedareswara rao Appana #include <linux/err.h> 3102ca6c40SRandy Dunlap #include <linux/delay.h> 32e1d5b659SRichard Röjfors #include <linux/platform_device.h> 33e1d5b659SRichard Röjfors #include <linux/i2c.h> 34e1d5b659SRichard Röjfors #include <linux/interrupt.h> 35e1d5b659SRichard Röjfors #include <linux/wait.h> 36e1d5b659SRichard Röjfors #include <linux/i2c-xiic.h> 37e1d5b659SRichard Röjfors #include <linux/io.h> 385a0e3ad6STejun Heo #include <linux/slab.h> 394edd65e6SSachin Kamat #include <linux/of.h> 4036ecbcabSShubhrajyoti Datta #include <linux/clk.h> 4136ecbcabSShubhrajyoti Datta #include <linux/pm_runtime.h> 42e1d5b659SRichard Röjfors 43e1d5b659SRichard Röjfors #define DRIVER_NAME "xiic-i2c" 44e1d5b659SRichard Röjfors 45e1d5b659SRichard Röjfors enum xilinx_i2c_state { 46e1d5b659SRichard Röjfors STATE_DONE, 47e1d5b659SRichard Röjfors STATE_ERROR, 48e1d5b659SRichard Röjfors STATE_START 49e1d5b659SRichard Röjfors }; 50e1d5b659SRichard Röjfors 5148ef3ca9SThomas Gessler enum xiic_endian { 5248ef3ca9SThomas Gessler LITTLE, 5348ef3ca9SThomas Gessler BIG 5448ef3ca9SThomas Gessler }; 5548ef3ca9SThomas Gessler 56e1d5b659SRichard Röjfors /** 57e1d5b659SRichard Röjfors * struct xiic_i2c - Internal representation of the XIIC I2C bus 58e1d5b659SRichard Röjfors * @base: Memory base of the HW registers 59e1d5b659SRichard Röjfors * @wait: Wait queue for callers 60e1d5b659SRichard Röjfors * @adap: Kernel adapter representation 61e1d5b659SRichard Röjfors * @tx_msg: Messages from above to be sent 62e1d5b659SRichard Röjfors * @lock: Mutual exclusion 63e1d5b659SRichard Röjfors * @tx_pos: Current pos in TX message 64e1d5b659SRichard Röjfors * @nmsgs: Number of messages in tx_msg 65e1d5b659SRichard Röjfors * @state: See STATE_ 66e1d5b659SRichard Röjfors * @rx_msg: Current RX message 67e1d5b659SRichard Röjfors * @rx_pos: Position within current RX message 68bea6ff02SShubhrajyoti Datta * @endianness: big/little-endian byte order 69e1d5b659SRichard Röjfors */ 70e1d5b659SRichard Röjfors struct xiic_i2c { 7136ecbcabSShubhrajyoti Datta struct device *dev; 72e1d5b659SRichard Röjfors void __iomem *base; 73e1d5b659SRichard Röjfors wait_queue_head_t wait; 74e1d5b659SRichard Röjfors struct i2c_adapter adap; 75e1d5b659SRichard Röjfors struct i2c_msg *tx_msg; 7677c68019SLars-Peter Clausen struct mutex lock; 77e1d5b659SRichard Röjfors unsigned int tx_pos; 78e1d5b659SRichard Röjfors unsigned int nmsgs; 79e1d5b659SRichard Röjfors enum xilinx_i2c_state state; 80e1d5b659SRichard Röjfors struct i2c_msg *rx_msg; 81e1d5b659SRichard Röjfors int rx_pos; 8248ef3ca9SThomas Gessler enum xiic_endian endianness; 8336ecbcabSShubhrajyoti Datta struct clk *clk; 84e1d5b659SRichard Röjfors }; 85e1d5b659SRichard Röjfors 86e1d5b659SRichard Röjfors 87e1d5b659SRichard Röjfors #define XIIC_MSB_OFFSET 0 88e1d5b659SRichard Röjfors #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 89e1d5b659SRichard Röjfors 90e1d5b659SRichard Röjfors /* 91e1d5b659SRichard Röjfors * Register offsets in bytes from RegisterBase. Three is added to the 92e1d5b659SRichard Röjfors * base offset to access LSB (IBM style) of the word 93e1d5b659SRichard Röjfors */ 94e1d5b659SRichard Röjfors #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 95e1d5b659SRichard Röjfors #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 96e1d5b659SRichard Röjfors #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 97e1d5b659SRichard Röjfors #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 98e1d5b659SRichard Röjfors #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 99e1d5b659SRichard Röjfors #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 100e1d5b659SRichard Röjfors #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 101e1d5b659SRichard Röjfors #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 102e1d5b659SRichard Röjfors #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 103e1d5b659SRichard Röjfors #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 104e1d5b659SRichard Röjfors 105e1d5b659SRichard Röjfors /* Control Register masks */ 106e1d5b659SRichard Röjfors #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 107e1d5b659SRichard Röjfors #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 108e1d5b659SRichard Röjfors #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 109e1d5b659SRichard Röjfors #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 110e1d5b659SRichard Röjfors #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 111e1d5b659SRichard Röjfors #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 112e1d5b659SRichard Röjfors #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 113e1d5b659SRichard Röjfors 114e1d5b659SRichard Röjfors /* Status Register masks */ 115e1d5b659SRichard Röjfors #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 116e1d5b659SRichard Röjfors #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 117e1d5b659SRichard Röjfors #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 118e1d5b659SRichard Röjfors #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 119e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 120e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 121e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 122e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 123e1d5b659SRichard Röjfors 124e1d5b659SRichard Röjfors /* Interrupt Status Register masks Interrupt occurs when... */ 125e1d5b659SRichard Röjfors #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 126e1d5b659SRichard Röjfors #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 127e1d5b659SRichard Röjfors #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 128e1d5b659SRichard Röjfors #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 129e1d5b659SRichard Röjfors #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 130e1d5b659SRichard Röjfors #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 131e1d5b659SRichard Röjfors #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 132e1d5b659SRichard Röjfors #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 133e1d5b659SRichard Röjfors 134e1d5b659SRichard Röjfors /* The following constants specify the depth of the FIFOs */ 135e1d5b659SRichard Röjfors #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 136e1d5b659SRichard Röjfors #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 137e1d5b659SRichard Röjfors 138e1d5b659SRichard Röjfors /* The following constants specify groups of interrupts that are typically 139e1d5b659SRichard Röjfors * enabled or disables at the same time 140e1d5b659SRichard Röjfors */ 141e1d5b659SRichard Röjfors #define XIIC_TX_INTERRUPTS \ 142e1d5b659SRichard Röjfors (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 143e1d5b659SRichard Röjfors 144e1d5b659SRichard Röjfors #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 145e1d5b659SRichard Röjfors 146e1d5b659SRichard Röjfors /* The following constants are used with the following macros to specify the 147e1d5b659SRichard Röjfors * operation, a read or write operation. 148e1d5b659SRichard Röjfors */ 149e1d5b659SRichard Röjfors #define XIIC_READ_OPERATION 1 150e1d5b659SRichard Röjfors #define XIIC_WRITE_OPERATION 0 151e1d5b659SRichard Röjfors 152e1d5b659SRichard Röjfors /* 153e1d5b659SRichard Röjfors * Tx Fifo upper bit masks. 154e1d5b659SRichard Röjfors */ 155e1d5b659SRichard Röjfors #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 156e1d5b659SRichard Röjfors #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 157e1d5b659SRichard Röjfors 158e1d5b659SRichard Röjfors /* 159e1d5b659SRichard Röjfors * The following constants define the register offsets for the Interrupt 160e1d5b659SRichard Röjfors * registers. There are some holes in the memory map for reserved addresses 161e1d5b659SRichard Röjfors * to allow other registers to be added and still match the memory map of the 162e1d5b659SRichard Röjfors * interrupt controller registers 163e1d5b659SRichard Röjfors */ 164e1d5b659SRichard Röjfors #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 165e1d5b659SRichard Röjfors #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 166e1d5b659SRichard Röjfors #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 167e1d5b659SRichard Röjfors #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 168e1d5b659SRichard Röjfors 169e1d5b659SRichard Röjfors #define XIIC_RESET_MASK 0xAUL 170e1d5b659SRichard Röjfors 17136ecbcabSShubhrajyoti Datta #define XIIC_PM_TIMEOUT 1000 /* ms */ 172e1d5b659SRichard Röjfors /* 173e1d5b659SRichard Röjfors * The following constant is used for the device global interrupt enable 174e1d5b659SRichard Röjfors * register, to enable all interrupts for the device, this is the only bit 175e1d5b659SRichard Röjfors * in the register 176e1d5b659SRichard Röjfors */ 177e1d5b659SRichard Röjfors #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 178e1d5b659SRichard Röjfors 179e1d5b659SRichard Röjfors #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 180e1d5b659SRichard Röjfors #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 181e1d5b659SRichard Röjfors 182e1d5b659SRichard Röjfors static void xiic_start_xfer(struct xiic_i2c *i2c); 183e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c); 184e1d5b659SRichard Röjfors 18548ef3ca9SThomas Gessler /* 18648ef3ca9SThomas Gessler * For the register read and write functions, a little-endian and big-endian 18748ef3ca9SThomas Gessler * version are necessary. Endianness is detected during the probe function. 18848ef3ca9SThomas Gessler * Only the least significant byte [doublet] of the register are ever 18948ef3ca9SThomas Gessler * accessed. This requires an offset of 3 [2] from the base address for 19048ef3ca9SThomas Gessler * big-endian systems. 19148ef3ca9SThomas Gessler */ 19248ef3ca9SThomas Gessler 193e1d5b659SRichard Röjfors static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 194e1d5b659SRichard Röjfors { 19548ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 196e1d5b659SRichard Röjfors iowrite8(value, i2c->base + reg); 19748ef3ca9SThomas Gessler else 19848ef3ca9SThomas Gessler iowrite8(value, i2c->base + reg + 3); 199e1d5b659SRichard Röjfors } 200e1d5b659SRichard Röjfors 201e1d5b659SRichard Röjfors static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 202e1d5b659SRichard Röjfors { 20348ef3ca9SThomas Gessler u8 ret; 20448ef3ca9SThomas Gessler 20548ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 20648ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg); 20748ef3ca9SThomas Gessler else 20848ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg + 3); 20948ef3ca9SThomas Gessler return ret; 210e1d5b659SRichard Röjfors } 211e1d5b659SRichard Röjfors 212e1d5b659SRichard Röjfors static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 213e1d5b659SRichard Röjfors { 21448ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 215e1d5b659SRichard Röjfors iowrite16(value, i2c->base + reg); 21648ef3ca9SThomas Gessler else 21748ef3ca9SThomas Gessler iowrite16be(value, i2c->base + reg + 2); 218e1d5b659SRichard Röjfors } 219e1d5b659SRichard Röjfors 220e1d5b659SRichard Röjfors static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 221e1d5b659SRichard Röjfors { 22248ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 223e1d5b659SRichard Röjfors iowrite32(value, i2c->base + reg); 22448ef3ca9SThomas Gessler else 22548ef3ca9SThomas Gessler iowrite32be(value, i2c->base + reg); 226e1d5b659SRichard Röjfors } 227e1d5b659SRichard Röjfors 228e1d5b659SRichard Röjfors static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 229e1d5b659SRichard Röjfors { 23048ef3ca9SThomas Gessler u32 ret; 23148ef3ca9SThomas Gessler 23248ef3ca9SThomas Gessler if (i2c->endianness == LITTLE) 23348ef3ca9SThomas Gessler ret = ioread32(i2c->base + reg); 23448ef3ca9SThomas Gessler else 23548ef3ca9SThomas Gessler ret = ioread32be(i2c->base + reg); 23648ef3ca9SThomas Gessler return ret; 237e1d5b659SRichard Röjfors } 238e1d5b659SRichard Röjfors 239e1d5b659SRichard Röjfors static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 240e1d5b659SRichard Röjfors { 241e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 242e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 243e1d5b659SRichard Röjfors } 244e1d5b659SRichard Röjfors 245e1d5b659SRichard Röjfors static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 246e1d5b659SRichard Röjfors { 247e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 248e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 249e1d5b659SRichard Röjfors } 250e1d5b659SRichard Röjfors 251e1d5b659SRichard Röjfors static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 252e1d5b659SRichard Röjfors { 253e1d5b659SRichard Röjfors u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 254e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 255e1d5b659SRichard Röjfors } 256e1d5b659SRichard Röjfors 257e1d5b659SRichard Röjfors static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 258e1d5b659SRichard Röjfors { 259e1d5b659SRichard Röjfors xiic_irq_clr(i2c, mask); 260e1d5b659SRichard Röjfors xiic_irq_en(i2c, mask); 261e1d5b659SRichard Röjfors } 262e1d5b659SRichard Röjfors 263e1d5b659SRichard Röjfors static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) 264e1d5b659SRichard Röjfors { 265e1d5b659SRichard Röjfors u8 sr; 266e1d5b659SRichard Röjfors for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 267e1d5b659SRichard Röjfors !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 268e1d5b659SRichard Röjfors sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) 269e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 270e1d5b659SRichard Röjfors } 271e1d5b659SRichard Röjfors 272e1d5b659SRichard Röjfors static void xiic_reinit(struct xiic_i2c *i2c) 273e1d5b659SRichard Röjfors { 274e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 275e1d5b659SRichard Röjfors 276e1d5b659SRichard Röjfors /* Set receive Fifo depth to maximum (zero based). */ 277e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 278e1d5b659SRichard Röjfors 279e1d5b659SRichard Röjfors /* Reset Tx Fifo. */ 280e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 281e1d5b659SRichard Röjfors 282e1d5b659SRichard Röjfors /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 283e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 284e1d5b659SRichard Röjfors 285e1d5b659SRichard Röjfors /* make sure RX fifo is empty */ 286e1d5b659SRichard Röjfors xiic_clear_rx_fifo(i2c); 287e1d5b659SRichard Röjfors 288e1d5b659SRichard Röjfors /* Enable interrupts */ 289e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 290e1d5b659SRichard Röjfors 291542e2a9bSShubhrajyoti Datta xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 292e1d5b659SRichard Röjfors } 293e1d5b659SRichard Röjfors 294e1d5b659SRichard Röjfors static void xiic_deinit(struct xiic_i2c *i2c) 295e1d5b659SRichard Röjfors { 296e1d5b659SRichard Röjfors u8 cr; 297e1d5b659SRichard Röjfors 298e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 299e1d5b659SRichard Röjfors 300e1d5b659SRichard Röjfors /* Disable IIC Device. */ 301e1d5b659SRichard Röjfors cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 302e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 303e1d5b659SRichard Röjfors } 304e1d5b659SRichard Röjfors 305e1d5b659SRichard Röjfors static void xiic_read_rx(struct xiic_i2c *i2c) 306e1d5b659SRichard Röjfors { 307e1d5b659SRichard Röjfors u8 bytes_in_fifo; 308e1d5b659SRichard Röjfors int i; 309e1d5b659SRichard Röjfors 310e1d5b659SRichard Röjfors bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 311e1d5b659SRichard Röjfors 312f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, 313f1e9f89aSKedareswara rao Appana "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 314e1d5b659SRichard Röjfors __func__, bytes_in_fifo, xiic_rx_space(i2c), 315e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 316e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 317e1d5b659SRichard Röjfors 318e1d5b659SRichard Röjfors if (bytes_in_fifo > xiic_rx_space(i2c)) 319e1d5b659SRichard Röjfors bytes_in_fifo = xiic_rx_space(i2c); 320e1d5b659SRichard Röjfors 321e1d5b659SRichard Röjfors for (i = 0; i < bytes_in_fifo; i++) 322e1d5b659SRichard Röjfors i2c->rx_msg->buf[i2c->rx_pos++] = 323e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 324e1d5b659SRichard Röjfors 325e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 326e1d5b659SRichard Röjfors (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 327e1d5b659SRichard Röjfors IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 328e1d5b659SRichard Röjfors } 329e1d5b659SRichard Röjfors 330e1d5b659SRichard Röjfors static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 331e1d5b659SRichard Röjfors { 332e1d5b659SRichard Röjfors /* return the actual space left in the FIFO */ 333e1d5b659SRichard Röjfors return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 334e1d5b659SRichard Röjfors } 335e1d5b659SRichard Röjfors 336e1d5b659SRichard Röjfors static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 337e1d5b659SRichard Röjfors { 338e1d5b659SRichard Röjfors u8 fifo_space = xiic_tx_fifo_space(i2c); 339e1d5b659SRichard Röjfors int len = xiic_tx_space(i2c); 340e1d5b659SRichard Röjfors 341e1d5b659SRichard Röjfors len = (len > fifo_space) ? fifo_space : len; 342e1d5b659SRichard Röjfors 343e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 344e1d5b659SRichard Röjfors __func__, len, fifo_space); 345e1d5b659SRichard Röjfors 346e1d5b659SRichard Röjfors while (len--) { 347e1d5b659SRichard Röjfors u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 348e1d5b659SRichard Röjfors if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 349e1d5b659SRichard Röjfors /* last message in transfer -> STOP */ 350e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 351e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 352c39e8e43SSteven A. Falco } 353e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 354e1d5b659SRichard Röjfors } 355e1d5b659SRichard Röjfors } 356e1d5b659SRichard Röjfors 357e1d5b659SRichard Röjfors static void xiic_wakeup(struct xiic_i2c *i2c, int code) 358e1d5b659SRichard Röjfors { 359e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 360e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 361e1d5b659SRichard Röjfors i2c->nmsgs = 0; 362e1d5b659SRichard Röjfors i2c->state = code; 363e1d5b659SRichard Röjfors wake_up(&i2c->wait); 364e1d5b659SRichard Röjfors } 365e1d5b659SRichard Röjfors 366fcc2fac6SShubhrajyoti Datta static irqreturn_t xiic_process(int irq, void *dev_id) 367e1d5b659SRichard Röjfors { 368fcc2fac6SShubhrajyoti Datta struct xiic_i2c *i2c = dev_id; 369e1d5b659SRichard Röjfors u32 pend, isr, ier; 370e1d5b659SRichard Röjfors u32 clr = 0; 371e1d5b659SRichard Röjfors 372e1d5b659SRichard Röjfors /* Get the interrupt Status from the IPIF. There is no clearing of 373e1d5b659SRichard Röjfors * interrupts in the IPIF. Interrupts must be cleared at the source. 374e1d5b659SRichard Röjfors * To find which interrupts are pending; AND interrupts pending with 375e1d5b659SRichard Röjfors * interrupts masked. 376e1d5b659SRichard Röjfors */ 37777c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 378e1d5b659SRichard Röjfors isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 379e1d5b659SRichard Röjfors ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 380e1d5b659SRichard Röjfors pend = isr & ier; 381e1d5b659SRichard Röjfors 382f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 383f1e9f89aSKedareswara rao Appana __func__, ier, isr, pend); 384f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 385f1e9f89aSKedareswara rao Appana __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 386e1d5b659SRichard Röjfors i2c->tx_msg, i2c->nmsgs); 387e1d5b659SRichard Röjfors 388e1d5b659SRichard Röjfors 389e1d5b659SRichard Röjfors /* Service requesting interrupt */ 390e1d5b659SRichard Röjfors if ((pend & XIIC_INTR_ARB_LOST_MASK) || 391e1d5b659SRichard Röjfors ((pend & XIIC_INTR_TX_ERROR_MASK) && 392e1d5b659SRichard Röjfors !(pend & XIIC_INTR_RX_FULL_MASK))) { 393e1d5b659SRichard Röjfors /* bus arbritration lost, or... 394e1d5b659SRichard Röjfors * Transmit error _OR_ RX completed 395e1d5b659SRichard Röjfors * if this happens when RX_FULL is not set 396e1d5b659SRichard Röjfors * this is probably a TX error 397e1d5b659SRichard Röjfors */ 398e1d5b659SRichard Röjfors 399e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 400e1d5b659SRichard Röjfors 401e1d5b659SRichard Röjfors /* dynamic mode seem to suffer from problems if we just flushes 402e1d5b659SRichard Röjfors * fifos and the next message is a TX with len 0 (only addr) 403e1d5b659SRichard Röjfors * reset the IP instead of just flush fifos 404e1d5b659SRichard Röjfors */ 405e1d5b659SRichard Röjfors xiic_reinit(i2c); 406e1d5b659SRichard Röjfors 4076b0c8dc3SShubhrajyoti Datta if (i2c->rx_msg) 4086b0c8dc3SShubhrajyoti Datta xiic_wakeup(i2c, STATE_ERROR); 409e1d5b659SRichard Röjfors if (i2c->tx_msg) 410e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_ERROR); 4117f9906bdSShubhrajyoti Datta } 4127f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_RX_FULL_MASK) { 413e1d5b659SRichard Röjfors /* Receive register/FIFO is full */ 414e1d5b659SRichard Röjfors 4157f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_RX_FULL_MASK; 416e1d5b659SRichard Röjfors if (!i2c->rx_msg) { 417e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 418e1d5b659SRichard Röjfors "%s unexpexted RX IRQ\n", __func__); 419e1d5b659SRichard Röjfors xiic_clear_rx_fifo(i2c); 420e1d5b659SRichard Röjfors goto out; 421e1d5b659SRichard Röjfors } 422e1d5b659SRichard Röjfors 423e1d5b659SRichard Röjfors xiic_read_rx(i2c); 424e1d5b659SRichard Röjfors if (xiic_rx_space(i2c) == 0) { 425e1d5b659SRichard Röjfors /* this is the last part of the message */ 426e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 427e1d5b659SRichard Röjfors 428e1d5b659SRichard Röjfors /* also clear TX error if there (RX complete) */ 429e1d5b659SRichard Röjfors clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 430e1d5b659SRichard Röjfors 431e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 432e1d5b659SRichard Röjfors "%s end of message, nmsgs: %d\n", 433e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 434e1d5b659SRichard Röjfors 435e1d5b659SRichard Röjfors /* send next message if this wasn't the last, 436e1d5b659SRichard Röjfors * otherwise the transfer will be finialise when 437e1d5b659SRichard Röjfors * receiving the bus not busy interrupt 438e1d5b659SRichard Röjfors */ 439e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 440e1d5b659SRichard Röjfors i2c->nmsgs--; 441e1d5b659SRichard Röjfors i2c->tx_msg++; 442e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 443e1d5b659SRichard Röjfors "%s will start next...\n", __func__); 444e1d5b659SRichard Röjfors 445e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 446e1d5b659SRichard Röjfors } 447e1d5b659SRichard Röjfors } 4487f9906bdSShubhrajyoti Datta } 4497f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_BNB_MASK) { 450e1d5b659SRichard Röjfors /* IIC bus has transitioned to not busy */ 4517f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_BNB_MASK; 452e1d5b659SRichard Röjfors 453e1d5b659SRichard Röjfors /* The bus is not busy, disable BusNotBusy interrupt */ 454e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 455e1d5b659SRichard Röjfors 456e1d5b659SRichard Röjfors if (!i2c->tx_msg) 457e1d5b659SRichard Röjfors goto out; 458e1d5b659SRichard Röjfors 459e1d5b659SRichard Röjfors if ((i2c->nmsgs == 1) && !i2c->rx_msg && 460e1d5b659SRichard Röjfors xiic_tx_space(i2c) == 0) 461e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_DONE); 462e1d5b659SRichard Röjfors else 463e1d5b659SRichard Röjfors xiic_wakeup(i2c, STATE_ERROR); 4647f9906bdSShubhrajyoti Datta } 4657f9906bdSShubhrajyoti Datta if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 466d36b6910SAl Viro /* Transmit register/FIFO is empty or ½ empty */ 467e1d5b659SRichard Röjfors 4687f9906bdSShubhrajyoti Datta clr |= (pend & 4697f9906bdSShubhrajyoti Datta (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 470e1d5b659SRichard Röjfors 471e1d5b659SRichard Röjfors if (!i2c->tx_msg) { 472e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 473e1d5b659SRichard Röjfors "%s unexpexted TX IRQ\n", __func__); 474e1d5b659SRichard Röjfors goto out; 475e1d5b659SRichard Röjfors } 476e1d5b659SRichard Röjfors 477e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c); 478e1d5b659SRichard Röjfors 479e1d5b659SRichard Röjfors /* current message sent and there is space in the fifo */ 480e1d5b659SRichard Röjfors if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 481e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 482e1d5b659SRichard Röjfors "%s end of message sent, nmsgs: %d\n", 483e1d5b659SRichard Röjfors __func__, i2c->nmsgs); 484e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) { 485e1d5b659SRichard Röjfors i2c->nmsgs--; 486e1d5b659SRichard Röjfors i2c->tx_msg++; 487e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 488e1d5b659SRichard Röjfors } else { 489e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 490e1d5b659SRichard Röjfors 491e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, 492e1d5b659SRichard Röjfors "%s Got TX IRQ but no more to do...\n", 493e1d5b659SRichard Röjfors __func__); 494e1d5b659SRichard Röjfors } 495e1d5b659SRichard Röjfors } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 496e1d5b659SRichard Röjfors /* current frame is sent and is last, 497e1d5b659SRichard Röjfors * make sure to disable tx half 498e1d5b659SRichard Röjfors */ 499e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 500e1d5b659SRichard Röjfors } 501e1d5b659SRichard Röjfors out: 502e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 503e1d5b659SRichard Röjfors 504e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 50577c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 506fcc2fac6SShubhrajyoti Datta return IRQ_HANDLED; 507e1d5b659SRichard Röjfors } 508e1d5b659SRichard Röjfors 509e1d5b659SRichard Röjfors static int xiic_bus_busy(struct xiic_i2c *i2c) 510e1d5b659SRichard Röjfors { 511e1d5b659SRichard Röjfors u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 512e1d5b659SRichard Röjfors 513e1d5b659SRichard Röjfors return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 514e1d5b659SRichard Röjfors } 515e1d5b659SRichard Röjfors 516e1d5b659SRichard Röjfors static int xiic_busy(struct xiic_i2c *i2c) 517e1d5b659SRichard Röjfors { 518e1d5b659SRichard Röjfors int tries = 3; 519e1d5b659SRichard Röjfors int err; 520e1d5b659SRichard Röjfors 521e1d5b659SRichard Röjfors if (i2c->tx_msg) 522e1d5b659SRichard Röjfors return -EBUSY; 523e1d5b659SRichard Röjfors 524e1d5b659SRichard Röjfors /* for instance if previous transfer was terminated due to TX error 525e1d5b659SRichard Röjfors * it might be that the bus is on it's way to become available 526e1d5b659SRichard Röjfors * give it at most 3 ms to wake 527e1d5b659SRichard Röjfors */ 528e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 529e1d5b659SRichard Röjfors while (err && tries--) { 530b33aa252SShubhrajyoti Datta msleep(1); 531e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c); 532e1d5b659SRichard Röjfors } 533e1d5b659SRichard Röjfors 534e1d5b659SRichard Röjfors return err; 535e1d5b659SRichard Röjfors } 536e1d5b659SRichard Röjfors 537e1d5b659SRichard Röjfors static void xiic_start_recv(struct xiic_i2c *i2c) 538e1d5b659SRichard Röjfors { 539e1d5b659SRichard Röjfors u8 rx_watermark; 540e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 541e1d5b659SRichard Röjfors 542e1d5b659SRichard Röjfors /* Clear and enable Rx full interrupt. */ 543e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 544e1d5b659SRichard Röjfors 545e1d5b659SRichard Röjfors /* we want to get all but last byte, because the TX_ERROR IRQ is used 546e1d5b659SRichard Röjfors * to inidicate error ACK on the address, and negative ack on the last 547e1d5b659SRichard Röjfors * received byte, so to not mix them receive all but last. 548e1d5b659SRichard Röjfors * In the case where there is only one byte to receive 549e1d5b659SRichard Röjfors * we can check if ERROR and RX full is set at the same time 550e1d5b659SRichard Röjfors */ 551e1d5b659SRichard Röjfors rx_watermark = msg->len; 552e1d5b659SRichard Röjfors if (rx_watermark > IIC_RX_FIFO_DEPTH) 553e1d5b659SRichard Röjfors rx_watermark = IIC_RX_FIFO_DEPTH; 554e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 555e1d5b659SRichard Röjfors 556e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) 557e1d5b659SRichard Röjfors /* write the address */ 558e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 559e1d5b659SRichard Röjfors (msg->addr << 1) | XIIC_READ_OPERATION | 560e1d5b659SRichard Röjfors XIIC_TX_DYN_START_MASK); 561e1d5b659SRichard Röjfors 562e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 563e1d5b659SRichard Röjfors 564e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 565e1d5b659SRichard Röjfors msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 566e1d5b659SRichard Röjfors if (i2c->nmsgs == 1) 567e1d5b659SRichard Röjfors /* very last, enable bus not busy as well */ 568e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 569e1d5b659SRichard Röjfors 570e1d5b659SRichard Röjfors /* the message is tx:ed */ 571e1d5b659SRichard Röjfors i2c->tx_pos = msg->len; 572e1d5b659SRichard Röjfors } 573e1d5b659SRichard Röjfors 574e1d5b659SRichard Röjfors static void xiic_start_send(struct xiic_i2c *i2c) 575e1d5b659SRichard Röjfors { 576e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->tx_msg; 577e1d5b659SRichard Röjfors 578e1d5b659SRichard Röjfors xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); 579e1d5b659SRichard Röjfors 580f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 581f1e9f89aSKedareswara rao Appana __func__, msg, msg->len); 582f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 583f1e9f89aSKedareswara rao Appana __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 584e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 585e1d5b659SRichard Röjfors 586e1d5b659SRichard Röjfors if (!(msg->flags & I2C_M_NOSTART)) { 587e1d5b659SRichard Röjfors /* write the address */ 588e1d5b659SRichard Röjfors u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION | 589e1d5b659SRichard Röjfors XIIC_TX_DYN_START_MASK; 590e1d5b659SRichard Röjfors if ((i2c->nmsgs == 1) && msg->len == 0) 591e1d5b659SRichard Röjfors /* no data and last message -> add STOP */ 592e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK; 593e1d5b659SRichard Röjfors 594e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 595e1d5b659SRichard Röjfors } 596e1d5b659SRichard Röjfors 597e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c); 598e1d5b659SRichard Röjfors 599e1d5b659SRichard Röjfors /* Clear any pending Tx empty, Tx Error and then enable them. */ 600e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 601e1d5b659SRichard Röjfors XIIC_INTR_BNB_MASK); 602e1d5b659SRichard Röjfors } 603e1d5b659SRichard Röjfors 604e1d5b659SRichard Röjfors static irqreturn_t xiic_isr(int irq, void *dev_id) 605e1d5b659SRichard Röjfors { 606e1d5b659SRichard Röjfors struct xiic_i2c *i2c = dev_id; 607fcc2fac6SShubhrajyoti Datta u32 pend, isr, ier; 608fcc2fac6SShubhrajyoti Datta irqreturn_t ret = IRQ_NONE; 609fcc2fac6SShubhrajyoti Datta /* Do not processes a devices interrupts if the device has no 610fcc2fac6SShubhrajyoti Datta * interrupts pending 611fcc2fac6SShubhrajyoti Datta */ 612e1d5b659SRichard Röjfors 613e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); 614e1d5b659SRichard Röjfors 615fcc2fac6SShubhrajyoti Datta isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 616fcc2fac6SShubhrajyoti Datta ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 617fcc2fac6SShubhrajyoti Datta pend = isr & ier; 618fcc2fac6SShubhrajyoti Datta if (pend) 619fcc2fac6SShubhrajyoti Datta ret = IRQ_WAKE_THREAD; 620e1d5b659SRichard Röjfors 621fcc2fac6SShubhrajyoti Datta return ret; 622e1d5b659SRichard Röjfors } 623e1d5b659SRichard Röjfors 624e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c) 625e1d5b659SRichard Röjfors { 626e1d5b659SRichard Röjfors int first = 1; 627e1d5b659SRichard Röjfors int fifo_space = xiic_tx_fifo_space(i2c); 628e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 629e1d5b659SRichard Röjfors __func__, i2c->tx_msg, fifo_space); 630e1d5b659SRichard Röjfors 631e1d5b659SRichard Röjfors if (!i2c->tx_msg) 632e1d5b659SRichard Röjfors return; 633e1d5b659SRichard Röjfors 634e1d5b659SRichard Röjfors i2c->rx_pos = 0; 635e1d5b659SRichard Röjfors i2c->tx_pos = 0; 636e1d5b659SRichard Röjfors i2c->state = STATE_START; 637e1d5b659SRichard Röjfors while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { 638e1d5b659SRichard Röjfors if (!first) { 639e1d5b659SRichard Röjfors i2c->nmsgs--; 640e1d5b659SRichard Röjfors i2c->tx_msg++; 641e1d5b659SRichard Röjfors i2c->tx_pos = 0; 642e1d5b659SRichard Röjfors } else 643e1d5b659SRichard Röjfors first = 0; 644e1d5b659SRichard Röjfors 645e1d5b659SRichard Röjfors if (i2c->tx_msg->flags & I2C_M_RD) { 646e1d5b659SRichard Röjfors /* we dont date putting several reads in the FIFO */ 647e1d5b659SRichard Röjfors xiic_start_recv(i2c); 648e1d5b659SRichard Röjfors return; 649e1d5b659SRichard Röjfors } else { 650e1d5b659SRichard Röjfors xiic_start_send(i2c); 651e1d5b659SRichard Röjfors if (xiic_tx_space(i2c) != 0) { 652e1d5b659SRichard Röjfors /* the message could not be completely sent */ 653e1d5b659SRichard Röjfors break; 654e1d5b659SRichard Röjfors } 655e1d5b659SRichard Röjfors } 656e1d5b659SRichard Röjfors 657e1d5b659SRichard Röjfors fifo_space = xiic_tx_fifo_space(i2c); 658e1d5b659SRichard Röjfors } 659e1d5b659SRichard Röjfors 660e1d5b659SRichard Röjfors /* there are more messages or the current one could not be completely 661e1d5b659SRichard Röjfors * put into the FIFO, also enable the half empty interrupt 662e1d5b659SRichard Röjfors */ 663e1d5b659SRichard Röjfors if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) 664e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); 665e1d5b659SRichard Röjfors 666e1d5b659SRichard Röjfors } 667e1d5b659SRichard Röjfors 668e1d5b659SRichard Röjfors static void xiic_start_xfer(struct xiic_i2c *i2c) 669e1d5b659SRichard Röjfors { 67077c68019SLars-Peter Clausen mutex_lock(&i2c->lock); 6719656eeebSLars-Peter Clausen xiic_reinit(i2c); 672e1d5b659SRichard Röjfors __xiic_start_xfer(i2c); 67377c68019SLars-Peter Clausen mutex_unlock(&i2c->lock); 674e1d5b659SRichard Röjfors } 675e1d5b659SRichard Röjfors 676e1d5b659SRichard Röjfors static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 677e1d5b659SRichard Röjfors { 678e1d5b659SRichard Röjfors struct xiic_i2c *i2c = i2c_get_adapdata(adap); 679e1d5b659SRichard Röjfors int err; 680e1d5b659SRichard Röjfors 681e1d5b659SRichard Röjfors dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 682e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 683e1d5b659SRichard Röjfors 68436ecbcabSShubhrajyoti Datta err = pm_runtime_get_sync(i2c->dev); 68536ecbcabSShubhrajyoti Datta if (err < 0) 68636ecbcabSShubhrajyoti Datta return err; 68736ecbcabSShubhrajyoti Datta 688e1d5b659SRichard Röjfors err = xiic_busy(i2c); 689e1d5b659SRichard Röjfors if (err) 69036ecbcabSShubhrajyoti Datta goto out; 691e1d5b659SRichard Röjfors 692e1d5b659SRichard Röjfors i2c->tx_msg = msgs; 693e1d5b659SRichard Röjfors i2c->nmsgs = num; 694e1d5b659SRichard Röjfors 695e1d5b659SRichard Röjfors xiic_start_xfer(i2c); 696e1d5b659SRichard Röjfors 697e1d5b659SRichard Röjfors if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 69836ecbcabSShubhrajyoti Datta (i2c->state == STATE_DONE), HZ)) { 69936ecbcabSShubhrajyoti Datta err = (i2c->state == STATE_DONE) ? num : -EIO; 70036ecbcabSShubhrajyoti Datta goto out; 70136ecbcabSShubhrajyoti Datta } else { 702e1d5b659SRichard Röjfors i2c->tx_msg = NULL; 703e1d5b659SRichard Röjfors i2c->rx_msg = NULL; 704e1d5b659SRichard Röjfors i2c->nmsgs = 0; 70536ecbcabSShubhrajyoti Datta err = -ETIMEDOUT; 70636ecbcabSShubhrajyoti Datta goto out; 707e1d5b659SRichard Röjfors } 70836ecbcabSShubhrajyoti Datta out: 70936ecbcabSShubhrajyoti Datta pm_runtime_mark_last_busy(i2c->dev); 71036ecbcabSShubhrajyoti Datta pm_runtime_put_autosuspend(i2c->dev); 71136ecbcabSShubhrajyoti Datta return err; 712e1d5b659SRichard Röjfors } 713e1d5b659SRichard Röjfors 714e1d5b659SRichard Röjfors static u32 xiic_func(struct i2c_adapter *adap) 715e1d5b659SRichard Röjfors { 716e1d5b659SRichard Röjfors return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 717e1d5b659SRichard Röjfors } 718e1d5b659SRichard Röjfors 719e1d5b659SRichard Röjfors static const struct i2c_algorithm xiic_algorithm = { 720e1d5b659SRichard Röjfors .master_xfer = xiic_xfer, 721e1d5b659SRichard Röjfors .functionality = xiic_func, 722e1d5b659SRichard Röjfors }; 723e1d5b659SRichard Röjfors 724e1d5b659SRichard Röjfors static struct i2c_adapter xiic_adapter = { 725e1d5b659SRichard Röjfors .owner = THIS_MODULE, 726e1d5b659SRichard Röjfors .name = DRIVER_NAME, 7274db5beedSWolfram Sang .class = I2C_CLASS_DEPRECATED, 728e1d5b659SRichard Röjfors .algo = &xiic_algorithm, 729e1d5b659SRichard Röjfors }; 730e1d5b659SRichard Röjfors 731e1d5b659SRichard Röjfors 7320b255e92SBill Pemberton static int xiic_i2c_probe(struct platform_device *pdev) 733e1d5b659SRichard Röjfors { 734e1d5b659SRichard Röjfors struct xiic_i2c *i2c; 735e1d5b659SRichard Röjfors struct xiic_i2c_platform_data *pdata; 736e1d5b659SRichard Röjfors struct resource *res; 737e1d5b659SRichard Röjfors int ret, irq; 738e1d5b659SRichard Röjfors u8 i; 73948ef3ca9SThomas Gessler u32 sr; 740e1d5b659SRichard Röjfors 741168e722dSKedareswara rao Appana i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 742e1d5b659SRichard Röjfors if (!i2c) 743e1d5b659SRichard Röjfors return -ENOMEM; 744e1d5b659SRichard Röjfors 745168e722dSKedareswara rao Appana res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 746168e722dSKedareswara rao Appana i2c->base = devm_ioremap_resource(&pdev->dev, res); 747168e722dSKedareswara rao Appana if (IS_ERR(i2c->base)) 748168e722dSKedareswara rao Appana return PTR_ERR(i2c->base); 749e1d5b659SRichard Röjfors 750168e722dSKedareswara rao Appana irq = platform_get_irq(pdev, 0); 751168e722dSKedareswara rao Appana if (irq < 0) 752168e722dSKedareswara rao Appana return irq; 753168e722dSKedareswara rao Appana 754168e722dSKedareswara rao Appana pdata = dev_get_platdata(&pdev->dev); 755e1d5b659SRichard Röjfors 756e1d5b659SRichard Röjfors /* hook up driver to tree */ 757e1d5b659SRichard Röjfors platform_set_drvdata(pdev, i2c); 758e1d5b659SRichard Röjfors i2c->adap = xiic_adapter; 759e1d5b659SRichard Röjfors i2c_set_adapdata(&i2c->adap, i2c); 760e1d5b659SRichard Röjfors i2c->adap.dev.parent = &pdev->dev; 7613ac0b337SLars-Peter Clausen i2c->adap.dev.of_node = pdev->dev.of_node; 762e1d5b659SRichard Röjfors 76377c68019SLars-Peter Clausen mutex_init(&i2c->lock); 764e1d5b659SRichard Röjfors init_waitqueue_head(&i2c->wait); 765168e722dSKedareswara rao Appana 76636ecbcabSShubhrajyoti Datta i2c->clk = devm_clk_get(&pdev->dev, NULL); 76736ecbcabSShubhrajyoti Datta if (IS_ERR(i2c->clk)) { 76836ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "input clock not found.\n"); 76936ecbcabSShubhrajyoti Datta return PTR_ERR(i2c->clk); 77036ecbcabSShubhrajyoti Datta } 77136ecbcabSShubhrajyoti Datta ret = clk_prepare_enable(i2c->clk); 77236ecbcabSShubhrajyoti Datta if (ret) { 77336ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "Unable to enable clock.\n"); 77436ecbcabSShubhrajyoti Datta return ret; 77536ecbcabSShubhrajyoti Datta } 77636ecbcabSShubhrajyoti Datta i2c->dev = &pdev->dev; 77736ecbcabSShubhrajyoti Datta pm_runtime_enable(i2c->dev); 77836ecbcabSShubhrajyoti Datta pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 77936ecbcabSShubhrajyoti Datta pm_runtime_use_autosuspend(i2c->dev); 78036ecbcabSShubhrajyoti Datta pm_runtime_set_active(i2c->dev); 781fcc2fac6SShubhrajyoti Datta ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr, 782fcc2fac6SShubhrajyoti Datta xiic_process, IRQF_ONESHOT, 783fcc2fac6SShubhrajyoti Datta pdev->name, i2c); 784fcc2fac6SShubhrajyoti Datta 785168e722dSKedareswara rao Appana if (ret < 0) { 786e1d5b659SRichard Röjfors dev_err(&pdev->dev, "Cannot claim IRQ\n"); 78736ecbcabSShubhrajyoti Datta goto err_clk_dis; 788e1d5b659SRichard Röjfors } 789e1d5b659SRichard Röjfors 79048ef3ca9SThomas Gessler /* 79148ef3ca9SThomas Gessler * Detect endianness 79248ef3ca9SThomas Gessler * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 79348ef3ca9SThomas Gessler * set, assume that the endianness was wrong and swap. 79448ef3ca9SThomas Gessler */ 79548ef3ca9SThomas Gessler i2c->endianness = LITTLE; 79648ef3ca9SThomas Gessler xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 79748ef3ca9SThomas Gessler /* Reset is cleared in xiic_reinit */ 79848ef3ca9SThomas Gessler sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 79948ef3ca9SThomas Gessler if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 80048ef3ca9SThomas Gessler i2c->endianness = BIG; 80148ef3ca9SThomas Gessler 802617bdcbcSMichal Simek xiic_reinit(i2c); 803617bdcbcSMichal Simek 804e1d5b659SRichard Röjfors /* add i2c adapter to i2c tree */ 805e1d5b659SRichard Röjfors ret = i2c_add_adapter(&i2c->adap); 806e1d5b659SRichard Röjfors if (ret) { 807e1d5b659SRichard Röjfors dev_err(&pdev->dev, "Failed to add adapter\n"); 808168e722dSKedareswara rao Appana xiic_deinit(i2c); 80936ecbcabSShubhrajyoti Datta goto err_clk_dis; 810e1d5b659SRichard Röjfors } 811e1d5b659SRichard Röjfors 8123ac0b337SLars-Peter Clausen if (pdata) { 813e1d5b659SRichard Röjfors /* add in known devices to the bus */ 814e1d5b659SRichard Röjfors for (i = 0; i < pdata->num_devices; i++) 815e1d5b659SRichard Röjfors i2c_new_device(&i2c->adap, pdata->devices + i); 8163ac0b337SLars-Peter Clausen } 8173ac0b337SLars-Peter Clausen 818e1d5b659SRichard Röjfors return 0; 81936ecbcabSShubhrajyoti Datta 82036ecbcabSShubhrajyoti Datta err_clk_dis: 82136ecbcabSShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev); 82236ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 82336ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 82436ecbcabSShubhrajyoti Datta return ret; 825e1d5b659SRichard Röjfors } 826e1d5b659SRichard Röjfors 8270b255e92SBill Pemberton static int xiic_i2c_remove(struct platform_device *pdev) 828e1d5b659SRichard Röjfors { 829e1d5b659SRichard Röjfors struct xiic_i2c *i2c = platform_get_drvdata(pdev); 83036ecbcabSShubhrajyoti Datta int ret; 831e1d5b659SRichard Röjfors 832e1d5b659SRichard Röjfors /* remove adapter & data */ 833e1d5b659SRichard Röjfors i2c_del_adapter(&i2c->adap); 834e1d5b659SRichard Röjfors 83536ecbcabSShubhrajyoti Datta ret = clk_prepare_enable(i2c->clk); 83636ecbcabSShubhrajyoti Datta if (ret) { 83736ecbcabSShubhrajyoti Datta dev_err(&pdev->dev, "Unable to enable clock.\n"); 83836ecbcabSShubhrajyoti Datta return ret; 83936ecbcabSShubhrajyoti Datta } 840e1d5b659SRichard Röjfors xiic_deinit(i2c); 84136ecbcabSShubhrajyoti Datta clk_disable_unprepare(i2c->clk); 84236ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev); 843e1d5b659SRichard Röjfors 844e1d5b659SRichard Röjfors return 0; 845e1d5b659SRichard Röjfors } 846e1d5b659SRichard Röjfors 8473ac0b337SLars-Peter Clausen #if defined(CONFIG_OF) 8480b255e92SBill Pemberton static const struct of_device_id xiic_of_match[] = { 8493ac0b337SLars-Peter Clausen { .compatible = "xlnx,xps-iic-2.00.a", }, 8503ac0b337SLars-Peter Clausen {}, 8513ac0b337SLars-Peter Clausen }; 8523ac0b337SLars-Peter Clausen MODULE_DEVICE_TABLE(of, xiic_of_match); 8533ac0b337SLars-Peter Clausen #endif 8543ac0b337SLars-Peter Clausen 85536ecbcabSShubhrajyoti Datta static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) 85636ecbcabSShubhrajyoti Datta { 85736ecbcabSShubhrajyoti Datta struct platform_device *pdev = to_platform_device(dev); 85836ecbcabSShubhrajyoti Datta struct xiic_i2c *i2c = platform_get_drvdata(pdev); 85936ecbcabSShubhrajyoti Datta 86036ecbcabSShubhrajyoti Datta clk_disable(i2c->clk); 86136ecbcabSShubhrajyoti Datta 86236ecbcabSShubhrajyoti Datta return 0; 86336ecbcabSShubhrajyoti Datta } 86436ecbcabSShubhrajyoti Datta 86536ecbcabSShubhrajyoti Datta static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) 86636ecbcabSShubhrajyoti Datta { 86736ecbcabSShubhrajyoti Datta struct platform_device *pdev = to_platform_device(dev); 86836ecbcabSShubhrajyoti Datta struct xiic_i2c *i2c = platform_get_drvdata(pdev); 86936ecbcabSShubhrajyoti Datta int ret; 87036ecbcabSShubhrajyoti Datta 87136ecbcabSShubhrajyoti Datta ret = clk_enable(i2c->clk); 87236ecbcabSShubhrajyoti Datta if (ret) { 87336ecbcabSShubhrajyoti Datta dev_err(dev, "Cannot enable clock.\n"); 87436ecbcabSShubhrajyoti Datta return ret; 87536ecbcabSShubhrajyoti Datta } 87636ecbcabSShubhrajyoti Datta 87736ecbcabSShubhrajyoti Datta return 0; 87836ecbcabSShubhrajyoti Datta } 87936ecbcabSShubhrajyoti Datta 88036ecbcabSShubhrajyoti Datta static const struct dev_pm_ops xiic_dev_pm_ops = { 88136ecbcabSShubhrajyoti Datta SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, 88236ecbcabSShubhrajyoti Datta cdns_i2c_runtime_resume, NULL) 88336ecbcabSShubhrajyoti Datta }; 884e1d5b659SRichard Röjfors static struct platform_driver xiic_i2c_driver = { 885e1d5b659SRichard Röjfors .probe = xiic_i2c_probe, 8860b255e92SBill Pemberton .remove = xiic_i2c_remove, 887e1d5b659SRichard Röjfors .driver = { 888e1d5b659SRichard Röjfors .name = DRIVER_NAME, 8893ac0b337SLars-Peter Clausen .of_match_table = of_match_ptr(xiic_of_match), 89036ecbcabSShubhrajyoti Datta .pm = &xiic_dev_pm_ops, 891e1d5b659SRichard Röjfors }, 892e1d5b659SRichard Röjfors }; 893e1d5b659SRichard Röjfors 894a3664b51SAxel Lin module_platform_driver(xiic_i2c_driver); 895e1d5b659SRichard Röjfors 896e1d5b659SRichard Röjfors MODULE_AUTHOR("info@mocean-labs.com"); 897e1d5b659SRichard Röjfors MODULE_DESCRIPTION("Xilinx I2C bus driver"); 898e1d5b659SRichard Röjfors MODULE_LICENSE("GPL v2"); 899a3664b51SAxel Lin MODULE_ALIAS("platform:"DRIVER_NAME); 900