1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Wondermedia I2C Master Mode Driver 4 * 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 6 * 7 * Derived from GPLv2+ licensed source: 8 * - Copyright (C) 2008 WonderMedia Technologies, Inc. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/platform_device.h> 22 23 #define REG_CR 0x00 24 #define REG_TCR 0x02 25 #define REG_CSR 0x04 26 #define REG_ISR 0x06 27 #define REG_IMR 0x08 28 #define REG_CDR 0x0A 29 #define REG_TR 0x0C 30 #define REG_MCR 0x0E 31 #define REG_SLAVE_CR 0x10 32 #define REG_SLAVE_SR 0x12 33 #define REG_SLAVE_ISR 0x14 34 #define REG_SLAVE_IMR 0x16 35 #define REG_SLAVE_DR 0x18 36 #define REG_SLAVE_TR 0x1A 37 38 /* REG_CR Bit fields */ 39 #define CR_TX_NEXT_ACK 0x0000 40 #define CR_ENABLE 0x0001 41 #define CR_TX_NEXT_NO_ACK 0x0002 42 #define CR_TX_END 0x0004 43 #define CR_CPU_RDY 0x0008 44 #define SLAV_MODE_SEL 0x8000 45 46 /* REG_TCR Bit fields */ 47 #define TCR_STANDARD_MODE 0x0000 48 #define TCR_MASTER_WRITE 0x0000 49 #define TCR_HS_MODE 0x2000 50 #define TCR_MASTER_READ 0x4000 51 #define TCR_FAST_MODE 0x8000 52 #define TCR_SLAVE_ADDR_MASK 0x007F 53 54 /* REG_ISR Bit fields */ 55 #define ISR_NACK_ADDR 0x0001 56 #define ISR_BYTE_END 0x0002 57 #define ISR_SCL_TIMEOUT 0x0004 58 #define ISR_WRITE_ALL 0x0007 59 60 /* REG_IMR Bit fields */ 61 #define IMR_ENABLE_ALL 0x0007 62 63 /* REG_CSR Bit fields */ 64 #define CSR_RCV_NOT_ACK 0x0001 65 #define CSR_RCV_ACK_MASK 0x0001 66 #define CSR_READY_MASK 0x0002 67 68 /* REG_TR */ 69 #define SCL_TIMEOUT(x) (((x) & 0xFF) << 8) 70 #define TR_STD 0x0064 71 #define TR_HS 0x0019 72 73 /* REG_MCR */ 74 #define MCR_APB_96M 7 75 #define MCR_APB_166M 12 76 77 #define I2C_MODE_STANDARD 0 78 #define I2C_MODE_FAST 1 79 80 #define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000)) 81 82 struct wmt_i2c_dev { 83 struct i2c_adapter adapter; 84 struct completion complete; 85 struct device *dev; 86 void __iomem *base; 87 struct clk *clk; 88 int mode; 89 int irq; 90 u16 cmd_status; 91 }; 92 93 static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev) 94 { 95 unsigned long timeout; 96 97 timeout = jiffies + WMT_I2C_TIMEOUT; 98 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { 99 if (time_after(jiffies, timeout)) { 100 dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n"); 101 return -EBUSY; 102 } 103 msleep(20); 104 } 105 106 return 0; 107 } 108 109 static int wmt_check_status(struct wmt_i2c_dev *i2c_dev) 110 { 111 int ret = 0; 112 113 if (i2c_dev->cmd_status & ISR_NACK_ADDR) 114 ret = -EIO; 115 116 if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT) 117 ret = -ETIMEDOUT; 118 119 return ret; 120 } 121 122 static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg, 123 int last) 124 { 125 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 126 u16 val, tcr_val; 127 int ret; 128 unsigned long wait_result; 129 int xfer_len = 0; 130 131 if (!(pmsg->flags & I2C_M_NOSTART)) { 132 ret = wmt_i2c_wait_bus_not_busy(i2c_dev); 133 if (ret < 0) 134 return ret; 135 } 136 137 if (pmsg->len == 0) { 138 /* 139 * We still need to run through the while (..) once, so 140 * start at -1 and break out early from the loop 141 */ 142 xfer_len = -1; 143 writew(0, i2c_dev->base + REG_CDR); 144 } else { 145 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); 146 } 147 148 if (!(pmsg->flags & I2C_M_NOSTART)) { 149 val = readw(i2c_dev->base + REG_CR); 150 val &= ~CR_TX_END; 151 writew(val, i2c_dev->base + REG_CR); 152 153 val = readw(i2c_dev->base + REG_CR); 154 val |= CR_CPU_RDY; 155 writew(val, i2c_dev->base + REG_CR); 156 } 157 158 reinit_completion(&i2c_dev->complete); 159 160 if (i2c_dev->mode == I2C_MODE_STANDARD) 161 tcr_val = TCR_STANDARD_MODE; 162 else 163 tcr_val = TCR_FAST_MODE; 164 165 tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK)); 166 167 writew(tcr_val, i2c_dev->base + REG_TCR); 168 169 if (pmsg->flags & I2C_M_NOSTART) { 170 val = readw(i2c_dev->base + REG_CR); 171 val |= CR_CPU_RDY; 172 writew(val, i2c_dev->base + REG_CR); 173 } 174 175 while (xfer_len < pmsg->len) { 176 wait_result = wait_for_completion_timeout(&i2c_dev->complete, 177 msecs_to_jiffies(500)); 178 179 if (wait_result == 0) 180 return -ETIMEDOUT; 181 182 ret = wmt_check_status(i2c_dev); 183 if (ret) 184 return ret; 185 186 xfer_len++; 187 188 val = readw(i2c_dev->base + REG_CSR); 189 if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) { 190 dev_dbg(i2c_dev->dev, "write RCV NACK error\n"); 191 return -EIO; 192 } 193 194 if (pmsg->len == 0) { 195 val = CR_TX_END | CR_CPU_RDY | CR_ENABLE; 196 writew(val, i2c_dev->base + REG_CR); 197 break; 198 } 199 200 if (xfer_len == pmsg->len) { 201 if (last != 1) 202 writew(CR_ENABLE, i2c_dev->base + REG_CR); 203 } else { 204 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + 205 REG_CDR); 206 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); 207 } 208 } 209 210 return 0; 211 } 212 213 static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg, 214 int last) 215 { 216 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 217 u16 val, tcr_val; 218 int ret; 219 unsigned long wait_result; 220 u32 xfer_len = 0; 221 222 if (!(pmsg->flags & I2C_M_NOSTART)) { 223 ret = wmt_i2c_wait_bus_not_busy(i2c_dev); 224 if (ret < 0) 225 return ret; 226 } 227 228 val = readw(i2c_dev->base + REG_CR); 229 val &= ~CR_TX_END; 230 writew(val, i2c_dev->base + REG_CR); 231 232 val = readw(i2c_dev->base + REG_CR); 233 val &= ~CR_TX_NEXT_NO_ACK; 234 writew(val, i2c_dev->base + REG_CR); 235 236 if (!(pmsg->flags & I2C_M_NOSTART)) { 237 val = readw(i2c_dev->base + REG_CR); 238 val |= CR_CPU_RDY; 239 writew(val, i2c_dev->base + REG_CR); 240 } 241 242 if (pmsg->len == 1) { 243 val = readw(i2c_dev->base + REG_CR); 244 val |= CR_TX_NEXT_NO_ACK; 245 writew(val, i2c_dev->base + REG_CR); 246 } 247 248 reinit_completion(&i2c_dev->complete); 249 250 if (i2c_dev->mode == I2C_MODE_STANDARD) 251 tcr_val = TCR_STANDARD_MODE; 252 else 253 tcr_val = TCR_FAST_MODE; 254 255 tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK); 256 257 writew(tcr_val, i2c_dev->base + REG_TCR); 258 259 if (pmsg->flags & I2C_M_NOSTART) { 260 val = readw(i2c_dev->base + REG_CR); 261 val |= CR_CPU_RDY; 262 writew(val, i2c_dev->base + REG_CR); 263 } 264 265 while (xfer_len < pmsg->len) { 266 wait_result = wait_for_completion_timeout(&i2c_dev->complete, 267 msecs_to_jiffies(500)); 268 269 if (!wait_result) 270 return -ETIMEDOUT; 271 272 ret = wmt_check_status(i2c_dev); 273 if (ret) 274 return ret; 275 276 pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8; 277 xfer_len++; 278 279 if (xfer_len == pmsg->len - 1) { 280 val = readw(i2c_dev->base + REG_CR); 281 val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY); 282 writew(val, i2c_dev->base + REG_CR); 283 } else { 284 val = readw(i2c_dev->base + REG_CR); 285 val |= CR_CPU_RDY; 286 writew(val, i2c_dev->base + REG_CR); 287 } 288 } 289 290 return 0; 291 } 292 293 static int wmt_i2c_xfer(struct i2c_adapter *adap, 294 struct i2c_msg msgs[], 295 int num) 296 { 297 struct i2c_msg *pmsg; 298 int i, is_last; 299 int ret = 0; 300 301 for (i = 0; ret >= 0 && i < num; i++) { 302 is_last = ((i + 1) == num); 303 304 pmsg = &msgs[i]; 305 if (pmsg->flags & I2C_M_RD) 306 ret = wmt_i2c_read(adap, pmsg, is_last); 307 else 308 ret = wmt_i2c_write(adap, pmsg, is_last); 309 } 310 311 return (ret < 0) ? ret : i; 312 } 313 314 static u32 wmt_i2c_func(struct i2c_adapter *adap) 315 { 316 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART; 317 } 318 319 static const struct i2c_algorithm wmt_i2c_algo = { 320 .master_xfer = wmt_i2c_xfer, 321 .functionality = wmt_i2c_func, 322 }; 323 324 static irqreturn_t wmt_i2c_isr(int irq, void *data) 325 { 326 struct wmt_i2c_dev *i2c_dev = data; 327 328 /* save the status and write-clear it */ 329 i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR); 330 writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR); 331 332 complete(&i2c_dev->complete); 333 334 return IRQ_HANDLED; 335 } 336 337 static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev) 338 { 339 int err; 340 341 err = clk_prepare_enable(i2c_dev->clk); 342 if (err) { 343 dev_err(i2c_dev->dev, "failed to enable clock\n"); 344 return err; 345 } 346 347 err = clk_set_rate(i2c_dev->clk, 20000000); 348 if (err) { 349 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n"); 350 clk_disable_unprepare(i2c_dev->clk); 351 return err; 352 } 353 354 writew(0, i2c_dev->base + REG_CR); 355 writew(MCR_APB_166M, i2c_dev->base + REG_MCR); 356 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); 357 writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR); 358 writew(CR_ENABLE, i2c_dev->base + REG_CR); 359 readw(i2c_dev->base + REG_CSR); /* read clear */ 360 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); 361 362 if (i2c_dev->mode == I2C_MODE_STANDARD) 363 writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR); 364 else 365 writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR); 366 367 return 0; 368 } 369 370 static int wmt_i2c_probe(struct platform_device *pdev) 371 { 372 struct device_node *np = pdev->dev.of_node; 373 struct wmt_i2c_dev *i2c_dev; 374 struct i2c_adapter *adap; 375 struct resource *res; 376 int err; 377 u32 clk_rate; 378 379 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 380 if (!i2c_dev) 381 return -ENOMEM; 382 383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 384 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 385 if (IS_ERR(i2c_dev->base)) 386 return PTR_ERR(i2c_dev->base); 387 388 i2c_dev->irq = irq_of_parse_and_map(np, 0); 389 if (!i2c_dev->irq) { 390 dev_err(&pdev->dev, "irq missing or invalid\n"); 391 return -EINVAL; 392 } 393 394 i2c_dev->clk = of_clk_get(np, 0); 395 if (IS_ERR(i2c_dev->clk)) { 396 dev_err(&pdev->dev, "unable to request clock\n"); 397 return PTR_ERR(i2c_dev->clk); 398 } 399 400 i2c_dev->mode = I2C_MODE_STANDARD; 401 err = of_property_read_u32(np, "clock-frequency", &clk_rate); 402 if ((!err) && (clk_rate == 400000)) 403 i2c_dev->mode = I2C_MODE_FAST; 404 405 i2c_dev->dev = &pdev->dev; 406 407 err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0, 408 "i2c", i2c_dev); 409 if (err) { 410 dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq); 411 return err; 412 } 413 414 adap = &i2c_dev->adapter; 415 i2c_set_adapdata(adap, i2c_dev); 416 strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); 417 adap->owner = THIS_MODULE; 418 adap->algo = &wmt_i2c_algo; 419 adap->dev.parent = &pdev->dev; 420 adap->dev.of_node = pdev->dev.of_node; 421 422 init_completion(&i2c_dev->complete); 423 424 err = wmt_i2c_reset_hardware(i2c_dev); 425 if (err) { 426 dev_err(&pdev->dev, "error initializing hardware\n"); 427 return err; 428 } 429 430 err = i2c_add_adapter(adap); 431 if (err) 432 return err; 433 434 platform_set_drvdata(pdev, i2c_dev); 435 436 return 0; 437 } 438 439 static int wmt_i2c_remove(struct platform_device *pdev) 440 { 441 struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 442 443 /* Disable interrupts, clock and delete adapter */ 444 writew(0, i2c_dev->base + REG_IMR); 445 clk_disable_unprepare(i2c_dev->clk); 446 i2c_del_adapter(&i2c_dev->adapter); 447 448 return 0; 449 } 450 451 static const struct of_device_id wmt_i2c_dt_ids[] = { 452 { .compatible = "wm,wm8505-i2c" }, 453 { /* Sentinel */ }, 454 }; 455 456 static struct platform_driver wmt_i2c_driver = { 457 .probe = wmt_i2c_probe, 458 .remove = wmt_i2c_remove, 459 .driver = { 460 .name = "wmt-i2c", 461 .of_match_table = wmt_i2c_dt_ids, 462 }, 463 }; 464 465 module_platform_driver(wmt_i2c_driver); 466 467 MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter"); 468 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); 469 MODULE_LICENSE("GPL"); 470 MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids); 471