1 /* 2 * Wondermedia I2C Master Mode Driver 3 * 4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 5 * 6 * Derived from GPLv2+ licensed source: 7 * - Copyright (C) 2008 WonderMedia Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2, or 11 * (at your option) any later version. as published by the Free Software 12 * Foundation 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/i2c.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/platform_device.h> 26 27 #define REG_CR 0x00 28 #define REG_TCR 0x02 29 #define REG_CSR 0x04 30 #define REG_ISR 0x06 31 #define REG_IMR 0x08 32 #define REG_CDR 0x0A 33 #define REG_TR 0x0C 34 #define REG_MCR 0x0E 35 #define REG_SLAVE_CR 0x10 36 #define REG_SLAVE_SR 0x12 37 #define REG_SLAVE_ISR 0x14 38 #define REG_SLAVE_IMR 0x16 39 #define REG_SLAVE_DR 0x18 40 #define REG_SLAVE_TR 0x1A 41 42 /* REG_CR Bit fields */ 43 #define CR_TX_NEXT_ACK 0x0000 44 #define CR_ENABLE 0x0001 45 #define CR_TX_NEXT_NO_ACK 0x0002 46 #define CR_TX_END 0x0004 47 #define CR_CPU_RDY 0x0008 48 #define SLAV_MODE_SEL 0x8000 49 50 /* REG_TCR Bit fields */ 51 #define TCR_STANDARD_MODE 0x0000 52 #define TCR_MASTER_WRITE 0x0000 53 #define TCR_HS_MODE 0x2000 54 #define TCR_MASTER_READ 0x4000 55 #define TCR_FAST_MODE 0x8000 56 #define TCR_SLAVE_ADDR_MASK 0x007F 57 58 /* REG_ISR Bit fields */ 59 #define ISR_NACK_ADDR 0x0001 60 #define ISR_BYTE_END 0x0002 61 #define ISR_SCL_TIMEOUT 0x0004 62 #define ISR_WRITE_ALL 0x0007 63 64 /* REG_IMR Bit fields */ 65 #define IMR_ENABLE_ALL 0x0007 66 67 /* REG_CSR Bit fields */ 68 #define CSR_RCV_NOT_ACK 0x0001 69 #define CSR_RCV_ACK_MASK 0x0001 70 #define CSR_READY_MASK 0x0002 71 72 /* REG_TR */ 73 #define SCL_TIMEOUT(x) (((x) & 0xFF) << 8) 74 #define TR_STD 0x0064 75 #define TR_HS 0x0019 76 77 /* REG_MCR */ 78 #define MCR_APB_96M 7 79 #define MCR_APB_166M 12 80 81 #define I2C_MODE_STANDARD 0 82 #define I2C_MODE_FAST 1 83 84 #define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000)) 85 86 struct wmt_i2c_dev { 87 struct i2c_adapter adapter; 88 struct completion complete; 89 struct device *dev; 90 void __iomem *base; 91 struct clk *clk; 92 int mode; 93 int irq; 94 u16 cmd_status; 95 }; 96 97 static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev) 98 { 99 unsigned long timeout; 100 101 timeout = jiffies + WMT_I2C_TIMEOUT; 102 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { 103 if (time_after(jiffies, timeout)) { 104 dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n"); 105 return -EBUSY; 106 } 107 msleep(20); 108 } 109 110 return 0; 111 } 112 113 static int wmt_check_status(struct wmt_i2c_dev *i2c_dev) 114 { 115 int ret = 0; 116 117 if (i2c_dev->cmd_status & ISR_NACK_ADDR) 118 ret = -EIO; 119 120 if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT) 121 ret = -ETIMEDOUT; 122 123 return ret; 124 } 125 126 static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg, 127 int last) 128 { 129 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 130 u16 val, tcr_val; 131 int ret, wait_result; 132 int xfer_len = 0; 133 134 if (!(pmsg->flags & I2C_M_NOSTART)) { 135 ret = wmt_i2c_wait_bus_not_busy(i2c_dev); 136 if (ret < 0) 137 return ret; 138 } 139 140 if (pmsg->len == 0) { 141 /* 142 * We still need to run through the while (..) once, so 143 * start at -1 and break out early from the loop 144 */ 145 xfer_len = -1; 146 writew(0, i2c_dev->base + REG_CDR); 147 } else { 148 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); 149 } 150 151 if (!(pmsg->flags & I2C_M_NOSTART)) { 152 val = readw(i2c_dev->base + REG_CR); 153 val &= ~CR_TX_END; 154 writew(val, i2c_dev->base + REG_CR); 155 156 val = readw(i2c_dev->base + REG_CR); 157 val |= CR_CPU_RDY; 158 writew(val, i2c_dev->base + REG_CR); 159 } 160 161 reinit_completion(&i2c_dev->complete); 162 163 if (i2c_dev->mode == I2C_MODE_STANDARD) 164 tcr_val = TCR_STANDARD_MODE; 165 else 166 tcr_val = TCR_FAST_MODE; 167 168 tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK)); 169 170 writew(tcr_val, i2c_dev->base + REG_TCR); 171 172 if (pmsg->flags & I2C_M_NOSTART) { 173 val = readw(i2c_dev->base + REG_CR); 174 val |= CR_CPU_RDY; 175 writew(val, i2c_dev->base + REG_CR); 176 } 177 178 while (xfer_len < pmsg->len) { 179 wait_result = wait_for_completion_timeout(&i2c_dev->complete, 180 500 * HZ / 1000); 181 182 if (wait_result == 0) 183 return -ETIMEDOUT; 184 185 ret = wmt_check_status(i2c_dev); 186 if (ret) 187 return ret; 188 189 xfer_len++; 190 191 val = readw(i2c_dev->base + REG_CSR); 192 if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) { 193 dev_dbg(i2c_dev->dev, "write RCV NACK error\n"); 194 return -EIO; 195 } 196 197 if (pmsg->len == 0) { 198 val = CR_TX_END | CR_CPU_RDY | CR_ENABLE; 199 writew(val, i2c_dev->base + REG_CR); 200 break; 201 } 202 203 if (xfer_len == pmsg->len) { 204 if (last != 1) 205 writew(CR_ENABLE, i2c_dev->base + REG_CR); 206 } else { 207 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + 208 REG_CDR); 209 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); 210 } 211 } 212 213 return 0; 214 } 215 216 static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg, 217 int last) 218 { 219 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 220 u16 val, tcr_val; 221 int ret, wait_result; 222 u32 xfer_len = 0; 223 224 if (!(pmsg->flags & I2C_M_NOSTART)) { 225 ret = wmt_i2c_wait_bus_not_busy(i2c_dev); 226 if (ret < 0) 227 return ret; 228 } 229 230 val = readw(i2c_dev->base + REG_CR); 231 val &= ~CR_TX_END; 232 writew(val, i2c_dev->base + REG_CR); 233 234 val = readw(i2c_dev->base + REG_CR); 235 val &= ~CR_TX_NEXT_NO_ACK; 236 writew(val, i2c_dev->base + REG_CR); 237 238 if (!(pmsg->flags & I2C_M_NOSTART)) { 239 val = readw(i2c_dev->base + REG_CR); 240 val |= CR_CPU_RDY; 241 writew(val, i2c_dev->base + REG_CR); 242 } 243 244 if (pmsg->len == 1) { 245 val = readw(i2c_dev->base + REG_CR); 246 val |= CR_TX_NEXT_NO_ACK; 247 writew(val, i2c_dev->base + REG_CR); 248 } 249 250 reinit_completion(&i2c_dev->complete); 251 252 if (i2c_dev->mode == I2C_MODE_STANDARD) 253 tcr_val = TCR_STANDARD_MODE; 254 else 255 tcr_val = TCR_FAST_MODE; 256 257 tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK); 258 259 writew(tcr_val, i2c_dev->base + REG_TCR); 260 261 if (pmsg->flags & I2C_M_NOSTART) { 262 val = readw(i2c_dev->base + REG_CR); 263 val |= CR_CPU_RDY; 264 writew(val, i2c_dev->base + REG_CR); 265 } 266 267 while (xfer_len < pmsg->len) { 268 wait_result = wait_for_completion_timeout(&i2c_dev->complete, 269 500 * HZ / 1000); 270 271 if (!wait_result) 272 return -ETIMEDOUT; 273 274 ret = wmt_check_status(i2c_dev); 275 if (ret) 276 return ret; 277 278 pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8; 279 xfer_len++; 280 281 if (xfer_len == pmsg->len - 1) { 282 val = readw(i2c_dev->base + REG_CR); 283 val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY); 284 writew(val, i2c_dev->base + REG_CR); 285 } else { 286 val = readw(i2c_dev->base + REG_CR); 287 val |= CR_CPU_RDY; 288 writew(val, i2c_dev->base + REG_CR); 289 } 290 } 291 292 return 0; 293 } 294 295 static int wmt_i2c_xfer(struct i2c_adapter *adap, 296 struct i2c_msg msgs[], 297 int num) 298 { 299 struct i2c_msg *pmsg; 300 int i, is_last; 301 int ret = 0; 302 303 for (i = 0; ret >= 0 && i < num; i++) { 304 is_last = ((i + 1) == num); 305 306 pmsg = &msgs[i]; 307 if (pmsg->flags & I2C_M_RD) 308 ret = wmt_i2c_read(adap, pmsg, is_last); 309 else 310 ret = wmt_i2c_write(adap, pmsg, is_last); 311 } 312 313 return (ret < 0) ? ret : i; 314 } 315 316 static u32 wmt_i2c_func(struct i2c_adapter *adap) 317 { 318 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART; 319 } 320 321 static const struct i2c_algorithm wmt_i2c_algo = { 322 .master_xfer = wmt_i2c_xfer, 323 .functionality = wmt_i2c_func, 324 }; 325 326 static irqreturn_t wmt_i2c_isr(int irq, void *data) 327 { 328 struct wmt_i2c_dev *i2c_dev = data; 329 330 /* save the status and write-clear it */ 331 i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR); 332 writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR); 333 334 complete(&i2c_dev->complete); 335 336 return IRQ_HANDLED; 337 } 338 339 static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev) 340 { 341 int err; 342 343 err = clk_prepare_enable(i2c_dev->clk); 344 if (err) { 345 dev_err(i2c_dev->dev, "failed to enable clock\n"); 346 return err; 347 } 348 349 err = clk_set_rate(i2c_dev->clk, 20000000); 350 if (err) { 351 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n"); 352 clk_disable_unprepare(i2c_dev->clk); 353 return err; 354 } 355 356 writew(0, i2c_dev->base + REG_CR); 357 writew(MCR_APB_166M, i2c_dev->base + REG_MCR); 358 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); 359 writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR); 360 writew(CR_ENABLE, i2c_dev->base + REG_CR); 361 readw(i2c_dev->base + REG_CSR); /* read clear */ 362 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); 363 364 if (i2c_dev->mode == I2C_MODE_STANDARD) 365 writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR); 366 else 367 writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR); 368 369 return 0; 370 } 371 372 static int wmt_i2c_probe(struct platform_device *pdev) 373 { 374 struct device_node *np = pdev->dev.of_node; 375 struct wmt_i2c_dev *i2c_dev; 376 struct i2c_adapter *adap; 377 struct resource *res; 378 int err; 379 u32 clk_rate; 380 381 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 382 if (!i2c_dev) 383 return -ENOMEM; 384 385 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 386 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 387 if (IS_ERR(i2c_dev->base)) 388 return PTR_ERR(i2c_dev->base); 389 390 i2c_dev->irq = irq_of_parse_and_map(np, 0); 391 if (!i2c_dev->irq) { 392 dev_err(&pdev->dev, "irq missing or invalid\n"); 393 return -EINVAL; 394 } 395 396 i2c_dev->clk = of_clk_get(np, 0); 397 if (IS_ERR(i2c_dev->clk)) { 398 dev_err(&pdev->dev, "unable to request clock\n"); 399 return PTR_ERR(i2c_dev->clk); 400 } 401 402 i2c_dev->mode = I2C_MODE_STANDARD; 403 err = of_property_read_u32(np, "clock-frequency", &clk_rate); 404 if ((!err) && (clk_rate == 400000)) 405 i2c_dev->mode = I2C_MODE_FAST; 406 407 i2c_dev->dev = &pdev->dev; 408 409 err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0, 410 "i2c", i2c_dev); 411 if (err) { 412 dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq); 413 return err; 414 } 415 416 adap = &i2c_dev->adapter; 417 i2c_set_adapdata(adap, i2c_dev); 418 strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); 419 adap->owner = THIS_MODULE; 420 adap->algo = &wmt_i2c_algo; 421 adap->dev.parent = &pdev->dev; 422 adap->dev.of_node = pdev->dev.of_node; 423 424 init_completion(&i2c_dev->complete); 425 426 err = wmt_i2c_reset_hardware(i2c_dev); 427 if (err) { 428 dev_err(&pdev->dev, "error initializing hardware\n"); 429 return err; 430 } 431 432 err = i2c_add_adapter(adap); 433 if (err) { 434 dev_err(&pdev->dev, "failed to add adapter\n"); 435 return err; 436 } 437 438 platform_set_drvdata(pdev, i2c_dev); 439 440 return 0; 441 } 442 443 static int wmt_i2c_remove(struct platform_device *pdev) 444 { 445 struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 446 447 /* Disable interrupts, clock and delete adapter */ 448 writew(0, i2c_dev->base + REG_IMR); 449 clk_disable_unprepare(i2c_dev->clk); 450 i2c_del_adapter(&i2c_dev->adapter); 451 452 return 0; 453 } 454 455 static const struct of_device_id wmt_i2c_dt_ids[] = { 456 { .compatible = "wm,wm8505-i2c" }, 457 { /* Sentinel */ }, 458 }; 459 460 static struct platform_driver wmt_i2c_driver = { 461 .probe = wmt_i2c_probe, 462 .remove = wmt_i2c_remove, 463 .driver = { 464 .name = "wmt-i2c", 465 .owner = THIS_MODULE, 466 .of_match_table = wmt_i2c_dt_ids, 467 }, 468 }; 469 470 module_platform_driver(wmt_i2c_driver); 471 472 MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter"); 473 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); 474 MODULE_LICENSE("GPL"); 475 MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids); 476