1 /*
2  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #include <linux/clk.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 
22 #define UNIPHIER_I2C_DTRM	0x00	/* TX register */
23 #define     UNIPHIER_I2C_DTRM_IRQEN	BIT(11)	/* enable interrupt */
24 #define     UNIPHIER_I2C_DTRM_STA	BIT(10)	/* start condition */
25 #define     UNIPHIER_I2C_DTRM_STO	BIT(9)	/* stop condition */
26 #define     UNIPHIER_I2C_DTRM_NACK	BIT(8)	/* do not return ACK */
27 #define     UNIPHIER_I2C_DTRM_RD	BIT(0)	/* read transaction */
28 #define UNIPHIER_I2C_DREC	0x04	/* RX register */
29 #define     UNIPHIER_I2C_DREC_MST	BIT(14)	/* 1 = master, 0 = slave */
30 #define     UNIPHIER_I2C_DREC_TX	BIT(13)	/* 1 = transmit, 0 = receive */
31 #define     UNIPHIER_I2C_DREC_STS	BIT(12)	/* stop condition detected */
32 #define     UNIPHIER_I2C_DREC_LRB	BIT(11)	/* no ACK */
33 #define     UNIPHIER_I2C_DREC_LAB	BIT(9)	/* arbitration lost */
34 #define     UNIPHIER_I2C_DREC_BBN	BIT(8)	/* bus not busy */
35 #define UNIPHIER_I2C_MYAD	0x08	/* slave address */
36 #define UNIPHIER_I2C_CLK	0x0c	/* clock frequency control */
37 #define UNIPHIER_I2C_BRST	0x10	/* bus reset */
38 #define     UNIPHIER_I2C_BRST_FOEN	BIT(1)	/* normal operation */
39 #define     UNIPHIER_I2C_BRST_RSCL	BIT(0)	/* release SCL */
40 #define UNIPHIER_I2C_HOLD	0x14	/* hold time control */
41 #define UNIPHIER_I2C_BSTS	0x18	/* bus status monitor */
42 #define     UNIPHIER_I2C_BSTS_SDA	BIT(1)	/* readback of SDA line */
43 #define     UNIPHIER_I2C_BSTS_SCL	BIT(0)	/* readback of SCL line */
44 #define UNIPHIER_I2C_NOISE	0x1c	/* noise filter control */
45 #define UNIPHIER_I2C_SETUP	0x20	/* setup time control */
46 
47 #define UNIPHIER_I2C_DEFAULT_SPEED	100000
48 #define UNIPHIER_I2C_MAX_SPEED		400000
49 
50 struct uniphier_i2c_priv {
51 	struct completion comp;
52 	struct i2c_adapter adap;
53 	void __iomem *membase;
54 	struct clk *clk;
55 	unsigned int busy_cnt;
56 	unsigned int clk_cycle;
57 };
58 
59 static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
60 {
61 	struct uniphier_i2c_priv *priv = dev_id;
62 
63 	/*
64 	 * This hardware uses edge triggered interrupt.  Do not touch the
65 	 * hardware registers in this handler to make sure to catch the next
66 	 * interrupt edge.  Just send a complete signal and return.
67 	 */
68 	complete(&priv->comp);
69 
70 	return IRQ_HANDLED;
71 }
72 
73 static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
74 				  u32 *rxdatap)
75 {
76 	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
77 	unsigned long time_left;
78 	u32 rxdata;
79 
80 	reinit_completion(&priv->comp);
81 
82 	txdata |= UNIPHIER_I2C_DTRM_IRQEN;
83 	dev_dbg(&adap->dev, "write data: 0x%04x\n", txdata);
84 	writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
85 
86 	time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
87 	if (unlikely(!time_left)) {
88 		dev_err(&adap->dev, "transaction timeout\n");
89 		return -ETIMEDOUT;
90 	}
91 
92 	rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
93 	dev_dbg(&adap->dev, "read data: 0x%04x\n", rxdata);
94 
95 	if (rxdatap)
96 		*rxdatap = rxdata;
97 
98 	return 0;
99 }
100 
101 static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
102 {
103 	u32 rxdata;
104 	int ret;
105 
106 	ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
107 	if (ret)
108 		return ret;
109 
110 	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB)) {
111 		dev_dbg(&adap->dev, "arbitration lost\n");
112 		return -EAGAIN;
113 	}
114 	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB)) {
115 		dev_dbg(&adap->dev, "could not get ACK\n");
116 		return -ENXIO;
117 	}
118 
119 	return 0;
120 }
121 
122 static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
123 			   const u8 *buf)
124 {
125 	int ret;
126 
127 	dev_dbg(&adap->dev, "start condition\n");
128 	ret = uniphier_i2c_send_byte(adap, addr << 1 |
129 				     UNIPHIER_I2C_DTRM_STA |
130 				     UNIPHIER_I2C_DTRM_NACK);
131 	if (ret)
132 		return ret;
133 
134 	while (len--) {
135 		ret = uniphier_i2c_send_byte(adap,
136 					     UNIPHIER_I2C_DTRM_NACK | *buf++);
137 		if (ret)
138 			return ret;
139 	}
140 
141 	return 0;
142 }
143 
144 static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
145 			   u8 *buf)
146 {
147 	int ret;
148 
149 	dev_dbg(&adap->dev, "start condition\n");
150 	ret = uniphier_i2c_send_byte(adap, addr << 1 |
151 				     UNIPHIER_I2C_DTRM_STA |
152 				     UNIPHIER_I2C_DTRM_NACK |
153 				     UNIPHIER_I2C_DTRM_RD);
154 	if (ret)
155 		return ret;
156 
157 	while (len--) {
158 		u32 rxdata;
159 
160 		ret = uniphier_i2c_xfer_byte(adap,
161 					     len ? 0 : UNIPHIER_I2C_DTRM_NACK,
162 					     &rxdata);
163 		if (ret)
164 			return ret;
165 		*buf++ = rxdata;
166 	}
167 
168 	return 0;
169 }
170 
171 static int uniphier_i2c_stop(struct i2c_adapter *adap)
172 {
173 	dev_dbg(&adap->dev, "stop condition\n");
174 	return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO |
175 				      UNIPHIER_I2C_DTRM_NACK);
176 }
177 
178 static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap,
179 					struct i2c_msg *msg, bool stop)
180 {
181 	bool is_read = msg->flags & I2C_M_RD;
182 	bool recovery = false;
183 	int ret;
184 
185 	dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
186 		is_read ? "receive" : "transmit", msg->addr, msg->len, stop);
187 
188 	if (is_read)
189 		ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
190 	else
191 		ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);
192 
193 	if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
194 		return ret;
195 
196 	if (ret == -ETIMEDOUT) {
197 		/* This error is fatal.  Needs recovery. */
198 		stop = false;
199 		recovery = true;
200 	}
201 
202 	if (stop) {
203 		int ret2 = uniphier_i2c_stop(adap);
204 
205 		if (ret2) {
206 			/* Failed to issue STOP.  The bus needs recovery. */
207 			recovery = true;
208 			ret = ret ?: ret2;
209 		}
210 	}
211 
212 	if (recovery)
213 		i2c_recover_bus(adap);
214 
215 	return ret;
216 }
217 
218 static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
219 {
220 	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
221 
222 	if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
223 						UNIPHIER_I2C_DREC_BBN)) {
224 		if (priv->busy_cnt++ > 3) {
225 			/*
226 			 * If bus busy continues too long, it is probably
227 			 * in a wrong state.  Try bus recovery.
228 			 */
229 			i2c_recover_bus(adap);
230 			priv->busy_cnt = 0;
231 		}
232 
233 		return -EAGAIN;
234 	}
235 
236 	priv->busy_cnt = 0;
237 	return 0;
238 }
239 
240 static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
241 				    struct i2c_msg *msgs, int num)
242 {
243 	struct i2c_msg *msg, *emsg = msgs + num;
244 	int ret;
245 
246 	ret = uniphier_i2c_check_bus_busy(adap);
247 	if (ret)
248 		return ret;
249 
250 	for (msg = msgs; msg < emsg; msg++) {
251 		/* Emit STOP if it is the last message or I2C_M_STOP is set. */
252 		bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
253 
254 		ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
255 		if (ret)
256 			return ret;
257 	}
258 
259 	return num;
260 }
261 
262 static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
263 {
264 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
265 }
266 
267 static const struct i2c_algorithm uniphier_i2c_algo = {
268 	.master_xfer = uniphier_i2c_master_xfer,
269 	.functionality = uniphier_i2c_functionality,
270 };
271 
272 static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
273 {
274 	u32 val = UNIPHIER_I2C_BRST_RSCL;
275 
276 	val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
277 	writel(val, priv->membase + UNIPHIER_I2C_BRST);
278 }
279 
280 static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
281 {
282 	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
283 
284 	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
285 							UNIPHIER_I2C_BSTS_SCL);
286 }
287 
288 static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
289 {
290 	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
291 
292 	writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
293 	       priv->membase + UNIPHIER_I2C_BRST);
294 }
295 
296 static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
297 {
298 	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
299 
300 	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
301 							UNIPHIER_I2C_BSTS_SDA);
302 }
303 
304 static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
305 {
306 	uniphier_i2c_reset(i2c_get_adapdata(adap), false);
307 }
308 
309 static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
310 	.recover_bus = i2c_generic_scl_recovery,
311 	.get_scl = uniphier_i2c_get_scl,
312 	.set_scl = uniphier_i2c_set_scl,
313 	.get_sda = uniphier_i2c_get_sda,
314 	.unprepare_recovery = uniphier_i2c_unprepare_recovery,
315 };
316 
317 static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
318 {
319 	unsigned int cyc = priv->clk_cycle;
320 
321 	uniphier_i2c_reset(priv, true);
322 
323 	/*
324 	 * Bit30-16: clock cycles of tLOW.
325 	 *  Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us
326 	 *  Fast-mode:     tLOW = 1.3 us, tHIGH = 0.6 us
327 	 * "tLow/tHIGH = 5/4" meets both.
328 	 */
329 	writel((cyc * 5 / 9 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK);
330 
331 	uniphier_i2c_reset(priv, false);
332 }
333 
334 static int uniphier_i2c_probe(struct platform_device *pdev)
335 {
336 	struct device *dev = &pdev->dev;
337 	struct uniphier_i2c_priv *priv;
338 	struct resource *regs;
339 	u32 bus_speed;
340 	unsigned long clk_rate;
341 	int irq, ret;
342 
343 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
344 	if (!priv)
345 		return -ENOMEM;
346 
347 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
348 	priv->membase = devm_ioremap_resource(dev, regs);
349 	if (IS_ERR(priv->membase))
350 		return PTR_ERR(priv->membase);
351 
352 	irq = platform_get_irq(pdev, 0);
353 	if (irq < 0) {
354 		dev_err(dev, "failed to get IRQ number\n");
355 		return irq;
356 	}
357 
358 	if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
359 		bus_speed = UNIPHIER_I2C_DEFAULT_SPEED;
360 
361 	if (!bus_speed || bus_speed > UNIPHIER_I2C_MAX_SPEED) {
362 		dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
363 		return -EINVAL;
364 	}
365 
366 	priv->clk = devm_clk_get(dev, NULL);
367 	if (IS_ERR(priv->clk)) {
368 		dev_err(dev, "failed to get clock\n");
369 		return PTR_ERR(priv->clk);
370 	}
371 
372 	ret = clk_prepare_enable(priv->clk);
373 	if (ret)
374 		return ret;
375 
376 	clk_rate = clk_get_rate(priv->clk);
377 	if (!clk_rate) {
378 		dev_err(dev, "input clock rate should not be zero\n");
379 		ret = -EINVAL;
380 		goto disable_clk;
381 	}
382 
383 	priv->clk_cycle = clk_rate / bus_speed;
384 	init_completion(&priv->comp);
385 	priv->adap.owner = THIS_MODULE;
386 	priv->adap.algo = &uniphier_i2c_algo;
387 	priv->adap.dev.parent = dev;
388 	priv->adap.dev.of_node = dev->of_node;
389 	strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
390 	priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
391 	i2c_set_adapdata(&priv->adap, priv);
392 	platform_set_drvdata(pdev, priv);
393 
394 	uniphier_i2c_hw_init(priv);
395 
396 	ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
397 			       priv);
398 	if (ret) {
399 		dev_err(dev, "failed to request irq %d\n", irq);
400 		goto disable_clk;
401 	}
402 
403 	ret = i2c_add_adapter(&priv->adap);
404 disable_clk:
405 	if (ret)
406 		clk_disable_unprepare(priv->clk);
407 
408 	return ret;
409 }
410 
411 static int uniphier_i2c_remove(struct platform_device *pdev)
412 {
413 	struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);
414 
415 	i2c_del_adapter(&priv->adap);
416 	clk_disable_unprepare(priv->clk);
417 
418 	return 0;
419 }
420 
421 static int __maybe_unused uniphier_i2c_suspend(struct device *dev)
422 {
423 	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
424 
425 	clk_disable_unprepare(priv->clk);
426 
427 	return 0;
428 }
429 
430 static int __maybe_unused uniphier_i2c_resume(struct device *dev)
431 {
432 	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
433 	int ret;
434 
435 	ret = clk_prepare_enable(priv->clk);
436 	if (ret)
437 		return ret;
438 
439 	uniphier_i2c_hw_init(priv);
440 
441 	return 0;
442 }
443 
444 static const struct dev_pm_ops uniphier_i2c_pm_ops = {
445 	SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
446 };
447 
448 static const struct of_device_id uniphier_i2c_match[] = {
449 	{ .compatible = "socionext,uniphier-i2c" },
450 	{ /* sentinel */ }
451 };
452 MODULE_DEVICE_TABLE(of, uniphier_i2c_match);
453 
454 static struct platform_driver uniphier_i2c_drv = {
455 	.probe  = uniphier_i2c_probe,
456 	.remove = uniphier_i2c_remove,
457 	.driver = {
458 		.name  = "uniphier-i2c",
459 		.of_match_table = uniphier_i2c_match,
460 		.pm = &uniphier_i2c_pm_ops,
461 	},
462 };
463 module_platform_driver(uniphier_i2c_drv);
464 
465 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
466 MODULE_DESCRIPTION("UniPhier I2C bus driver");
467 MODULE_LICENSE("GPL");
468