1 /* 2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/i2c.h> 17 #include <linux/iopoll.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 23 #define UNIPHIER_FI2C_CR 0x00 /* control register */ 24 #define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */ 25 #define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */ 26 #define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */ 27 #define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */ 28 #define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */ 29 #define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */ 30 #define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */ 31 #define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */ 32 #define UNIPHIER_FI2C_SLAD 0x0c /* slave address */ 33 #define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */ 34 #define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */ 35 #define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */ 36 #define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */ 37 #define UNIPHIER_FI2C_INT 0x20 /* interrupt status */ 38 #define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */ 39 #define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */ 40 #define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */ 41 #define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */ 42 #define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */ 43 #define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */ 44 #define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */ 45 #define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */ 46 #define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */ 47 #define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */ 48 #define UNIPHIER_FI2C_SR 0x2c /* status register */ 49 #define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */ 50 #define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */ 51 #define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */ 52 #define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */ 53 #define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */ 54 #define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */ 55 #define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */ 56 #define UNIPHIER_FI2C_RST 0x34 /* reset control */ 57 #define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */ 58 #define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */ 59 #define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */ 60 #define UNIPHIER_FI2C_BM 0x38 /* bus monitor */ 61 #define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */ 62 #define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */ 63 #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */ 64 #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */ 65 #define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */ 66 #define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */ 67 #define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */ 68 #define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */ 69 #define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */ 70 #define UNIPHIER_FI2C_BRST 0x50 /* bus reset */ 71 #define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */ 72 #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */ 73 74 #define UNIPHIER_FI2C_INT_FAULTS \ 75 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL) 76 #define UNIPHIER_FI2C_INT_STOP \ 77 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC) 78 79 #define UNIPHIER_FI2C_RD BIT(0) 80 #define UNIPHIER_FI2C_STOP BIT(1) 81 #define UNIPHIER_FI2C_MANUAL_NACK BIT(2) 82 #define UNIPHIER_FI2C_BYTE_WISE BIT(3) 83 #define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4) 84 85 #define UNIPHIER_FI2C_DEFAULT_SPEED 100000 86 #define UNIPHIER_FI2C_MAX_SPEED 400000 87 #define UNIPHIER_FI2C_FIFO_SIZE 8 88 89 struct uniphier_fi2c_priv { 90 struct completion comp; 91 struct i2c_adapter adap; 92 void __iomem *membase; 93 struct clk *clk; 94 unsigned int len; 95 u8 *buf; 96 u32 enabled_irqs; 97 int error; 98 unsigned int flags; 99 unsigned int busy_cnt; 100 unsigned int clk_cycle; 101 }; 102 103 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv, 104 bool first) 105 { 106 int fifo_space = UNIPHIER_FI2C_FIFO_SIZE; 107 108 /* 109 * TX-FIFO stores slave address in it for the first access. 110 * Decrement the counter. 111 */ 112 if (first) 113 fifo_space--; 114 115 while (priv->len) { 116 if (fifo_space-- <= 0) 117 break; 118 119 dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf); 120 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); 121 priv->len--; 122 } 123 } 124 125 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv) 126 { 127 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? 128 1 : UNIPHIER_FI2C_FIFO_SIZE; 129 130 while (priv->len) { 131 if (fifo_left-- <= 0) 132 break; 133 134 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); 135 dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]); 136 priv->len--; 137 } 138 } 139 140 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv) 141 { 142 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); 143 } 144 145 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv) 146 { 147 writel(-1, priv->membase + UNIPHIER_FI2C_IC); 148 } 149 150 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv) 151 { 152 dev_dbg(&priv->adap.dev, "stop condition\n"); 153 154 priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP; 155 uniphier_fi2c_set_irqs(priv); 156 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO, 157 priv->membase + UNIPHIER_FI2C_CR); 158 } 159 160 static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id) 161 { 162 struct uniphier_fi2c_priv *priv = dev_id; 163 u32 irq_status; 164 165 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); 166 167 dev_dbg(&priv->adap.dev, 168 "interrupt: enabled_irqs=%04x, irq_status=%04x\n", 169 priv->enabled_irqs, irq_status); 170 171 if (irq_status & UNIPHIER_FI2C_INT_STOP) 172 goto complete; 173 174 if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) { 175 dev_dbg(&priv->adap.dev, "arbitration lost\n"); 176 priv->error = -EAGAIN; 177 goto complete; 178 } 179 180 if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) { 181 dev_dbg(&priv->adap.dev, "could not get ACK\n"); 182 priv->error = -ENXIO; 183 if (priv->flags & UNIPHIER_FI2C_RD) { 184 /* 185 * work around a hardware bug: 186 * The receive-completed interrupt is never set even if 187 * STOP condition is detected after the address phase 188 * of read transaction fails to get ACK. 189 * To avoid time-out error, we issue STOP here, 190 * but do not wait for its completion. 191 * It should be checked after exiting this handler. 192 */ 193 uniphier_fi2c_stop(priv); 194 priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP; 195 goto complete; 196 } 197 goto stop; 198 } 199 200 if (irq_status & UNIPHIER_FI2C_INT_TE) { 201 if (!priv->len) 202 goto data_done; 203 204 uniphier_fi2c_fill_txfifo(priv, false); 205 goto handled; 206 } 207 208 if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) { 209 uniphier_fi2c_drain_rxfifo(priv); 210 if (!priv->len) 211 goto data_done; 212 213 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) { 214 if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE && 215 !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) { 216 dev_dbg(&priv->adap.dev, 217 "enable read byte count IRQ\n"); 218 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB; 219 uniphier_fi2c_set_irqs(priv); 220 priv->flags |= UNIPHIER_FI2C_BYTE_WISE; 221 } 222 if (priv->len <= 1) { 223 dev_dbg(&priv->adap.dev, "set NACK\n"); 224 writel(UNIPHIER_FI2C_CR_MST | 225 UNIPHIER_FI2C_CR_NACK, 226 priv->membase + UNIPHIER_FI2C_CR); 227 } 228 } 229 230 goto handled; 231 } 232 233 return IRQ_NONE; 234 235 data_done: 236 if (priv->flags & UNIPHIER_FI2C_STOP) { 237 stop: 238 uniphier_fi2c_stop(priv); 239 } else { 240 complete: 241 priv->enabled_irqs = 0; 242 uniphier_fi2c_set_irqs(priv); 243 complete(&priv->comp); 244 } 245 246 handled: 247 uniphier_fi2c_clear_irqs(priv); 248 249 return IRQ_HANDLED; 250 } 251 252 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr) 253 { 254 priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE; 255 /* do not use TX byte counter */ 256 writel(0, priv->membase + UNIPHIER_FI2C_TBC); 257 /* set slave address */ 258 writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1, 259 priv->membase + UNIPHIER_FI2C_DTTX); 260 /* first chunk of data */ 261 uniphier_fi2c_fill_txfifo(priv, true); 262 } 263 264 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr) 265 { 266 priv->flags |= UNIPHIER_FI2C_RD; 267 268 if (likely(priv->len < 256)) { 269 /* 270 * If possible, use RX byte counter. 271 * It can automatically handle NACK for the last byte. 272 */ 273 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC); 274 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF | 275 UNIPHIER_FI2C_INT_RB; 276 } else { 277 /* 278 * The byte counter can not count over 256. In this case, 279 * do not use it at all. Drain data when FIFO gets full, 280 * but treat the last portion as a special case. 281 */ 282 writel(0, priv->membase + UNIPHIER_FI2C_RBC); 283 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK; 284 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF; 285 } 286 287 /* set slave address with RD bit */ 288 writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1, 289 priv->membase + UNIPHIER_FI2C_DTTX); 290 } 291 292 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv) 293 { 294 writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST); 295 } 296 297 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv) 298 { 299 writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL, 300 priv->membase + UNIPHIER_FI2C_BRST); 301 } 302 303 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv) 304 { 305 uniphier_fi2c_reset(priv); 306 i2c_recover_bus(&priv->adap); 307 } 308 309 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap, 310 struct i2c_msg *msg, bool stop) 311 { 312 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 313 bool is_read = msg->flags & I2C_M_RD; 314 unsigned long time_left; 315 316 dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n", 317 is_read ? "receive" : "transmit", msg->addr, msg->len, stop); 318 319 priv->len = msg->len; 320 priv->buf = msg->buf; 321 priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS; 322 priv->error = 0; 323 priv->flags = 0; 324 325 if (stop) 326 priv->flags |= UNIPHIER_FI2C_STOP; 327 328 reinit_completion(&priv->comp); 329 uniphier_fi2c_clear_irqs(priv); 330 writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST, 331 priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */ 332 333 if (is_read) 334 uniphier_fi2c_rx_init(priv, msg->addr); 335 else 336 uniphier_fi2c_tx_init(priv, msg->addr); 337 338 uniphier_fi2c_set_irqs(priv); 339 340 dev_dbg(&adap->dev, "start condition\n"); 341 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA, 342 priv->membase + UNIPHIER_FI2C_CR); 343 344 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout); 345 if (!time_left) { 346 dev_err(&adap->dev, "transaction timeout.\n"); 347 uniphier_fi2c_recover(priv); 348 return -ETIMEDOUT; 349 } 350 dev_dbg(&adap->dev, "complete\n"); 351 352 if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) { 353 u32 status; 354 int ret; 355 356 ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR, 357 status, 358 (status & UNIPHIER_FI2C_SR_STS) && 359 !(status & UNIPHIER_FI2C_SR_BB), 360 1, 20); 361 if (ret) { 362 dev_err(&adap->dev, 363 "stop condition was not completed.\n"); 364 uniphier_fi2c_recover(priv); 365 return ret; 366 } 367 } 368 369 return priv->error; 370 } 371 372 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap) 373 { 374 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 375 376 if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) { 377 if (priv->busy_cnt++ > 3) { 378 /* 379 * If bus busy continues too long, it is probably 380 * in a wrong state. Try bus recovery. 381 */ 382 uniphier_fi2c_recover(priv); 383 priv->busy_cnt = 0; 384 } 385 386 return -EAGAIN; 387 } 388 389 priv->busy_cnt = 0; 390 return 0; 391 } 392 393 static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap, 394 struct i2c_msg *msgs, int num) 395 { 396 struct i2c_msg *msg, *emsg = msgs + num; 397 int ret; 398 399 ret = uniphier_fi2c_check_bus_busy(adap); 400 if (ret) 401 return ret; 402 403 for (msg = msgs; msg < emsg; msg++) { 404 /* If next message is read, skip the stop condition */ 405 bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD); 406 /* but, force it if I2C_M_STOP is set */ 407 if (msg->flags & I2C_M_STOP) 408 stop = true; 409 410 ret = uniphier_fi2c_master_xfer_one(adap, msg, stop); 411 if (ret) 412 return ret; 413 } 414 415 return num; 416 } 417 418 static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap) 419 { 420 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 421 } 422 423 static const struct i2c_algorithm uniphier_fi2c_algo = { 424 .master_xfer = uniphier_fi2c_master_xfer, 425 .functionality = uniphier_fi2c_functionality, 426 }; 427 428 static int uniphier_fi2c_get_scl(struct i2c_adapter *adap) 429 { 430 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 431 432 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & 433 UNIPHIER_FI2C_BM_SCLS); 434 } 435 436 static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val) 437 { 438 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 439 440 writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0, 441 priv->membase + UNIPHIER_FI2C_BRST); 442 } 443 444 static int uniphier_fi2c_get_sda(struct i2c_adapter *adap) 445 { 446 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 447 448 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & 449 UNIPHIER_FI2C_BM_SDAS); 450 } 451 452 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap) 453 { 454 uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap)); 455 } 456 457 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = { 458 .recover_bus = i2c_generic_scl_recovery, 459 .get_scl = uniphier_fi2c_get_scl, 460 .set_scl = uniphier_fi2c_set_scl, 461 .get_sda = uniphier_fi2c_get_sda, 462 .unprepare_recovery = uniphier_fi2c_unprepare_recovery, 463 }; 464 465 static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv) 466 { 467 unsigned int cyc = priv->clk_cycle; 468 u32 tmp; 469 470 tmp = readl(priv->membase + UNIPHIER_FI2C_CR); 471 tmp |= UNIPHIER_FI2C_CR_MST; 472 writel(tmp, priv->membase + UNIPHIER_FI2C_CR); 473 474 uniphier_fi2c_reset(priv); 475 476 writel(cyc, priv->membase + UNIPHIER_FI2C_CYC); 477 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_LCTL); 478 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT); 479 writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT); 480 481 uniphier_fi2c_prepare_operation(priv); 482 } 483 484 static int uniphier_fi2c_probe(struct platform_device *pdev) 485 { 486 struct device *dev = &pdev->dev; 487 struct uniphier_fi2c_priv *priv; 488 struct resource *regs; 489 u32 bus_speed; 490 unsigned long clk_rate; 491 int irq, ret; 492 493 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 494 if (!priv) 495 return -ENOMEM; 496 497 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 498 priv->membase = devm_ioremap_resource(dev, regs); 499 if (IS_ERR(priv->membase)) 500 return PTR_ERR(priv->membase); 501 502 irq = platform_get_irq(pdev, 0); 503 if (irq < 0) { 504 dev_err(dev, "failed to get IRQ number\n"); 505 return irq; 506 } 507 508 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed)) 509 bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED; 510 511 if (!bus_speed || bus_speed > UNIPHIER_FI2C_MAX_SPEED) { 512 dev_err(dev, "invalid clock-frequency %d\n", bus_speed); 513 return -EINVAL; 514 } 515 516 priv->clk = devm_clk_get(dev, NULL); 517 if (IS_ERR(priv->clk)) { 518 dev_err(dev, "failed to get clock\n"); 519 return PTR_ERR(priv->clk); 520 } 521 522 ret = clk_prepare_enable(priv->clk); 523 if (ret) 524 return ret; 525 526 clk_rate = clk_get_rate(priv->clk); 527 if (!clk_rate) { 528 dev_err(dev, "input clock rate should not be zero\n"); 529 ret = -EINVAL; 530 goto disable_clk; 531 } 532 533 priv->clk_cycle = clk_rate / bus_speed; 534 init_completion(&priv->comp); 535 priv->adap.owner = THIS_MODULE; 536 priv->adap.algo = &uniphier_fi2c_algo; 537 priv->adap.dev.parent = dev; 538 priv->adap.dev.of_node = dev->of_node; 539 strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); 540 priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; 541 i2c_set_adapdata(&priv->adap, priv); 542 platform_set_drvdata(pdev, priv); 543 544 uniphier_fi2c_hw_init(priv); 545 546 ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0, 547 pdev->name, priv); 548 if (ret) { 549 dev_err(dev, "failed to request irq %d\n", irq); 550 goto disable_clk; 551 } 552 553 ret = i2c_add_adapter(&priv->adap); 554 disable_clk: 555 if (ret) 556 clk_disable_unprepare(priv->clk); 557 558 return ret; 559 } 560 561 static int uniphier_fi2c_remove(struct platform_device *pdev) 562 { 563 struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev); 564 565 i2c_del_adapter(&priv->adap); 566 clk_disable_unprepare(priv->clk); 567 568 return 0; 569 } 570 571 static int __maybe_unused uniphier_fi2c_suspend(struct device *dev) 572 { 573 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 574 575 clk_disable_unprepare(priv->clk); 576 577 return 0; 578 } 579 580 static int __maybe_unused uniphier_fi2c_resume(struct device *dev) 581 { 582 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 583 int ret; 584 585 ret = clk_prepare_enable(priv->clk); 586 if (ret) 587 return ret; 588 589 uniphier_fi2c_hw_init(priv); 590 591 return 0; 592 } 593 594 static const struct dev_pm_ops uniphier_fi2c_pm_ops = { 595 SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume) 596 }; 597 598 static const struct of_device_id uniphier_fi2c_match[] = { 599 { .compatible = "socionext,uniphier-fi2c" }, 600 { /* sentinel */ } 601 }; 602 MODULE_DEVICE_TABLE(of, uniphier_fi2c_match); 603 604 static struct platform_driver uniphier_fi2c_drv = { 605 .probe = uniphier_fi2c_probe, 606 .remove = uniphier_fi2c_remove, 607 .driver = { 608 .name = "uniphier-fi2c", 609 .of_match_table = uniphier_fi2c_match, 610 .pm = &uniphier_fi2c_pm_ops, 611 }, 612 }; 613 module_platform_driver(uniphier_fi2c_drv); 614 615 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 616 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver"); 617 MODULE_LICENSE("GPL"); 618