1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/i2c.h> 8 #include <linux/iopoll.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #define UNIPHIER_FI2C_CR 0x00 /* control register */ 15 #define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */ 16 #define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */ 17 #define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */ 18 #define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */ 19 #define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */ 20 #define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */ 21 #define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */ 22 #define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */ 23 #define UNIPHIER_FI2C_SLAD 0x0c /* slave address */ 24 #define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */ 25 #define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */ 26 #define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */ 27 #define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */ 28 #define UNIPHIER_FI2C_INT 0x20 /* interrupt status */ 29 #define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */ 30 #define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */ 31 #define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */ 32 #define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */ 33 #define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */ 34 #define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */ 35 #define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */ 36 #define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */ 37 #define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */ 38 #define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */ 39 #define UNIPHIER_FI2C_SR 0x2c /* status register */ 40 #define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */ 41 #define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */ 42 #define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */ 43 #define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */ 44 #define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */ 45 #define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */ 46 #define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */ 47 #define UNIPHIER_FI2C_RST 0x34 /* reset control */ 48 #define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */ 49 #define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */ 50 #define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */ 51 #define UNIPHIER_FI2C_BM 0x38 /* bus monitor */ 52 #define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */ 53 #define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */ 54 #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */ 55 #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */ 56 #define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */ 57 #define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */ 58 #define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */ 59 #define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */ 60 #define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */ 61 #define UNIPHIER_FI2C_BRST 0x50 /* bus reset */ 62 #define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */ 63 #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */ 64 65 #define UNIPHIER_FI2C_INT_FAULTS \ 66 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL) 67 #define UNIPHIER_FI2C_INT_STOP \ 68 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC) 69 70 #define UNIPHIER_FI2C_RD BIT(0) 71 #define UNIPHIER_FI2C_STOP BIT(1) 72 #define UNIPHIER_FI2C_MANUAL_NACK BIT(2) 73 #define UNIPHIER_FI2C_BYTE_WISE BIT(3) 74 #define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4) 75 76 #define UNIPHIER_FI2C_DEFAULT_SPEED 100000 77 #define UNIPHIER_FI2C_MAX_SPEED 400000 78 #define UNIPHIER_FI2C_FIFO_SIZE 8 79 80 struct uniphier_fi2c_priv { 81 struct completion comp; 82 struct i2c_adapter adap; 83 void __iomem *membase; 84 struct clk *clk; 85 unsigned int len; 86 u8 *buf; 87 u32 enabled_irqs; 88 int error; 89 unsigned int flags; 90 unsigned int busy_cnt; 91 unsigned int clk_cycle; 92 spinlock_t lock; /* IRQ synchronization */ 93 }; 94 95 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv, 96 bool first) 97 { 98 int fifo_space = UNIPHIER_FI2C_FIFO_SIZE; 99 100 /* 101 * TX-FIFO stores slave address in it for the first access. 102 * Decrement the counter. 103 */ 104 if (first) 105 fifo_space--; 106 107 while (priv->len) { 108 if (fifo_space-- <= 0) 109 break; 110 111 dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf); 112 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); 113 priv->len--; 114 } 115 } 116 117 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv) 118 { 119 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? 120 1 : UNIPHIER_FI2C_FIFO_SIZE; 121 122 while (priv->len) { 123 if (fifo_left-- <= 0) 124 break; 125 126 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); 127 dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]); 128 priv->len--; 129 } 130 } 131 132 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv) 133 { 134 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); 135 } 136 137 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv, 138 u32 mask) 139 { 140 writel(mask, priv->membase + UNIPHIER_FI2C_IC); 141 } 142 143 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv) 144 { 145 dev_dbg(&priv->adap.dev, "stop condition\n"); 146 147 priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP; 148 uniphier_fi2c_set_irqs(priv); 149 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO, 150 priv->membase + UNIPHIER_FI2C_CR); 151 } 152 153 static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id) 154 { 155 struct uniphier_fi2c_priv *priv = dev_id; 156 u32 irq_status; 157 158 spin_lock(&priv->lock); 159 160 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); 161 irq_status &= priv->enabled_irqs; 162 163 dev_dbg(&priv->adap.dev, 164 "interrupt: enabled_irqs=%04x, irq_status=%04x\n", 165 priv->enabled_irqs, irq_status); 166 167 if (irq_status & UNIPHIER_FI2C_INT_STOP) 168 goto complete; 169 170 if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) { 171 dev_dbg(&priv->adap.dev, "arbitration lost\n"); 172 priv->error = -EAGAIN; 173 goto complete; 174 } 175 176 if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) { 177 dev_dbg(&priv->adap.dev, "could not get ACK\n"); 178 priv->error = -ENXIO; 179 if (priv->flags & UNIPHIER_FI2C_RD) { 180 /* 181 * work around a hardware bug: 182 * The receive-completed interrupt is never set even if 183 * STOP condition is detected after the address phase 184 * of read transaction fails to get ACK. 185 * To avoid time-out error, we issue STOP here, 186 * but do not wait for its completion. 187 * It should be checked after exiting this handler. 188 */ 189 uniphier_fi2c_stop(priv); 190 priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP; 191 goto complete; 192 } 193 goto stop; 194 } 195 196 if (irq_status & UNIPHIER_FI2C_INT_TE) { 197 if (!priv->len) 198 goto data_done; 199 200 uniphier_fi2c_fill_txfifo(priv, false); 201 goto handled; 202 } 203 204 if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) { 205 uniphier_fi2c_drain_rxfifo(priv); 206 /* 207 * If the number of bytes to read is multiple of the FIFO size 208 * (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little 209 * earlier than INT_RB. We wait for INT_RB to confirm the 210 * completion of the current message. 211 */ 212 if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB)) 213 goto data_done; 214 215 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) { 216 if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE && 217 !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) { 218 dev_dbg(&priv->adap.dev, 219 "enable read byte count IRQ\n"); 220 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB; 221 uniphier_fi2c_set_irqs(priv); 222 priv->flags |= UNIPHIER_FI2C_BYTE_WISE; 223 } 224 if (priv->len <= 1) { 225 dev_dbg(&priv->adap.dev, "set NACK\n"); 226 writel(UNIPHIER_FI2C_CR_MST | 227 UNIPHIER_FI2C_CR_NACK, 228 priv->membase + UNIPHIER_FI2C_CR); 229 } 230 } 231 232 goto handled; 233 } 234 235 spin_unlock(&priv->lock); 236 237 return IRQ_NONE; 238 239 data_done: 240 if (priv->flags & UNIPHIER_FI2C_STOP) { 241 stop: 242 uniphier_fi2c_stop(priv); 243 } else { 244 complete: 245 priv->enabled_irqs = 0; 246 uniphier_fi2c_set_irqs(priv); 247 complete(&priv->comp); 248 } 249 250 handled: 251 /* 252 * This controller makes a pause while any bit of the IRQ status is 253 * asserted. Clear the asserted bit to kick the controller just before 254 * exiting the handler. 255 */ 256 uniphier_fi2c_clear_irqs(priv, irq_status); 257 258 spin_unlock(&priv->lock); 259 260 return IRQ_HANDLED; 261 } 262 263 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr, 264 bool repeat) 265 { 266 priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE; 267 uniphier_fi2c_set_irqs(priv); 268 269 /* do not use TX byte counter */ 270 writel(0, priv->membase + UNIPHIER_FI2C_TBC); 271 /* set slave address */ 272 writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1, 273 priv->membase + UNIPHIER_FI2C_DTTX); 274 /* 275 * First chunk of data. For a repeated START condition, do not write 276 * data to the TX fifo here to avoid the timing issue. 277 */ 278 if (!repeat) 279 uniphier_fi2c_fill_txfifo(priv, true); 280 } 281 282 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr) 283 { 284 priv->flags |= UNIPHIER_FI2C_RD; 285 286 if (likely(priv->len < 256)) { 287 /* 288 * If possible, use RX byte counter. 289 * It can automatically handle NACK for the last byte. 290 */ 291 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC); 292 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF | 293 UNIPHIER_FI2C_INT_RB; 294 } else { 295 /* 296 * The byte counter can not count over 256. In this case, 297 * do not use it at all. Drain data when FIFO gets full, 298 * but treat the last portion as a special case. 299 */ 300 writel(0, priv->membase + UNIPHIER_FI2C_RBC); 301 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK; 302 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF; 303 } 304 305 uniphier_fi2c_set_irqs(priv); 306 307 /* set slave address with RD bit */ 308 writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1, 309 priv->membase + UNIPHIER_FI2C_DTTX); 310 } 311 312 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv) 313 { 314 writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST); 315 } 316 317 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv) 318 { 319 writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL, 320 priv->membase + UNIPHIER_FI2C_BRST); 321 } 322 323 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv) 324 { 325 uniphier_fi2c_reset(priv); 326 i2c_recover_bus(&priv->adap); 327 } 328 329 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap, 330 struct i2c_msg *msg, bool repeat, 331 bool stop) 332 { 333 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 334 bool is_read = msg->flags & I2C_M_RD; 335 unsigned long time_left, flags; 336 337 dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, repeat=%d, stop=%d\n", 338 is_read ? "receive" : "transmit", msg->addr, msg->len, 339 repeat, stop); 340 341 priv->len = msg->len; 342 priv->buf = msg->buf; 343 priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS; 344 priv->error = 0; 345 priv->flags = 0; 346 347 if (stop) 348 priv->flags |= UNIPHIER_FI2C_STOP; 349 350 reinit_completion(&priv->comp); 351 uniphier_fi2c_clear_irqs(priv, U32_MAX); 352 writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST, 353 priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */ 354 355 spin_lock_irqsave(&priv->lock, flags); 356 357 if (is_read) 358 uniphier_fi2c_rx_init(priv, msg->addr); 359 else 360 uniphier_fi2c_tx_init(priv, msg->addr, repeat); 361 362 dev_dbg(&adap->dev, "start condition\n"); 363 /* 364 * For a repeated START condition, writing a slave address to the FIFO 365 * kicks the controller. So, the UNIPHIER_FI2C_CR register should be 366 * written only for a non-repeated START condition. 367 */ 368 if (!repeat) 369 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA, 370 priv->membase + UNIPHIER_FI2C_CR); 371 372 spin_unlock_irqrestore(&priv->lock, flags); 373 374 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout); 375 376 spin_lock_irqsave(&priv->lock, flags); 377 priv->enabled_irqs = 0; 378 uniphier_fi2c_set_irqs(priv); 379 spin_unlock_irqrestore(&priv->lock, flags); 380 381 if (!time_left) { 382 dev_err(&adap->dev, "transaction timeout.\n"); 383 uniphier_fi2c_recover(priv); 384 return -ETIMEDOUT; 385 } 386 dev_dbg(&adap->dev, "complete\n"); 387 388 if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) { 389 u32 status; 390 int ret; 391 392 ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR, 393 status, 394 (status & UNIPHIER_FI2C_SR_STS) && 395 !(status & UNIPHIER_FI2C_SR_BB), 396 1, 20); 397 if (ret) { 398 dev_err(&adap->dev, 399 "stop condition was not completed.\n"); 400 uniphier_fi2c_recover(priv); 401 return ret; 402 } 403 } 404 405 return priv->error; 406 } 407 408 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap) 409 { 410 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 411 412 if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) { 413 if (priv->busy_cnt++ > 3) { 414 /* 415 * If bus busy continues too long, it is probably 416 * in a wrong state. Try bus recovery. 417 */ 418 uniphier_fi2c_recover(priv); 419 priv->busy_cnt = 0; 420 } 421 422 return -EAGAIN; 423 } 424 425 priv->busy_cnt = 0; 426 return 0; 427 } 428 429 static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap, 430 struct i2c_msg *msgs, int num) 431 { 432 struct i2c_msg *msg, *emsg = msgs + num; 433 bool repeat = false; 434 int ret; 435 436 ret = uniphier_fi2c_check_bus_busy(adap); 437 if (ret) 438 return ret; 439 440 for (msg = msgs; msg < emsg; msg++) { 441 /* Emit STOP if it is the last message or I2C_M_STOP is set. */ 442 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP); 443 444 ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop); 445 if (ret) 446 return ret; 447 448 repeat = !stop; 449 } 450 451 return num; 452 } 453 454 static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap) 455 { 456 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 457 } 458 459 static const struct i2c_algorithm uniphier_fi2c_algo = { 460 .master_xfer = uniphier_fi2c_master_xfer, 461 .functionality = uniphier_fi2c_functionality, 462 }; 463 464 static int uniphier_fi2c_get_scl(struct i2c_adapter *adap) 465 { 466 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 467 468 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & 469 UNIPHIER_FI2C_BM_SCLS); 470 } 471 472 static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val) 473 { 474 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 475 476 writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0, 477 priv->membase + UNIPHIER_FI2C_BRST); 478 } 479 480 static int uniphier_fi2c_get_sda(struct i2c_adapter *adap) 481 { 482 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 483 484 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & 485 UNIPHIER_FI2C_BM_SDAS); 486 } 487 488 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap) 489 { 490 uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap)); 491 } 492 493 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = { 494 .recover_bus = i2c_generic_scl_recovery, 495 .get_scl = uniphier_fi2c_get_scl, 496 .set_scl = uniphier_fi2c_set_scl, 497 .get_sda = uniphier_fi2c_get_sda, 498 .unprepare_recovery = uniphier_fi2c_unprepare_recovery, 499 }; 500 501 static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv) 502 { 503 unsigned int cyc = priv->clk_cycle; 504 u32 tmp; 505 506 tmp = readl(priv->membase + UNIPHIER_FI2C_CR); 507 tmp |= UNIPHIER_FI2C_CR_MST; 508 writel(tmp, priv->membase + UNIPHIER_FI2C_CR); 509 510 uniphier_fi2c_reset(priv); 511 512 /* 513 * Standard-mode: tLOW + tHIGH = 10 us 514 * Fast-mode: tLOW + tHIGH = 2.5 us 515 */ 516 writel(cyc, priv->membase + UNIPHIER_FI2C_CYC); 517 /* 518 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us 519 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us 520 * "tLow/tHIGH = 5/4" meets both. 521 */ 522 writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL); 523 /* 524 * Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us 525 * Fast-mode: tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us 526 */ 527 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT); 528 /* 529 * Standard-mode: tSU;DAT = 250 ns 530 * Fast-mode: tSU;DAT = 100 ns 531 */ 532 writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT); 533 534 uniphier_fi2c_prepare_operation(priv); 535 } 536 537 static int uniphier_fi2c_probe(struct platform_device *pdev) 538 { 539 struct device *dev = &pdev->dev; 540 struct uniphier_fi2c_priv *priv; 541 struct resource *regs; 542 u32 bus_speed; 543 unsigned long clk_rate; 544 int irq, ret; 545 546 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 547 if (!priv) 548 return -ENOMEM; 549 550 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 551 priv->membase = devm_ioremap_resource(dev, regs); 552 if (IS_ERR(priv->membase)) 553 return PTR_ERR(priv->membase); 554 555 irq = platform_get_irq(pdev, 0); 556 if (irq < 0) { 557 dev_err(dev, "failed to get IRQ number\n"); 558 return irq; 559 } 560 561 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed)) 562 bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED; 563 564 if (!bus_speed || bus_speed > UNIPHIER_FI2C_MAX_SPEED) { 565 dev_err(dev, "invalid clock-frequency %d\n", bus_speed); 566 return -EINVAL; 567 } 568 569 priv->clk = devm_clk_get(dev, NULL); 570 if (IS_ERR(priv->clk)) { 571 dev_err(dev, "failed to get clock\n"); 572 return PTR_ERR(priv->clk); 573 } 574 575 ret = clk_prepare_enable(priv->clk); 576 if (ret) 577 return ret; 578 579 clk_rate = clk_get_rate(priv->clk); 580 if (!clk_rate) { 581 dev_err(dev, "input clock rate should not be zero\n"); 582 ret = -EINVAL; 583 goto disable_clk; 584 } 585 586 priv->clk_cycle = clk_rate / bus_speed; 587 init_completion(&priv->comp); 588 spin_lock_init(&priv->lock); 589 priv->adap.owner = THIS_MODULE; 590 priv->adap.algo = &uniphier_fi2c_algo; 591 priv->adap.dev.parent = dev; 592 priv->adap.dev.of_node = dev->of_node; 593 strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); 594 priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; 595 i2c_set_adapdata(&priv->adap, priv); 596 platform_set_drvdata(pdev, priv); 597 598 uniphier_fi2c_hw_init(priv); 599 600 ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0, 601 pdev->name, priv); 602 if (ret) { 603 dev_err(dev, "failed to request irq %d\n", irq); 604 goto disable_clk; 605 } 606 607 ret = i2c_add_adapter(&priv->adap); 608 disable_clk: 609 if (ret) 610 clk_disable_unprepare(priv->clk); 611 612 return ret; 613 } 614 615 static int uniphier_fi2c_remove(struct platform_device *pdev) 616 { 617 struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev); 618 619 i2c_del_adapter(&priv->adap); 620 clk_disable_unprepare(priv->clk); 621 622 return 0; 623 } 624 625 static int __maybe_unused uniphier_fi2c_suspend(struct device *dev) 626 { 627 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 628 629 clk_disable_unprepare(priv->clk); 630 631 return 0; 632 } 633 634 static int __maybe_unused uniphier_fi2c_resume(struct device *dev) 635 { 636 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 637 int ret; 638 639 ret = clk_prepare_enable(priv->clk); 640 if (ret) 641 return ret; 642 643 uniphier_fi2c_hw_init(priv); 644 645 return 0; 646 } 647 648 static const struct dev_pm_ops uniphier_fi2c_pm_ops = { 649 SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume) 650 }; 651 652 static const struct of_device_id uniphier_fi2c_match[] = { 653 { .compatible = "socionext,uniphier-fi2c" }, 654 { /* sentinel */ } 655 }; 656 MODULE_DEVICE_TABLE(of, uniphier_fi2c_match); 657 658 static struct platform_driver uniphier_fi2c_drv = { 659 .probe = uniphier_fi2c_probe, 660 .remove = uniphier_fi2c_remove, 661 .driver = { 662 .name = "uniphier-fi2c", 663 .of_match_table = uniphier_fi2c_match, 664 .pm = &uniphier_fi2c_pm_ops, 665 }, 666 }; 667 module_platform_driver(uniphier_fi2c_drv); 668 669 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 670 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver"); 671 MODULE_LICENSE("GPL"); 672