1 /* 2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/i2c.h> 17 #include <linux/iopoll.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 23 #define UNIPHIER_FI2C_CR 0x00 /* control register */ 24 #define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */ 25 #define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */ 26 #define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */ 27 #define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */ 28 #define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */ 29 #define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */ 30 #define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */ 31 #define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */ 32 #define UNIPHIER_FI2C_SLAD 0x0c /* slave address */ 33 #define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */ 34 #define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */ 35 #define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */ 36 #define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */ 37 #define UNIPHIER_FI2C_INT 0x20 /* interrupt status */ 38 #define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */ 39 #define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */ 40 #define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */ 41 #define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */ 42 #define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */ 43 #define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */ 44 #define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */ 45 #define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */ 46 #define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */ 47 #define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */ 48 #define UNIPHIER_FI2C_SR 0x2c /* status register */ 49 #define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */ 50 #define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */ 51 #define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */ 52 #define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */ 53 #define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */ 54 #define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */ 55 #define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */ 56 #define UNIPHIER_FI2C_RST 0x34 /* reset control */ 57 #define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */ 58 #define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */ 59 #define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */ 60 #define UNIPHIER_FI2C_BM 0x38 /* bus monitor */ 61 #define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */ 62 #define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */ 63 #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */ 64 #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */ 65 #define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */ 66 #define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */ 67 #define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */ 68 #define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */ 69 #define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */ 70 #define UNIPHIER_FI2C_BRST 0x50 /* bus reset */ 71 #define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */ 72 #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */ 73 74 #define UNIPHIER_FI2C_INT_FAULTS \ 75 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL) 76 #define UNIPHIER_FI2C_INT_STOP \ 77 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC) 78 79 #define UNIPHIER_FI2C_RD BIT(0) 80 #define UNIPHIER_FI2C_STOP BIT(1) 81 #define UNIPHIER_FI2C_MANUAL_NACK BIT(2) 82 #define UNIPHIER_FI2C_BYTE_WISE BIT(3) 83 #define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4) 84 85 #define UNIPHIER_FI2C_DEFAULT_SPEED 100000 86 #define UNIPHIER_FI2C_MAX_SPEED 400000 87 #define UNIPHIER_FI2C_FIFO_SIZE 8 88 89 struct uniphier_fi2c_priv { 90 struct completion comp; 91 struct i2c_adapter adap; 92 void __iomem *membase; 93 struct clk *clk; 94 unsigned int len; 95 u8 *buf; 96 u32 enabled_irqs; 97 int error; 98 unsigned int flags; 99 unsigned int busy_cnt; 100 unsigned int clk_cycle; 101 spinlock_t lock; /* IRQ synchronization */ 102 }; 103 104 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv, 105 bool first) 106 { 107 int fifo_space = UNIPHIER_FI2C_FIFO_SIZE; 108 109 /* 110 * TX-FIFO stores slave address in it for the first access. 111 * Decrement the counter. 112 */ 113 if (first) 114 fifo_space--; 115 116 while (priv->len) { 117 if (fifo_space-- <= 0) 118 break; 119 120 dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf); 121 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); 122 priv->len--; 123 } 124 } 125 126 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv) 127 { 128 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? 129 1 : UNIPHIER_FI2C_FIFO_SIZE; 130 131 while (priv->len) { 132 if (fifo_left-- <= 0) 133 break; 134 135 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); 136 dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]); 137 priv->len--; 138 } 139 } 140 141 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv) 142 { 143 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); 144 } 145 146 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv, 147 u32 mask) 148 { 149 writel(mask, priv->membase + UNIPHIER_FI2C_IC); 150 } 151 152 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv) 153 { 154 dev_dbg(&priv->adap.dev, "stop condition\n"); 155 156 priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP; 157 uniphier_fi2c_set_irqs(priv); 158 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO, 159 priv->membase + UNIPHIER_FI2C_CR); 160 } 161 162 static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id) 163 { 164 struct uniphier_fi2c_priv *priv = dev_id; 165 u32 irq_status; 166 167 spin_lock(&priv->lock); 168 169 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); 170 irq_status &= priv->enabled_irqs; 171 172 dev_dbg(&priv->adap.dev, 173 "interrupt: enabled_irqs=%04x, irq_status=%04x\n", 174 priv->enabled_irqs, irq_status); 175 176 uniphier_fi2c_clear_irqs(priv, irq_status); 177 178 if (irq_status & UNIPHIER_FI2C_INT_STOP) 179 goto complete; 180 181 if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) { 182 dev_dbg(&priv->adap.dev, "arbitration lost\n"); 183 priv->error = -EAGAIN; 184 goto complete; 185 } 186 187 if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) { 188 dev_dbg(&priv->adap.dev, "could not get ACK\n"); 189 priv->error = -ENXIO; 190 if (priv->flags & UNIPHIER_FI2C_RD) { 191 /* 192 * work around a hardware bug: 193 * The receive-completed interrupt is never set even if 194 * STOP condition is detected after the address phase 195 * of read transaction fails to get ACK. 196 * To avoid time-out error, we issue STOP here, 197 * but do not wait for its completion. 198 * It should be checked after exiting this handler. 199 */ 200 uniphier_fi2c_stop(priv); 201 priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP; 202 goto complete; 203 } 204 goto stop; 205 } 206 207 if (irq_status & UNIPHIER_FI2C_INT_TE) { 208 if (!priv->len) 209 goto data_done; 210 211 uniphier_fi2c_fill_txfifo(priv, false); 212 goto handled; 213 } 214 215 if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) { 216 uniphier_fi2c_drain_rxfifo(priv); 217 if (!priv->len) 218 goto data_done; 219 220 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) { 221 if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE && 222 !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) { 223 dev_dbg(&priv->adap.dev, 224 "enable read byte count IRQ\n"); 225 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB; 226 uniphier_fi2c_set_irqs(priv); 227 priv->flags |= UNIPHIER_FI2C_BYTE_WISE; 228 } 229 if (priv->len <= 1) { 230 dev_dbg(&priv->adap.dev, "set NACK\n"); 231 writel(UNIPHIER_FI2C_CR_MST | 232 UNIPHIER_FI2C_CR_NACK, 233 priv->membase + UNIPHIER_FI2C_CR); 234 } 235 } 236 237 goto handled; 238 } 239 240 spin_unlock(&priv->lock); 241 242 return IRQ_NONE; 243 244 data_done: 245 if (priv->flags & UNIPHIER_FI2C_STOP) { 246 stop: 247 uniphier_fi2c_stop(priv); 248 } else { 249 complete: 250 priv->enabled_irqs = 0; 251 uniphier_fi2c_set_irqs(priv); 252 complete(&priv->comp); 253 } 254 255 handled: 256 spin_unlock(&priv->lock); 257 258 return IRQ_HANDLED; 259 } 260 261 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr) 262 { 263 priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE; 264 uniphier_fi2c_set_irqs(priv); 265 266 /* do not use TX byte counter */ 267 writel(0, priv->membase + UNIPHIER_FI2C_TBC); 268 /* set slave address */ 269 writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1, 270 priv->membase + UNIPHIER_FI2C_DTTX); 271 /* first chunk of data */ 272 uniphier_fi2c_fill_txfifo(priv, true); 273 } 274 275 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr) 276 { 277 priv->flags |= UNIPHIER_FI2C_RD; 278 279 if (likely(priv->len < 256)) { 280 /* 281 * If possible, use RX byte counter. 282 * It can automatically handle NACK for the last byte. 283 */ 284 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC); 285 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF | 286 UNIPHIER_FI2C_INT_RB; 287 } else { 288 /* 289 * The byte counter can not count over 256. In this case, 290 * do not use it at all. Drain data when FIFO gets full, 291 * but treat the last portion as a special case. 292 */ 293 writel(0, priv->membase + UNIPHIER_FI2C_RBC); 294 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK; 295 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF; 296 } 297 298 uniphier_fi2c_set_irqs(priv); 299 300 /* set slave address with RD bit */ 301 writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1, 302 priv->membase + UNIPHIER_FI2C_DTTX); 303 } 304 305 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv) 306 { 307 writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST); 308 } 309 310 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv) 311 { 312 writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL, 313 priv->membase + UNIPHIER_FI2C_BRST); 314 } 315 316 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv) 317 { 318 uniphier_fi2c_reset(priv); 319 i2c_recover_bus(&priv->adap); 320 } 321 322 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap, 323 struct i2c_msg *msg, bool repeat, 324 bool stop) 325 { 326 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 327 bool is_read = msg->flags & I2C_M_RD; 328 unsigned long time_left, flags; 329 330 dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, repeat=%d, stop=%d\n", 331 is_read ? "receive" : "transmit", msg->addr, msg->len, 332 repeat, stop); 333 334 priv->len = msg->len; 335 priv->buf = msg->buf; 336 priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS; 337 priv->error = 0; 338 priv->flags = 0; 339 340 if (stop) 341 priv->flags |= UNIPHIER_FI2C_STOP; 342 343 reinit_completion(&priv->comp); 344 uniphier_fi2c_clear_irqs(priv, U32_MAX); 345 writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST, 346 priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */ 347 348 spin_lock_irqsave(&priv->lock, flags); 349 350 if (is_read) 351 uniphier_fi2c_rx_init(priv, msg->addr); 352 else 353 uniphier_fi2c_tx_init(priv, msg->addr); 354 355 dev_dbg(&adap->dev, "start condition\n"); 356 /* 357 * For a repeated START condition, writing a slave address to the FIFO 358 * kicks the controller. So, the UNIPHIER_FI2C_CR register should be 359 * written only for a non-repeated START condition. 360 */ 361 if (!repeat) 362 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA, 363 priv->membase + UNIPHIER_FI2C_CR); 364 365 spin_unlock_irqrestore(&priv->lock, flags); 366 367 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout); 368 369 spin_lock_irqsave(&priv->lock, flags); 370 priv->enabled_irqs = 0; 371 uniphier_fi2c_set_irqs(priv); 372 spin_unlock_irqrestore(&priv->lock, flags); 373 374 if (!time_left) { 375 dev_err(&adap->dev, "transaction timeout.\n"); 376 uniphier_fi2c_recover(priv); 377 return -ETIMEDOUT; 378 } 379 dev_dbg(&adap->dev, "complete\n"); 380 381 if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) { 382 u32 status; 383 int ret; 384 385 ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR, 386 status, 387 (status & UNIPHIER_FI2C_SR_STS) && 388 !(status & UNIPHIER_FI2C_SR_BB), 389 1, 20); 390 if (ret) { 391 dev_err(&adap->dev, 392 "stop condition was not completed.\n"); 393 uniphier_fi2c_recover(priv); 394 return ret; 395 } 396 } 397 398 return priv->error; 399 } 400 401 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap) 402 { 403 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 404 405 if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) { 406 if (priv->busy_cnt++ > 3) { 407 /* 408 * If bus busy continues too long, it is probably 409 * in a wrong state. Try bus recovery. 410 */ 411 uniphier_fi2c_recover(priv); 412 priv->busy_cnt = 0; 413 } 414 415 return -EAGAIN; 416 } 417 418 priv->busy_cnt = 0; 419 return 0; 420 } 421 422 static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap, 423 struct i2c_msg *msgs, int num) 424 { 425 struct i2c_msg *msg, *emsg = msgs + num; 426 bool repeat = false; 427 int ret; 428 429 ret = uniphier_fi2c_check_bus_busy(adap); 430 if (ret) 431 return ret; 432 433 for (msg = msgs; msg < emsg; msg++) { 434 /* Emit STOP if it is the last message or I2C_M_STOP is set. */ 435 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP); 436 437 ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop); 438 if (ret) 439 return ret; 440 441 repeat = !stop; 442 } 443 444 return num; 445 } 446 447 static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap) 448 { 449 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 450 } 451 452 static const struct i2c_algorithm uniphier_fi2c_algo = { 453 .master_xfer = uniphier_fi2c_master_xfer, 454 .functionality = uniphier_fi2c_functionality, 455 }; 456 457 static int uniphier_fi2c_get_scl(struct i2c_adapter *adap) 458 { 459 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 460 461 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & 462 UNIPHIER_FI2C_BM_SCLS); 463 } 464 465 static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val) 466 { 467 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 468 469 writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0, 470 priv->membase + UNIPHIER_FI2C_BRST); 471 } 472 473 static int uniphier_fi2c_get_sda(struct i2c_adapter *adap) 474 { 475 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap); 476 477 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & 478 UNIPHIER_FI2C_BM_SDAS); 479 } 480 481 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap) 482 { 483 uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap)); 484 } 485 486 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = { 487 .recover_bus = i2c_generic_scl_recovery, 488 .get_scl = uniphier_fi2c_get_scl, 489 .set_scl = uniphier_fi2c_set_scl, 490 .get_sda = uniphier_fi2c_get_sda, 491 .unprepare_recovery = uniphier_fi2c_unprepare_recovery, 492 }; 493 494 static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv) 495 { 496 unsigned int cyc = priv->clk_cycle; 497 u32 tmp; 498 499 tmp = readl(priv->membase + UNIPHIER_FI2C_CR); 500 tmp |= UNIPHIER_FI2C_CR_MST; 501 writel(tmp, priv->membase + UNIPHIER_FI2C_CR); 502 503 uniphier_fi2c_reset(priv); 504 505 writel(cyc, priv->membase + UNIPHIER_FI2C_CYC); 506 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_LCTL); 507 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT); 508 writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT); 509 510 uniphier_fi2c_prepare_operation(priv); 511 } 512 513 static int uniphier_fi2c_probe(struct platform_device *pdev) 514 { 515 struct device *dev = &pdev->dev; 516 struct uniphier_fi2c_priv *priv; 517 struct resource *regs; 518 u32 bus_speed; 519 unsigned long clk_rate; 520 int irq, ret; 521 522 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 523 if (!priv) 524 return -ENOMEM; 525 526 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 527 priv->membase = devm_ioremap_resource(dev, regs); 528 if (IS_ERR(priv->membase)) 529 return PTR_ERR(priv->membase); 530 531 irq = platform_get_irq(pdev, 0); 532 if (irq < 0) { 533 dev_err(dev, "failed to get IRQ number\n"); 534 return irq; 535 } 536 537 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed)) 538 bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED; 539 540 if (!bus_speed || bus_speed > UNIPHIER_FI2C_MAX_SPEED) { 541 dev_err(dev, "invalid clock-frequency %d\n", bus_speed); 542 return -EINVAL; 543 } 544 545 priv->clk = devm_clk_get(dev, NULL); 546 if (IS_ERR(priv->clk)) { 547 dev_err(dev, "failed to get clock\n"); 548 return PTR_ERR(priv->clk); 549 } 550 551 ret = clk_prepare_enable(priv->clk); 552 if (ret) 553 return ret; 554 555 clk_rate = clk_get_rate(priv->clk); 556 if (!clk_rate) { 557 dev_err(dev, "input clock rate should not be zero\n"); 558 ret = -EINVAL; 559 goto disable_clk; 560 } 561 562 priv->clk_cycle = clk_rate / bus_speed; 563 init_completion(&priv->comp); 564 spin_lock_init(&priv->lock); 565 priv->adap.owner = THIS_MODULE; 566 priv->adap.algo = &uniphier_fi2c_algo; 567 priv->adap.dev.parent = dev; 568 priv->adap.dev.of_node = dev->of_node; 569 strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); 570 priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; 571 i2c_set_adapdata(&priv->adap, priv); 572 platform_set_drvdata(pdev, priv); 573 574 uniphier_fi2c_hw_init(priv); 575 576 ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0, 577 pdev->name, priv); 578 if (ret) { 579 dev_err(dev, "failed to request irq %d\n", irq); 580 goto disable_clk; 581 } 582 583 ret = i2c_add_adapter(&priv->adap); 584 disable_clk: 585 if (ret) 586 clk_disable_unprepare(priv->clk); 587 588 return ret; 589 } 590 591 static int uniphier_fi2c_remove(struct platform_device *pdev) 592 { 593 struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev); 594 595 i2c_del_adapter(&priv->adap); 596 clk_disable_unprepare(priv->clk); 597 598 return 0; 599 } 600 601 static int __maybe_unused uniphier_fi2c_suspend(struct device *dev) 602 { 603 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 604 605 clk_disable_unprepare(priv->clk); 606 607 return 0; 608 } 609 610 static int __maybe_unused uniphier_fi2c_resume(struct device *dev) 611 { 612 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev); 613 int ret; 614 615 ret = clk_prepare_enable(priv->clk); 616 if (ret) 617 return ret; 618 619 uniphier_fi2c_hw_init(priv); 620 621 return 0; 622 } 623 624 static const struct dev_pm_ops uniphier_fi2c_pm_ops = { 625 SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume) 626 }; 627 628 static const struct of_device_id uniphier_fi2c_match[] = { 629 { .compatible = "socionext,uniphier-fi2c" }, 630 { /* sentinel */ } 631 }; 632 MODULE_DEVICE_TABLE(of, uniphier_fi2c_match); 633 634 static struct platform_driver uniphier_fi2c_drv = { 635 .probe = uniphier_fi2c_probe, 636 .remove = uniphier_fi2c_remove, 637 .driver = { 638 .name = "uniphier-fi2c", 639 .of_match_table = uniphier_fi2c_match, 640 .pm = &uniphier_fi2c_pm_ops, 641 }, 642 }; 643 module_platform_driver(uniphier_fi2c_drv); 644 645 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 646 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver"); 647 MODULE_LICENSE("GPL"); 648