1 /* 2 * drivers/i2c/busses/i2c-tegra.c 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * Author: Colin Cross <ccross@android.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/err.h> 23 #include <linux/i2c.h> 24 #include <linux/io.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 #include <linux/of_device.h> 29 #include <linux/module.h> 30 #include <linux/reset.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/iopoll.h> 34 35 #include <asm/unaligned.h> 36 37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 38 #define BYTES_PER_FIFO_WORD 4 39 40 #define I2C_CNFG 0x000 41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 42 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 43 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 44 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 45 #define I2C_STATUS 0x01C 46 #define I2C_SL_CNFG 0x020 47 #define I2C_SL_CNFG_NACK BIT(1) 48 #define I2C_SL_CNFG_NEWSL BIT(2) 49 #define I2C_SL_ADDR1 0x02c 50 #define I2C_SL_ADDR2 0x030 51 #define I2C_TX_FIFO 0x050 52 #define I2C_RX_FIFO 0x054 53 #define I2C_PACKET_TRANSFER_STATUS 0x058 54 #define I2C_FIFO_CONTROL 0x05c 55 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 56 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 59 #define I2C_FIFO_STATUS 0x060 60 #define I2C_FIFO_STATUS_TX_MASK 0xF0 61 #define I2C_FIFO_STATUS_TX_SHIFT 4 62 #define I2C_FIFO_STATUS_RX_MASK 0x0F 63 #define I2C_FIFO_STATUS_RX_SHIFT 0 64 #define I2C_INT_MASK 0x064 65 #define I2C_INT_STATUS 0x068 66 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6) 68 #define I2C_INT_TX_FIFO_OVERFLOW BIT(5) 69 #define I2C_INT_RX_FIFO_UNDERFLOW BIT(4) 70 #define I2C_INT_NO_ACK BIT(3) 71 #define I2C_INT_ARBITRATION_LOST BIT(2) 72 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 73 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 74 #define I2C_CLK_DIVISOR 0x06c 75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 77 78 #define DVC_CTRL_REG1 0x000 79 #define DVC_CTRL_REG1_INTR_EN BIT(10) 80 #define DVC_CTRL_REG2 0x004 81 #define DVC_CTRL_REG3 0x008 82 #define DVC_CTRL_REG3_SW_PROG BIT(26) 83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 84 #define DVC_STATUS 0x00c 85 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 86 87 #define I2C_ERR_NONE 0x00 88 #define I2C_ERR_NO_ACK 0x01 89 #define I2C_ERR_ARBITRATION_LOST 0x02 90 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 91 92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 93 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 94 #define PACKET_HEADER0_CONT_ID_SHIFT 12 95 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4) 96 97 #define I2C_HEADER_HIGHSPEED_MODE BIT(22) 98 #define I2C_HEADER_CONT_ON_NAK BIT(21) 99 #define I2C_HEADER_SEND_START_BYTE BIT(20) 100 #define I2C_HEADER_READ BIT(19) 101 #define I2C_HEADER_10BIT_ADDR BIT(18) 102 #define I2C_HEADER_IE_ENABLE BIT(17) 103 #define I2C_HEADER_REPEAT_START BIT(16) 104 #define I2C_HEADER_CONTINUE_XFER BIT(15) 105 #define I2C_HEADER_MASTER_ADDR_SHIFT 12 106 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 107 108 #define I2C_CONFIG_LOAD 0x08C 109 #define I2C_MSTR_CONFIG_LOAD BIT(0) 110 #define I2C_SLV_CONFIG_LOAD BIT(1) 111 #define I2C_TIMEOUT_CONFIG_LOAD BIT(2) 112 113 #define I2C_CLKEN_OVERRIDE 0x090 114 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 115 116 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 117 118 /* 119 * msg_end_type: The bus control which need to be send at end of transfer. 120 * @MSG_END_STOP: Send stop pulse at end of transfer. 121 * @MSG_END_REPEAT_START: Send repeat start at end of transfer. 122 * @MSG_END_CONTINUE: The following on message is coming and so do not send 123 * stop or repeat start. 124 */ 125 enum msg_end_type { 126 MSG_END_STOP, 127 MSG_END_REPEAT_START, 128 MSG_END_CONTINUE, 129 }; 130 131 /** 132 * struct tegra_i2c_hw_feature : Different HW support on Tegra 133 * @has_continue_xfer_support: Continue transfer supports. 134 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 135 * complete interrupt per packet basis. 136 * @has_single_clk_source: The i2c controller has single clock source. Tegra30 137 * and earlier Socs has two clock sources i.e. div-clk and 138 * fast-clk. 139 * @has_config_load_reg: Has the config load register to load the new 140 * configuration. 141 * @clk_divisor_hs_mode: Clock divisor in HS mode. 142 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is 143 * applicable if there is no fast clock source i.e. single clock 144 * source. 145 */ 146 147 struct tegra_i2c_hw_feature { 148 bool has_continue_xfer_support; 149 bool has_per_pkt_xfer_complete_irq; 150 bool has_single_clk_source; 151 bool has_config_load_reg; 152 int clk_divisor_hs_mode; 153 int clk_divisor_std_fast_mode; 154 u16 clk_divisor_fast_plus_mode; 155 bool has_multi_master_mode; 156 bool has_slcg_override_reg; 157 }; 158 159 /** 160 * struct tegra_i2c_dev - per device i2c context 161 * @dev: device reference for power management 162 * @hw: Tegra i2c hw feature. 163 * @adapter: core i2c layer adapter information 164 * @div_clk: clock reference for div clock of i2c controller. 165 * @fast_clk: clock reference for fast clock of i2c controller. 166 * @base: ioremapped registers cookie 167 * @cont_id: i2c controller id, used for for packet header 168 * @irq: irq number of transfer complete interrupt 169 * @is_dvc: identifies the DVC i2c controller, has a different register layout 170 * @msg_complete: transfer completion notifier 171 * @msg_err: error code for completed message 172 * @msg_buf: pointer to current message data 173 * @msg_buf_remaining: size of unsent data in the message buffer 174 * @msg_read: identifies read transfers 175 * @bus_clk_rate: current i2c bus clock rate 176 */ 177 struct tegra_i2c_dev { 178 struct device *dev; 179 const struct tegra_i2c_hw_feature *hw; 180 struct i2c_adapter adapter; 181 struct clk *div_clk; 182 struct clk *fast_clk; 183 struct reset_control *rst; 184 void __iomem *base; 185 int cont_id; 186 int irq; 187 bool irq_disabled; 188 int is_dvc; 189 struct completion msg_complete; 190 int msg_err; 191 u8 *msg_buf; 192 size_t msg_buf_remaining; 193 int msg_read; 194 u32 bus_clk_rate; 195 u16 clk_divisor_non_hs_mode; 196 bool is_multimaster_mode; 197 spinlock_t xfer_lock; 198 }; 199 200 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 201 unsigned long reg) 202 { 203 writel(val, i2c_dev->base + reg); 204 } 205 206 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 207 { 208 return readl(i2c_dev->base + reg); 209 } 210 211 /* 212 * i2c_writel and i2c_readl will offset the register if necessary to talk 213 * to the I2C block inside the DVC block 214 */ 215 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 216 unsigned long reg) 217 { 218 if (i2c_dev->is_dvc) 219 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 220 return reg; 221 } 222 223 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 224 unsigned long reg) 225 { 226 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 227 228 /* Read back register to make sure that register writes completed */ 229 if (reg != I2C_TX_FIFO) 230 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 231 } 232 233 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 234 { 235 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 236 } 237 238 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 239 unsigned long reg, int len) 240 { 241 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 242 } 243 244 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 245 unsigned long reg, int len) 246 { 247 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 248 } 249 250 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 251 { 252 u32 int_mask; 253 254 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 255 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 256 } 257 258 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 259 { 260 u32 int_mask; 261 262 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 263 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 264 } 265 266 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 267 { 268 unsigned long timeout = jiffies + HZ; 269 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); 270 271 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; 272 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 273 274 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & 275 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { 276 if (time_after(jiffies, timeout)) { 277 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 278 return -ETIMEDOUT; 279 } 280 msleep(1); 281 } 282 return 0; 283 } 284 285 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 286 { 287 u32 val; 288 int rx_fifo_avail; 289 u8 *buf = i2c_dev->msg_buf; 290 size_t buf_remaining = i2c_dev->msg_buf_remaining; 291 int words_to_transfer; 292 293 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 294 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 295 I2C_FIFO_STATUS_RX_SHIFT; 296 297 /* Rounds down to not include partial word at the end of buf */ 298 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 299 if (words_to_transfer > rx_fifo_avail) 300 words_to_transfer = rx_fifo_avail; 301 302 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 303 304 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 305 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 306 rx_fifo_avail -= words_to_transfer; 307 308 /* 309 * If there is a partial word at the end of buf, handle it manually to 310 * prevent overwriting past the end of buf 311 */ 312 if (rx_fifo_avail > 0 && buf_remaining > 0) { 313 BUG_ON(buf_remaining > 3); 314 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 315 val = cpu_to_le32(val); 316 memcpy(buf, &val, buf_remaining); 317 buf_remaining = 0; 318 rx_fifo_avail--; 319 } 320 321 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); 322 i2c_dev->msg_buf_remaining = buf_remaining; 323 i2c_dev->msg_buf = buf; 324 return 0; 325 } 326 327 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 328 { 329 u32 val; 330 int tx_fifo_avail; 331 u8 *buf = i2c_dev->msg_buf; 332 size_t buf_remaining = i2c_dev->msg_buf_remaining; 333 int words_to_transfer; 334 335 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 336 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 337 I2C_FIFO_STATUS_TX_SHIFT; 338 339 /* Rounds down to not include partial word at the end of buf */ 340 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 341 342 /* It's very common to have < 4 bytes, so optimize that case. */ 343 if (words_to_transfer) { 344 if (words_to_transfer > tx_fifo_avail) 345 words_to_transfer = tx_fifo_avail; 346 347 /* 348 * Update state before writing to FIFO. If this casues us 349 * to finish writing all bytes (AKA buf_remaining goes to 0) we 350 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 351 * not maskable). We need to make sure that the isr sees 352 * buf_remaining as 0 and doesn't call us back re-entrantly. 353 */ 354 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 355 tx_fifo_avail -= words_to_transfer; 356 i2c_dev->msg_buf_remaining = buf_remaining; 357 i2c_dev->msg_buf = buf + 358 words_to_transfer * BYTES_PER_FIFO_WORD; 359 barrier(); 360 361 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 362 363 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 364 } 365 366 /* 367 * If there is a partial word at the end of buf, handle it manually to 368 * prevent reading past the end of buf, which could cross a page 369 * boundary and fault. 370 */ 371 if (tx_fifo_avail > 0 && buf_remaining > 0) { 372 BUG_ON(buf_remaining > 3); 373 memcpy(&val, buf, buf_remaining); 374 val = le32_to_cpu(val); 375 376 /* Again update before writing to FIFO to make sure isr sees. */ 377 i2c_dev->msg_buf_remaining = 0; 378 i2c_dev->msg_buf = NULL; 379 barrier(); 380 381 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 382 } 383 384 return 0; 385 } 386 387 /* 388 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 389 * block. This block is identical to the rest of the I2C blocks, except that 390 * it only supports master mode, it has registers moved around, and it needs 391 * some extra init to get it into I2C mode. The register moves are handled 392 * by i2c_readl and i2c_writel 393 */ 394 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 395 { 396 u32 val; 397 398 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 399 val |= DVC_CTRL_REG3_SW_PROG; 400 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 401 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 402 403 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 404 val |= DVC_CTRL_REG1_INTR_EN; 405 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 406 } 407 408 static int tegra_i2c_runtime_resume(struct device *dev) 409 { 410 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 411 int ret; 412 413 ret = pinctrl_pm_select_default_state(i2c_dev->dev); 414 if (ret) 415 return ret; 416 417 if (!i2c_dev->hw->has_single_clk_source) { 418 ret = clk_enable(i2c_dev->fast_clk); 419 if (ret < 0) { 420 dev_err(i2c_dev->dev, 421 "Enabling fast clk failed, err %d\n", ret); 422 return ret; 423 } 424 } 425 426 ret = clk_enable(i2c_dev->div_clk); 427 if (ret < 0) { 428 dev_err(i2c_dev->dev, 429 "Enabling div clk failed, err %d\n", ret); 430 clk_disable(i2c_dev->fast_clk); 431 return ret; 432 } 433 434 return 0; 435 } 436 437 static int tegra_i2c_runtime_suspend(struct device *dev) 438 { 439 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 440 441 clk_disable(i2c_dev->div_clk); 442 if (!i2c_dev->hw->has_single_clk_source) 443 clk_disable(i2c_dev->fast_clk); 444 445 return pinctrl_pm_select_idle_state(i2c_dev->dev); 446 } 447 448 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 449 { 450 unsigned long reg_offset; 451 void __iomem *addr; 452 u32 val; 453 int err; 454 455 if (i2c_dev->hw->has_config_load_reg) { 456 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); 457 addr = i2c_dev->base + reg_offset; 458 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 459 if (in_interrupt()) 460 err = readl_poll_timeout_atomic(addr, val, val == 0, 461 1000, I2C_CONFIG_LOAD_TIMEOUT); 462 else 463 err = readl_poll_timeout(addr, val, val == 0, 464 1000, I2C_CONFIG_LOAD_TIMEOUT); 465 466 if (err) { 467 dev_warn(i2c_dev->dev, 468 "timeout waiting for config load\n"); 469 return err; 470 } 471 } 472 473 return 0; 474 } 475 476 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 477 { 478 u32 val; 479 int err; 480 u32 clk_divisor; 481 482 err = pm_runtime_get_sync(i2c_dev->dev); 483 if (err < 0) { 484 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err); 485 return err; 486 } 487 488 reset_control_assert(i2c_dev->rst); 489 udelay(2); 490 reset_control_deassert(i2c_dev->rst); 491 492 if (i2c_dev->is_dvc) 493 tegra_dvc_init(i2c_dev); 494 495 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 496 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 497 498 if (i2c_dev->hw->has_multi_master_mode) 499 val |= I2C_CNFG_MULTI_MASTER_MODE; 500 501 i2c_writel(i2c_dev, val, I2C_CNFG); 502 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 503 504 /* Make sure clock divisor programmed correctly */ 505 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; 506 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << 507 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; 508 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 509 510 if (!i2c_dev->is_dvc) { 511 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 512 513 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 514 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 515 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 516 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 517 } 518 519 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | 520 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; 521 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 522 523 err = tegra_i2c_flush_fifos(i2c_dev); 524 if (err) 525 goto err; 526 527 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 528 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 529 530 err = tegra_i2c_wait_for_config_load(i2c_dev); 531 if (err) 532 goto err; 533 534 if (i2c_dev->irq_disabled) { 535 i2c_dev->irq_disabled = false; 536 enable_irq(i2c_dev->irq); 537 } 538 539 err: 540 pm_runtime_put(i2c_dev->dev); 541 return err; 542 } 543 544 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 545 { 546 u32 cnfg; 547 548 /* 549 * NACK interrupt is generated before the I2C controller generates 550 * the STOP condition on the bus. So wait for 2 clock periods 551 * before disabling the controller so that the STOP condition has 552 * been delivered properly. 553 */ 554 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 555 556 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 557 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 558 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 559 560 return tegra_i2c_wait_for_config_load(i2c_dev); 561 } 562 563 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 564 { 565 u32 status; 566 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 567 struct tegra_i2c_dev *i2c_dev = dev_id; 568 unsigned long flags; 569 570 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 571 572 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); 573 if (status == 0) { 574 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 575 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 576 i2c_readl(i2c_dev, I2C_STATUS), 577 i2c_readl(i2c_dev, I2C_CNFG)); 578 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 579 580 if (!i2c_dev->irq_disabled) { 581 disable_irq_nosync(i2c_dev->irq); 582 i2c_dev->irq_disabled = true; 583 } 584 goto err; 585 } 586 587 if (unlikely(status & status_err)) { 588 tegra_i2c_disable_packet_mode(i2c_dev); 589 if (status & I2C_INT_NO_ACK) 590 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 591 if (status & I2C_INT_ARBITRATION_LOST) 592 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 593 goto err; 594 } 595 596 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 597 if (i2c_dev->msg_buf_remaining) 598 tegra_i2c_empty_rx_fifo(i2c_dev); 599 else 600 BUG(); 601 } 602 603 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 604 if (i2c_dev->msg_buf_remaining) 605 tegra_i2c_fill_tx_fifo(i2c_dev); 606 else 607 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); 608 } 609 610 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 611 if (i2c_dev->is_dvc) 612 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 613 614 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 615 BUG_ON(i2c_dev->msg_buf_remaining); 616 complete(&i2c_dev->msg_complete); 617 } 618 goto done; 619 err: 620 /* An error occurred, mask all interrupts */ 621 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 622 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 623 I2C_INT_RX_FIFO_DATA_REQ); 624 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 625 if (i2c_dev->is_dvc) 626 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 627 628 complete(&i2c_dev->msg_complete); 629 done: 630 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); 631 return IRQ_HANDLED; 632 } 633 634 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 635 struct i2c_msg *msg, enum msg_end_type end_state) 636 { 637 u32 packet_header; 638 u32 int_mask; 639 unsigned long time_left; 640 unsigned long flags; 641 642 tegra_i2c_flush_fifos(i2c_dev); 643 644 if (msg->len == 0) 645 return -EINVAL; 646 647 i2c_dev->msg_buf = msg->buf; 648 i2c_dev->msg_buf_remaining = msg->len; 649 i2c_dev->msg_err = I2C_ERR_NONE; 650 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 651 reinit_completion(&i2c_dev->msg_complete); 652 653 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); 654 655 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 656 tegra_i2c_unmask_irq(i2c_dev, int_mask); 657 658 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 659 PACKET_HEADER0_PROTOCOL_I2C | 660 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 661 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 662 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 663 664 packet_header = msg->len - 1; 665 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 666 667 packet_header = I2C_HEADER_IE_ENABLE; 668 if (end_state == MSG_END_CONTINUE) 669 packet_header |= I2C_HEADER_CONTINUE_XFER; 670 else if (end_state == MSG_END_REPEAT_START) 671 packet_header |= I2C_HEADER_REPEAT_START; 672 if (msg->flags & I2C_M_TEN) { 673 packet_header |= msg->addr; 674 packet_header |= I2C_HEADER_10BIT_ADDR; 675 } else { 676 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 677 } 678 if (msg->flags & I2C_M_IGNORE_NAK) 679 packet_header |= I2C_HEADER_CONT_ON_NAK; 680 if (msg->flags & I2C_M_RD) 681 packet_header |= I2C_HEADER_READ; 682 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 683 684 if (!(msg->flags & I2C_M_RD)) 685 tegra_i2c_fill_tx_fifo(i2c_dev); 686 687 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 688 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 689 if (msg->flags & I2C_M_RD) 690 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 691 else if (i2c_dev->msg_buf_remaining) 692 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 693 694 tegra_i2c_unmask_irq(i2c_dev, int_mask); 695 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); 696 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 697 i2c_readl(i2c_dev, I2C_INT_MASK)); 698 699 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 700 TEGRA_I2C_TIMEOUT); 701 tegra_i2c_mask_irq(i2c_dev, int_mask); 702 703 if (time_left == 0) { 704 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 705 706 tegra_i2c_init(i2c_dev); 707 return -ETIMEDOUT; 708 } 709 710 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 711 time_left, completion_done(&i2c_dev->msg_complete), 712 i2c_dev->msg_err); 713 714 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 715 return 0; 716 717 tegra_i2c_init(i2c_dev); 718 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 719 if (msg->flags & I2C_M_IGNORE_NAK) 720 return 0; 721 return -EREMOTEIO; 722 } 723 724 return -EIO; 725 } 726 727 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 728 int num) 729 { 730 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 731 int i; 732 int ret = 0; 733 734 ret = pm_runtime_get_sync(i2c_dev->dev); 735 if (ret < 0) { 736 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 737 return ret; 738 } 739 740 for (i = 0; i < num; i++) { 741 enum msg_end_type end_type = MSG_END_STOP; 742 743 if (i < (num - 1)) { 744 if (msgs[i + 1].flags & I2C_M_NOSTART) 745 end_type = MSG_END_CONTINUE; 746 else 747 end_type = MSG_END_REPEAT_START; 748 } 749 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 750 if (ret) 751 break; 752 } 753 754 pm_runtime_put(i2c_dev->dev); 755 756 return ret ?: i; 757 } 758 759 static u32 tegra_i2c_func(struct i2c_adapter *adap) 760 { 761 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 762 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 763 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 764 765 if (i2c_dev->hw->has_continue_xfer_support) 766 ret |= I2C_FUNC_NOSTART; 767 return ret; 768 } 769 770 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 771 { 772 struct device_node *np = i2c_dev->dev->of_node; 773 int ret; 774 775 ret = of_property_read_u32(np, "clock-frequency", 776 &i2c_dev->bus_clk_rate); 777 if (ret) 778 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ 779 780 i2c_dev->is_multimaster_mode = of_property_read_bool(np, 781 "multi-master"); 782 } 783 784 static const struct i2c_algorithm tegra_i2c_algo = { 785 .master_xfer = tegra_i2c_xfer, 786 .functionality = tegra_i2c_func, 787 }; 788 789 /* payload size is only 12 bit */ 790 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 791 .max_read_len = 4096, 792 .max_write_len = 4096, 793 }; 794 795 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 796 .has_continue_xfer_support = false, 797 .has_per_pkt_xfer_complete_irq = false, 798 .has_single_clk_source = false, 799 .clk_divisor_hs_mode = 3, 800 .clk_divisor_std_fast_mode = 0, 801 .clk_divisor_fast_plus_mode = 0, 802 .has_config_load_reg = false, 803 .has_multi_master_mode = false, 804 .has_slcg_override_reg = false, 805 }; 806 807 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 808 .has_continue_xfer_support = true, 809 .has_per_pkt_xfer_complete_irq = false, 810 .has_single_clk_source = false, 811 .clk_divisor_hs_mode = 3, 812 .clk_divisor_std_fast_mode = 0, 813 .clk_divisor_fast_plus_mode = 0, 814 .has_config_load_reg = false, 815 .has_multi_master_mode = false, 816 .has_slcg_override_reg = false, 817 }; 818 819 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 820 .has_continue_xfer_support = true, 821 .has_per_pkt_xfer_complete_irq = true, 822 .has_single_clk_source = true, 823 .clk_divisor_hs_mode = 1, 824 .clk_divisor_std_fast_mode = 0x19, 825 .clk_divisor_fast_plus_mode = 0x10, 826 .has_config_load_reg = false, 827 .has_multi_master_mode = false, 828 .has_slcg_override_reg = false, 829 }; 830 831 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 832 .has_continue_xfer_support = true, 833 .has_per_pkt_xfer_complete_irq = true, 834 .has_single_clk_source = true, 835 .clk_divisor_hs_mode = 1, 836 .clk_divisor_std_fast_mode = 0x19, 837 .clk_divisor_fast_plus_mode = 0x10, 838 .has_config_load_reg = true, 839 .has_multi_master_mode = false, 840 .has_slcg_override_reg = true, 841 }; 842 843 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 844 .has_continue_xfer_support = true, 845 .has_per_pkt_xfer_complete_irq = true, 846 .has_single_clk_source = true, 847 .clk_divisor_hs_mode = 1, 848 .clk_divisor_std_fast_mode = 0x19, 849 .clk_divisor_fast_plus_mode = 0x10, 850 .has_config_load_reg = true, 851 .has_multi_master_mode = true, 852 .has_slcg_override_reg = true, 853 }; 854 855 /* Match table for of_platform binding */ 856 static const struct of_device_id tegra_i2c_of_match[] = { 857 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 858 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 859 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 860 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 861 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 862 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 863 {}, 864 }; 865 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 866 867 static int tegra_i2c_probe(struct platform_device *pdev) 868 { 869 struct tegra_i2c_dev *i2c_dev; 870 struct resource *res; 871 struct clk *div_clk; 872 struct clk *fast_clk; 873 void __iomem *base; 874 int irq; 875 int ret = 0; 876 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE; 877 878 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 879 base = devm_ioremap_resource(&pdev->dev, res); 880 if (IS_ERR(base)) 881 return PTR_ERR(base); 882 883 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 884 if (!res) { 885 dev_err(&pdev->dev, "no irq resource\n"); 886 return -EINVAL; 887 } 888 irq = res->start; 889 890 div_clk = devm_clk_get(&pdev->dev, "div-clk"); 891 if (IS_ERR(div_clk)) { 892 dev_err(&pdev->dev, "missing controller clock\n"); 893 return PTR_ERR(div_clk); 894 } 895 896 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 897 if (!i2c_dev) 898 return -ENOMEM; 899 900 i2c_dev->base = base; 901 i2c_dev->div_clk = div_clk; 902 i2c_dev->adapter.algo = &tegra_i2c_algo; 903 i2c_dev->adapter.quirks = &tegra_i2c_quirks; 904 i2c_dev->irq = irq; 905 i2c_dev->cont_id = pdev->id; 906 i2c_dev->dev = &pdev->dev; 907 908 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); 909 if (IS_ERR(i2c_dev->rst)) { 910 dev_err(&pdev->dev, "missing controller reset\n"); 911 return PTR_ERR(i2c_dev->rst); 912 } 913 914 tegra_i2c_parse_dt(i2c_dev); 915 916 i2c_dev->hw = of_device_get_match_data(&pdev->dev); 917 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 918 "nvidia,tegra20-i2c-dvc"); 919 init_completion(&i2c_dev->msg_complete); 920 spin_lock_init(&i2c_dev->xfer_lock); 921 922 if (!i2c_dev->hw->has_single_clk_source) { 923 fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); 924 if (IS_ERR(fast_clk)) { 925 dev_err(&pdev->dev, "missing fast clock\n"); 926 return PTR_ERR(fast_clk); 927 } 928 i2c_dev->fast_clk = fast_clk; 929 } 930 931 platform_set_drvdata(pdev, i2c_dev); 932 933 if (!i2c_dev->hw->has_single_clk_source) { 934 ret = clk_prepare(i2c_dev->fast_clk); 935 if (ret < 0) { 936 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 937 return ret; 938 } 939 } 940 941 i2c_dev->clk_divisor_non_hs_mode = 942 i2c_dev->hw->clk_divisor_std_fast_mode; 943 if (i2c_dev->hw->clk_divisor_fast_plus_mode && 944 (i2c_dev->bus_clk_rate == 1000000)) 945 i2c_dev->clk_divisor_non_hs_mode = 946 i2c_dev->hw->clk_divisor_fast_plus_mode; 947 948 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); 949 ret = clk_set_rate(i2c_dev->div_clk, 950 i2c_dev->bus_clk_rate * clk_multiplier); 951 if (ret) { 952 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret); 953 goto unprepare_fast_clk; 954 } 955 956 ret = clk_prepare(i2c_dev->div_clk); 957 if (ret < 0) { 958 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 959 goto unprepare_fast_clk; 960 } 961 962 pm_runtime_enable(&pdev->dev); 963 if (!pm_runtime_enabled(&pdev->dev)) { 964 ret = tegra_i2c_runtime_resume(&pdev->dev); 965 if (ret < 0) { 966 dev_err(&pdev->dev, "runtime resume failed\n"); 967 goto unprepare_div_clk; 968 } 969 } 970 971 if (i2c_dev->is_multimaster_mode) { 972 ret = clk_enable(i2c_dev->div_clk); 973 if (ret < 0) { 974 dev_err(i2c_dev->dev, "div_clk enable failed %d\n", 975 ret); 976 goto disable_rpm; 977 } 978 } 979 980 ret = tegra_i2c_init(i2c_dev); 981 if (ret) { 982 dev_err(&pdev->dev, "Failed to initialize i2c controller\n"); 983 goto disable_div_clk; 984 } 985 986 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 987 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); 988 if (ret) { 989 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 990 goto disable_div_clk; 991 } 992 993 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 994 i2c_dev->adapter.owner = THIS_MODULE; 995 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 996 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev), 997 sizeof(i2c_dev->adapter.name)); 998 i2c_dev->adapter.dev.parent = &pdev->dev; 999 i2c_dev->adapter.nr = pdev->id; 1000 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 1001 1002 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 1003 if (ret) 1004 goto disable_div_clk; 1005 1006 return 0; 1007 1008 disable_div_clk: 1009 if (i2c_dev->is_multimaster_mode) 1010 clk_disable(i2c_dev->div_clk); 1011 1012 disable_rpm: 1013 pm_runtime_disable(&pdev->dev); 1014 if (!pm_runtime_status_suspended(&pdev->dev)) 1015 tegra_i2c_runtime_suspend(&pdev->dev); 1016 1017 unprepare_div_clk: 1018 clk_unprepare(i2c_dev->div_clk); 1019 1020 unprepare_fast_clk: 1021 if (!i2c_dev->hw->has_single_clk_source) 1022 clk_unprepare(i2c_dev->fast_clk); 1023 1024 return ret; 1025 } 1026 1027 static int tegra_i2c_remove(struct platform_device *pdev) 1028 { 1029 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1030 1031 i2c_del_adapter(&i2c_dev->adapter); 1032 1033 if (i2c_dev->is_multimaster_mode) 1034 clk_disable(i2c_dev->div_clk); 1035 1036 pm_runtime_disable(&pdev->dev); 1037 if (!pm_runtime_status_suspended(&pdev->dev)) 1038 tegra_i2c_runtime_suspend(&pdev->dev); 1039 1040 clk_unprepare(i2c_dev->div_clk); 1041 if (!i2c_dev->hw->has_single_clk_source) 1042 clk_unprepare(i2c_dev->fast_clk); 1043 1044 return 0; 1045 } 1046 1047 #ifdef CONFIG_PM_SLEEP 1048 static const struct dev_pm_ops tegra_i2c_pm = { 1049 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1050 NULL) 1051 }; 1052 #define TEGRA_I2C_PM (&tegra_i2c_pm) 1053 #else 1054 #define TEGRA_I2C_PM NULL 1055 #endif 1056 1057 static struct platform_driver tegra_i2c_driver = { 1058 .probe = tegra_i2c_probe, 1059 .remove = tegra_i2c_remove, 1060 .driver = { 1061 .name = "tegra-i2c", 1062 .of_match_table = tegra_i2c_of_match, 1063 .pm = TEGRA_I2C_PM, 1064 }, 1065 }; 1066 1067 static int __init tegra_i2c_init_driver(void) 1068 { 1069 return platform_driver_register(&tegra_i2c_driver); 1070 } 1071 1072 static void __exit tegra_i2c_exit_driver(void) 1073 { 1074 platform_driver_unregister(&tegra_i2c_driver); 1075 } 1076 1077 subsys_initcall(tegra_i2c_init_driver); 1078 module_exit(tegra_i2c_exit_driver); 1079 1080 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 1081 MODULE_AUTHOR("Colin Cross"); 1082 MODULE_LICENSE("GPL v2"); 1083