1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/kernel.h> 23 #include <linux/ktime.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/reset.h> 30 31 #define BYTES_PER_FIFO_WORD 4 32 33 #define I2C_CNFG 0x000 34 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 35 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 36 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 37 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 38 #define I2C_STATUS 0x01c 39 #define I2C_SL_CNFG 0x020 40 #define I2C_SL_CNFG_NACK BIT(1) 41 #define I2C_SL_CNFG_NEWSL BIT(2) 42 #define I2C_SL_ADDR1 0x02c 43 #define I2C_SL_ADDR2 0x030 44 #define I2C_TLOW_SEXT 0x034 45 #define I2C_TX_FIFO 0x050 46 #define I2C_RX_FIFO 0x054 47 #define I2C_PACKET_TRANSFER_STATUS 0x058 48 #define I2C_FIFO_CONTROL 0x05c 49 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 50 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 53 #define I2C_FIFO_STATUS 0x060 54 #define I2C_FIFO_STATUS_TX GENMASK(7, 4) 55 #define I2C_FIFO_STATUS_RX GENMASK(3, 0) 56 #define I2C_INT_MASK 0x064 57 #define I2C_INT_STATUS 0x068 58 #define I2C_INT_BUS_CLR_DONE BIT(11) 59 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 60 #define I2C_INT_NO_ACK BIT(3) 61 #define I2C_INT_ARBITRATION_LOST BIT(2) 62 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 63 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 64 #define I2C_CLK_DIVISOR 0x06c 65 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 66 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 67 68 #define DVC_CTRL_REG1 0x000 69 #define DVC_CTRL_REG1_INTR_EN BIT(10) 70 #define DVC_CTRL_REG3 0x008 71 #define DVC_CTRL_REG3_SW_PROG BIT(26) 72 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 73 #define DVC_STATUS 0x00c 74 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 75 76 #define I2C_ERR_NONE 0x00 77 #define I2C_ERR_NO_ACK BIT(0) 78 #define I2C_ERR_ARBITRATION_LOST BIT(1) 79 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 80 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 81 82 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28) 83 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16) 84 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12) 85 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 86 #define PACKET_HEADER0_PROTOCOL_I2C 1 87 88 #define I2C_HEADER_CONT_ON_NAK BIT(21) 89 #define I2C_HEADER_READ BIT(19) 90 #define I2C_HEADER_10BIT_ADDR BIT(18) 91 #define I2C_HEADER_IE_ENABLE BIT(17) 92 #define I2C_HEADER_REPEAT_START BIT(16) 93 #define I2C_HEADER_CONTINUE_XFER BIT(15) 94 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 95 96 #define I2C_BUS_CLEAR_CNFG 0x084 97 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 98 #define I2C_BC_STOP_COND BIT(2) 99 #define I2C_BC_TERMINATE BIT(1) 100 #define I2C_BC_ENABLE BIT(0) 101 #define I2C_BUS_CLEAR_STATUS 0x088 102 #define I2C_BC_STATUS BIT(0) 103 104 #define I2C_CONFIG_LOAD 0x08c 105 #define I2C_MSTR_CONFIG_LOAD BIT(0) 106 107 #define I2C_CLKEN_OVERRIDE 0x090 108 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 109 110 #define I2C_INTERFACE_TIMING_0 0x094 111 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 112 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 113 #define I2C_INTERFACE_TIMING_1 0x098 114 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 115 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 116 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 117 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 118 119 #define I2C_HS_INTERFACE_TIMING_0 0x09c 120 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 121 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 122 #define I2C_HS_INTERFACE_TIMING_1 0x0a0 123 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 124 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 125 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 126 127 #define I2C_MST_FIFO_CONTROL 0x0b4 128 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 129 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 132 133 #define I2C_MST_FIFO_STATUS 0x0b8 134 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 135 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 136 137 /* configuration load timeout in microseconds */ 138 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 139 140 /* packet header size in bytes */ 141 #define I2C_PACKET_HEADER_SIZE 12 142 143 /* 144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 145 * avoid DMA overhead, otherwise external APB DMA controller will be used. 146 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 147 * I2C_PACKET_HEADER_SIZE. 148 */ 149 #define I2C_PIO_MODE_PREFERRED_LEN 32 150 151 /* 152 * msg_end_type: The bus control which needs to be sent at end of transfer. 153 * @MSG_END_STOP: Send stop pulse. 154 * @MSG_END_REPEAT_START: Send repeat-start. 155 * @MSG_END_CONTINUE: Don't send stop or repeat-start. 156 */ 157 enum msg_end_type { 158 MSG_END_STOP, 159 MSG_END_REPEAT_START, 160 MSG_END_CONTINUE, 161 }; 162 163 /** 164 * struct tegra_i2c_hw_feature : per hardware generation features 165 * @has_continue_xfer_support: continue-transfer supported 166 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 167 * completion interrupt on per packet basis. 168 * @has_config_load_reg: Has the config load register to load the new 169 * configuration. 170 * @clk_divisor_hs_mode: Clock divisor in HS mode. 171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 172 * applicable if there is no fast clock source i.e. single clock 173 * source. 174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 175 * applicable if there is no fast clock source i.e. single clock 176 * source. 177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 178 * applicable if there is no fast clock source (i.e. single 179 * clock source). 180 * @has_multi_master_mode: The I2C controller supports running in single-master 181 * or multi-master mode. 182 * @has_slcg_override_reg: The I2C controller supports a register that 183 * overrides the second level clock gating. 184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 185 * provides additional features and allows for longer messages to 186 * be transferred in one go. 187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not 188 * allowing 0 length transfers. 189 * @supports_bus_clear: Bus Clear support to recover from bus hang during 190 * SDA stuck low from device for some unknown reasons. 191 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 192 * @tlow_std_mode: Low period of the clock in standard mode. 193 * @thigh_std_mode: High period of the clock in standard mode. 194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 196 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 197 * in standard mode. 198 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 199 * conditions in fast/fast-plus modes. 200 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 201 * in HS mode. 202 * @has_interface_timing_reg: Has interface timing register to program the tuned 203 * timing settings. 204 */ 205 struct tegra_i2c_hw_feature { 206 bool has_continue_xfer_support; 207 bool has_per_pkt_xfer_complete_irq; 208 bool has_config_load_reg; 209 u32 clk_divisor_hs_mode; 210 u32 clk_divisor_std_mode; 211 u32 clk_divisor_fast_mode; 212 u32 clk_divisor_fast_plus_mode; 213 bool has_multi_master_mode; 214 bool has_slcg_override_reg; 215 bool has_mst_fifo; 216 const struct i2c_adapter_quirks *quirks; 217 bool supports_bus_clear; 218 bool has_apb_dma; 219 u32 tlow_std_mode; 220 u32 thigh_std_mode; 221 u32 tlow_fast_fastplus_mode; 222 u32 thigh_fast_fastplus_mode; 223 u32 setup_hold_time_std_mode; 224 u32 setup_hold_time_fast_fast_plus_mode; 225 u32 setup_hold_time_hs_mode; 226 bool has_interface_timing_reg; 227 }; 228 229 /** 230 * struct tegra_i2c_dev - per device I2C context 231 * @dev: device reference for power management 232 * @hw: Tegra I2C HW feature 233 * @adapter: core I2C layer adapter information 234 * @div_clk: clock reference for div clock of I2C controller 235 * @clocks: array of I2C controller clocks 236 * @nclocks: number of clocks in the array 237 * @rst: reset control for the I2C controller 238 * @base: ioremapped registers cookie 239 * @base_phys: physical base address of the I2C controller 240 * @cont_id: I2C controller ID, used for packet header 241 * @irq: IRQ number of transfer complete interrupt 242 * @is_dvc: identifies the DVC I2C controller, has a different register layout 243 * @is_vi: identifies the VI I2C controller, has a different register layout 244 * @msg_complete: transfer completion notifier 245 * @msg_err: error code for completed message 246 * @msg_buf: pointer to current message data 247 * @msg_buf_remaining: size of unsent data in the message buffer 248 * @msg_read: indicates that the transfer is a read access 249 * @timings: i2c timings information like bus frequency 250 * @multimaster_mode: indicates that I2C controller is in multi-master mode 251 * @tx_dma_chan: DMA transmit channel 252 * @rx_dma_chan: DMA receive channel 253 * @dma_phys: handle to DMA resources 254 * @dma_buf: pointer to allocated DMA buffer 255 * @dma_buf_size: DMA buffer size 256 * @dma_mode: indicates active DMA transfer 257 * @dma_complete: DMA completion notifier 258 * @atomic_mode: indicates active atomic transfer 259 */ 260 struct tegra_i2c_dev { 261 struct device *dev; 262 struct i2c_adapter adapter; 263 264 const struct tegra_i2c_hw_feature *hw; 265 struct reset_control *rst; 266 unsigned int cont_id; 267 unsigned int irq; 268 269 phys_addr_t base_phys; 270 void __iomem *base; 271 272 struct clk_bulk_data clocks[2]; 273 unsigned int nclocks; 274 275 struct clk *div_clk; 276 struct i2c_timings timings; 277 278 struct completion msg_complete; 279 size_t msg_buf_remaining; 280 int msg_err; 281 u8 *msg_buf; 282 283 struct completion dma_complete; 284 struct dma_chan *tx_dma_chan; 285 struct dma_chan *rx_dma_chan; 286 unsigned int dma_buf_size; 287 dma_addr_t dma_phys; 288 void *dma_buf; 289 290 bool multimaster_mode; 291 bool atomic_mode; 292 bool dma_mode; 293 bool msg_read; 294 bool is_dvc; 295 bool is_vi; 296 }; 297 298 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 299 unsigned int reg) 300 { 301 writel_relaxed(val, i2c_dev->base + reg); 302 } 303 304 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 305 { 306 return readl_relaxed(i2c_dev->base + reg); 307 } 308 309 /* 310 * If necessary, i2c_writel() and i2c_readl() will offset the register 311 * in order to talk to the I2C block inside the DVC block. 312 */ 313 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 314 { 315 if (i2c_dev->is_dvc) 316 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 317 else if (i2c_dev->is_vi) 318 reg = 0xc00 + (reg << 2); 319 320 return reg; 321 } 322 323 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 324 { 325 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 326 327 /* read back register to make sure that register writes completed */ 328 if (reg != I2C_TX_FIFO) 329 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 330 else if (i2c_dev->is_vi) 331 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 332 } 333 334 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 335 { 336 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 337 } 338 339 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 340 unsigned int reg, unsigned int len) 341 { 342 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 343 } 344 345 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, 346 unsigned int reg, unsigned int len) 347 { 348 u32 *data32 = data; 349 350 /* 351 * VI I2C controller has known hardware bug where writes get stuck 352 * when immediate multiple writes happen to TX_FIFO register. 353 * Recommended software work around is to read I2C register after 354 * each write to TX_FIFO register to flush out the data. 355 */ 356 while (len--) 357 i2c_writel(i2c_dev, *data32++, reg); 358 } 359 360 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 361 unsigned int reg, unsigned int len) 362 { 363 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 364 } 365 366 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 367 { 368 u32 int_mask; 369 370 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 371 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 372 } 373 374 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 375 { 376 u32 int_mask; 377 378 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 379 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 380 } 381 382 static void tegra_i2c_dma_complete(void *args) 383 { 384 struct tegra_i2c_dev *i2c_dev = args; 385 386 complete(&i2c_dev->dma_complete); 387 } 388 389 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 390 { 391 struct dma_async_tx_descriptor *dma_desc; 392 enum dma_transfer_direction dir; 393 struct dma_chan *chan; 394 395 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 396 397 reinit_completion(&i2c_dev->dma_complete); 398 399 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 400 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; 401 402 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, 403 len, dir, DMA_PREP_INTERRUPT | 404 DMA_CTRL_ACK); 405 if (!dma_desc) { 406 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", 407 i2c_dev->msg_read ? "RX" : "TX"); 408 return -EINVAL; 409 } 410 411 dma_desc->callback = tegra_i2c_dma_complete; 412 dma_desc->callback_param = i2c_dev; 413 414 dmaengine_submit(dma_desc); 415 dma_async_issue_pending(chan); 416 417 return 0; 418 } 419 420 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 421 { 422 if (i2c_dev->dma_buf) { 423 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 424 i2c_dev->dma_buf, i2c_dev->dma_phys); 425 i2c_dev->dma_buf = NULL; 426 } 427 428 if (i2c_dev->tx_dma_chan) { 429 dma_release_channel(i2c_dev->tx_dma_chan); 430 i2c_dev->tx_dma_chan = NULL; 431 } 432 433 if (i2c_dev->rx_dma_chan) { 434 dma_release_channel(i2c_dev->rx_dma_chan); 435 i2c_dev->rx_dma_chan = NULL; 436 } 437 } 438 439 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 440 { 441 struct dma_chan *chan; 442 dma_addr_t dma_phys; 443 u32 *dma_buf; 444 int err; 445 446 if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) 447 return 0; 448 449 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 450 dev_dbg(i2c_dev->dev, "DMA support not enabled\n"); 451 return 0; 452 } 453 454 chan = dma_request_chan(i2c_dev->dev, "rx"); 455 if (IS_ERR(chan)) { 456 err = PTR_ERR(chan); 457 goto err_out; 458 } 459 460 i2c_dev->rx_dma_chan = chan; 461 462 chan = dma_request_chan(i2c_dev->dev, "tx"); 463 if (IS_ERR(chan)) { 464 err = PTR_ERR(chan); 465 goto err_out; 466 } 467 468 i2c_dev->tx_dma_chan = chan; 469 470 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + 471 I2C_PACKET_HEADER_SIZE; 472 473 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 474 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 475 if (!dma_buf) { 476 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); 477 err = -ENOMEM; 478 goto err_out; 479 } 480 481 i2c_dev->dma_buf = dma_buf; 482 i2c_dev->dma_phys = dma_phys; 483 484 return 0; 485 486 err_out: 487 tegra_i2c_release_dma(i2c_dev); 488 if (err != -EPROBE_DEFER) { 489 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 490 dev_err(i2c_dev->dev, "falling back to PIO\n"); 491 return 0; 492 } 493 494 return err; 495 } 496 497 /* 498 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 499 * block. This block is identical to the rest of the I2C blocks, except that 500 * it only supports master mode, it has registers moved around, and it needs 501 * some extra init to get it into I2C mode. The register moves are handled 502 * by i2c_readl() and i2c_writel(). 503 */ 504 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 505 { 506 u32 val; 507 508 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 509 val |= DVC_CTRL_REG3_SW_PROG; 510 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 511 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 512 513 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 514 val |= DVC_CTRL_REG1_INTR_EN; 515 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 516 } 517 518 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) 519 { 520 u32 value; 521 522 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 523 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 524 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 525 526 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 527 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 528 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 529 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 530 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 531 532 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 533 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 534 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 535 536 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 537 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 538 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 539 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 540 541 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 542 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 543 544 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 545 } 546 547 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 548 u32 reg, u32 mask, u32 delay_us, 549 u32 timeout_us) 550 { 551 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 552 u32 val; 553 554 if (!i2c_dev->atomic_mode) 555 return readl_relaxed_poll_timeout(addr, val, !(val & mask), 556 delay_us, timeout_us); 557 558 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), 559 delay_us, timeout_us); 560 } 561 562 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 563 { 564 u32 mask, val, offset; 565 int err; 566 567 if (i2c_dev->hw->has_mst_fifo) { 568 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 569 I2C_MST_FIFO_CONTROL_RX_FLUSH; 570 offset = I2C_MST_FIFO_CONTROL; 571 } else { 572 mask = I2C_FIFO_CONTROL_TX_FLUSH | 573 I2C_FIFO_CONTROL_RX_FLUSH; 574 offset = I2C_FIFO_CONTROL; 575 } 576 577 val = i2c_readl(i2c_dev, offset); 578 val |= mask; 579 i2c_writel(i2c_dev, val, offset); 580 581 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000); 582 if (err) { 583 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); 584 return err; 585 } 586 587 return 0; 588 } 589 590 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 591 { 592 int err; 593 594 if (!i2c_dev->hw->has_config_load_reg) 595 return 0; 596 597 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 598 599 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 600 1000, I2C_CONFIG_LOAD_TIMEOUT); 601 if (err) { 602 dev_err(i2c_dev->dev, "failed to load config\n"); 603 return err; 604 } 605 606 return 0; 607 } 608 609 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 610 { 611 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 612 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); 613 struct i2c_timings *t = &i2c_dev->timings; 614 int err; 615 616 /* 617 * The reset shouldn't ever fail in practice. The failure will be a 618 * sign of a severe problem that needs to be resolved. Still we don't 619 * want to fail the initialization completely because this may break 620 * kernel boot up since voltage regulators use I2C. Hence, we will 621 * emit a noisy warning on error, which won't stay unnoticed and 622 * won't hose machine entirely. 623 */ 624 if (handle) 625 err = acpi_evaluate_object(handle, "_RST", NULL, NULL); 626 else 627 err = reset_control_reset(i2c_dev->rst); 628 629 WARN_ON_ONCE(err); 630 631 if (i2c_dev->is_dvc) 632 tegra_dvc_init(i2c_dev); 633 634 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 635 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); 636 637 if (i2c_dev->hw->has_multi_master_mode) 638 val |= I2C_CNFG_MULTI_MASTER_MODE; 639 640 i2c_writel(i2c_dev, val, I2C_CNFG); 641 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 642 643 if (i2c_dev->is_vi) 644 tegra_i2c_vi_init(i2c_dev); 645 646 switch (t->bus_freq_hz) { 647 case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 648 default: 649 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 650 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 651 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 652 653 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 654 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 655 else 656 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 657 break; 658 659 case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 660 tlow = i2c_dev->hw->tlow_std_mode; 661 thigh = i2c_dev->hw->thigh_std_mode; 662 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 663 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 664 break; 665 } 666 667 /* make sure clock divisor programmed correctly */ 668 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 669 i2c_dev->hw->clk_divisor_hs_mode) | 670 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 671 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 672 673 if (i2c_dev->hw->has_interface_timing_reg) { 674 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 675 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 676 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 677 } 678 679 /* 680 * Configure setup and hold times only when tsu_thd is non-zero. 681 * Otherwise, preserve the chip default values. 682 */ 683 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 684 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 685 686 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 687 688 err = clk_set_rate(i2c_dev->div_clk, 689 t->bus_freq_hz * clk_multiplier); 690 if (err) { 691 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); 692 return err; 693 } 694 695 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) { 696 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 697 698 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 699 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 700 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 701 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 702 } 703 704 err = tegra_i2c_flush_fifos(i2c_dev); 705 if (err) 706 return err; 707 708 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 709 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 710 711 err = tegra_i2c_wait_for_config_load(i2c_dev); 712 if (err) 713 return err; 714 715 return 0; 716 } 717 718 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 719 { 720 u32 cnfg; 721 722 /* 723 * NACK interrupt is generated before the I2C controller generates 724 * the STOP condition on the bus. So, wait for 2 clock periods 725 * before disabling the controller so that the STOP condition has 726 * been delivered properly. 727 */ 728 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); 729 730 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 731 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 732 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 733 734 return tegra_i2c_wait_for_config_load(i2c_dev); 735 } 736 737 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 738 { 739 size_t buf_remaining = i2c_dev->msg_buf_remaining; 740 unsigned int words_to_transfer, rx_fifo_avail; 741 u8 *buf = i2c_dev->msg_buf; 742 u32 val; 743 744 /* 745 * Catch overflow due to message fully sent before the check for 746 * RX FIFO availability. 747 */ 748 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 749 return -EINVAL; 750 751 if (i2c_dev->hw->has_mst_fifo) { 752 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 753 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 754 } else { 755 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 756 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 757 } 758 759 /* round down to exclude partial word at the end of buffer */ 760 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 761 if (words_to_transfer > rx_fifo_avail) 762 words_to_transfer = rx_fifo_avail; 763 764 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 765 766 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 767 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 768 rx_fifo_avail -= words_to_transfer; 769 770 /* 771 * If there is a partial word at the end of buffer, handle it 772 * manually to prevent overwriting past the end of buffer. 773 */ 774 if (rx_fifo_avail > 0 && buf_remaining > 0) { 775 /* 776 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 777 * when (words_to_transfer was > rx_fifo_avail) earlier 778 * in this function. 779 */ 780 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 781 val = cpu_to_le32(val); 782 memcpy(buf, &val, buf_remaining); 783 buf_remaining = 0; 784 rx_fifo_avail--; 785 } 786 787 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 788 if (WARN_ON_ONCE(rx_fifo_avail)) 789 return -EINVAL; 790 791 i2c_dev->msg_buf_remaining = buf_remaining; 792 i2c_dev->msg_buf = buf; 793 794 return 0; 795 } 796 797 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 798 { 799 size_t buf_remaining = i2c_dev->msg_buf_remaining; 800 unsigned int words_to_transfer, tx_fifo_avail; 801 u8 *buf = i2c_dev->msg_buf; 802 u32 val; 803 804 if (i2c_dev->hw->has_mst_fifo) { 805 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 806 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 807 } else { 808 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 809 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 810 } 811 812 /* round down to exclude partial word at the end of buffer */ 813 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 814 815 /* 816 * This hunk pushes 4 bytes at a time into the TX FIFO. 817 * 818 * It's very common to have < 4 bytes, hence there is no word 819 * to push if we have less than 4 bytes to transfer. 820 */ 821 if (words_to_transfer) { 822 if (words_to_transfer > tx_fifo_avail) 823 words_to_transfer = tx_fifo_avail; 824 825 /* 826 * Update state before writing to FIFO. Note that this may 827 * cause us to finish writing all bytes (AKA buf_remaining 828 * goes to 0), hence we have a potential for an interrupt 829 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt 830 * is disabled at this point. 831 */ 832 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 833 tx_fifo_avail -= words_to_transfer; 834 835 i2c_dev->msg_buf_remaining = buf_remaining; 836 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 837 838 if (i2c_dev->is_vi) 839 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 840 else 841 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 842 843 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 844 } 845 846 /* 847 * If there is a partial word at the end of buffer, handle it manually 848 * to prevent reading past the end of buffer, which could cross a page 849 * boundary and fault. 850 */ 851 if (tx_fifo_avail > 0 && buf_remaining > 0) { 852 /* 853 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 854 * when (words_to_transfer was > tx_fifo_avail) earlier 855 * in this function for non-zero words_to_transfer. 856 */ 857 memcpy(&val, buf, buf_remaining); 858 val = le32_to_cpu(val); 859 860 i2c_dev->msg_buf_remaining = 0; 861 i2c_dev->msg_buf = NULL; 862 863 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 864 } 865 866 return 0; 867 } 868 869 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 870 { 871 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 872 struct tegra_i2c_dev *i2c_dev = dev_id; 873 u32 status; 874 875 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 876 877 if (status == 0) { 878 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 879 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 880 i2c_readl(i2c_dev, I2C_STATUS), 881 i2c_readl(i2c_dev, I2C_CNFG)); 882 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 883 goto err; 884 } 885 886 if (status & status_err) { 887 tegra_i2c_disable_packet_mode(i2c_dev); 888 if (status & I2C_INT_NO_ACK) 889 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 890 if (status & I2C_INT_ARBITRATION_LOST) 891 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 892 goto err; 893 } 894 895 /* 896 * I2C transfer is terminated during the bus clear, so skip 897 * processing the other interrupts. 898 */ 899 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 900 goto err; 901 902 if (!i2c_dev->dma_mode) { 903 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 904 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 905 /* 906 * Overflow error condition: message fully sent, 907 * with no XFER_COMPLETE interrupt but hardware 908 * asks to transfer more. 909 */ 910 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 911 goto err; 912 } 913 } 914 915 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 916 if (i2c_dev->msg_buf_remaining) 917 tegra_i2c_fill_tx_fifo(i2c_dev); 918 else 919 tegra_i2c_mask_irq(i2c_dev, 920 I2C_INT_TX_FIFO_DATA_REQ); 921 } 922 } 923 924 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 925 if (i2c_dev->is_dvc) 926 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 927 928 /* 929 * During message read XFER_COMPLETE interrupt is triggered prior to 930 * DMA completion and during message write XFER_COMPLETE interrupt is 931 * triggered after DMA completion. 932 * 933 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer, 934 * so forcing msg_buf_remaining to 0 in DMA mode. 935 */ 936 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 937 if (i2c_dev->dma_mode) 938 i2c_dev->msg_buf_remaining = 0; 939 /* 940 * Underflow error condition: XFER_COMPLETE before message 941 * fully sent. 942 */ 943 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 944 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 945 goto err; 946 } 947 complete(&i2c_dev->msg_complete); 948 } 949 goto done; 950 err: 951 /* mask all interrupts on error */ 952 tegra_i2c_mask_irq(i2c_dev, 953 I2C_INT_NO_ACK | 954 I2C_INT_ARBITRATION_LOST | 955 I2C_INT_PACKET_XFER_COMPLETE | 956 I2C_INT_TX_FIFO_DATA_REQ | 957 I2C_INT_RX_FIFO_DATA_REQ); 958 959 if (i2c_dev->hw->supports_bus_clear) 960 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 961 962 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 963 964 if (i2c_dev->is_dvc) 965 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 966 967 if (i2c_dev->dma_mode) { 968 if (i2c_dev->msg_read) 969 dmaengine_terminate_async(i2c_dev->rx_dma_chan); 970 else 971 dmaengine_terminate_async(i2c_dev->tx_dma_chan); 972 973 complete(&i2c_dev->dma_complete); 974 } 975 976 complete(&i2c_dev->msg_complete); 977 done: 978 return IRQ_HANDLED; 979 } 980 981 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 982 size_t len) 983 { 984 struct dma_slave_config slv_config = {0}; 985 u32 val, reg, dma_burst, reg_offset; 986 struct dma_chan *chan; 987 int err; 988 989 if (i2c_dev->hw->has_mst_fifo) 990 reg = I2C_MST_FIFO_CONTROL; 991 else 992 reg = I2C_FIFO_CONTROL; 993 994 if (i2c_dev->dma_mode) { 995 if (len & 0xF) 996 dma_burst = 1; 997 else if (len & 0x10) 998 dma_burst = 4; 999 else 1000 dma_burst = 8; 1001 1002 if (i2c_dev->msg_read) { 1003 chan = i2c_dev->rx_dma_chan; 1004 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 1005 1006 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 1007 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1008 slv_config.src_maxburst = dma_burst; 1009 1010 if (i2c_dev->hw->has_mst_fifo) 1011 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 1012 else 1013 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1014 } else { 1015 chan = i2c_dev->tx_dma_chan; 1016 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1017 1018 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1019 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1020 slv_config.dst_maxburst = dma_burst; 1021 1022 if (i2c_dev->hw->has_mst_fifo) 1023 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 1024 else 1025 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 1026 } 1027 1028 slv_config.device_fc = true; 1029 err = dmaengine_slave_config(chan, &slv_config); 1030 if (err) { 1031 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); 1032 dev_err(i2c_dev->dev, "falling back to PIO\n"); 1033 1034 tegra_i2c_release_dma(i2c_dev); 1035 i2c_dev->dma_mode = false; 1036 } else { 1037 goto out; 1038 } 1039 } 1040 1041 if (i2c_dev->hw->has_mst_fifo) 1042 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 1043 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 1044 else 1045 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 1046 I2C_FIFO_CONTROL_RX_TRIG(1); 1047 out: 1048 i2c_writel(i2c_dev, val, reg); 1049 } 1050 1051 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev, 1052 struct completion *complete, 1053 unsigned int timeout_ms) 1054 { 1055 ktime_t ktime = ktime_get(); 1056 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1057 1058 do { 1059 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1060 1061 if (status) 1062 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1063 1064 if (completion_done(complete)) { 1065 s64 delta = ktime_ms_delta(ktimeout, ktime); 1066 1067 return msecs_to_jiffies(delta) ?: 1; 1068 } 1069 1070 ktime = ktime_get(); 1071 1072 } while (ktime_before(ktime, ktimeout)); 1073 1074 return 0; 1075 } 1076 1077 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev, 1078 struct completion *complete, 1079 unsigned int timeout_ms) 1080 { 1081 unsigned long ret; 1082 1083 if (i2c_dev->atomic_mode) { 1084 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms); 1085 } else { 1086 enable_irq(i2c_dev->irq); 1087 ret = wait_for_completion_timeout(complete, 1088 msecs_to_jiffies(timeout_ms)); 1089 disable_irq(i2c_dev->irq); 1090 1091 /* 1092 * Under some rare circumstances (like running KASAN + 1093 * NFS root) CPU, which handles interrupt, may stuck in 1094 * uninterruptible state for a significant time. In this 1095 * case we will get timeout if I2C transfer is running on 1096 * a sibling CPU, despite of IRQ being raised. 1097 * 1098 * In order to handle this rare condition, the IRQ status 1099 * needs to be checked after timeout. 1100 */ 1101 if (ret == 0) 1102 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0); 1103 } 1104 1105 return ret; 1106 } 1107 1108 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1109 { 1110 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1111 u32 val, time_left; 1112 int err; 1113 1114 reinit_completion(&i2c_dev->msg_complete); 1115 1116 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1117 I2C_BC_TERMINATE; 1118 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1119 1120 err = tegra_i2c_wait_for_config_load(i2c_dev); 1121 if (err) 1122 return err; 1123 1124 val |= I2C_BC_ENABLE; 1125 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1126 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1127 1128 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); 1129 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1130 1131 if (time_left == 0) { 1132 dev_err(i2c_dev->dev, "failed to clear bus\n"); 1133 return -ETIMEDOUT; 1134 } 1135 1136 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1137 if (!(val & I2C_BC_STATUS)) { 1138 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1139 return -EIO; 1140 } 1141 1142 return -EAGAIN; 1143 } 1144 1145 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, 1146 struct i2c_msg *msg, 1147 enum msg_end_type end_state) 1148 { 1149 u32 *dma_buf = i2c_dev->dma_buf; 1150 u32 packet_header; 1151 1152 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) | 1153 FIELD_PREP(PACKET_HEADER0_PROTOCOL, 1154 PACKET_HEADER0_PROTOCOL_I2C) | 1155 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | 1156 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1); 1157 1158 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1159 *dma_buf++ = packet_header; 1160 else 1161 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1162 1163 packet_header = msg->len - 1; 1164 1165 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1166 *dma_buf++ = packet_header; 1167 else 1168 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1169 1170 packet_header = I2C_HEADER_IE_ENABLE; 1171 1172 if (end_state == MSG_END_CONTINUE) 1173 packet_header |= I2C_HEADER_CONTINUE_XFER; 1174 else if (end_state == MSG_END_REPEAT_START) 1175 packet_header |= I2C_HEADER_REPEAT_START; 1176 1177 if (msg->flags & I2C_M_TEN) { 1178 packet_header |= msg->addr; 1179 packet_header |= I2C_HEADER_10BIT_ADDR; 1180 } else { 1181 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1182 } 1183 1184 if (msg->flags & I2C_M_IGNORE_NAK) 1185 packet_header |= I2C_HEADER_CONT_ON_NAK; 1186 1187 if (msg->flags & I2C_M_RD) 1188 packet_header |= I2C_HEADER_READ; 1189 1190 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1191 *dma_buf++ = packet_header; 1192 else 1193 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1194 } 1195 1196 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, 1197 struct i2c_msg *msg) 1198 { 1199 if (i2c_dev->msg_err == I2C_ERR_NONE) 1200 return 0; 1201 1202 tegra_i2c_init(i2c_dev); 1203 1204 /* start recovery upon arbitration loss in single master mode */ 1205 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1206 if (!i2c_dev->multimaster_mode) 1207 return i2c_recover_bus(&i2c_dev->adapter); 1208 1209 return -EAGAIN; 1210 } 1211 1212 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1213 if (msg->flags & I2C_M_IGNORE_NAK) 1214 return 0; 1215 1216 return -EREMOTEIO; 1217 } 1218 1219 return -EIO; 1220 } 1221 1222 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1223 struct i2c_msg *msg, 1224 enum msg_end_type end_state) 1225 { 1226 unsigned long time_left, xfer_time = 100; 1227 size_t xfer_size; 1228 u32 int_mask; 1229 int err; 1230 1231 err = tegra_i2c_flush_fifos(i2c_dev); 1232 if (err) 1233 return err; 1234 1235 i2c_dev->msg_buf = msg->buf; 1236 1237 /* The condition true implies smbus block read and len is already read */ 1238 if (msg->flags & I2C_M_RECV_LEN && end_state != MSG_END_CONTINUE) 1239 i2c_dev->msg_buf = msg->buf + 1; 1240 1241 i2c_dev->msg_buf_remaining = msg->len; 1242 i2c_dev->msg_err = I2C_ERR_NONE; 1243 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); 1244 reinit_completion(&i2c_dev->msg_complete); 1245 1246 if (i2c_dev->msg_read) 1247 xfer_size = msg->len; 1248 else 1249 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; 1250 1251 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1252 1253 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && 1254 i2c_dev->dma_buf && !i2c_dev->atomic_mode; 1255 1256 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1257 1258 /* 1259 * Transfer time in mSec = Total bits / transfer rate 1260 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1261 */ 1262 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1263 i2c_dev->timings.bus_freq_hz); 1264 1265 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1266 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1267 1268 if (i2c_dev->dma_mode) { 1269 if (i2c_dev->msg_read) { 1270 dma_sync_single_for_device(i2c_dev->dev, 1271 i2c_dev->dma_phys, 1272 xfer_size, DMA_FROM_DEVICE); 1273 1274 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1275 if (err) 1276 return err; 1277 } else { 1278 dma_sync_single_for_cpu(i2c_dev->dev, 1279 i2c_dev->dma_phys, 1280 xfer_size, DMA_TO_DEVICE); 1281 } 1282 } 1283 1284 tegra_i2c_push_packet_header(i2c_dev, msg, end_state); 1285 1286 if (!i2c_dev->msg_read) { 1287 if (i2c_dev->dma_mode) { 1288 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, 1289 msg->buf, msg->len); 1290 1291 dma_sync_single_for_device(i2c_dev->dev, 1292 i2c_dev->dma_phys, 1293 xfer_size, DMA_TO_DEVICE); 1294 1295 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1296 if (err) 1297 return err; 1298 } else { 1299 tegra_i2c_fill_tx_fifo(i2c_dev); 1300 } 1301 } 1302 1303 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1304 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1305 1306 if (!i2c_dev->dma_mode) { 1307 if (msg->flags & I2C_M_RD) 1308 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1309 else if (i2c_dev->msg_buf_remaining) 1310 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1311 } 1312 1313 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1314 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1315 i2c_readl(i2c_dev, I2C_INT_MASK)); 1316 1317 if (i2c_dev->dma_mode) { 1318 time_left = tegra_i2c_wait_completion(i2c_dev, 1319 &i2c_dev->dma_complete, 1320 xfer_time); 1321 1322 /* 1323 * Synchronize DMA first, since dmaengine_terminate_sync() 1324 * performs synchronization after the transfer's termination 1325 * and we want to get a completion if transfer succeeded. 1326 */ 1327 dmaengine_synchronize(i2c_dev->msg_read ? 1328 i2c_dev->rx_dma_chan : 1329 i2c_dev->tx_dma_chan); 1330 1331 dmaengine_terminate_sync(i2c_dev->msg_read ? 1332 i2c_dev->rx_dma_chan : 1333 i2c_dev->tx_dma_chan); 1334 1335 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1336 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); 1337 tegra_i2c_init(i2c_dev); 1338 return -ETIMEDOUT; 1339 } 1340 1341 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1342 dma_sync_single_for_cpu(i2c_dev->dev, 1343 i2c_dev->dma_phys, 1344 xfer_size, DMA_FROM_DEVICE); 1345 1346 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len); 1347 } 1348 } 1349 1350 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 1351 xfer_time); 1352 1353 tegra_i2c_mask_irq(i2c_dev, int_mask); 1354 1355 if (time_left == 0) { 1356 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); 1357 tegra_i2c_init(i2c_dev); 1358 return -ETIMEDOUT; 1359 } 1360 1361 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1362 time_left, completion_done(&i2c_dev->msg_complete), 1363 i2c_dev->msg_err); 1364 1365 i2c_dev->dma_mode = false; 1366 1367 err = tegra_i2c_error_recover(i2c_dev, msg); 1368 if (err) 1369 return err; 1370 1371 return 0; 1372 } 1373 1374 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1375 int num) 1376 { 1377 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1378 int i, ret; 1379 1380 ret = pm_runtime_get_sync(i2c_dev->dev); 1381 if (ret < 0) { 1382 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1383 pm_runtime_put_noidle(i2c_dev->dev); 1384 return ret; 1385 } 1386 1387 for (i = 0; i < num; i++) { 1388 enum msg_end_type end_type = MSG_END_STOP; 1389 1390 if (i < (num - 1)) { 1391 /* check whether follow up message is coming */ 1392 if (msgs[i + 1].flags & I2C_M_NOSTART) 1393 end_type = MSG_END_CONTINUE; 1394 else 1395 end_type = MSG_END_REPEAT_START; 1396 } 1397 /* If M_RECV_LEN use ContinueXfer to read the first byte */ 1398 if (msgs[i].flags & I2C_M_RECV_LEN) { 1399 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE); 1400 if (ret) 1401 break; 1402 /* Set the read byte as msg len */ 1403 msgs[i].len = msgs[i].buf[0]; 1404 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); 1405 } 1406 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1407 if (ret) 1408 break; 1409 } 1410 1411 pm_runtime_put(i2c_dev->dev); 1412 1413 return ret ?: i; 1414 } 1415 1416 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1417 struct i2c_msg msgs[], int num) 1418 { 1419 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1420 int ret; 1421 1422 i2c_dev->atomic_mode = true; 1423 ret = tegra_i2c_xfer(adap, msgs, num); 1424 i2c_dev->atomic_mode = false; 1425 1426 return ret; 1427 } 1428 1429 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1430 { 1431 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1432 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1433 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1434 1435 if (i2c_dev->hw->has_continue_xfer_support) 1436 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1437 1438 return ret; 1439 } 1440 1441 static const struct i2c_algorithm tegra_i2c_algo = { 1442 .master_xfer = tegra_i2c_xfer, 1443 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1444 .functionality = tegra_i2c_func, 1445 }; 1446 1447 /* payload size is only 12 bit */ 1448 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1449 .flags = I2C_AQ_NO_ZERO_LEN, 1450 .max_read_len = SZ_4K, 1451 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1452 }; 1453 1454 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1455 .flags = I2C_AQ_NO_ZERO_LEN, 1456 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1457 }; 1458 1459 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1460 .recover_bus = tegra_i2c_issue_bus_clear, 1461 }; 1462 1463 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1464 .has_continue_xfer_support = false, 1465 .has_per_pkt_xfer_complete_irq = false, 1466 .clk_divisor_hs_mode = 3, 1467 .clk_divisor_std_mode = 0, 1468 .clk_divisor_fast_mode = 0, 1469 .clk_divisor_fast_plus_mode = 0, 1470 .has_config_load_reg = false, 1471 .has_multi_master_mode = false, 1472 .has_slcg_override_reg = false, 1473 .has_mst_fifo = false, 1474 .quirks = &tegra_i2c_quirks, 1475 .supports_bus_clear = false, 1476 .has_apb_dma = true, 1477 .tlow_std_mode = 0x4, 1478 .thigh_std_mode = 0x2, 1479 .tlow_fast_fastplus_mode = 0x4, 1480 .thigh_fast_fastplus_mode = 0x2, 1481 .setup_hold_time_std_mode = 0x0, 1482 .setup_hold_time_fast_fast_plus_mode = 0x0, 1483 .setup_hold_time_hs_mode = 0x0, 1484 .has_interface_timing_reg = false, 1485 }; 1486 1487 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1488 .has_continue_xfer_support = true, 1489 .has_per_pkt_xfer_complete_irq = false, 1490 .clk_divisor_hs_mode = 3, 1491 .clk_divisor_std_mode = 0, 1492 .clk_divisor_fast_mode = 0, 1493 .clk_divisor_fast_plus_mode = 0, 1494 .has_config_load_reg = false, 1495 .has_multi_master_mode = false, 1496 .has_slcg_override_reg = false, 1497 .has_mst_fifo = false, 1498 .quirks = &tegra_i2c_quirks, 1499 .supports_bus_clear = false, 1500 .has_apb_dma = true, 1501 .tlow_std_mode = 0x4, 1502 .thigh_std_mode = 0x2, 1503 .tlow_fast_fastplus_mode = 0x4, 1504 .thigh_fast_fastplus_mode = 0x2, 1505 .setup_hold_time_std_mode = 0x0, 1506 .setup_hold_time_fast_fast_plus_mode = 0x0, 1507 .setup_hold_time_hs_mode = 0x0, 1508 .has_interface_timing_reg = false, 1509 }; 1510 1511 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1512 .has_continue_xfer_support = true, 1513 .has_per_pkt_xfer_complete_irq = true, 1514 .clk_divisor_hs_mode = 1, 1515 .clk_divisor_std_mode = 0x19, 1516 .clk_divisor_fast_mode = 0x19, 1517 .clk_divisor_fast_plus_mode = 0x10, 1518 .has_config_load_reg = false, 1519 .has_multi_master_mode = false, 1520 .has_slcg_override_reg = false, 1521 .has_mst_fifo = false, 1522 .quirks = &tegra_i2c_quirks, 1523 .supports_bus_clear = true, 1524 .has_apb_dma = true, 1525 .tlow_std_mode = 0x4, 1526 .thigh_std_mode = 0x2, 1527 .tlow_fast_fastplus_mode = 0x4, 1528 .thigh_fast_fastplus_mode = 0x2, 1529 .setup_hold_time_std_mode = 0x0, 1530 .setup_hold_time_fast_fast_plus_mode = 0x0, 1531 .setup_hold_time_hs_mode = 0x0, 1532 .has_interface_timing_reg = false, 1533 }; 1534 1535 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1536 .has_continue_xfer_support = true, 1537 .has_per_pkt_xfer_complete_irq = true, 1538 .clk_divisor_hs_mode = 1, 1539 .clk_divisor_std_mode = 0x19, 1540 .clk_divisor_fast_mode = 0x19, 1541 .clk_divisor_fast_plus_mode = 0x10, 1542 .has_config_load_reg = true, 1543 .has_multi_master_mode = false, 1544 .has_slcg_override_reg = true, 1545 .has_mst_fifo = false, 1546 .quirks = &tegra_i2c_quirks, 1547 .supports_bus_clear = true, 1548 .has_apb_dma = true, 1549 .tlow_std_mode = 0x4, 1550 .thigh_std_mode = 0x2, 1551 .tlow_fast_fastplus_mode = 0x4, 1552 .thigh_fast_fastplus_mode = 0x2, 1553 .setup_hold_time_std_mode = 0x0, 1554 .setup_hold_time_fast_fast_plus_mode = 0x0, 1555 .setup_hold_time_hs_mode = 0x0, 1556 .has_interface_timing_reg = true, 1557 }; 1558 1559 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1560 .has_continue_xfer_support = true, 1561 .has_per_pkt_xfer_complete_irq = true, 1562 .clk_divisor_hs_mode = 1, 1563 .clk_divisor_std_mode = 0x19, 1564 .clk_divisor_fast_mode = 0x19, 1565 .clk_divisor_fast_plus_mode = 0x10, 1566 .has_config_load_reg = true, 1567 .has_multi_master_mode = false, 1568 .has_slcg_override_reg = true, 1569 .has_mst_fifo = false, 1570 .quirks = &tegra_i2c_quirks, 1571 .supports_bus_clear = true, 1572 .has_apb_dma = true, 1573 .tlow_std_mode = 0x4, 1574 .thigh_std_mode = 0x2, 1575 .tlow_fast_fastplus_mode = 0x4, 1576 .thigh_fast_fastplus_mode = 0x2, 1577 .setup_hold_time_std_mode = 0, 1578 .setup_hold_time_fast_fast_plus_mode = 0, 1579 .setup_hold_time_hs_mode = 0, 1580 .has_interface_timing_reg = true, 1581 }; 1582 1583 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1584 .has_continue_xfer_support = true, 1585 .has_per_pkt_xfer_complete_irq = true, 1586 .clk_divisor_hs_mode = 1, 1587 .clk_divisor_std_mode = 0x16, 1588 .clk_divisor_fast_mode = 0x19, 1589 .clk_divisor_fast_plus_mode = 0x10, 1590 .has_config_load_reg = true, 1591 .has_multi_master_mode = false, 1592 .has_slcg_override_reg = true, 1593 .has_mst_fifo = false, 1594 .quirks = &tegra_i2c_quirks, 1595 .supports_bus_clear = true, 1596 .has_apb_dma = false, 1597 .tlow_std_mode = 0x4, 1598 .thigh_std_mode = 0x3, 1599 .tlow_fast_fastplus_mode = 0x4, 1600 .thigh_fast_fastplus_mode = 0x2, 1601 .setup_hold_time_std_mode = 0, 1602 .setup_hold_time_fast_fast_plus_mode = 0, 1603 .setup_hold_time_hs_mode = 0, 1604 .has_interface_timing_reg = true, 1605 }; 1606 1607 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1608 .has_continue_xfer_support = true, 1609 .has_per_pkt_xfer_complete_irq = true, 1610 .clk_divisor_hs_mode = 1, 1611 .clk_divisor_std_mode = 0x4f, 1612 .clk_divisor_fast_mode = 0x3c, 1613 .clk_divisor_fast_plus_mode = 0x16, 1614 .has_config_load_reg = true, 1615 .has_multi_master_mode = true, 1616 .has_slcg_override_reg = true, 1617 .has_mst_fifo = true, 1618 .quirks = &tegra194_i2c_quirks, 1619 .supports_bus_clear = true, 1620 .has_apb_dma = false, 1621 .tlow_std_mode = 0x8, 1622 .thigh_std_mode = 0x7, 1623 .tlow_fast_fastplus_mode = 0x2, 1624 .thigh_fast_fastplus_mode = 0x2, 1625 .setup_hold_time_std_mode = 0x08080808, 1626 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1627 .setup_hold_time_hs_mode = 0x090909, 1628 .has_interface_timing_reg = true, 1629 }; 1630 1631 static const struct of_device_id tegra_i2c_of_match[] = { 1632 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1633 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1634 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1635 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1636 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1637 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1638 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1639 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1640 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1641 {}, 1642 }; 1643 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1644 1645 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1646 { 1647 struct device_node *np = i2c_dev->dev->of_node; 1648 bool multi_mode; 1649 1650 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); 1651 1652 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); 1653 i2c_dev->multimaster_mode = multi_mode; 1654 1655 if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 1656 i2c_dev->is_dvc = true; 1657 1658 if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 1659 i2c_dev->is_vi = true; 1660 } 1661 1662 static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) 1663 { 1664 if (ACPI_HANDLE(i2c_dev->dev)) 1665 return 0; 1666 1667 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); 1668 if (IS_ERR(i2c_dev->rst)) 1669 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), 1670 "failed to get reset control\n"); 1671 1672 return 0; 1673 } 1674 1675 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) 1676 { 1677 int err; 1678 1679 if (ACPI_HANDLE(i2c_dev->dev)) 1680 return 0; 1681 1682 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; 1683 1684 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) 1685 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; 1686 1687 if (i2c_dev->is_vi) 1688 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; 1689 1690 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, 1691 i2c_dev->clocks); 1692 if (err) 1693 return err; 1694 1695 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); 1696 if (err) 1697 return err; 1698 1699 i2c_dev->div_clk = i2c_dev->clocks[0].clk; 1700 1701 if (!i2c_dev->multimaster_mode) 1702 return 0; 1703 1704 err = clk_enable(i2c_dev->div_clk); 1705 if (err) { 1706 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); 1707 goto unprepare_clocks; 1708 } 1709 1710 return 0; 1711 1712 unprepare_clocks: 1713 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1714 1715 return err; 1716 } 1717 1718 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev) 1719 { 1720 if (i2c_dev->multimaster_mode) 1721 clk_disable(i2c_dev->div_clk); 1722 1723 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1724 } 1725 1726 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev) 1727 { 1728 int ret; 1729 1730 ret = pm_runtime_get_sync(i2c_dev->dev); 1731 if (ret < 0) 1732 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); 1733 else 1734 ret = tegra_i2c_init(i2c_dev); 1735 1736 pm_runtime_put_sync(i2c_dev->dev); 1737 1738 return ret; 1739 } 1740 1741 static int tegra_i2c_probe(struct platform_device *pdev) 1742 { 1743 struct tegra_i2c_dev *i2c_dev; 1744 struct resource *res; 1745 int err; 1746 1747 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1748 if (!i2c_dev) 1749 return -ENOMEM; 1750 1751 platform_set_drvdata(pdev, i2c_dev); 1752 1753 init_completion(&i2c_dev->msg_complete); 1754 init_completion(&i2c_dev->dma_complete); 1755 1756 i2c_dev->hw = device_get_match_data(&pdev->dev); 1757 i2c_dev->cont_id = pdev->id; 1758 i2c_dev->dev = &pdev->dev; 1759 1760 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1761 if (IS_ERR(i2c_dev->base)) 1762 return PTR_ERR(i2c_dev->base); 1763 1764 i2c_dev->base_phys = res->start; 1765 1766 err = platform_get_irq(pdev, 0); 1767 if (err < 0) 1768 return err; 1769 1770 i2c_dev->irq = err; 1771 1772 /* interrupt will be enabled during of transfer time */ 1773 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1774 1775 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, 1776 NULL, tegra_i2c_isr, 1777 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1778 dev_name(i2c_dev->dev), i2c_dev); 1779 if (err) 1780 return err; 1781 1782 tegra_i2c_parse_dt(i2c_dev); 1783 1784 err = tegra_i2c_init_reset(i2c_dev); 1785 if (err) 1786 return err; 1787 1788 err = tegra_i2c_init_clocks(i2c_dev); 1789 if (err) 1790 return err; 1791 1792 err = tegra_i2c_init_dma(i2c_dev); 1793 if (err) 1794 goto release_clocks; 1795 1796 /* 1797 * VI I2C is in VE power domain which is not always ON and not 1798 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a 1799 * non IRQ-safe domain because this prevents powering off the power 1800 * domain. 1801 * 1802 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't 1803 * be used for atomic transfers. 1804 */ 1805 if (!i2c_dev->is_vi) 1806 pm_runtime_irq_safe(i2c_dev->dev); 1807 1808 pm_runtime_enable(i2c_dev->dev); 1809 1810 err = tegra_i2c_init_hardware(i2c_dev); 1811 if (err) 1812 goto release_rpm; 1813 1814 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1815 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1816 i2c_dev->adapter.dev.parent = i2c_dev->dev; 1817 i2c_dev->adapter.retries = 1; 1818 i2c_dev->adapter.timeout = 6 * HZ; 1819 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1820 i2c_dev->adapter.owner = THIS_MODULE; 1821 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1822 i2c_dev->adapter.algo = &tegra_i2c_algo; 1823 i2c_dev->adapter.nr = pdev->id; 1824 1825 if (i2c_dev->hw->supports_bus_clear) 1826 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1827 1828 strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1829 sizeof(i2c_dev->adapter.name)); 1830 1831 err = i2c_add_numbered_adapter(&i2c_dev->adapter); 1832 if (err) 1833 goto release_rpm; 1834 1835 return 0; 1836 1837 release_rpm: 1838 pm_runtime_disable(i2c_dev->dev); 1839 1840 tegra_i2c_release_dma(i2c_dev); 1841 release_clocks: 1842 tegra_i2c_release_clocks(i2c_dev); 1843 1844 return err; 1845 } 1846 1847 static int tegra_i2c_remove(struct platform_device *pdev) 1848 { 1849 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1850 1851 i2c_del_adapter(&i2c_dev->adapter); 1852 pm_runtime_force_suspend(i2c_dev->dev); 1853 1854 tegra_i2c_release_dma(i2c_dev); 1855 tegra_i2c_release_clocks(i2c_dev); 1856 1857 return 0; 1858 } 1859 1860 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 1861 { 1862 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1863 int err; 1864 1865 err = pinctrl_pm_select_default_state(dev); 1866 if (err) 1867 return err; 1868 1869 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); 1870 if (err) 1871 return err; 1872 1873 /* 1874 * VI I2C device is attached to VE power domain which goes through 1875 * power ON/OFF during runtime PM resume/suspend, meaning that 1876 * controller needs to be re-initialized after power ON. 1877 */ 1878 if (i2c_dev->is_vi) { 1879 err = tegra_i2c_init(i2c_dev); 1880 if (err) 1881 goto disable_clocks; 1882 } 1883 1884 return 0; 1885 1886 disable_clocks: 1887 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1888 1889 return err; 1890 } 1891 1892 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 1893 { 1894 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1895 1896 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1897 1898 return pinctrl_pm_select_idle_state(dev); 1899 } 1900 1901 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1902 { 1903 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1904 int err; 1905 1906 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1907 1908 if (!pm_runtime_status_suspended(dev)) { 1909 err = tegra_i2c_runtime_suspend(dev); 1910 if (err) 1911 return err; 1912 } 1913 1914 return 0; 1915 } 1916 1917 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1918 { 1919 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1920 int err; 1921 1922 /* 1923 * We need to ensure that clocks are enabled so that registers can be 1924 * restored in tegra_i2c_init(). 1925 */ 1926 err = tegra_i2c_runtime_resume(dev); 1927 if (err) 1928 return err; 1929 1930 err = tegra_i2c_init(i2c_dev); 1931 if (err) 1932 return err; 1933 1934 /* 1935 * In case we are runtime suspended, disable clocks again so that we 1936 * don't unbalance the clock reference counts during the next runtime 1937 * resume transition. 1938 */ 1939 if (pm_runtime_status_suspended(dev)) { 1940 err = tegra_i2c_runtime_suspend(dev); 1941 if (err) 1942 return err; 1943 } 1944 1945 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1946 1947 return 0; 1948 } 1949 1950 static const struct dev_pm_ops tegra_i2c_pm = { 1951 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1952 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1953 NULL) 1954 }; 1955 1956 static const struct acpi_device_id tegra_i2c_acpi_match[] = { 1957 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 1958 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 1959 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 1960 { } 1961 }; 1962 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); 1963 1964 static struct platform_driver tegra_i2c_driver = { 1965 .probe = tegra_i2c_probe, 1966 .remove = tegra_i2c_remove, 1967 .driver = { 1968 .name = "tegra-i2c", 1969 .of_match_table = tegra_i2c_of_match, 1970 .acpi_match_table = tegra_i2c_acpi_match, 1971 .pm = &tegra_i2c_pm, 1972 }, 1973 }; 1974 module_platform_driver(tegra_i2c_driver); 1975 1976 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver"); 1977 MODULE_AUTHOR("Colin Cross"); 1978 MODULE_LICENSE("GPL v2"); 1979