1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/err.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/kernel.h> 22 #include <linux/ktime.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 30 #define BYTES_PER_FIFO_WORD 4 31 32 #define I2C_CNFG 0x000 33 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 34 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 35 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 36 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 37 #define I2C_STATUS 0x01c 38 #define I2C_SL_CNFG 0x020 39 #define I2C_SL_CNFG_NACK BIT(1) 40 #define I2C_SL_CNFG_NEWSL BIT(2) 41 #define I2C_SL_ADDR1 0x02c 42 #define I2C_SL_ADDR2 0x030 43 #define I2C_TLOW_SEXT 0x034 44 #define I2C_TX_FIFO 0x050 45 #define I2C_RX_FIFO 0x054 46 #define I2C_PACKET_TRANSFER_STATUS 0x058 47 #define I2C_FIFO_CONTROL 0x05c 48 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 49 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 50 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 51 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 52 #define I2C_FIFO_STATUS 0x060 53 #define I2C_FIFO_STATUS_TX GENMASK(7, 4) 54 #define I2C_FIFO_STATUS_RX GENMASK(3, 0) 55 #define I2C_INT_MASK 0x064 56 #define I2C_INT_STATUS 0x068 57 #define I2C_INT_BUS_CLR_DONE BIT(11) 58 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 59 #define I2C_INT_NO_ACK BIT(3) 60 #define I2C_INT_ARBITRATION_LOST BIT(2) 61 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 62 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 63 #define I2C_CLK_DIVISOR 0x06c 64 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 65 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 66 67 #define DVC_CTRL_REG1 0x000 68 #define DVC_CTRL_REG1_INTR_EN BIT(10) 69 #define DVC_CTRL_REG3 0x008 70 #define DVC_CTRL_REG3_SW_PROG BIT(26) 71 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 72 #define DVC_STATUS 0x00c 73 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 74 75 #define I2C_ERR_NONE 0x00 76 #define I2C_ERR_NO_ACK BIT(0) 77 #define I2C_ERR_ARBITRATION_LOST BIT(1) 78 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 79 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 80 81 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28) 82 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16) 83 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12) 84 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 85 #define PACKET_HEADER0_PROTOCOL_I2C 1 86 87 #define I2C_HEADER_CONT_ON_NAK BIT(21) 88 #define I2C_HEADER_READ BIT(19) 89 #define I2C_HEADER_10BIT_ADDR BIT(18) 90 #define I2C_HEADER_IE_ENABLE BIT(17) 91 #define I2C_HEADER_REPEAT_START BIT(16) 92 #define I2C_HEADER_CONTINUE_XFER BIT(15) 93 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 94 95 #define I2C_BUS_CLEAR_CNFG 0x084 96 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 97 #define I2C_BC_STOP_COND BIT(2) 98 #define I2C_BC_TERMINATE BIT(1) 99 #define I2C_BC_ENABLE BIT(0) 100 #define I2C_BUS_CLEAR_STATUS 0x088 101 #define I2C_BC_STATUS BIT(0) 102 103 #define I2C_CONFIG_LOAD 0x08c 104 #define I2C_MSTR_CONFIG_LOAD BIT(0) 105 106 #define I2C_CLKEN_OVERRIDE 0x090 107 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 108 109 #define I2C_INTERFACE_TIMING_0 0x094 110 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 111 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 112 #define I2C_INTERFACE_TIMING_1 0x098 113 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 114 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 115 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 116 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 117 118 #define I2C_HS_INTERFACE_TIMING_0 0x09c 119 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 120 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 121 #define I2C_HS_INTERFACE_TIMING_1 0x0a0 122 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 123 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 124 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 125 126 #define I2C_MST_FIFO_CONTROL 0x0b4 127 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 128 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 129 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 130 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 131 132 #define I2C_MST_FIFO_STATUS 0x0b8 133 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 134 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 135 136 /* configuration load timeout in microseconds */ 137 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 138 139 /* packet header size in bytes */ 140 #define I2C_PACKET_HEADER_SIZE 12 141 142 /* 143 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 144 * avoid DMA overhead, otherwise external APB DMA controller will be used. 145 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 146 * I2C_PACKET_HEADER_SIZE. 147 */ 148 #define I2C_PIO_MODE_PREFERRED_LEN 32 149 150 /* 151 * msg_end_type: The bus control which needs to be sent at end of transfer. 152 * @MSG_END_STOP: Send stop pulse. 153 * @MSG_END_REPEAT_START: Send repeat-start. 154 * @MSG_END_CONTINUE: Don't send stop or repeat-start. 155 */ 156 enum msg_end_type { 157 MSG_END_STOP, 158 MSG_END_REPEAT_START, 159 MSG_END_CONTINUE, 160 }; 161 162 /** 163 * struct tegra_i2c_hw_feature : per hardware generation features 164 * @has_continue_xfer_support: continue-transfer supported 165 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 166 * completion interrupt on per packet basis. 167 * @has_config_load_reg: Has the config load register to load the new 168 * configuration. 169 * @clk_divisor_hs_mode: Clock divisor in HS mode. 170 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 171 * applicable if there is no fast clock source i.e. single clock 172 * source. 173 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 174 * applicable if there is no fast clock source i.e. single clock 175 * source. 176 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 177 * applicable if there is no fast clock source (i.e. single 178 * clock source). 179 * @has_multi_master_mode: The I2C controller supports running in single-master 180 * or multi-master mode. 181 * @has_slcg_override_reg: The I2C controller supports a register that 182 * overrides the second level clock gating. 183 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 184 * provides additional features and allows for longer messages to 185 * be transferred in one go. 186 * @quirks: I2C adapter quirks for limiting write/read transfer size and not 187 * allowing 0 length transfers. 188 * @supports_bus_clear: Bus Clear support to recover from bus hang during 189 * SDA stuck low from device for some unknown reasons. 190 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 191 * @tlow_std_mode: Low period of the clock in standard mode. 192 * @thigh_std_mode: High period of the clock in standard mode. 193 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 194 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 195 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 196 * in standard mode. 197 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 198 * conditions in fast/fast-plus modes. 199 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 200 * in HS mode. 201 * @has_interface_timing_reg: Has interface timing register to program the tuned 202 * timing settings. 203 */ 204 struct tegra_i2c_hw_feature { 205 bool has_continue_xfer_support; 206 bool has_per_pkt_xfer_complete_irq; 207 bool has_config_load_reg; 208 u32 clk_divisor_hs_mode; 209 u32 clk_divisor_std_mode; 210 u32 clk_divisor_fast_mode; 211 u32 clk_divisor_fast_plus_mode; 212 bool has_multi_master_mode; 213 bool has_slcg_override_reg; 214 bool has_mst_fifo; 215 const struct i2c_adapter_quirks *quirks; 216 bool supports_bus_clear; 217 bool has_apb_dma; 218 u32 tlow_std_mode; 219 u32 thigh_std_mode; 220 u32 tlow_fast_fastplus_mode; 221 u32 thigh_fast_fastplus_mode; 222 u32 setup_hold_time_std_mode; 223 u32 setup_hold_time_fast_fast_plus_mode; 224 u32 setup_hold_time_hs_mode; 225 bool has_interface_timing_reg; 226 }; 227 228 /** 229 * struct tegra_i2c_dev - per device I2C context 230 * @dev: device reference for power management 231 * @hw: Tegra I2C HW feature 232 * @adapter: core I2C layer adapter information 233 * @div_clk: clock reference for div clock of I2C controller 234 * @clocks: array of I2C controller clocks 235 * @nclocks: number of clocks in the array 236 * @rst: reset control for the I2C controller 237 * @base: ioremapped registers cookie 238 * @base_phys: physical base address of the I2C controller 239 * @cont_id: I2C controller ID, used for packet header 240 * @irq: IRQ number of transfer complete interrupt 241 * @is_dvc: identifies the DVC I2C controller, has a different register layout 242 * @is_vi: identifies the VI I2C controller, has a different register layout 243 * @msg_complete: transfer completion notifier 244 * @msg_err: error code for completed message 245 * @msg_buf: pointer to current message data 246 * @msg_buf_remaining: size of unsent data in the message buffer 247 * @msg_read: indicates that the transfer is a read access 248 * @bus_clk_rate: current I2C bus clock rate 249 * @multimaster_mode: indicates that I2C controller is in multi-master mode 250 * @tx_dma_chan: DMA transmit channel 251 * @rx_dma_chan: DMA receive channel 252 * @dma_phys: handle to DMA resources 253 * @dma_buf: pointer to allocated DMA buffer 254 * @dma_buf_size: DMA buffer size 255 * @dma_mode: indicates active DMA transfer 256 * @dma_complete: DMA completion notifier 257 * @atomic_mode: indicates active atomic transfer 258 */ 259 struct tegra_i2c_dev { 260 struct device *dev; 261 struct i2c_adapter adapter; 262 263 const struct tegra_i2c_hw_feature *hw; 264 struct reset_control *rst; 265 unsigned int cont_id; 266 unsigned int irq; 267 268 phys_addr_t base_phys; 269 void __iomem *base; 270 271 struct clk_bulk_data clocks[2]; 272 unsigned int nclocks; 273 274 struct clk *div_clk; 275 u32 bus_clk_rate; 276 277 struct completion msg_complete; 278 size_t msg_buf_remaining; 279 int msg_err; 280 u8 *msg_buf; 281 282 struct completion dma_complete; 283 struct dma_chan *tx_dma_chan; 284 struct dma_chan *rx_dma_chan; 285 unsigned int dma_buf_size; 286 dma_addr_t dma_phys; 287 void *dma_buf; 288 289 bool multimaster_mode; 290 bool atomic_mode; 291 bool dma_mode; 292 bool msg_read; 293 bool is_dvc; 294 bool is_vi; 295 }; 296 297 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 298 unsigned int reg) 299 { 300 writel_relaxed(val, i2c_dev->base + reg); 301 } 302 303 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 304 { 305 return readl_relaxed(i2c_dev->base + reg); 306 } 307 308 /* 309 * If necessary, i2c_writel() and i2c_readl() will offset the register 310 * in order to talk to the I2C block inside the DVC block. 311 */ 312 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 313 { 314 if (i2c_dev->is_dvc) 315 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 316 else if (i2c_dev->is_vi) 317 reg = 0xc00 + (reg << 2); 318 319 return reg; 320 } 321 322 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 323 { 324 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 325 326 /* read back register to make sure that register writes completed */ 327 if (reg != I2C_TX_FIFO) 328 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 329 else if (i2c_dev->is_vi) 330 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 331 } 332 333 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 334 { 335 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 336 } 337 338 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 339 unsigned int reg, unsigned int len) 340 { 341 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 342 } 343 344 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, 345 unsigned int reg, unsigned int len) 346 { 347 u32 *data32 = data; 348 349 /* 350 * VI I2C controller has known hardware bug where writes get stuck 351 * when immediate multiple writes happen to TX_FIFO register. 352 * Recommended software work around is to read I2C register after 353 * each write to TX_FIFO register to flush out the data. 354 */ 355 while (len--) 356 i2c_writel(i2c_dev, *data32++, reg); 357 } 358 359 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 360 unsigned int reg, unsigned int len) 361 { 362 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 363 } 364 365 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 366 { 367 u32 int_mask; 368 369 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 370 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 371 } 372 373 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 374 { 375 u32 int_mask; 376 377 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 378 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 379 } 380 381 static void tegra_i2c_dma_complete(void *args) 382 { 383 struct tegra_i2c_dev *i2c_dev = args; 384 385 complete(&i2c_dev->dma_complete); 386 } 387 388 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 389 { 390 struct dma_async_tx_descriptor *dma_desc; 391 enum dma_transfer_direction dir; 392 struct dma_chan *chan; 393 394 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 395 396 reinit_completion(&i2c_dev->dma_complete); 397 398 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 399 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; 400 401 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, 402 len, dir, DMA_PREP_INTERRUPT | 403 DMA_CTRL_ACK); 404 if (!dma_desc) { 405 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", 406 i2c_dev->msg_read ? "RX" : "TX"); 407 return -EINVAL; 408 } 409 410 dma_desc->callback = tegra_i2c_dma_complete; 411 dma_desc->callback_param = i2c_dev; 412 413 dmaengine_submit(dma_desc); 414 dma_async_issue_pending(chan); 415 416 return 0; 417 } 418 419 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 420 { 421 if (i2c_dev->dma_buf) { 422 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 423 i2c_dev->dma_buf, i2c_dev->dma_phys); 424 i2c_dev->dma_buf = NULL; 425 } 426 427 if (i2c_dev->tx_dma_chan) { 428 dma_release_channel(i2c_dev->tx_dma_chan); 429 i2c_dev->tx_dma_chan = NULL; 430 } 431 432 if (i2c_dev->rx_dma_chan) { 433 dma_release_channel(i2c_dev->rx_dma_chan); 434 i2c_dev->rx_dma_chan = NULL; 435 } 436 } 437 438 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 439 { 440 struct dma_chan *chan; 441 dma_addr_t dma_phys; 442 u32 *dma_buf; 443 int err; 444 445 if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) 446 return 0; 447 448 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 449 dev_dbg(i2c_dev->dev, "DMA support not enabled\n"); 450 return 0; 451 } 452 453 chan = dma_request_chan(i2c_dev->dev, "rx"); 454 if (IS_ERR(chan)) { 455 err = PTR_ERR(chan); 456 goto err_out; 457 } 458 459 i2c_dev->rx_dma_chan = chan; 460 461 chan = dma_request_chan(i2c_dev->dev, "tx"); 462 if (IS_ERR(chan)) { 463 err = PTR_ERR(chan); 464 goto err_out; 465 } 466 467 i2c_dev->tx_dma_chan = chan; 468 469 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + 470 I2C_PACKET_HEADER_SIZE; 471 472 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 473 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 474 if (!dma_buf) { 475 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); 476 err = -ENOMEM; 477 goto err_out; 478 } 479 480 i2c_dev->dma_buf = dma_buf; 481 i2c_dev->dma_phys = dma_phys; 482 483 return 0; 484 485 err_out: 486 tegra_i2c_release_dma(i2c_dev); 487 if (err != -EPROBE_DEFER) { 488 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 489 dev_err(i2c_dev->dev, "falling back to PIO\n"); 490 return 0; 491 } 492 493 return err; 494 } 495 496 /* 497 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 498 * block. This block is identical to the rest of the I2C blocks, except that 499 * it only supports master mode, it has registers moved around, and it needs 500 * some extra init to get it into I2C mode. The register moves are handled 501 * by i2c_readl() and i2c_writel(). 502 */ 503 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 504 { 505 u32 val; 506 507 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 508 val |= DVC_CTRL_REG3_SW_PROG; 509 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 510 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 511 512 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 513 val |= DVC_CTRL_REG1_INTR_EN; 514 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 515 } 516 517 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) 518 { 519 u32 value; 520 521 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 522 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 523 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 524 525 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 526 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 527 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 528 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 529 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 530 531 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 532 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 533 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 534 535 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 536 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 537 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 538 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 539 540 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 541 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 542 543 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 544 } 545 546 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 547 u32 reg, u32 mask, u32 delay_us, 548 u32 timeout_us) 549 { 550 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 551 u32 val; 552 553 if (!i2c_dev->atomic_mode) 554 return readl_relaxed_poll_timeout(addr, val, !(val & mask), 555 delay_us, timeout_us); 556 557 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), 558 delay_us, timeout_us); 559 } 560 561 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 562 { 563 u32 mask, val, offset; 564 int err; 565 566 if (i2c_dev->hw->has_mst_fifo) { 567 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 568 I2C_MST_FIFO_CONTROL_RX_FLUSH; 569 offset = I2C_MST_FIFO_CONTROL; 570 } else { 571 mask = I2C_FIFO_CONTROL_TX_FLUSH | 572 I2C_FIFO_CONTROL_RX_FLUSH; 573 offset = I2C_FIFO_CONTROL; 574 } 575 576 val = i2c_readl(i2c_dev, offset); 577 val |= mask; 578 i2c_writel(i2c_dev, val, offset); 579 580 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000); 581 if (err) { 582 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); 583 return err; 584 } 585 586 return 0; 587 } 588 589 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 590 { 591 int err; 592 593 if (!i2c_dev->hw->has_config_load_reg) 594 return 0; 595 596 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 597 598 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 599 1000, I2C_CONFIG_LOAD_TIMEOUT); 600 if (err) { 601 dev_err(i2c_dev->dev, "failed to load config\n"); 602 return err; 603 } 604 605 return 0; 606 } 607 608 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 609 { 610 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 611 int err; 612 613 /* 614 * The reset shouldn't ever fail in practice. The failure will be a 615 * sign of a severe problem that needs to be resolved. Still we don't 616 * want to fail the initialization completely because this may break 617 * kernel boot up since voltage regulators use I2C. Hence, we will 618 * emit a noisy warning on error, which won't stay unnoticed and 619 * won't hose machine entirely. 620 */ 621 err = reset_control_reset(i2c_dev->rst); 622 WARN_ON_ONCE(err); 623 624 if (i2c_dev->is_dvc) 625 tegra_dvc_init(i2c_dev); 626 627 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 628 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); 629 630 if (i2c_dev->hw->has_multi_master_mode) 631 val |= I2C_CNFG_MULTI_MASTER_MODE; 632 633 i2c_writel(i2c_dev, val, I2C_CNFG); 634 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 635 636 if (i2c_dev->is_vi) 637 tegra_i2c_vi_init(i2c_dev); 638 639 switch (i2c_dev->bus_clk_rate) { 640 case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 641 default: 642 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 643 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 644 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 645 646 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) 647 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 648 else 649 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 650 break; 651 652 case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 653 tlow = i2c_dev->hw->tlow_std_mode; 654 thigh = i2c_dev->hw->thigh_std_mode; 655 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 656 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 657 break; 658 } 659 660 /* make sure clock divisor programmed correctly */ 661 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 662 i2c_dev->hw->clk_divisor_hs_mode) | 663 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 664 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 665 666 if (i2c_dev->hw->has_interface_timing_reg) { 667 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 668 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 669 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 670 } 671 672 /* 673 * Configure setup and hold times only when tsu_thd is non-zero. 674 * Otherwise, preserve the chip default values. 675 */ 676 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 677 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 678 679 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 680 681 err = clk_set_rate(i2c_dev->div_clk, 682 i2c_dev->bus_clk_rate * clk_multiplier); 683 if (err) { 684 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); 685 return err; 686 } 687 688 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) { 689 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 690 691 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 692 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 693 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 694 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 695 } 696 697 err = tegra_i2c_flush_fifos(i2c_dev); 698 if (err) 699 return err; 700 701 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 702 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 703 704 err = tegra_i2c_wait_for_config_load(i2c_dev); 705 if (err) 706 return err; 707 708 return 0; 709 } 710 711 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 712 { 713 u32 cnfg; 714 715 /* 716 * NACK interrupt is generated before the I2C controller generates 717 * the STOP condition on the bus. So, wait for 2 clock periods 718 * before disabling the controller so that the STOP condition has 719 * been delivered properly. 720 */ 721 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 722 723 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 724 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 725 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 726 727 return tegra_i2c_wait_for_config_load(i2c_dev); 728 } 729 730 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 731 { 732 size_t buf_remaining = i2c_dev->msg_buf_remaining; 733 unsigned int words_to_transfer, rx_fifo_avail; 734 u8 *buf = i2c_dev->msg_buf; 735 u32 val; 736 737 /* 738 * Catch overflow due to message fully sent before the check for 739 * RX FIFO availability. 740 */ 741 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 742 return -EINVAL; 743 744 if (i2c_dev->hw->has_mst_fifo) { 745 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 746 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 747 } else { 748 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 749 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 750 } 751 752 /* round down to exclude partial word at the end of buffer */ 753 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 754 if (words_to_transfer > rx_fifo_avail) 755 words_to_transfer = rx_fifo_avail; 756 757 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 758 759 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 760 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 761 rx_fifo_avail -= words_to_transfer; 762 763 /* 764 * If there is a partial word at the end of buffer, handle it 765 * manually to prevent overwriting past the end of buffer. 766 */ 767 if (rx_fifo_avail > 0 && buf_remaining > 0) { 768 /* 769 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 770 * when (words_to_transfer was > rx_fifo_avail) earlier 771 * in this function. 772 */ 773 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 774 val = cpu_to_le32(val); 775 memcpy(buf, &val, buf_remaining); 776 buf_remaining = 0; 777 rx_fifo_avail--; 778 } 779 780 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 781 if (WARN_ON_ONCE(rx_fifo_avail)) 782 return -EINVAL; 783 784 i2c_dev->msg_buf_remaining = buf_remaining; 785 i2c_dev->msg_buf = buf; 786 787 return 0; 788 } 789 790 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 791 { 792 size_t buf_remaining = i2c_dev->msg_buf_remaining; 793 unsigned int words_to_transfer, tx_fifo_avail; 794 u8 *buf = i2c_dev->msg_buf; 795 u32 val; 796 797 if (i2c_dev->hw->has_mst_fifo) { 798 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 799 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 800 } else { 801 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 802 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 803 } 804 805 /* round down to exclude partial word at the end of buffer */ 806 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 807 808 /* 809 * This hunk pushes 4 bytes at a time into the TX FIFO. 810 * 811 * It's very common to have < 4 bytes, hence there is no word 812 * to push if we have less than 4 bytes to transfer. 813 */ 814 if (words_to_transfer) { 815 if (words_to_transfer > tx_fifo_avail) 816 words_to_transfer = tx_fifo_avail; 817 818 /* 819 * Update state before writing to FIFO. Note that this may 820 * cause us to finish writing all bytes (AKA buf_remaining 821 * goes to 0), hence we have a potential for an interrupt 822 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt 823 * is disabled at this point. 824 */ 825 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 826 tx_fifo_avail -= words_to_transfer; 827 828 i2c_dev->msg_buf_remaining = buf_remaining; 829 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 830 831 if (i2c_dev->is_vi) 832 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 833 else 834 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 835 836 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 837 } 838 839 /* 840 * If there is a partial word at the end of buffer, handle it manually 841 * to prevent reading past the end of buffer, which could cross a page 842 * boundary and fault. 843 */ 844 if (tx_fifo_avail > 0 && buf_remaining > 0) { 845 /* 846 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 847 * when (words_to_transfer was > tx_fifo_avail) earlier 848 * in this function for non-zero words_to_transfer. 849 */ 850 memcpy(&val, buf, buf_remaining); 851 val = le32_to_cpu(val); 852 853 i2c_dev->msg_buf_remaining = 0; 854 i2c_dev->msg_buf = NULL; 855 856 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 857 } 858 859 return 0; 860 } 861 862 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 863 { 864 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 865 struct tegra_i2c_dev *i2c_dev = dev_id; 866 u32 status; 867 868 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 869 870 if (status == 0) { 871 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 872 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 873 i2c_readl(i2c_dev, I2C_STATUS), 874 i2c_readl(i2c_dev, I2C_CNFG)); 875 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 876 goto err; 877 } 878 879 if (status & status_err) { 880 tegra_i2c_disable_packet_mode(i2c_dev); 881 if (status & I2C_INT_NO_ACK) 882 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 883 if (status & I2C_INT_ARBITRATION_LOST) 884 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 885 goto err; 886 } 887 888 /* 889 * I2C transfer is terminated during the bus clear, so skip 890 * processing the other interrupts. 891 */ 892 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 893 goto err; 894 895 if (!i2c_dev->dma_mode) { 896 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 897 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 898 /* 899 * Overflow error condition: message fully sent, 900 * with no XFER_COMPLETE interrupt but hardware 901 * asks to transfer more. 902 */ 903 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 904 goto err; 905 } 906 } 907 908 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 909 if (i2c_dev->msg_buf_remaining) 910 tegra_i2c_fill_tx_fifo(i2c_dev); 911 else 912 tegra_i2c_mask_irq(i2c_dev, 913 I2C_INT_TX_FIFO_DATA_REQ); 914 } 915 } 916 917 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 918 if (i2c_dev->is_dvc) 919 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 920 921 /* 922 * During message read XFER_COMPLETE interrupt is triggered prior to 923 * DMA completion and during message write XFER_COMPLETE interrupt is 924 * triggered after DMA completion. 925 * 926 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer, 927 * so forcing msg_buf_remaining to 0 in DMA mode. 928 */ 929 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 930 if (i2c_dev->dma_mode) 931 i2c_dev->msg_buf_remaining = 0; 932 /* 933 * Underflow error condition: XFER_COMPLETE before message 934 * fully sent. 935 */ 936 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 937 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 938 goto err; 939 } 940 complete(&i2c_dev->msg_complete); 941 } 942 goto done; 943 err: 944 /* mask all interrupts on error */ 945 tegra_i2c_mask_irq(i2c_dev, 946 I2C_INT_NO_ACK | 947 I2C_INT_ARBITRATION_LOST | 948 I2C_INT_PACKET_XFER_COMPLETE | 949 I2C_INT_TX_FIFO_DATA_REQ | 950 I2C_INT_RX_FIFO_DATA_REQ); 951 952 if (i2c_dev->hw->supports_bus_clear) 953 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 954 955 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 956 957 if (i2c_dev->is_dvc) 958 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 959 960 if (i2c_dev->dma_mode) { 961 if (i2c_dev->msg_read) 962 dmaengine_terminate_async(i2c_dev->rx_dma_chan); 963 else 964 dmaengine_terminate_async(i2c_dev->tx_dma_chan); 965 966 complete(&i2c_dev->dma_complete); 967 } 968 969 complete(&i2c_dev->msg_complete); 970 done: 971 return IRQ_HANDLED; 972 } 973 974 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 975 size_t len) 976 { 977 struct dma_slave_config slv_config = {0}; 978 u32 val, reg, dma_burst, reg_offset; 979 struct dma_chan *chan; 980 int err; 981 982 if (i2c_dev->hw->has_mst_fifo) 983 reg = I2C_MST_FIFO_CONTROL; 984 else 985 reg = I2C_FIFO_CONTROL; 986 987 if (i2c_dev->dma_mode) { 988 if (len & 0xF) 989 dma_burst = 1; 990 else if (len & 0x10) 991 dma_burst = 4; 992 else 993 dma_burst = 8; 994 995 if (i2c_dev->msg_read) { 996 chan = i2c_dev->rx_dma_chan; 997 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 998 999 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 1000 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1001 slv_config.src_maxburst = dma_burst; 1002 1003 if (i2c_dev->hw->has_mst_fifo) 1004 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 1005 else 1006 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1007 } else { 1008 chan = i2c_dev->tx_dma_chan; 1009 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1010 1011 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1012 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1013 slv_config.dst_maxburst = dma_burst; 1014 1015 if (i2c_dev->hw->has_mst_fifo) 1016 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 1017 else 1018 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 1019 } 1020 1021 slv_config.device_fc = true; 1022 err = dmaengine_slave_config(chan, &slv_config); 1023 if (err) { 1024 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); 1025 dev_err(i2c_dev->dev, "falling back to PIO\n"); 1026 1027 tegra_i2c_release_dma(i2c_dev); 1028 i2c_dev->dma_mode = false; 1029 } else { 1030 goto out; 1031 } 1032 } 1033 1034 if (i2c_dev->hw->has_mst_fifo) 1035 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 1036 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 1037 else 1038 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 1039 I2C_FIFO_CONTROL_RX_TRIG(1); 1040 out: 1041 i2c_writel(i2c_dev, val, reg); 1042 } 1043 1044 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev, 1045 struct completion *complete, 1046 unsigned int timeout_ms) 1047 { 1048 ktime_t ktime = ktime_get(); 1049 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1050 1051 do { 1052 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1053 1054 if (status) 1055 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1056 1057 if (completion_done(complete)) { 1058 s64 delta = ktime_ms_delta(ktimeout, ktime); 1059 1060 return msecs_to_jiffies(delta) ?: 1; 1061 } 1062 1063 ktime = ktime_get(); 1064 1065 } while (ktime_before(ktime, ktimeout)); 1066 1067 return 0; 1068 } 1069 1070 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev, 1071 struct completion *complete, 1072 unsigned int timeout_ms) 1073 { 1074 unsigned long ret; 1075 1076 if (i2c_dev->atomic_mode) { 1077 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms); 1078 } else { 1079 enable_irq(i2c_dev->irq); 1080 ret = wait_for_completion_timeout(complete, 1081 msecs_to_jiffies(timeout_ms)); 1082 disable_irq(i2c_dev->irq); 1083 1084 /* 1085 * Under some rare circumstances (like running KASAN + 1086 * NFS root) CPU, which handles interrupt, may stuck in 1087 * uninterruptible state for a significant time. In this 1088 * case we will get timeout if I2C transfer is running on 1089 * a sibling CPU, despite of IRQ being raised. 1090 * 1091 * In order to handle this rare condition, the IRQ status 1092 * needs to be checked after timeout. 1093 */ 1094 if (ret == 0) 1095 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0); 1096 } 1097 1098 return ret; 1099 } 1100 1101 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1102 { 1103 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1104 u32 val, time_left; 1105 int err; 1106 1107 reinit_completion(&i2c_dev->msg_complete); 1108 1109 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1110 I2C_BC_TERMINATE; 1111 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1112 1113 err = tegra_i2c_wait_for_config_load(i2c_dev); 1114 if (err) 1115 return err; 1116 1117 val |= I2C_BC_ENABLE; 1118 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1119 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1120 1121 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); 1122 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1123 1124 if (time_left == 0) { 1125 dev_err(i2c_dev->dev, "failed to clear bus\n"); 1126 return -ETIMEDOUT; 1127 } 1128 1129 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1130 if (!(val & I2C_BC_STATUS)) { 1131 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1132 return -EIO; 1133 } 1134 1135 return -EAGAIN; 1136 } 1137 1138 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, 1139 struct i2c_msg *msg, 1140 enum msg_end_type end_state) 1141 { 1142 u32 *dma_buf = i2c_dev->dma_buf; 1143 u32 packet_header; 1144 1145 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) | 1146 FIELD_PREP(PACKET_HEADER0_PROTOCOL, 1147 PACKET_HEADER0_PROTOCOL_I2C) | 1148 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | 1149 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1); 1150 1151 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1152 *dma_buf++ = packet_header; 1153 else 1154 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1155 1156 packet_header = msg->len - 1; 1157 1158 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1159 *dma_buf++ = packet_header; 1160 else 1161 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1162 1163 packet_header = I2C_HEADER_IE_ENABLE; 1164 1165 if (end_state == MSG_END_CONTINUE) 1166 packet_header |= I2C_HEADER_CONTINUE_XFER; 1167 else if (end_state == MSG_END_REPEAT_START) 1168 packet_header |= I2C_HEADER_REPEAT_START; 1169 1170 if (msg->flags & I2C_M_TEN) { 1171 packet_header |= msg->addr; 1172 packet_header |= I2C_HEADER_10BIT_ADDR; 1173 } else { 1174 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1175 } 1176 1177 if (msg->flags & I2C_M_IGNORE_NAK) 1178 packet_header |= I2C_HEADER_CONT_ON_NAK; 1179 1180 if (msg->flags & I2C_M_RD) 1181 packet_header |= I2C_HEADER_READ; 1182 1183 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1184 *dma_buf++ = packet_header; 1185 else 1186 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1187 } 1188 1189 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, 1190 struct i2c_msg *msg) 1191 { 1192 if (i2c_dev->msg_err == I2C_ERR_NONE) 1193 return 0; 1194 1195 tegra_i2c_init(i2c_dev); 1196 1197 /* start recovery upon arbitration loss in single master mode */ 1198 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1199 if (!i2c_dev->multimaster_mode) 1200 return i2c_recover_bus(&i2c_dev->adapter); 1201 1202 return -EAGAIN; 1203 } 1204 1205 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1206 if (msg->flags & I2C_M_IGNORE_NAK) 1207 return 0; 1208 1209 return -EREMOTEIO; 1210 } 1211 1212 return -EIO; 1213 } 1214 1215 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1216 struct i2c_msg *msg, 1217 enum msg_end_type end_state) 1218 { 1219 unsigned long time_left, xfer_time = 100; 1220 size_t xfer_size; 1221 u32 int_mask; 1222 int err; 1223 1224 err = tegra_i2c_flush_fifos(i2c_dev); 1225 if (err) 1226 return err; 1227 1228 i2c_dev->msg_buf = msg->buf; 1229 i2c_dev->msg_buf_remaining = msg->len; 1230 i2c_dev->msg_err = I2C_ERR_NONE; 1231 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); 1232 reinit_completion(&i2c_dev->msg_complete); 1233 1234 if (i2c_dev->msg_read) 1235 xfer_size = msg->len; 1236 else 1237 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; 1238 1239 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1240 1241 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && 1242 i2c_dev->dma_buf && !i2c_dev->atomic_mode; 1243 1244 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1245 1246 /* 1247 * Transfer time in mSec = Total bits / transfer rate 1248 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1249 */ 1250 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1251 i2c_dev->bus_clk_rate); 1252 1253 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1254 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1255 1256 if (i2c_dev->dma_mode) { 1257 if (i2c_dev->msg_read) { 1258 dma_sync_single_for_device(i2c_dev->dev, 1259 i2c_dev->dma_phys, 1260 xfer_size, DMA_FROM_DEVICE); 1261 1262 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1263 if (err) 1264 return err; 1265 } else { 1266 dma_sync_single_for_cpu(i2c_dev->dev, 1267 i2c_dev->dma_phys, 1268 xfer_size, DMA_TO_DEVICE); 1269 } 1270 } 1271 1272 tegra_i2c_push_packet_header(i2c_dev, msg, end_state); 1273 1274 if (!i2c_dev->msg_read) { 1275 if (i2c_dev->dma_mode) { 1276 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, 1277 msg->buf, msg->len); 1278 1279 dma_sync_single_for_device(i2c_dev->dev, 1280 i2c_dev->dma_phys, 1281 xfer_size, DMA_TO_DEVICE); 1282 1283 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1284 if (err) 1285 return err; 1286 } else { 1287 tegra_i2c_fill_tx_fifo(i2c_dev); 1288 } 1289 } 1290 1291 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1292 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1293 1294 if (!i2c_dev->dma_mode) { 1295 if (msg->flags & I2C_M_RD) 1296 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1297 else if (i2c_dev->msg_buf_remaining) 1298 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1299 } 1300 1301 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1302 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1303 i2c_readl(i2c_dev, I2C_INT_MASK)); 1304 1305 if (i2c_dev->dma_mode) { 1306 time_left = tegra_i2c_wait_completion(i2c_dev, 1307 &i2c_dev->dma_complete, 1308 xfer_time); 1309 1310 /* 1311 * Synchronize DMA first, since dmaengine_terminate_sync() 1312 * performs synchronization after the transfer's termination 1313 * and we want to get a completion if transfer succeeded. 1314 */ 1315 dmaengine_synchronize(i2c_dev->msg_read ? 1316 i2c_dev->rx_dma_chan : 1317 i2c_dev->tx_dma_chan); 1318 1319 dmaengine_terminate_sync(i2c_dev->msg_read ? 1320 i2c_dev->rx_dma_chan : 1321 i2c_dev->tx_dma_chan); 1322 1323 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1324 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); 1325 tegra_i2c_init(i2c_dev); 1326 return -ETIMEDOUT; 1327 } 1328 1329 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1330 dma_sync_single_for_cpu(i2c_dev->dev, 1331 i2c_dev->dma_phys, 1332 xfer_size, DMA_FROM_DEVICE); 1333 1334 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len); 1335 } 1336 } 1337 1338 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 1339 xfer_time); 1340 1341 tegra_i2c_mask_irq(i2c_dev, int_mask); 1342 1343 if (time_left == 0) { 1344 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); 1345 tegra_i2c_init(i2c_dev); 1346 return -ETIMEDOUT; 1347 } 1348 1349 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1350 time_left, completion_done(&i2c_dev->msg_complete), 1351 i2c_dev->msg_err); 1352 1353 i2c_dev->dma_mode = false; 1354 1355 err = tegra_i2c_error_recover(i2c_dev, msg); 1356 if (err) 1357 return err; 1358 1359 return 0; 1360 } 1361 1362 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1363 int num) 1364 { 1365 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1366 int i, ret; 1367 1368 ret = pm_runtime_get_sync(i2c_dev->dev); 1369 if (ret < 0) { 1370 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1371 pm_runtime_put_noidle(i2c_dev->dev); 1372 return ret; 1373 } 1374 1375 for (i = 0; i < num; i++) { 1376 enum msg_end_type end_type = MSG_END_STOP; 1377 1378 if (i < (num - 1)) { 1379 /* check whether follow up message is coming */ 1380 if (msgs[i + 1].flags & I2C_M_NOSTART) 1381 end_type = MSG_END_CONTINUE; 1382 else 1383 end_type = MSG_END_REPEAT_START; 1384 } 1385 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1386 if (ret) 1387 break; 1388 } 1389 1390 pm_runtime_put(i2c_dev->dev); 1391 1392 return ret ?: i; 1393 } 1394 1395 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1396 struct i2c_msg msgs[], int num) 1397 { 1398 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1399 int ret; 1400 1401 i2c_dev->atomic_mode = true; 1402 ret = tegra_i2c_xfer(adap, msgs, num); 1403 i2c_dev->atomic_mode = false; 1404 1405 return ret; 1406 } 1407 1408 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1409 { 1410 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1411 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1412 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1413 1414 if (i2c_dev->hw->has_continue_xfer_support) 1415 ret |= I2C_FUNC_NOSTART; 1416 1417 return ret; 1418 } 1419 1420 static const struct i2c_algorithm tegra_i2c_algo = { 1421 .master_xfer = tegra_i2c_xfer, 1422 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1423 .functionality = tegra_i2c_func, 1424 }; 1425 1426 /* payload size is only 12 bit */ 1427 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1428 .flags = I2C_AQ_NO_ZERO_LEN, 1429 .max_read_len = SZ_4K, 1430 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1431 }; 1432 1433 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1434 .flags = I2C_AQ_NO_ZERO_LEN, 1435 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1436 }; 1437 1438 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1439 .recover_bus = tegra_i2c_issue_bus_clear, 1440 }; 1441 1442 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1443 .has_continue_xfer_support = false, 1444 .has_per_pkt_xfer_complete_irq = false, 1445 .clk_divisor_hs_mode = 3, 1446 .clk_divisor_std_mode = 0, 1447 .clk_divisor_fast_mode = 0, 1448 .clk_divisor_fast_plus_mode = 0, 1449 .has_config_load_reg = false, 1450 .has_multi_master_mode = false, 1451 .has_slcg_override_reg = false, 1452 .has_mst_fifo = false, 1453 .quirks = &tegra_i2c_quirks, 1454 .supports_bus_clear = false, 1455 .has_apb_dma = true, 1456 .tlow_std_mode = 0x4, 1457 .thigh_std_mode = 0x2, 1458 .tlow_fast_fastplus_mode = 0x4, 1459 .thigh_fast_fastplus_mode = 0x2, 1460 .setup_hold_time_std_mode = 0x0, 1461 .setup_hold_time_fast_fast_plus_mode = 0x0, 1462 .setup_hold_time_hs_mode = 0x0, 1463 .has_interface_timing_reg = false, 1464 }; 1465 1466 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1467 .has_continue_xfer_support = true, 1468 .has_per_pkt_xfer_complete_irq = false, 1469 .clk_divisor_hs_mode = 3, 1470 .clk_divisor_std_mode = 0, 1471 .clk_divisor_fast_mode = 0, 1472 .clk_divisor_fast_plus_mode = 0, 1473 .has_config_load_reg = false, 1474 .has_multi_master_mode = false, 1475 .has_slcg_override_reg = false, 1476 .has_mst_fifo = false, 1477 .quirks = &tegra_i2c_quirks, 1478 .supports_bus_clear = false, 1479 .has_apb_dma = true, 1480 .tlow_std_mode = 0x4, 1481 .thigh_std_mode = 0x2, 1482 .tlow_fast_fastplus_mode = 0x4, 1483 .thigh_fast_fastplus_mode = 0x2, 1484 .setup_hold_time_std_mode = 0x0, 1485 .setup_hold_time_fast_fast_plus_mode = 0x0, 1486 .setup_hold_time_hs_mode = 0x0, 1487 .has_interface_timing_reg = false, 1488 }; 1489 1490 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1491 .has_continue_xfer_support = true, 1492 .has_per_pkt_xfer_complete_irq = true, 1493 .clk_divisor_hs_mode = 1, 1494 .clk_divisor_std_mode = 0x19, 1495 .clk_divisor_fast_mode = 0x19, 1496 .clk_divisor_fast_plus_mode = 0x10, 1497 .has_config_load_reg = false, 1498 .has_multi_master_mode = false, 1499 .has_slcg_override_reg = false, 1500 .has_mst_fifo = false, 1501 .quirks = &tegra_i2c_quirks, 1502 .supports_bus_clear = true, 1503 .has_apb_dma = true, 1504 .tlow_std_mode = 0x4, 1505 .thigh_std_mode = 0x2, 1506 .tlow_fast_fastplus_mode = 0x4, 1507 .thigh_fast_fastplus_mode = 0x2, 1508 .setup_hold_time_std_mode = 0x0, 1509 .setup_hold_time_fast_fast_plus_mode = 0x0, 1510 .setup_hold_time_hs_mode = 0x0, 1511 .has_interface_timing_reg = false, 1512 }; 1513 1514 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1515 .has_continue_xfer_support = true, 1516 .has_per_pkt_xfer_complete_irq = true, 1517 .clk_divisor_hs_mode = 1, 1518 .clk_divisor_std_mode = 0x19, 1519 .clk_divisor_fast_mode = 0x19, 1520 .clk_divisor_fast_plus_mode = 0x10, 1521 .has_config_load_reg = true, 1522 .has_multi_master_mode = false, 1523 .has_slcg_override_reg = true, 1524 .has_mst_fifo = false, 1525 .quirks = &tegra_i2c_quirks, 1526 .supports_bus_clear = true, 1527 .has_apb_dma = true, 1528 .tlow_std_mode = 0x4, 1529 .thigh_std_mode = 0x2, 1530 .tlow_fast_fastplus_mode = 0x4, 1531 .thigh_fast_fastplus_mode = 0x2, 1532 .setup_hold_time_std_mode = 0x0, 1533 .setup_hold_time_fast_fast_plus_mode = 0x0, 1534 .setup_hold_time_hs_mode = 0x0, 1535 .has_interface_timing_reg = true, 1536 }; 1537 1538 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1539 .has_continue_xfer_support = true, 1540 .has_per_pkt_xfer_complete_irq = true, 1541 .clk_divisor_hs_mode = 1, 1542 .clk_divisor_std_mode = 0x19, 1543 .clk_divisor_fast_mode = 0x19, 1544 .clk_divisor_fast_plus_mode = 0x10, 1545 .has_config_load_reg = true, 1546 .has_multi_master_mode = false, 1547 .has_slcg_override_reg = true, 1548 .has_mst_fifo = false, 1549 .quirks = &tegra_i2c_quirks, 1550 .supports_bus_clear = true, 1551 .has_apb_dma = true, 1552 .tlow_std_mode = 0x4, 1553 .thigh_std_mode = 0x2, 1554 .tlow_fast_fastplus_mode = 0x4, 1555 .thigh_fast_fastplus_mode = 0x2, 1556 .setup_hold_time_std_mode = 0, 1557 .setup_hold_time_fast_fast_plus_mode = 0, 1558 .setup_hold_time_hs_mode = 0, 1559 .has_interface_timing_reg = true, 1560 }; 1561 1562 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1563 .has_continue_xfer_support = true, 1564 .has_per_pkt_xfer_complete_irq = true, 1565 .clk_divisor_hs_mode = 1, 1566 .clk_divisor_std_mode = 0x16, 1567 .clk_divisor_fast_mode = 0x19, 1568 .clk_divisor_fast_plus_mode = 0x10, 1569 .has_config_load_reg = true, 1570 .has_multi_master_mode = false, 1571 .has_slcg_override_reg = true, 1572 .has_mst_fifo = false, 1573 .quirks = &tegra_i2c_quirks, 1574 .supports_bus_clear = true, 1575 .has_apb_dma = false, 1576 .tlow_std_mode = 0x4, 1577 .thigh_std_mode = 0x3, 1578 .tlow_fast_fastplus_mode = 0x4, 1579 .thigh_fast_fastplus_mode = 0x2, 1580 .setup_hold_time_std_mode = 0, 1581 .setup_hold_time_fast_fast_plus_mode = 0, 1582 .setup_hold_time_hs_mode = 0, 1583 .has_interface_timing_reg = true, 1584 }; 1585 1586 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1587 .has_continue_xfer_support = true, 1588 .has_per_pkt_xfer_complete_irq = true, 1589 .clk_divisor_hs_mode = 1, 1590 .clk_divisor_std_mode = 0x4f, 1591 .clk_divisor_fast_mode = 0x3c, 1592 .clk_divisor_fast_plus_mode = 0x16, 1593 .has_config_load_reg = true, 1594 .has_multi_master_mode = true, 1595 .has_slcg_override_reg = true, 1596 .has_mst_fifo = true, 1597 .quirks = &tegra194_i2c_quirks, 1598 .supports_bus_clear = true, 1599 .has_apb_dma = false, 1600 .tlow_std_mode = 0x8, 1601 .thigh_std_mode = 0x7, 1602 .tlow_fast_fastplus_mode = 0x2, 1603 .thigh_fast_fastplus_mode = 0x2, 1604 .setup_hold_time_std_mode = 0x08080808, 1605 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1606 .setup_hold_time_hs_mode = 0x090909, 1607 .has_interface_timing_reg = true, 1608 }; 1609 1610 static const struct of_device_id tegra_i2c_of_match[] = { 1611 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1612 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1613 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1614 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1615 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1616 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1617 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1618 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1619 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1620 {}, 1621 }; 1622 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1623 1624 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1625 { 1626 struct device_node *np = i2c_dev->dev->of_node; 1627 bool multi_mode; 1628 int err; 1629 1630 err = of_property_read_u32(np, "clock-frequency", 1631 &i2c_dev->bus_clk_rate); 1632 if (err) 1633 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; 1634 1635 multi_mode = of_property_read_bool(np, "multi-master"); 1636 i2c_dev->multimaster_mode = multi_mode; 1637 1638 if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 1639 i2c_dev->is_dvc = true; 1640 1641 if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 1642 i2c_dev->is_vi = true; 1643 } 1644 1645 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) 1646 { 1647 int err; 1648 1649 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; 1650 1651 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) 1652 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; 1653 1654 if (i2c_dev->is_vi) 1655 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; 1656 1657 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, 1658 i2c_dev->clocks); 1659 if (err) 1660 return err; 1661 1662 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); 1663 if (err) 1664 return err; 1665 1666 i2c_dev->div_clk = i2c_dev->clocks[0].clk; 1667 1668 if (!i2c_dev->multimaster_mode) 1669 return 0; 1670 1671 err = clk_enable(i2c_dev->div_clk); 1672 if (err) { 1673 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); 1674 goto unprepare_clocks; 1675 } 1676 1677 return 0; 1678 1679 unprepare_clocks: 1680 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1681 1682 return err; 1683 } 1684 1685 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev) 1686 { 1687 if (i2c_dev->multimaster_mode) 1688 clk_disable(i2c_dev->div_clk); 1689 1690 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1691 } 1692 1693 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev) 1694 { 1695 int ret; 1696 1697 ret = pm_runtime_get_sync(i2c_dev->dev); 1698 if (ret < 0) 1699 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); 1700 else 1701 ret = tegra_i2c_init(i2c_dev); 1702 1703 pm_runtime_put(i2c_dev->dev); 1704 1705 return ret; 1706 } 1707 1708 static int tegra_i2c_probe(struct platform_device *pdev) 1709 { 1710 struct tegra_i2c_dev *i2c_dev; 1711 struct resource *res; 1712 int err; 1713 1714 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1715 if (!i2c_dev) 1716 return -ENOMEM; 1717 1718 platform_set_drvdata(pdev, i2c_dev); 1719 1720 init_completion(&i2c_dev->msg_complete); 1721 init_completion(&i2c_dev->dma_complete); 1722 1723 i2c_dev->hw = of_device_get_match_data(&pdev->dev); 1724 i2c_dev->cont_id = pdev->id; 1725 i2c_dev->dev = &pdev->dev; 1726 1727 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1728 if (IS_ERR(i2c_dev->base)) 1729 return PTR_ERR(i2c_dev->base); 1730 1731 i2c_dev->base_phys = res->start; 1732 1733 err = platform_get_irq(pdev, 0); 1734 if (err < 0) 1735 return err; 1736 1737 i2c_dev->irq = err; 1738 1739 /* interrupt will be enabled during of transfer time */ 1740 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1741 1742 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, 1743 NULL, tegra_i2c_isr, 1744 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1745 dev_name(i2c_dev->dev), i2c_dev); 1746 if (err) 1747 return err; 1748 1749 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); 1750 if (IS_ERR(i2c_dev->rst)) { 1751 dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), 1752 "failed to get reset control\n"); 1753 return PTR_ERR(i2c_dev->rst); 1754 } 1755 1756 tegra_i2c_parse_dt(i2c_dev); 1757 1758 err = tegra_i2c_init_clocks(i2c_dev); 1759 if (err) 1760 return err; 1761 1762 err = tegra_i2c_init_dma(i2c_dev); 1763 if (err) 1764 goto release_clocks; 1765 1766 /* 1767 * VI I2C is in VE power domain which is not always ON and not 1768 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a 1769 * non IRQ-safe domain because this prevents powering off the power 1770 * domain. 1771 * 1772 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't 1773 * be used for atomic transfers. 1774 */ 1775 if (!i2c_dev->is_vi) 1776 pm_runtime_irq_safe(i2c_dev->dev); 1777 1778 pm_runtime_enable(i2c_dev->dev); 1779 1780 err = tegra_i2c_init_hardware(i2c_dev); 1781 if (err) 1782 goto release_rpm; 1783 1784 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1785 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1786 i2c_dev->adapter.dev.parent = i2c_dev->dev; 1787 i2c_dev->adapter.retries = 1; 1788 i2c_dev->adapter.timeout = 6 * HZ; 1789 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1790 i2c_dev->adapter.owner = THIS_MODULE; 1791 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1792 i2c_dev->adapter.algo = &tegra_i2c_algo; 1793 i2c_dev->adapter.nr = pdev->id; 1794 1795 if (i2c_dev->hw->supports_bus_clear) 1796 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1797 1798 strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1799 sizeof(i2c_dev->adapter.name)); 1800 1801 err = i2c_add_numbered_adapter(&i2c_dev->adapter); 1802 if (err) 1803 goto release_rpm; 1804 1805 return 0; 1806 1807 release_rpm: 1808 pm_runtime_disable(i2c_dev->dev); 1809 1810 tegra_i2c_release_dma(i2c_dev); 1811 release_clocks: 1812 tegra_i2c_release_clocks(i2c_dev); 1813 1814 return err; 1815 } 1816 1817 static int tegra_i2c_remove(struct platform_device *pdev) 1818 { 1819 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1820 1821 i2c_del_adapter(&i2c_dev->adapter); 1822 pm_runtime_disable(i2c_dev->dev); 1823 1824 tegra_i2c_release_dma(i2c_dev); 1825 tegra_i2c_release_clocks(i2c_dev); 1826 1827 return 0; 1828 } 1829 1830 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 1831 { 1832 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1833 int err; 1834 1835 err = pinctrl_pm_select_default_state(dev); 1836 if (err) 1837 return err; 1838 1839 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); 1840 if (err) 1841 return err; 1842 1843 /* 1844 * VI I2C device is attached to VE power domain which goes through 1845 * power ON/OFF during runtime PM resume/suspend, meaning that 1846 * controller needs to be re-initialized after power ON. 1847 */ 1848 if (i2c_dev->is_vi) { 1849 err = tegra_i2c_init(i2c_dev); 1850 if (err) 1851 goto disable_clocks; 1852 } 1853 1854 return 0; 1855 1856 disable_clocks: 1857 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1858 1859 return err; 1860 } 1861 1862 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 1863 { 1864 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1865 1866 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1867 1868 return pinctrl_pm_select_idle_state(dev); 1869 } 1870 1871 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1872 { 1873 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1874 int err; 1875 1876 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1877 1878 if (!pm_runtime_status_suspended(dev)) { 1879 err = tegra_i2c_runtime_suspend(dev); 1880 if (err) 1881 return err; 1882 } 1883 1884 return 0; 1885 } 1886 1887 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1888 { 1889 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1890 int err; 1891 1892 /* 1893 * We need to ensure that clocks are enabled so that registers can be 1894 * restored in tegra_i2c_init(). 1895 */ 1896 err = tegra_i2c_runtime_resume(dev); 1897 if (err) 1898 return err; 1899 1900 err = tegra_i2c_init(i2c_dev); 1901 if (err) 1902 return err; 1903 1904 /* 1905 * In case we are runtime suspended, disable clocks again so that we 1906 * don't unbalance the clock reference counts during the next runtime 1907 * resume transition. 1908 */ 1909 if (pm_runtime_status_suspended(dev)) { 1910 err = tegra_i2c_runtime_suspend(dev); 1911 if (err) 1912 return err; 1913 } 1914 1915 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1916 1917 return 0; 1918 } 1919 1920 static const struct dev_pm_ops tegra_i2c_pm = { 1921 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1922 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1923 NULL) 1924 }; 1925 1926 static struct platform_driver tegra_i2c_driver = { 1927 .probe = tegra_i2c_probe, 1928 .remove = tegra_i2c_remove, 1929 .driver = { 1930 .name = "tegra-i2c", 1931 .of_match_table = tegra_i2c_of_match, 1932 .pm = &tegra_i2c_pm, 1933 }, 1934 }; 1935 module_platform_driver(tegra_i2c_driver); 1936 1937 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver"); 1938 MODULE_AUTHOR("Colin Cross"); 1939 MODULE_LICENSE("GPL v2"); 1940