1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/kernel.h> 23 #include <linux/ktime.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/reset.h> 30 31 #define BYTES_PER_FIFO_WORD 4 32 33 #define I2C_CNFG 0x000 34 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 35 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 36 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 37 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 38 #define I2C_STATUS 0x01c 39 #define I2C_SL_CNFG 0x020 40 #define I2C_SL_CNFG_NACK BIT(1) 41 #define I2C_SL_CNFG_NEWSL BIT(2) 42 #define I2C_SL_ADDR1 0x02c 43 #define I2C_SL_ADDR2 0x030 44 #define I2C_TLOW_SEXT 0x034 45 #define I2C_TX_FIFO 0x050 46 #define I2C_RX_FIFO 0x054 47 #define I2C_PACKET_TRANSFER_STATUS 0x058 48 #define I2C_FIFO_CONTROL 0x05c 49 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 50 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 53 #define I2C_FIFO_STATUS 0x060 54 #define I2C_FIFO_STATUS_TX GENMASK(7, 4) 55 #define I2C_FIFO_STATUS_RX GENMASK(3, 0) 56 #define I2C_INT_MASK 0x064 57 #define I2C_INT_STATUS 0x068 58 #define I2C_INT_BUS_CLR_DONE BIT(11) 59 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 60 #define I2C_INT_NO_ACK BIT(3) 61 #define I2C_INT_ARBITRATION_LOST BIT(2) 62 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 63 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 64 #define I2C_CLK_DIVISOR 0x06c 65 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 66 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 67 68 #define DVC_CTRL_REG1 0x000 69 #define DVC_CTRL_REG1_INTR_EN BIT(10) 70 #define DVC_CTRL_REG3 0x008 71 #define DVC_CTRL_REG3_SW_PROG BIT(26) 72 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 73 #define DVC_STATUS 0x00c 74 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 75 76 #define I2C_ERR_NONE 0x00 77 #define I2C_ERR_NO_ACK BIT(0) 78 #define I2C_ERR_ARBITRATION_LOST BIT(1) 79 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 80 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 81 82 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28) 83 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16) 84 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12) 85 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 86 #define PACKET_HEADER0_PROTOCOL_I2C 1 87 88 #define I2C_HEADER_CONT_ON_NAK BIT(21) 89 #define I2C_HEADER_READ BIT(19) 90 #define I2C_HEADER_10BIT_ADDR BIT(18) 91 #define I2C_HEADER_IE_ENABLE BIT(17) 92 #define I2C_HEADER_REPEAT_START BIT(16) 93 #define I2C_HEADER_CONTINUE_XFER BIT(15) 94 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 95 96 #define I2C_BUS_CLEAR_CNFG 0x084 97 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 98 #define I2C_BC_STOP_COND BIT(2) 99 #define I2C_BC_TERMINATE BIT(1) 100 #define I2C_BC_ENABLE BIT(0) 101 #define I2C_BUS_CLEAR_STATUS 0x088 102 #define I2C_BC_STATUS BIT(0) 103 104 #define I2C_CONFIG_LOAD 0x08c 105 #define I2C_MSTR_CONFIG_LOAD BIT(0) 106 107 #define I2C_CLKEN_OVERRIDE 0x090 108 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 109 110 #define I2C_INTERFACE_TIMING_0 0x094 111 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 112 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 113 #define I2C_INTERFACE_TIMING_1 0x098 114 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 115 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 116 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 117 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 118 119 #define I2C_HS_INTERFACE_TIMING_0 0x09c 120 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 121 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 122 #define I2C_HS_INTERFACE_TIMING_1 0x0a0 123 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 124 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 125 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 126 127 #define I2C_MST_FIFO_CONTROL 0x0b4 128 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 129 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 132 133 #define I2C_MST_FIFO_STATUS 0x0b8 134 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 135 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 136 137 /* configuration load timeout in microseconds */ 138 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 139 140 /* packet header size in bytes */ 141 #define I2C_PACKET_HEADER_SIZE 12 142 143 /* 144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 145 * avoid DMA overhead, otherwise external APB DMA controller will be used. 146 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 147 * I2C_PACKET_HEADER_SIZE. 148 */ 149 #define I2C_PIO_MODE_PREFERRED_LEN 32 150 151 /* 152 * msg_end_type: The bus control which needs to be sent at end of transfer. 153 * @MSG_END_STOP: Send stop pulse. 154 * @MSG_END_REPEAT_START: Send repeat-start. 155 * @MSG_END_CONTINUE: Don't send stop or repeat-start. 156 */ 157 enum msg_end_type { 158 MSG_END_STOP, 159 MSG_END_REPEAT_START, 160 MSG_END_CONTINUE, 161 }; 162 163 /** 164 * struct tegra_i2c_hw_feature : per hardware generation features 165 * @has_continue_xfer_support: continue-transfer supported 166 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 167 * completion interrupt on per packet basis. 168 * @has_config_load_reg: Has the config load register to load the new 169 * configuration. 170 * @clk_divisor_hs_mode: Clock divisor in HS mode. 171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 172 * applicable if there is no fast clock source i.e. single clock 173 * source. 174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 175 * applicable if there is no fast clock source i.e. single clock 176 * source. 177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 178 * applicable if there is no fast clock source (i.e. single 179 * clock source). 180 * @has_multi_master_mode: The I2C controller supports running in single-master 181 * or multi-master mode. 182 * @has_slcg_override_reg: The I2C controller supports a register that 183 * overrides the second level clock gating. 184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 185 * provides additional features and allows for longer messages to 186 * be transferred in one go. 187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not 188 * allowing 0 length transfers. 189 * @supports_bus_clear: Bus Clear support to recover from bus hang during 190 * SDA stuck low from device for some unknown reasons. 191 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 192 * @tlow_std_mode: Low period of the clock in standard mode. 193 * @thigh_std_mode: High period of the clock in standard mode. 194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 196 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 197 * in standard mode. 198 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 199 * conditions in fast/fast-plus modes. 200 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 201 * in HS mode. 202 * @has_interface_timing_reg: Has interface timing register to program the tuned 203 * timing settings. 204 */ 205 struct tegra_i2c_hw_feature { 206 bool has_continue_xfer_support; 207 bool has_per_pkt_xfer_complete_irq; 208 bool has_config_load_reg; 209 u32 clk_divisor_hs_mode; 210 u32 clk_divisor_std_mode; 211 u32 clk_divisor_fast_mode; 212 u32 clk_divisor_fast_plus_mode; 213 bool has_multi_master_mode; 214 bool has_slcg_override_reg; 215 bool has_mst_fifo; 216 const struct i2c_adapter_quirks *quirks; 217 bool supports_bus_clear; 218 bool has_apb_dma; 219 u32 tlow_std_mode; 220 u32 thigh_std_mode; 221 u32 tlow_fast_fastplus_mode; 222 u32 thigh_fast_fastplus_mode; 223 u32 setup_hold_time_std_mode; 224 u32 setup_hold_time_fast_fast_plus_mode; 225 u32 setup_hold_time_hs_mode; 226 bool has_interface_timing_reg; 227 }; 228 229 /** 230 * struct tegra_i2c_dev - per device I2C context 231 * @dev: device reference for power management 232 * @hw: Tegra I2C HW feature 233 * @adapter: core I2C layer adapter information 234 * @div_clk: clock reference for div clock of I2C controller 235 * @clocks: array of I2C controller clocks 236 * @nclocks: number of clocks in the array 237 * @rst: reset control for the I2C controller 238 * @base: ioremapped registers cookie 239 * @base_phys: physical base address of the I2C controller 240 * @cont_id: I2C controller ID, used for packet header 241 * @irq: IRQ number of transfer complete interrupt 242 * @is_dvc: identifies the DVC I2C controller, has a different register layout 243 * @is_vi: identifies the VI I2C controller, has a different register layout 244 * @msg_complete: transfer completion notifier 245 * @msg_err: error code for completed message 246 * @msg_buf: pointer to current message data 247 * @msg_buf_remaining: size of unsent data in the message buffer 248 * @msg_read: indicates that the transfer is a read access 249 * @timings: i2c timings information like bus frequency 250 * @multimaster_mode: indicates that I2C controller is in multi-master mode 251 * @tx_dma_chan: DMA transmit channel 252 * @rx_dma_chan: DMA receive channel 253 * @dma_phys: handle to DMA resources 254 * @dma_buf: pointer to allocated DMA buffer 255 * @dma_buf_size: DMA buffer size 256 * @dma_mode: indicates active DMA transfer 257 * @dma_complete: DMA completion notifier 258 * @atomic_mode: indicates active atomic transfer 259 */ 260 struct tegra_i2c_dev { 261 struct device *dev; 262 struct i2c_adapter adapter; 263 264 const struct tegra_i2c_hw_feature *hw; 265 struct reset_control *rst; 266 unsigned int cont_id; 267 unsigned int irq; 268 269 phys_addr_t base_phys; 270 void __iomem *base; 271 272 struct clk_bulk_data clocks[2]; 273 unsigned int nclocks; 274 275 struct clk *div_clk; 276 struct i2c_timings timings; 277 278 struct completion msg_complete; 279 size_t msg_buf_remaining; 280 int msg_err; 281 u8 *msg_buf; 282 283 struct completion dma_complete; 284 struct dma_chan *tx_dma_chan; 285 struct dma_chan *rx_dma_chan; 286 unsigned int dma_buf_size; 287 dma_addr_t dma_phys; 288 void *dma_buf; 289 290 bool multimaster_mode; 291 bool atomic_mode; 292 bool dma_mode; 293 bool msg_read; 294 bool is_dvc; 295 bool is_vi; 296 }; 297 298 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 299 unsigned int reg) 300 { 301 writel_relaxed(val, i2c_dev->base + reg); 302 } 303 304 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 305 { 306 return readl_relaxed(i2c_dev->base + reg); 307 } 308 309 /* 310 * If necessary, i2c_writel() and i2c_readl() will offset the register 311 * in order to talk to the I2C block inside the DVC block. 312 */ 313 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 314 { 315 if (i2c_dev->is_dvc) 316 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 317 else if (i2c_dev->is_vi) 318 reg = 0xc00 + (reg << 2); 319 320 return reg; 321 } 322 323 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 324 { 325 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 326 327 /* read back register to make sure that register writes completed */ 328 if (reg != I2C_TX_FIFO) 329 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 330 else if (i2c_dev->is_vi) 331 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 332 } 333 334 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 335 { 336 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 337 } 338 339 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 340 unsigned int reg, unsigned int len) 341 { 342 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 343 } 344 345 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, 346 unsigned int reg, unsigned int len) 347 { 348 u32 *data32 = data; 349 350 /* 351 * VI I2C controller has known hardware bug where writes get stuck 352 * when immediate multiple writes happen to TX_FIFO register. 353 * Recommended software work around is to read I2C register after 354 * each write to TX_FIFO register to flush out the data. 355 */ 356 while (len--) 357 i2c_writel(i2c_dev, *data32++, reg); 358 } 359 360 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 361 unsigned int reg, unsigned int len) 362 { 363 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 364 } 365 366 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 367 { 368 u32 int_mask; 369 370 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 371 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 372 } 373 374 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 375 { 376 u32 int_mask; 377 378 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 379 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 380 } 381 382 static void tegra_i2c_dma_complete(void *args) 383 { 384 struct tegra_i2c_dev *i2c_dev = args; 385 386 complete(&i2c_dev->dma_complete); 387 } 388 389 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 390 { 391 struct dma_async_tx_descriptor *dma_desc; 392 enum dma_transfer_direction dir; 393 struct dma_chan *chan; 394 395 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 396 397 reinit_completion(&i2c_dev->dma_complete); 398 399 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 400 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; 401 402 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, 403 len, dir, DMA_PREP_INTERRUPT | 404 DMA_CTRL_ACK); 405 if (!dma_desc) { 406 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", 407 i2c_dev->msg_read ? "RX" : "TX"); 408 return -EINVAL; 409 } 410 411 dma_desc->callback = tegra_i2c_dma_complete; 412 dma_desc->callback_param = i2c_dev; 413 414 dmaengine_submit(dma_desc); 415 dma_async_issue_pending(chan); 416 417 return 0; 418 } 419 420 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 421 { 422 if (i2c_dev->dma_buf) { 423 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 424 i2c_dev->dma_buf, i2c_dev->dma_phys); 425 i2c_dev->dma_buf = NULL; 426 } 427 428 if (i2c_dev->tx_dma_chan) { 429 dma_release_channel(i2c_dev->tx_dma_chan); 430 i2c_dev->tx_dma_chan = NULL; 431 } 432 433 if (i2c_dev->rx_dma_chan) { 434 dma_release_channel(i2c_dev->rx_dma_chan); 435 i2c_dev->rx_dma_chan = NULL; 436 } 437 } 438 439 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 440 { 441 struct dma_chan *chan; 442 dma_addr_t dma_phys; 443 u32 *dma_buf; 444 int err; 445 446 if (i2c_dev->is_vi) 447 return 0; 448 449 if (!i2c_dev->hw->has_apb_dma) { 450 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 451 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); 452 return 0; 453 } 454 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) { 455 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); 456 return 0; 457 } 458 459 chan = dma_request_chan(i2c_dev->dev, "rx"); 460 if (IS_ERR(chan)) { 461 err = PTR_ERR(chan); 462 goto err_out; 463 } 464 465 i2c_dev->rx_dma_chan = chan; 466 467 chan = dma_request_chan(i2c_dev->dev, "tx"); 468 if (IS_ERR(chan)) { 469 err = PTR_ERR(chan); 470 goto err_out; 471 } 472 473 i2c_dev->tx_dma_chan = chan; 474 475 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + 476 I2C_PACKET_HEADER_SIZE; 477 478 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 479 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 480 if (!dma_buf) { 481 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); 482 err = -ENOMEM; 483 goto err_out; 484 } 485 486 i2c_dev->dma_buf = dma_buf; 487 i2c_dev->dma_phys = dma_phys; 488 489 return 0; 490 491 err_out: 492 tegra_i2c_release_dma(i2c_dev); 493 if (err != -EPROBE_DEFER) { 494 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 495 dev_err(i2c_dev->dev, "falling back to PIO\n"); 496 return 0; 497 } 498 499 return err; 500 } 501 502 /* 503 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 504 * block. This block is identical to the rest of the I2C blocks, except that 505 * it only supports master mode, it has registers moved around, and it needs 506 * some extra init to get it into I2C mode. The register moves are handled 507 * by i2c_readl() and i2c_writel(). 508 */ 509 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 510 { 511 u32 val; 512 513 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 514 val |= DVC_CTRL_REG3_SW_PROG; 515 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 516 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 517 518 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 519 val |= DVC_CTRL_REG1_INTR_EN; 520 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 521 } 522 523 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) 524 { 525 u32 value; 526 527 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 528 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 529 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 530 531 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 532 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 533 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 534 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 535 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 536 537 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 538 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 539 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 540 541 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 542 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 543 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 544 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 545 546 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 547 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 548 549 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 550 } 551 552 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 553 u32 reg, u32 mask, u32 delay_us, 554 u32 timeout_us) 555 { 556 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 557 u32 val; 558 559 if (!i2c_dev->atomic_mode) 560 return readl_relaxed_poll_timeout(addr, val, !(val & mask), 561 delay_us, timeout_us); 562 563 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), 564 delay_us, timeout_us); 565 } 566 567 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 568 { 569 u32 mask, val, offset; 570 int err; 571 572 if (i2c_dev->hw->has_mst_fifo) { 573 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 574 I2C_MST_FIFO_CONTROL_RX_FLUSH; 575 offset = I2C_MST_FIFO_CONTROL; 576 } else { 577 mask = I2C_FIFO_CONTROL_TX_FLUSH | 578 I2C_FIFO_CONTROL_RX_FLUSH; 579 offset = I2C_FIFO_CONTROL; 580 } 581 582 val = i2c_readl(i2c_dev, offset); 583 val |= mask; 584 i2c_writel(i2c_dev, val, offset); 585 586 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000); 587 if (err) { 588 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); 589 return err; 590 } 591 592 return 0; 593 } 594 595 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 596 { 597 int err; 598 599 if (!i2c_dev->hw->has_config_load_reg) 600 return 0; 601 602 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 603 604 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 605 1000, I2C_CONFIG_LOAD_TIMEOUT); 606 if (err) { 607 dev_err(i2c_dev->dev, "failed to load config\n"); 608 return err; 609 } 610 611 return 0; 612 } 613 614 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 615 { 616 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 617 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); 618 struct i2c_timings *t = &i2c_dev->timings; 619 int err; 620 621 /* 622 * The reset shouldn't ever fail in practice. The failure will be a 623 * sign of a severe problem that needs to be resolved. Still we don't 624 * want to fail the initialization completely because this may break 625 * kernel boot up since voltage regulators use I2C. Hence, we will 626 * emit a noisy warning on error, which won't stay unnoticed and 627 * won't hose machine entirely. 628 */ 629 if (handle) 630 err = acpi_evaluate_object(handle, "_RST", NULL, NULL); 631 else 632 err = reset_control_reset(i2c_dev->rst); 633 634 WARN_ON_ONCE(err); 635 636 if (i2c_dev->is_dvc) 637 tegra_dvc_init(i2c_dev); 638 639 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 640 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); 641 642 if (i2c_dev->hw->has_multi_master_mode) 643 val |= I2C_CNFG_MULTI_MASTER_MODE; 644 645 i2c_writel(i2c_dev, val, I2C_CNFG); 646 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 647 648 if (i2c_dev->is_vi) 649 tegra_i2c_vi_init(i2c_dev); 650 651 switch (t->bus_freq_hz) { 652 case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 653 default: 654 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 655 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 656 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 657 658 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 659 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 660 else 661 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 662 break; 663 664 case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 665 tlow = i2c_dev->hw->tlow_std_mode; 666 thigh = i2c_dev->hw->thigh_std_mode; 667 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 668 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 669 break; 670 } 671 672 /* make sure clock divisor programmed correctly */ 673 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 674 i2c_dev->hw->clk_divisor_hs_mode) | 675 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 676 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 677 678 if (i2c_dev->hw->has_interface_timing_reg) { 679 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 680 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 681 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 682 } 683 684 /* 685 * Configure setup and hold times only when tsu_thd is non-zero. 686 * Otherwise, preserve the chip default values. 687 */ 688 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 689 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 690 691 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 692 693 err = clk_set_rate(i2c_dev->div_clk, 694 t->bus_freq_hz * clk_multiplier); 695 if (err) { 696 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); 697 return err; 698 } 699 700 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) { 701 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 702 703 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 704 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 705 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 706 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 707 } 708 709 err = tegra_i2c_flush_fifos(i2c_dev); 710 if (err) 711 return err; 712 713 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 714 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 715 716 err = tegra_i2c_wait_for_config_load(i2c_dev); 717 if (err) 718 return err; 719 720 return 0; 721 } 722 723 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 724 { 725 u32 cnfg; 726 727 /* 728 * NACK interrupt is generated before the I2C controller generates 729 * the STOP condition on the bus. So, wait for 2 clock periods 730 * before disabling the controller so that the STOP condition has 731 * been delivered properly. 732 */ 733 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); 734 735 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 736 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 737 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 738 739 return tegra_i2c_wait_for_config_load(i2c_dev); 740 } 741 742 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 743 { 744 size_t buf_remaining = i2c_dev->msg_buf_remaining; 745 unsigned int words_to_transfer, rx_fifo_avail; 746 u8 *buf = i2c_dev->msg_buf; 747 u32 val; 748 749 /* 750 * Catch overflow due to message fully sent before the check for 751 * RX FIFO availability. 752 */ 753 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 754 return -EINVAL; 755 756 if (i2c_dev->hw->has_mst_fifo) { 757 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 758 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 759 } else { 760 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 761 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 762 } 763 764 /* round down to exclude partial word at the end of buffer */ 765 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 766 if (words_to_transfer > rx_fifo_avail) 767 words_to_transfer = rx_fifo_avail; 768 769 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 770 771 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 772 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 773 rx_fifo_avail -= words_to_transfer; 774 775 /* 776 * If there is a partial word at the end of buffer, handle it 777 * manually to prevent overwriting past the end of buffer. 778 */ 779 if (rx_fifo_avail > 0 && buf_remaining > 0) { 780 /* 781 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 782 * when (words_to_transfer was > rx_fifo_avail) earlier 783 * in this function. 784 */ 785 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 786 val = cpu_to_le32(val); 787 memcpy(buf, &val, buf_remaining); 788 buf_remaining = 0; 789 rx_fifo_avail--; 790 } 791 792 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 793 if (WARN_ON_ONCE(rx_fifo_avail)) 794 return -EINVAL; 795 796 i2c_dev->msg_buf_remaining = buf_remaining; 797 i2c_dev->msg_buf = buf; 798 799 return 0; 800 } 801 802 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 803 { 804 size_t buf_remaining = i2c_dev->msg_buf_remaining; 805 unsigned int words_to_transfer, tx_fifo_avail; 806 u8 *buf = i2c_dev->msg_buf; 807 u32 val; 808 809 if (i2c_dev->hw->has_mst_fifo) { 810 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 811 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 812 } else { 813 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 814 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 815 } 816 817 /* round down to exclude partial word at the end of buffer */ 818 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 819 820 /* 821 * This hunk pushes 4 bytes at a time into the TX FIFO. 822 * 823 * It's very common to have < 4 bytes, hence there is no word 824 * to push if we have less than 4 bytes to transfer. 825 */ 826 if (words_to_transfer) { 827 if (words_to_transfer > tx_fifo_avail) 828 words_to_transfer = tx_fifo_avail; 829 830 /* 831 * Update state before writing to FIFO. Note that this may 832 * cause us to finish writing all bytes (AKA buf_remaining 833 * goes to 0), hence we have a potential for an interrupt 834 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt 835 * is disabled at this point. 836 */ 837 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 838 tx_fifo_avail -= words_to_transfer; 839 840 i2c_dev->msg_buf_remaining = buf_remaining; 841 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 842 843 if (i2c_dev->is_vi) 844 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 845 else 846 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 847 848 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 849 } 850 851 /* 852 * If there is a partial word at the end of buffer, handle it manually 853 * to prevent reading past the end of buffer, which could cross a page 854 * boundary and fault. 855 */ 856 if (tx_fifo_avail > 0 && buf_remaining > 0) { 857 /* 858 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 859 * when (words_to_transfer was > tx_fifo_avail) earlier 860 * in this function for non-zero words_to_transfer. 861 */ 862 memcpy(&val, buf, buf_remaining); 863 val = le32_to_cpu(val); 864 865 i2c_dev->msg_buf_remaining = 0; 866 i2c_dev->msg_buf = NULL; 867 868 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 869 } 870 871 return 0; 872 } 873 874 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 875 { 876 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 877 struct tegra_i2c_dev *i2c_dev = dev_id; 878 u32 status; 879 880 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 881 882 if (status == 0) { 883 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 884 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 885 i2c_readl(i2c_dev, I2C_STATUS), 886 i2c_readl(i2c_dev, I2C_CNFG)); 887 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 888 goto err; 889 } 890 891 if (status & status_err) { 892 tegra_i2c_disable_packet_mode(i2c_dev); 893 if (status & I2C_INT_NO_ACK) 894 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 895 if (status & I2C_INT_ARBITRATION_LOST) 896 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 897 goto err; 898 } 899 900 /* 901 * I2C transfer is terminated during the bus clear, so skip 902 * processing the other interrupts. 903 */ 904 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 905 goto err; 906 907 if (!i2c_dev->dma_mode) { 908 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 909 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 910 /* 911 * Overflow error condition: message fully sent, 912 * with no XFER_COMPLETE interrupt but hardware 913 * asks to transfer more. 914 */ 915 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 916 goto err; 917 } 918 } 919 920 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 921 if (i2c_dev->msg_buf_remaining) 922 tegra_i2c_fill_tx_fifo(i2c_dev); 923 else 924 tegra_i2c_mask_irq(i2c_dev, 925 I2C_INT_TX_FIFO_DATA_REQ); 926 } 927 } 928 929 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 930 if (i2c_dev->is_dvc) 931 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 932 933 /* 934 * During message read XFER_COMPLETE interrupt is triggered prior to 935 * DMA completion and during message write XFER_COMPLETE interrupt is 936 * triggered after DMA completion. 937 * 938 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer, 939 * so forcing msg_buf_remaining to 0 in DMA mode. 940 */ 941 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 942 if (i2c_dev->dma_mode) 943 i2c_dev->msg_buf_remaining = 0; 944 /* 945 * Underflow error condition: XFER_COMPLETE before message 946 * fully sent. 947 */ 948 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 949 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 950 goto err; 951 } 952 complete(&i2c_dev->msg_complete); 953 } 954 goto done; 955 err: 956 /* mask all interrupts on error */ 957 tegra_i2c_mask_irq(i2c_dev, 958 I2C_INT_NO_ACK | 959 I2C_INT_ARBITRATION_LOST | 960 I2C_INT_PACKET_XFER_COMPLETE | 961 I2C_INT_TX_FIFO_DATA_REQ | 962 I2C_INT_RX_FIFO_DATA_REQ); 963 964 if (i2c_dev->hw->supports_bus_clear) 965 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 966 967 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 968 969 if (i2c_dev->is_dvc) 970 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 971 972 if (i2c_dev->dma_mode) { 973 if (i2c_dev->msg_read) 974 dmaengine_terminate_async(i2c_dev->rx_dma_chan); 975 else 976 dmaengine_terminate_async(i2c_dev->tx_dma_chan); 977 978 complete(&i2c_dev->dma_complete); 979 } 980 981 complete(&i2c_dev->msg_complete); 982 done: 983 return IRQ_HANDLED; 984 } 985 986 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 987 size_t len) 988 { 989 struct dma_slave_config slv_config = {0}; 990 u32 val, reg, dma_burst, reg_offset; 991 struct dma_chan *chan; 992 int err; 993 994 if (i2c_dev->hw->has_mst_fifo) 995 reg = I2C_MST_FIFO_CONTROL; 996 else 997 reg = I2C_FIFO_CONTROL; 998 999 if (i2c_dev->dma_mode) { 1000 if (len & 0xF) 1001 dma_burst = 1; 1002 else if (len & 0x10) 1003 dma_burst = 4; 1004 else 1005 dma_burst = 8; 1006 1007 if (i2c_dev->msg_read) { 1008 chan = i2c_dev->rx_dma_chan; 1009 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 1010 1011 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 1012 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1013 slv_config.src_maxburst = dma_burst; 1014 1015 if (i2c_dev->hw->has_mst_fifo) 1016 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 1017 else 1018 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1019 } else { 1020 chan = i2c_dev->tx_dma_chan; 1021 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1022 1023 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1024 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1025 slv_config.dst_maxburst = dma_burst; 1026 1027 if (i2c_dev->hw->has_mst_fifo) 1028 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 1029 else 1030 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 1031 } 1032 1033 slv_config.device_fc = true; 1034 err = dmaengine_slave_config(chan, &slv_config); 1035 if (err) { 1036 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); 1037 dev_err(i2c_dev->dev, "falling back to PIO\n"); 1038 1039 tegra_i2c_release_dma(i2c_dev); 1040 i2c_dev->dma_mode = false; 1041 } else { 1042 goto out; 1043 } 1044 } 1045 1046 if (i2c_dev->hw->has_mst_fifo) 1047 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 1048 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 1049 else 1050 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 1051 I2C_FIFO_CONTROL_RX_TRIG(1); 1052 out: 1053 i2c_writel(i2c_dev, val, reg); 1054 } 1055 1056 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev, 1057 struct completion *complete, 1058 unsigned int timeout_ms) 1059 { 1060 ktime_t ktime = ktime_get(); 1061 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1062 1063 do { 1064 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1065 1066 if (status) 1067 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1068 1069 if (completion_done(complete)) { 1070 s64 delta = ktime_ms_delta(ktimeout, ktime); 1071 1072 return msecs_to_jiffies(delta) ?: 1; 1073 } 1074 1075 ktime = ktime_get(); 1076 1077 } while (ktime_before(ktime, ktimeout)); 1078 1079 return 0; 1080 } 1081 1082 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev, 1083 struct completion *complete, 1084 unsigned int timeout_ms) 1085 { 1086 unsigned long ret; 1087 1088 if (i2c_dev->atomic_mode) { 1089 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms); 1090 } else { 1091 enable_irq(i2c_dev->irq); 1092 ret = wait_for_completion_timeout(complete, 1093 msecs_to_jiffies(timeout_ms)); 1094 disable_irq(i2c_dev->irq); 1095 1096 /* 1097 * Under some rare circumstances (like running KASAN + 1098 * NFS root) CPU, which handles interrupt, may stuck in 1099 * uninterruptible state for a significant time. In this 1100 * case we will get timeout if I2C transfer is running on 1101 * a sibling CPU, despite of IRQ being raised. 1102 * 1103 * In order to handle this rare condition, the IRQ status 1104 * needs to be checked after timeout. 1105 */ 1106 if (ret == 0) 1107 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0); 1108 } 1109 1110 return ret; 1111 } 1112 1113 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1114 { 1115 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1116 u32 val, time_left; 1117 int err; 1118 1119 reinit_completion(&i2c_dev->msg_complete); 1120 1121 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1122 I2C_BC_TERMINATE; 1123 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1124 1125 err = tegra_i2c_wait_for_config_load(i2c_dev); 1126 if (err) 1127 return err; 1128 1129 val |= I2C_BC_ENABLE; 1130 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1131 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1132 1133 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); 1134 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1135 1136 if (time_left == 0) { 1137 dev_err(i2c_dev->dev, "failed to clear bus\n"); 1138 return -ETIMEDOUT; 1139 } 1140 1141 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1142 if (!(val & I2C_BC_STATUS)) { 1143 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1144 return -EIO; 1145 } 1146 1147 return -EAGAIN; 1148 } 1149 1150 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, 1151 struct i2c_msg *msg, 1152 enum msg_end_type end_state) 1153 { 1154 u32 *dma_buf = i2c_dev->dma_buf; 1155 u32 packet_header; 1156 1157 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) | 1158 FIELD_PREP(PACKET_HEADER0_PROTOCOL, 1159 PACKET_HEADER0_PROTOCOL_I2C) | 1160 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | 1161 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1); 1162 1163 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1164 *dma_buf++ = packet_header; 1165 else 1166 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1167 1168 packet_header = msg->len - 1; 1169 1170 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1171 *dma_buf++ = packet_header; 1172 else 1173 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1174 1175 packet_header = I2C_HEADER_IE_ENABLE; 1176 1177 if (end_state == MSG_END_CONTINUE) 1178 packet_header |= I2C_HEADER_CONTINUE_XFER; 1179 else if (end_state == MSG_END_REPEAT_START) 1180 packet_header |= I2C_HEADER_REPEAT_START; 1181 1182 if (msg->flags & I2C_M_TEN) { 1183 packet_header |= msg->addr; 1184 packet_header |= I2C_HEADER_10BIT_ADDR; 1185 } else { 1186 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1187 } 1188 1189 if (msg->flags & I2C_M_IGNORE_NAK) 1190 packet_header |= I2C_HEADER_CONT_ON_NAK; 1191 1192 if (msg->flags & I2C_M_RD) 1193 packet_header |= I2C_HEADER_READ; 1194 1195 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1196 *dma_buf++ = packet_header; 1197 else 1198 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1199 } 1200 1201 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, 1202 struct i2c_msg *msg) 1203 { 1204 if (i2c_dev->msg_err == I2C_ERR_NONE) 1205 return 0; 1206 1207 tegra_i2c_init(i2c_dev); 1208 1209 /* start recovery upon arbitration loss in single master mode */ 1210 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1211 if (!i2c_dev->multimaster_mode) 1212 return i2c_recover_bus(&i2c_dev->adapter); 1213 1214 return -EAGAIN; 1215 } 1216 1217 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1218 if (msg->flags & I2C_M_IGNORE_NAK) 1219 return 0; 1220 1221 return -EREMOTEIO; 1222 } 1223 1224 return -EIO; 1225 } 1226 1227 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1228 struct i2c_msg *msg, 1229 enum msg_end_type end_state) 1230 { 1231 unsigned long time_left, xfer_time = 100; 1232 size_t xfer_size; 1233 u32 int_mask; 1234 int err; 1235 1236 err = tegra_i2c_flush_fifos(i2c_dev); 1237 if (err) 1238 return err; 1239 1240 i2c_dev->msg_buf = msg->buf; 1241 1242 /* The condition true implies smbus block read and len is already read */ 1243 if (msg->flags & I2C_M_RECV_LEN && end_state != MSG_END_CONTINUE) 1244 i2c_dev->msg_buf = msg->buf + 1; 1245 1246 i2c_dev->msg_buf_remaining = msg->len; 1247 i2c_dev->msg_err = I2C_ERR_NONE; 1248 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); 1249 reinit_completion(&i2c_dev->msg_complete); 1250 1251 if (i2c_dev->msg_read) 1252 xfer_size = msg->len; 1253 else 1254 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; 1255 1256 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1257 1258 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && 1259 i2c_dev->dma_buf && !i2c_dev->atomic_mode; 1260 1261 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1262 1263 /* 1264 * Transfer time in mSec = Total bits / transfer rate 1265 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1266 */ 1267 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1268 i2c_dev->timings.bus_freq_hz); 1269 1270 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1271 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1272 1273 if (i2c_dev->dma_mode) { 1274 if (i2c_dev->msg_read) { 1275 dma_sync_single_for_device(i2c_dev->dev, 1276 i2c_dev->dma_phys, 1277 xfer_size, DMA_FROM_DEVICE); 1278 1279 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1280 if (err) 1281 return err; 1282 } else { 1283 dma_sync_single_for_cpu(i2c_dev->dev, 1284 i2c_dev->dma_phys, 1285 xfer_size, DMA_TO_DEVICE); 1286 } 1287 } 1288 1289 tegra_i2c_push_packet_header(i2c_dev, msg, end_state); 1290 1291 if (!i2c_dev->msg_read) { 1292 if (i2c_dev->dma_mode) { 1293 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, 1294 msg->buf, msg->len); 1295 1296 dma_sync_single_for_device(i2c_dev->dev, 1297 i2c_dev->dma_phys, 1298 xfer_size, DMA_TO_DEVICE); 1299 1300 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1301 if (err) 1302 return err; 1303 } else { 1304 tegra_i2c_fill_tx_fifo(i2c_dev); 1305 } 1306 } 1307 1308 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1309 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1310 1311 if (!i2c_dev->dma_mode) { 1312 if (msg->flags & I2C_M_RD) 1313 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1314 else if (i2c_dev->msg_buf_remaining) 1315 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1316 } 1317 1318 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1319 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1320 i2c_readl(i2c_dev, I2C_INT_MASK)); 1321 1322 if (i2c_dev->dma_mode) { 1323 time_left = tegra_i2c_wait_completion(i2c_dev, 1324 &i2c_dev->dma_complete, 1325 xfer_time); 1326 1327 /* 1328 * Synchronize DMA first, since dmaengine_terminate_sync() 1329 * performs synchronization after the transfer's termination 1330 * and we want to get a completion if transfer succeeded. 1331 */ 1332 dmaengine_synchronize(i2c_dev->msg_read ? 1333 i2c_dev->rx_dma_chan : 1334 i2c_dev->tx_dma_chan); 1335 1336 dmaengine_terminate_sync(i2c_dev->msg_read ? 1337 i2c_dev->rx_dma_chan : 1338 i2c_dev->tx_dma_chan); 1339 1340 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1341 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); 1342 tegra_i2c_init(i2c_dev); 1343 return -ETIMEDOUT; 1344 } 1345 1346 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1347 dma_sync_single_for_cpu(i2c_dev->dev, 1348 i2c_dev->dma_phys, 1349 xfer_size, DMA_FROM_DEVICE); 1350 1351 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len); 1352 } 1353 } 1354 1355 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 1356 xfer_time); 1357 1358 tegra_i2c_mask_irq(i2c_dev, int_mask); 1359 1360 if (time_left == 0) { 1361 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); 1362 tegra_i2c_init(i2c_dev); 1363 return -ETIMEDOUT; 1364 } 1365 1366 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1367 time_left, completion_done(&i2c_dev->msg_complete), 1368 i2c_dev->msg_err); 1369 1370 i2c_dev->dma_mode = false; 1371 1372 err = tegra_i2c_error_recover(i2c_dev, msg); 1373 if (err) 1374 return err; 1375 1376 return 0; 1377 } 1378 1379 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1380 int num) 1381 { 1382 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1383 int i, ret; 1384 1385 ret = pm_runtime_get_sync(i2c_dev->dev); 1386 if (ret < 0) { 1387 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1388 pm_runtime_put_noidle(i2c_dev->dev); 1389 return ret; 1390 } 1391 1392 for (i = 0; i < num; i++) { 1393 enum msg_end_type end_type = MSG_END_STOP; 1394 1395 if (i < (num - 1)) { 1396 /* check whether follow up message is coming */ 1397 if (msgs[i + 1].flags & I2C_M_NOSTART) 1398 end_type = MSG_END_CONTINUE; 1399 else 1400 end_type = MSG_END_REPEAT_START; 1401 } 1402 /* If M_RECV_LEN use ContinueXfer to read the first byte */ 1403 if (msgs[i].flags & I2C_M_RECV_LEN) { 1404 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE); 1405 if (ret) 1406 break; 1407 /* Set the read byte as msg len */ 1408 msgs[i].len = msgs[i].buf[0]; 1409 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); 1410 } 1411 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1412 if (ret) 1413 break; 1414 } 1415 1416 pm_runtime_put(i2c_dev->dev); 1417 1418 return ret ?: i; 1419 } 1420 1421 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1422 struct i2c_msg msgs[], int num) 1423 { 1424 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1425 int ret; 1426 1427 i2c_dev->atomic_mode = true; 1428 ret = tegra_i2c_xfer(adap, msgs, num); 1429 i2c_dev->atomic_mode = false; 1430 1431 return ret; 1432 } 1433 1434 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1435 { 1436 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1437 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1438 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1439 1440 if (i2c_dev->hw->has_continue_xfer_support) 1441 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1442 1443 return ret; 1444 } 1445 1446 static const struct i2c_algorithm tegra_i2c_algo = { 1447 .master_xfer = tegra_i2c_xfer, 1448 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1449 .functionality = tegra_i2c_func, 1450 }; 1451 1452 /* payload size is only 12 bit */ 1453 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1454 .flags = I2C_AQ_NO_ZERO_LEN, 1455 .max_read_len = SZ_4K, 1456 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1457 }; 1458 1459 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1460 .flags = I2C_AQ_NO_ZERO_LEN, 1461 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1462 }; 1463 1464 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1465 .recover_bus = tegra_i2c_issue_bus_clear, 1466 }; 1467 1468 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1469 .has_continue_xfer_support = false, 1470 .has_per_pkt_xfer_complete_irq = false, 1471 .clk_divisor_hs_mode = 3, 1472 .clk_divisor_std_mode = 0, 1473 .clk_divisor_fast_mode = 0, 1474 .clk_divisor_fast_plus_mode = 0, 1475 .has_config_load_reg = false, 1476 .has_multi_master_mode = false, 1477 .has_slcg_override_reg = false, 1478 .has_mst_fifo = false, 1479 .quirks = &tegra_i2c_quirks, 1480 .supports_bus_clear = false, 1481 .has_apb_dma = true, 1482 .tlow_std_mode = 0x4, 1483 .thigh_std_mode = 0x2, 1484 .tlow_fast_fastplus_mode = 0x4, 1485 .thigh_fast_fastplus_mode = 0x2, 1486 .setup_hold_time_std_mode = 0x0, 1487 .setup_hold_time_fast_fast_plus_mode = 0x0, 1488 .setup_hold_time_hs_mode = 0x0, 1489 .has_interface_timing_reg = false, 1490 }; 1491 1492 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1493 .has_continue_xfer_support = true, 1494 .has_per_pkt_xfer_complete_irq = false, 1495 .clk_divisor_hs_mode = 3, 1496 .clk_divisor_std_mode = 0, 1497 .clk_divisor_fast_mode = 0, 1498 .clk_divisor_fast_plus_mode = 0, 1499 .has_config_load_reg = false, 1500 .has_multi_master_mode = false, 1501 .has_slcg_override_reg = false, 1502 .has_mst_fifo = false, 1503 .quirks = &tegra_i2c_quirks, 1504 .supports_bus_clear = false, 1505 .has_apb_dma = true, 1506 .tlow_std_mode = 0x4, 1507 .thigh_std_mode = 0x2, 1508 .tlow_fast_fastplus_mode = 0x4, 1509 .thigh_fast_fastplus_mode = 0x2, 1510 .setup_hold_time_std_mode = 0x0, 1511 .setup_hold_time_fast_fast_plus_mode = 0x0, 1512 .setup_hold_time_hs_mode = 0x0, 1513 .has_interface_timing_reg = false, 1514 }; 1515 1516 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1517 .has_continue_xfer_support = true, 1518 .has_per_pkt_xfer_complete_irq = true, 1519 .clk_divisor_hs_mode = 1, 1520 .clk_divisor_std_mode = 0x19, 1521 .clk_divisor_fast_mode = 0x19, 1522 .clk_divisor_fast_plus_mode = 0x10, 1523 .has_config_load_reg = false, 1524 .has_multi_master_mode = false, 1525 .has_slcg_override_reg = false, 1526 .has_mst_fifo = false, 1527 .quirks = &tegra_i2c_quirks, 1528 .supports_bus_clear = true, 1529 .has_apb_dma = true, 1530 .tlow_std_mode = 0x4, 1531 .thigh_std_mode = 0x2, 1532 .tlow_fast_fastplus_mode = 0x4, 1533 .thigh_fast_fastplus_mode = 0x2, 1534 .setup_hold_time_std_mode = 0x0, 1535 .setup_hold_time_fast_fast_plus_mode = 0x0, 1536 .setup_hold_time_hs_mode = 0x0, 1537 .has_interface_timing_reg = false, 1538 }; 1539 1540 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1541 .has_continue_xfer_support = true, 1542 .has_per_pkt_xfer_complete_irq = true, 1543 .clk_divisor_hs_mode = 1, 1544 .clk_divisor_std_mode = 0x19, 1545 .clk_divisor_fast_mode = 0x19, 1546 .clk_divisor_fast_plus_mode = 0x10, 1547 .has_config_load_reg = true, 1548 .has_multi_master_mode = false, 1549 .has_slcg_override_reg = true, 1550 .has_mst_fifo = false, 1551 .quirks = &tegra_i2c_quirks, 1552 .supports_bus_clear = true, 1553 .has_apb_dma = true, 1554 .tlow_std_mode = 0x4, 1555 .thigh_std_mode = 0x2, 1556 .tlow_fast_fastplus_mode = 0x4, 1557 .thigh_fast_fastplus_mode = 0x2, 1558 .setup_hold_time_std_mode = 0x0, 1559 .setup_hold_time_fast_fast_plus_mode = 0x0, 1560 .setup_hold_time_hs_mode = 0x0, 1561 .has_interface_timing_reg = true, 1562 }; 1563 1564 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1565 .has_continue_xfer_support = true, 1566 .has_per_pkt_xfer_complete_irq = true, 1567 .clk_divisor_hs_mode = 1, 1568 .clk_divisor_std_mode = 0x19, 1569 .clk_divisor_fast_mode = 0x19, 1570 .clk_divisor_fast_plus_mode = 0x10, 1571 .has_config_load_reg = true, 1572 .has_multi_master_mode = false, 1573 .has_slcg_override_reg = true, 1574 .has_mst_fifo = false, 1575 .quirks = &tegra_i2c_quirks, 1576 .supports_bus_clear = true, 1577 .has_apb_dma = true, 1578 .tlow_std_mode = 0x4, 1579 .thigh_std_mode = 0x2, 1580 .tlow_fast_fastplus_mode = 0x4, 1581 .thigh_fast_fastplus_mode = 0x2, 1582 .setup_hold_time_std_mode = 0, 1583 .setup_hold_time_fast_fast_plus_mode = 0, 1584 .setup_hold_time_hs_mode = 0, 1585 .has_interface_timing_reg = true, 1586 }; 1587 1588 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1589 .has_continue_xfer_support = true, 1590 .has_per_pkt_xfer_complete_irq = true, 1591 .clk_divisor_hs_mode = 1, 1592 .clk_divisor_std_mode = 0x16, 1593 .clk_divisor_fast_mode = 0x19, 1594 .clk_divisor_fast_plus_mode = 0x10, 1595 .has_config_load_reg = true, 1596 .has_multi_master_mode = false, 1597 .has_slcg_override_reg = true, 1598 .has_mst_fifo = false, 1599 .quirks = &tegra_i2c_quirks, 1600 .supports_bus_clear = true, 1601 .has_apb_dma = false, 1602 .tlow_std_mode = 0x4, 1603 .thigh_std_mode = 0x3, 1604 .tlow_fast_fastplus_mode = 0x4, 1605 .thigh_fast_fastplus_mode = 0x2, 1606 .setup_hold_time_std_mode = 0, 1607 .setup_hold_time_fast_fast_plus_mode = 0, 1608 .setup_hold_time_hs_mode = 0, 1609 .has_interface_timing_reg = true, 1610 }; 1611 1612 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1613 .has_continue_xfer_support = true, 1614 .has_per_pkt_xfer_complete_irq = true, 1615 .clk_divisor_hs_mode = 1, 1616 .clk_divisor_std_mode = 0x4f, 1617 .clk_divisor_fast_mode = 0x3c, 1618 .clk_divisor_fast_plus_mode = 0x16, 1619 .has_config_load_reg = true, 1620 .has_multi_master_mode = true, 1621 .has_slcg_override_reg = true, 1622 .has_mst_fifo = true, 1623 .quirks = &tegra194_i2c_quirks, 1624 .supports_bus_clear = true, 1625 .has_apb_dma = false, 1626 .tlow_std_mode = 0x8, 1627 .thigh_std_mode = 0x7, 1628 .tlow_fast_fastplus_mode = 0x2, 1629 .thigh_fast_fastplus_mode = 0x2, 1630 .setup_hold_time_std_mode = 0x08080808, 1631 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1632 .setup_hold_time_hs_mode = 0x090909, 1633 .has_interface_timing_reg = true, 1634 }; 1635 1636 static const struct of_device_id tegra_i2c_of_match[] = { 1637 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1638 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1639 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1640 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1641 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1642 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1643 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1644 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1645 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1646 {}, 1647 }; 1648 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1649 1650 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1651 { 1652 struct device_node *np = i2c_dev->dev->of_node; 1653 bool multi_mode; 1654 1655 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); 1656 1657 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); 1658 i2c_dev->multimaster_mode = multi_mode; 1659 1660 if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 1661 i2c_dev->is_dvc = true; 1662 1663 if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 1664 i2c_dev->is_vi = true; 1665 } 1666 1667 static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) 1668 { 1669 if (ACPI_HANDLE(i2c_dev->dev)) 1670 return 0; 1671 1672 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); 1673 if (IS_ERR(i2c_dev->rst)) 1674 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), 1675 "failed to get reset control\n"); 1676 1677 return 0; 1678 } 1679 1680 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) 1681 { 1682 int err; 1683 1684 if (ACPI_HANDLE(i2c_dev->dev)) 1685 return 0; 1686 1687 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; 1688 1689 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) 1690 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; 1691 1692 if (i2c_dev->is_vi) 1693 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; 1694 1695 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, 1696 i2c_dev->clocks); 1697 if (err) 1698 return err; 1699 1700 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); 1701 if (err) 1702 return err; 1703 1704 i2c_dev->div_clk = i2c_dev->clocks[0].clk; 1705 1706 if (!i2c_dev->multimaster_mode) 1707 return 0; 1708 1709 err = clk_enable(i2c_dev->div_clk); 1710 if (err) { 1711 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); 1712 goto unprepare_clocks; 1713 } 1714 1715 return 0; 1716 1717 unprepare_clocks: 1718 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1719 1720 return err; 1721 } 1722 1723 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev) 1724 { 1725 if (i2c_dev->multimaster_mode) 1726 clk_disable(i2c_dev->div_clk); 1727 1728 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1729 } 1730 1731 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev) 1732 { 1733 int ret; 1734 1735 ret = pm_runtime_get_sync(i2c_dev->dev); 1736 if (ret < 0) 1737 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); 1738 else 1739 ret = tegra_i2c_init(i2c_dev); 1740 1741 pm_runtime_put_sync(i2c_dev->dev); 1742 1743 return ret; 1744 } 1745 1746 static int tegra_i2c_probe(struct platform_device *pdev) 1747 { 1748 struct tegra_i2c_dev *i2c_dev; 1749 struct resource *res; 1750 int err; 1751 1752 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1753 if (!i2c_dev) 1754 return -ENOMEM; 1755 1756 platform_set_drvdata(pdev, i2c_dev); 1757 1758 init_completion(&i2c_dev->msg_complete); 1759 init_completion(&i2c_dev->dma_complete); 1760 1761 i2c_dev->hw = device_get_match_data(&pdev->dev); 1762 i2c_dev->cont_id = pdev->id; 1763 i2c_dev->dev = &pdev->dev; 1764 1765 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1766 if (IS_ERR(i2c_dev->base)) 1767 return PTR_ERR(i2c_dev->base); 1768 1769 i2c_dev->base_phys = res->start; 1770 1771 err = platform_get_irq(pdev, 0); 1772 if (err < 0) 1773 return err; 1774 1775 i2c_dev->irq = err; 1776 1777 /* interrupt will be enabled during of transfer time */ 1778 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1779 1780 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, 1781 NULL, tegra_i2c_isr, 1782 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1783 dev_name(i2c_dev->dev), i2c_dev); 1784 if (err) 1785 return err; 1786 1787 tegra_i2c_parse_dt(i2c_dev); 1788 1789 err = tegra_i2c_init_reset(i2c_dev); 1790 if (err) 1791 return err; 1792 1793 err = tegra_i2c_init_clocks(i2c_dev); 1794 if (err) 1795 return err; 1796 1797 err = tegra_i2c_init_dma(i2c_dev); 1798 if (err) 1799 goto release_clocks; 1800 1801 /* 1802 * VI I2C is in VE power domain which is not always ON and not 1803 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a 1804 * non IRQ-safe domain because this prevents powering off the power 1805 * domain. 1806 * 1807 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't 1808 * be used for atomic transfers. 1809 */ 1810 if (!i2c_dev->is_vi) 1811 pm_runtime_irq_safe(i2c_dev->dev); 1812 1813 pm_runtime_enable(i2c_dev->dev); 1814 1815 err = tegra_i2c_init_hardware(i2c_dev); 1816 if (err) 1817 goto release_rpm; 1818 1819 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1820 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1821 i2c_dev->adapter.dev.parent = i2c_dev->dev; 1822 i2c_dev->adapter.retries = 1; 1823 i2c_dev->adapter.timeout = 6 * HZ; 1824 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1825 i2c_dev->adapter.owner = THIS_MODULE; 1826 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1827 i2c_dev->adapter.algo = &tegra_i2c_algo; 1828 i2c_dev->adapter.nr = pdev->id; 1829 1830 if (i2c_dev->hw->supports_bus_clear) 1831 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1832 1833 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1834 sizeof(i2c_dev->adapter.name)); 1835 1836 err = i2c_add_numbered_adapter(&i2c_dev->adapter); 1837 if (err) 1838 goto release_rpm; 1839 1840 return 0; 1841 1842 release_rpm: 1843 pm_runtime_disable(i2c_dev->dev); 1844 1845 tegra_i2c_release_dma(i2c_dev); 1846 release_clocks: 1847 tegra_i2c_release_clocks(i2c_dev); 1848 1849 return err; 1850 } 1851 1852 static int tegra_i2c_remove(struct platform_device *pdev) 1853 { 1854 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1855 1856 i2c_del_adapter(&i2c_dev->adapter); 1857 pm_runtime_force_suspend(i2c_dev->dev); 1858 1859 tegra_i2c_release_dma(i2c_dev); 1860 tegra_i2c_release_clocks(i2c_dev); 1861 1862 return 0; 1863 } 1864 1865 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 1866 { 1867 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1868 int err; 1869 1870 err = pinctrl_pm_select_default_state(dev); 1871 if (err) 1872 return err; 1873 1874 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); 1875 if (err) 1876 return err; 1877 1878 /* 1879 * VI I2C device is attached to VE power domain which goes through 1880 * power ON/OFF during runtime PM resume/suspend, meaning that 1881 * controller needs to be re-initialized after power ON. 1882 */ 1883 if (i2c_dev->is_vi) { 1884 err = tegra_i2c_init(i2c_dev); 1885 if (err) 1886 goto disable_clocks; 1887 } 1888 1889 return 0; 1890 1891 disable_clocks: 1892 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1893 1894 return err; 1895 } 1896 1897 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 1898 { 1899 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1900 1901 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1902 1903 return pinctrl_pm_select_idle_state(dev); 1904 } 1905 1906 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1907 { 1908 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1909 int err; 1910 1911 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1912 1913 if (!pm_runtime_status_suspended(dev)) { 1914 err = tegra_i2c_runtime_suspend(dev); 1915 if (err) 1916 return err; 1917 } 1918 1919 return 0; 1920 } 1921 1922 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1923 { 1924 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1925 int err; 1926 1927 /* 1928 * We need to ensure that clocks are enabled so that registers can be 1929 * restored in tegra_i2c_init(). 1930 */ 1931 err = tegra_i2c_runtime_resume(dev); 1932 if (err) 1933 return err; 1934 1935 err = tegra_i2c_init(i2c_dev); 1936 if (err) 1937 return err; 1938 1939 /* 1940 * In case we are runtime suspended, disable clocks again so that we 1941 * don't unbalance the clock reference counts during the next runtime 1942 * resume transition. 1943 */ 1944 if (pm_runtime_status_suspended(dev)) { 1945 err = tegra_i2c_runtime_suspend(dev); 1946 if (err) 1947 return err; 1948 } 1949 1950 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1951 1952 return 0; 1953 } 1954 1955 static const struct dev_pm_ops tegra_i2c_pm = { 1956 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1957 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1958 NULL) 1959 }; 1960 1961 static const struct acpi_device_id tegra_i2c_acpi_match[] = { 1962 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 1963 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 1964 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 1965 { } 1966 }; 1967 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); 1968 1969 static struct platform_driver tegra_i2c_driver = { 1970 .probe = tegra_i2c_probe, 1971 .remove = tegra_i2c_remove, 1972 .driver = { 1973 .name = "tegra-i2c", 1974 .of_match_table = tegra_i2c_of_match, 1975 .acpi_match_table = tegra_i2c_acpi_match, 1976 .pm = &tegra_i2c_pm, 1977 }, 1978 }; 1979 module_platform_driver(tegra_i2c_driver); 1980 1981 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver"); 1982 MODULE_AUTHOR("Colin Cross"); 1983 MODULE_LICENSE("GPL v2"); 1984