1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/err.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/kernel.h> 21 #include <linux/ktime.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 29 #define BYTES_PER_FIFO_WORD 4 30 31 #define I2C_CNFG 0x000 32 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 33 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 34 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 35 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 36 #define I2C_STATUS 0x01C 37 #define I2C_SL_CNFG 0x020 38 #define I2C_SL_CNFG_NACK BIT(1) 39 #define I2C_SL_CNFG_NEWSL BIT(2) 40 #define I2C_SL_ADDR1 0x02c 41 #define I2C_SL_ADDR2 0x030 42 #define I2C_TX_FIFO 0x050 43 #define I2C_RX_FIFO 0x054 44 #define I2C_PACKET_TRANSFER_STATUS 0x058 45 #define I2C_FIFO_CONTROL 0x05c 46 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 47 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 48 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 49 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 50 #define I2C_FIFO_STATUS 0x060 51 #define I2C_FIFO_STATUS_TX_MASK 0xF0 52 #define I2C_FIFO_STATUS_TX_SHIFT 4 53 #define I2C_FIFO_STATUS_RX_MASK 0x0F 54 #define I2C_FIFO_STATUS_RX_SHIFT 0 55 #define I2C_INT_MASK 0x064 56 #define I2C_INT_STATUS 0x068 57 #define I2C_INT_BUS_CLR_DONE BIT(11) 58 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 59 #define I2C_INT_NO_ACK BIT(3) 60 #define I2C_INT_ARBITRATION_LOST BIT(2) 61 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 62 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 63 #define I2C_CLK_DIVISOR 0x06c 64 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 65 66 #define DVC_CTRL_REG1 0x000 67 #define DVC_CTRL_REG1_INTR_EN BIT(10) 68 #define DVC_CTRL_REG3 0x008 69 #define DVC_CTRL_REG3_SW_PROG BIT(26) 70 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 71 #define DVC_STATUS 0x00c 72 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 73 74 #define I2C_ERR_NONE 0x00 75 #define I2C_ERR_NO_ACK BIT(0) 76 #define I2C_ERR_ARBITRATION_LOST BIT(1) 77 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 78 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 79 80 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 81 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 82 #define PACKET_HEADER0_CONT_ID_SHIFT 12 83 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4) 84 85 #define I2C_HEADER_CONT_ON_NAK BIT(21) 86 #define I2C_HEADER_READ BIT(19) 87 #define I2C_HEADER_10BIT_ADDR BIT(18) 88 #define I2C_HEADER_IE_ENABLE BIT(17) 89 #define I2C_HEADER_REPEAT_START BIT(16) 90 #define I2C_HEADER_CONTINUE_XFER BIT(15) 91 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 92 93 #define I2C_BUS_CLEAR_CNFG 0x084 94 #define I2C_BC_SCLK_THRESHOLD 9 95 #define I2C_BC_SCLK_THRESHOLD_SHIFT 16 96 #define I2C_BC_STOP_COND BIT(2) 97 #define I2C_BC_TERMINATE BIT(1) 98 #define I2C_BC_ENABLE BIT(0) 99 #define I2C_BUS_CLEAR_STATUS 0x088 100 #define I2C_BC_STATUS BIT(0) 101 102 #define I2C_CONFIG_LOAD 0x08C 103 #define I2C_MSTR_CONFIG_LOAD BIT(0) 104 105 #define I2C_CLKEN_OVERRIDE 0x090 106 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 107 108 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 109 110 #define I2C_MST_FIFO_CONTROL 0x0b4 111 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 112 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 113 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 114 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 115 116 #define I2C_MST_FIFO_STATUS 0x0b8 117 #define I2C_MST_FIFO_STATUS_RX_MASK 0xff 118 #define I2C_MST_FIFO_STATUS_RX_SHIFT 0 119 #define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000 120 #define I2C_MST_FIFO_STATUS_TX_SHIFT 16 121 122 #define I2C_INTERFACE_TIMING_0 0x94 123 #define I2C_THIGH_SHIFT 8 124 #define I2C_INTERFACE_TIMING_1 0x98 125 126 /* Packet header size in bytes */ 127 #define I2C_PACKET_HEADER_SIZE 12 128 129 /* 130 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 131 * avoid DMA overhead, otherwise external APB DMA controller will be used. 132 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 133 * I2C_PACKET_HEADER_SIZE. 134 */ 135 #define I2C_PIO_MODE_PREFERRED_LEN 32 136 137 /* 138 * msg_end_type: The bus control which need to be send at end of transfer. 139 * @MSG_END_STOP: Send stop pulse at end of transfer. 140 * @MSG_END_REPEAT_START: Send repeat start at end of transfer. 141 * @MSG_END_CONTINUE: The following on message is coming and so do not send 142 * stop or repeat start. 143 */ 144 enum msg_end_type { 145 MSG_END_STOP, 146 MSG_END_REPEAT_START, 147 MSG_END_CONTINUE, 148 }; 149 150 /** 151 * struct tegra_i2c_hw_feature : Different HW support on Tegra 152 * @has_continue_xfer_support: Continue transfer supports. 153 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 154 * complete interrupt per packet basis. 155 * @has_single_clk_source: The I2C controller has single clock source. Tegra30 156 * and earlier SoCs have two clock sources i.e. div-clk and 157 * fast-clk. 158 * @has_config_load_reg: Has the config load register to load the new 159 * configuration. 160 * @clk_divisor_hs_mode: Clock divisor in HS mode. 161 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 162 * applicable if there is no fast clock source i.e. single clock 163 * source. 164 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 165 * applicable if there is no fast clock source i.e. single clock 166 * source. 167 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 168 * applicable if there is no fast clock source (i.e. single 169 * clock source). 170 * @has_multi_master_mode: The I2C controller supports running in single-master 171 * or multi-master mode. 172 * @has_slcg_override_reg: The I2C controller supports a register that 173 * overrides the second level clock gating. 174 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 175 * provides additional features and allows for longer messages to 176 * be transferred in one go. 177 * @quirks: i2c adapter quirks for limiting write/read transfer size and not 178 * allowing 0 length transfers. 179 * @supports_bus_clear: Bus Clear support to recover from bus hang during 180 * SDA stuck low from device for some unknown reasons. 181 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 182 * @tlow_std_mode: Low period of the clock in standard mode. 183 * @thigh_std_mode: High period of the clock in standard mode. 184 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 185 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 186 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 187 * in standard mode. 188 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 189 * conditions in fast/fast-plus modes. 190 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 191 * in HS mode. 192 * @has_interface_timing_reg: Has interface timing register to program the tuned 193 * timing settings. 194 */ 195 struct tegra_i2c_hw_feature { 196 bool has_continue_xfer_support; 197 bool has_per_pkt_xfer_complete_irq; 198 bool has_single_clk_source; 199 bool has_config_load_reg; 200 int clk_divisor_hs_mode; 201 int clk_divisor_std_mode; 202 int clk_divisor_fast_mode; 203 u16 clk_divisor_fast_plus_mode; 204 bool has_multi_master_mode; 205 bool has_slcg_override_reg; 206 bool has_mst_fifo; 207 const struct i2c_adapter_quirks *quirks; 208 bool supports_bus_clear; 209 bool has_apb_dma; 210 u8 tlow_std_mode; 211 u8 thigh_std_mode; 212 u8 tlow_fast_fastplus_mode; 213 u8 thigh_fast_fastplus_mode; 214 u32 setup_hold_time_std_mode; 215 u32 setup_hold_time_fast_fast_plus_mode; 216 u32 setup_hold_time_hs_mode; 217 bool has_interface_timing_reg; 218 }; 219 220 /** 221 * struct tegra_i2c_dev - per device I2C context 222 * @dev: device reference for power management 223 * @hw: Tegra I2C HW feature 224 * @adapter: core I2C layer adapter information 225 * @div_clk: clock reference for div clock of I2C controller 226 * @fast_clk: clock reference for fast clock of I2C controller 227 * @rst: reset control for the I2C controller 228 * @base: ioremapped registers cookie 229 * @base_phys: physical base address of the I2C controller 230 * @cont_id: I2C controller ID, used for packet header 231 * @irq: IRQ number of transfer complete interrupt 232 * @is_dvc: identifies the DVC I2C controller, has a different register layout 233 * @msg_complete: transfer completion notifier 234 * @msg_err: error code for completed message 235 * @msg_buf: pointer to current message data 236 * @msg_buf_remaining: size of unsent data in the message buffer 237 * @msg_read: identifies read transfers 238 * @bus_clk_rate: current I2C bus clock rate 239 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes 240 * @is_multimaster_mode: track if I2C controller is in multi-master mode 241 * @tx_dma_chan: DMA transmit channel 242 * @rx_dma_chan: DMA receive channel 243 * @dma_phys: handle to DMA resources 244 * @dma_buf: pointer to allocated DMA buffer 245 * @dma_buf_size: DMA buffer size 246 * @is_curr_dma_xfer: indicates active DMA transfer 247 * @dma_complete: DMA completion notifier 248 * @is_curr_atomic_xfer: indicates active atomic transfer 249 */ 250 struct tegra_i2c_dev { 251 struct device *dev; 252 const struct tegra_i2c_hw_feature *hw; 253 struct i2c_adapter adapter; 254 struct clk *div_clk; 255 struct clk *fast_clk; 256 struct reset_control *rst; 257 void __iomem *base; 258 phys_addr_t base_phys; 259 int cont_id; 260 int irq; 261 int is_dvc; 262 struct completion msg_complete; 263 int msg_err; 264 u8 *msg_buf; 265 size_t msg_buf_remaining; 266 int msg_read; 267 u32 bus_clk_rate; 268 u16 clk_divisor_non_hs_mode; 269 bool is_multimaster_mode; 270 struct dma_chan *tx_dma_chan; 271 struct dma_chan *rx_dma_chan; 272 dma_addr_t dma_phys; 273 u32 *dma_buf; 274 unsigned int dma_buf_size; 275 bool is_curr_dma_xfer; 276 struct completion dma_complete; 277 bool is_curr_atomic_xfer; 278 }; 279 280 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 281 unsigned long reg) 282 { 283 writel_relaxed(val, i2c_dev->base + reg); 284 } 285 286 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 287 { 288 return readl_relaxed(i2c_dev->base + reg); 289 } 290 291 /* 292 * i2c_writel and i2c_readl will offset the register if necessary to talk 293 * to the I2C block inside the DVC block 294 */ 295 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 296 unsigned long reg) 297 { 298 if (i2c_dev->is_dvc) 299 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 300 return reg; 301 } 302 303 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 304 unsigned long reg) 305 { 306 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 307 308 /* Read back register to make sure that register writes completed */ 309 if (reg != I2C_TX_FIFO) 310 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 311 } 312 313 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 314 { 315 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 316 } 317 318 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 319 unsigned long reg, int len) 320 { 321 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 322 } 323 324 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 325 unsigned long reg, int len) 326 { 327 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 328 } 329 330 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 331 { 332 u32 int_mask; 333 334 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 335 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 336 } 337 338 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 339 { 340 u32 int_mask; 341 342 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 343 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 344 } 345 346 static void tegra_i2c_dma_complete(void *args) 347 { 348 struct tegra_i2c_dev *i2c_dev = args; 349 350 complete(&i2c_dev->dma_complete); 351 } 352 353 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 354 { 355 struct dma_async_tx_descriptor *dma_desc; 356 enum dma_transfer_direction dir; 357 struct dma_chan *chan; 358 359 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 360 reinit_completion(&i2c_dev->dma_complete); 361 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 362 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; 363 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, 364 len, dir, DMA_PREP_INTERRUPT | 365 DMA_CTRL_ACK); 366 if (!dma_desc) { 367 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n"); 368 return -EINVAL; 369 } 370 371 dma_desc->callback = tegra_i2c_dma_complete; 372 dma_desc->callback_param = i2c_dev; 373 dmaengine_submit(dma_desc); 374 dma_async_issue_pending(chan); 375 return 0; 376 } 377 378 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 379 { 380 if (i2c_dev->dma_buf) { 381 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 382 i2c_dev->dma_buf, i2c_dev->dma_phys); 383 i2c_dev->dma_buf = NULL; 384 } 385 386 if (i2c_dev->tx_dma_chan) { 387 dma_release_channel(i2c_dev->tx_dma_chan); 388 i2c_dev->tx_dma_chan = NULL; 389 } 390 391 if (i2c_dev->rx_dma_chan) { 392 dma_release_channel(i2c_dev->rx_dma_chan); 393 i2c_dev->rx_dma_chan = NULL; 394 } 395 } 396 397 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 398 { 399 struct dma_chan *chan; 400 u32 *dma_buf; 401 dma_addr_t dma_phys; 402 int err; 403 404 if (!i2c_dev->hw->has_apb_dma) 405 return 0; 406 407 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 408 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n"); 409 return 0; 410 } 411 412 chan = dma_request_chan(i2c_dev->dev, "rx"); 413 if (IS_ERR(chan)) { 414 err = PTR_ERR(chan); 415 goto err_out; 416 } 417 418 i2c_dev->rx_dma_chan = chan; 419 420 chan = dma_request_chan(i2c_dev->dev, "tx"); 421 if (IS_ERR(chan)) { 422 err = PTR_ERR(chan); 423 goto err_out; 424 } 425 426 i2c_dev->tx_dma_chan = chan; 427 428 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 429 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 430 if (!dma_buf) { 431 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n"); 432 err = -ENOMEM; 433 goto err_out; 434 } 435 436 i2c_dev->dma_buf = dma_buf; 437 i2c_dev->dma_phys = dma_phys; 438 return 0; 439 440 err_out: 441 tegra_i2c_release_dma(i2c_dev); 442 if (err != -EPROBE_DEFER) { 443 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 444 dev_err(i2c_dev->dev, "falling back to PIO\n"); 445 return 0; 446 } 447 448 return err; 449 } 450 451 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 452 { 453 unsigned long timeout = jiffies + HZ; 454 unsigned int offset; 455 u32 mask, val; 456 457 if (i2c_dev->hw->has_mst_fifo) { 458 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 459 I2C_MST_FIFO_CONTROL_RX_FLUSH; 460 offset = I2C_MST_FIFO_CONTROL; 461 } else { 462 mask = I2C_FIFO_CONTROL_TX_FLUSH | 463 I2C_FIFO_CONTROL_RX_FLUSH; 464 offset = I2C_FIFO_CONTROL; 465 } 466 467 val = i2c_readl(i2c_dev, offset); 468 val |= mask; 469 i2c_writel(i2c_dev, val, offset); 470 471 while (i2c_readl(i2c_dev, offset) & mask) { 472 if (time_after(jiffies, timeout)) { 473 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 474 return -ETIMEDOUT; 475 } 476 usleep_range(1000, 2000); 477 } 478 return 0; 479 } 480 481 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 482 { 483 u32 val; 484 int rx_fifo_avail; 485 u8 *buf = i2c_dev->msg_buf; 486 size_t buf_remaining = i2c_dev->msg_buf_remaining; 487 int words_to_transfer; 488 489 /* 490 * Catch overflow due to message fully sent 491 * before the check for RX FIFO availability. 492 */ 493 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 494 return -EINVAL; 495 496 if (i2c_dev->hw->has_mst_fifo) { 497 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 498 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >> 499 I2C_MST_FIFO_STATUS_RX_SHIFT; 500 } else { 501 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 502 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 503 I2C_FIFO_STATUS_RX_SHIFT; 504 } 505 506 /* Rounds down to not include partial word at the end of buf */ 507 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 508 if (words_to_transfer > rx_fifo_avail) 509 words_to_transfer = rx_fifo_avail; 510 511 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 512 513 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 514 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 515 rx_fifo_avail -= words_to_transfer; 516 517 /* 518 * If there is a partial word at the end of buf, handle it manually to 519 * prevent overwriting past the end of buf 520 */ 521 if (rx_fifo_avail > 0 && buf_remaining > 0) { 522 /* 523 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 524 * when (words_to_transfer was > rx_fifo_avail) earlier 525 * in this function. 526 */ 527 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 528 val = cpu_to_le32(val); 529 memcpy(buf, &val, buf_remaining); 530 buf_remaining = 0; 531 rx_fifo_avail--; 532 } 533 534 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 535 if (WARN_ON_ONCE(rx_fifo_avail)) 536 return -EINVAL; 537 538 i2c_dev->msg_buf_remaining = buf_remaining; 539 i2c_dev->msg_buf = buf; 540 541 return 0; 542 } 543 544 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 545 { 546 u32 val; 547 int tx_fifo_avail; 548 u8 *buf = i2c_dev->msg_buf; 549 size_t buf_remaining = i2c_dev->msg_buf_remaining; 550 int words_to_transfer; 551 552 if (i2c_dev->hw->has_mst_fifo) { 553 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 554 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >> 555 I2C_MST_FIFO_STATUS_TX_SHIFT; 556 } else { 557 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 558 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 559 I2C_FIFO_STATUS_TX_SHIFT; 560 } 561 562 /* Rounds down to not include partial word at the end of buf */ 563 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 564 565 /* It's very common to have < 4 bytes, so optimize that case. */ 566 if (words_to_transfer) { 567 if (words_to_transfer > tx_fifo_avail) 568 words_to_transfer = tx_fifo_avail; 569 570 /* 571 * Update state before writing to FIFO. If this casues us 572 * to finish writing all bytes (AKA buf_remaining goes to 0) we 573 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 574 * not maskable). We need to make sure that the isr sees 575 * buf_remaining as 0 and doesn't call us back re-entrantly. 576 */ 577 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 578 tx_fifo_avail -= words_to_transfer; 579 i2c_dev->msg_buf_remaining = buf_remaining; 580 i2c_dev->msg_buf = buf + 581 words_to_transfer * BYTES_PER_FIFO_WORD; 582 barrier(); 583 584 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 585 586 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 587 } 588 589 /* 590 * If there is a partial word at the end of buf, handle it manually to 591 * prevent reading past the end of buf, which could cross a page 592 * boundary and fault. 593 */ 594 if (tx_fifo_avail > 0 && buf_remaining > 0) { 595 /* 596 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 597 * when (words_to_transfer was > tx_fifo_avail) earlier 598 * in this function for non-zero words_to_transfer. 599 */ 600 memcpy(&val, buf, buf_remaining); 601 val = le32_to_cpu(val); 602 603 /* Again update before writing to FIFO to make sure isr sees. */ 604 i2c_dev->msg_buf_remaining = 0; 605 i2c_dev->msg_buf = NULL; 606 barrier(); 607 608 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 609 } 610 611 return 0; 612 } 613 614 /* 615 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 616 * block. This block is identical to the rest of the I2C blocks, except that 617 * it only supports master mode, it has registers moved around, and it needs 618 * some extra init to get it into I2C mode. The register moves are handled 619 * by i2c_readl and i2c_writel 620 */ 621 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 622 { 623 u32 val; 624 625 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 626 val |= DVC_CTRL_REG3_SW_PROG; 627 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 628 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 629 630 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 631 val |= DVC_CTRL_REG1_INTR_EN; 632 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 633 } 634 635 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 636 { 637 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 638 int ret; 639 640 ret = pinctrl_pm_select_default_state(i2c_dev->dev); 641 if (ret) 642 return ret; 643 644 if (!i2c_dev->hw->has_single_clk_source) { 645 ret = clk_enable(i2c_dev->fast_clk); 646 if (ret < 0) { 647 dev_err(i2c_dev->dev, 648 "Enabling fast clk failed, err %d\n", ret); 649 return ret; 650 } 651 } 652 653 ret = clk_enable(i2c_dev->div_clk); 654 if (ret < 0) { 655 dev_err(i2c_dev->dev, 656 "Enabling div clk failed, err %d\n", ret); 657 clk_disable(i2c_dev->fast_clk); 658 return ret; 659 } 660 661 return 0; 662 } 663 664 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 665 { 666 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 667 668 clk_disable(i2c_dev->div_clk); 669 if (!i2c_dev->hw->has_single_clk_source) 670 clk_disable(i2c_dev->fast_clk); 671 672 return pinctrl_pm_select_idle_state(i2c_dev->dev); 673 } 674 675 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 676 { 677 unsigned long reg_offset; 678 void __iomem *addr; 679 u32 val; 680 int err; 681 682 if (i2c_dev->hw->has_config_load_reg) { 683 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); 684 addr = i2c_dev->base + reg_offset; 685 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 686 687 if (i2c_dev->is_curr_atomic_xfer) 688 err = readl_relaxed_poll_timeout_atomic( 689 addr, val, val == 0, 1000, 690 I2C_CONFIG_LOAD_TIMEOUT); 691 else 692 err = readl_relaxed_poll_timeout( 693 addr, val, val == 0, 1000, 694 I2C_CONFIG_LOAD_TIMEOUT); 695 696 if (err) { 697 dev_warn(i2c_dev->dev, 698 "timeout waiting for config load\n"); 699 return err; 700 } 701 } 702 703 return 0; 704 } 705 706 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit) 707 { 708 u32 val; 709 int err; 710 u32 clk_divisor, clk_multiplier; 711 u32 tsu_thd; 712 u8 tlow, thigh; 713 714 reset_control_assert(i2c_dev->rst); 715 udelay(2); 716 reset_control_deassert(i2c_dev->rst); 717 718 if (i2c_dev->is_dvc) 719 tegra_dvc_init(i2c_dev); 720 721 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 722 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 723 724 if (i2c_dev->hw->has_multi_master_mode) 725 val |= I2C_CNFG_MULTI_MASTER_MODE; 726 727 i2c_writel(i2c_dev, val, I2C_CNFG); 728 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 729 730 /* Make sure clock divisor programmed correctly */ 731 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; 732 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << 733 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; 734 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 735 736 if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ && 737 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ) { 738 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 739 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 740 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 741 } else { 742 tlow = i2c_dev->hw->tlow_std_mode; 743 thigh = i2c_dev->hw->thigh_std_mode; 744 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 745 } 746 747 if (i2c_dev->hw->has_interface_timing_reg) { 748 val = (thigh << I2C_THIGH_SHIFT) | tlow; 749 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 750 } 751 752 /* 753 * configure setup and hold times only when tsu_thd is non-zero. 754 * otherwise, preserve the chip default values 755 */ 756 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 757 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 758 759 if (!clk_reinit) { 760 clk_multiplier = (tlow + thigh + 2); 761 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); 762 err = clk_set_rate(i2c_dev->div_clk, 763 i2c_dev->bus_clk_rate * clk_multiplier); 764 if (err) { 765 dev_err(i2c_dev->dev, 766 "failed changing clock rate: %d\n", err); 767 return err; 768 } 769 } 770 771 if (!i2c_dev->is_dvc) { 772 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 773 774 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 775 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 776 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 777 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 778 } 779 780 err = tegra_i2c_flush_fifos(i2c_dev); 781 if (err) 782 return err; 783 784 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 785 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 786 787 err = tegra_i2c_wait_for_config_load(i2c_dev); 788 if (err) 789 return err; 790 791 return 0; 792 } 793 794 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 795 { 796 u32 cnfg; 797 798 /* 799 * NACK interrupt is generated before the I2C controller generates 800 * the STOP condition on the bus. So wait for 2 clock periods 801 * before disabling the controller so that the STOP condition has 802 * been delivered properly. 803 */ 804 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 805 806 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 807 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 808 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 809 810 return tegra_i2c_wait_for_config_load(i2c_dev); 811 } 812 813 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 814 { 815 u32 status; 816 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 817 struct tegra_i2c_dev *i2c_dev = dev_id; 818 819 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 820 821 if (status == 0) { 822 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 823 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 824 i2c_readl(i2c_dev, I2C_STATUS), 825 i2c_readl(i2c_dev, I2C_CNFG)); 826 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 827 goto err; 828 } 829 830 if (unlikely(status & status_err)) { 831 tegra_i2c_disable_packet_mode(i2c_dev); 832 if (status & I2C_INT_NO_ACK) 833 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 834 if (status & I2C_INT_ARBITRATION_LOST) 835 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 836 goto err; 837 } 838 839 /* 840 * I2C transfer is terminated during the bus clear so skip 841 * processing the other interrupts. 842 */ 843 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 844 goto err; 845 846 if (!i2c_dev->is_curr_dma_xfer) { 847 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 848 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 849 /* 850 * Overflow error condition: message fully sent, 851 * with no XFER_COMPLETE interrupt but hardware 852 * asks to transfer more. 853 */ 854 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 855 goto err; 856 } 857 } 858 859 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 860 if (i2c_dev->msg_buf_remaining) 861 tegra_i2c_fill_tx_fifo(i2c_dev); 862 else 863 tegra_i2c_mask_irq(i2c_dev, 864 I2C_INT_TX_FIFO_DATA_REQ); 865 } 866 } 867 868 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 869 if (i2c_dev->is_dvc) 870 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 871 872 /* 873 * During message read XFER_COMPLETE interrupt is triggered prior to 874 * DMA completion and during message write XFER_COMPLETE interrupt is 875 * triggered after DMA completion. 876 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer. 877 * so forcing msg_buf_remaining to 0 in DMA mode. 878 */ 879 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 880 if (i2c_dev->is_curr_dma_xfer) 881 i2c_dev->msg_buf_remaining = 0; 882 /* 883 * Underflow error condition: XFER_COMPLETE before message 884 * fully sent. 885 */ 886 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 887 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 888 goto err; 889 } 890 complete(&i2c_dev->msg_complete); 891 } 892 goto done; 893 err: 894 /* An error occurred, mask all interrupts */ 895 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 896 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 897 I2C_INT_RX_FIFO_DATA_REQ); 898 if (i2c_dev->hw->supports_bus_clear) 899 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 900 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 901 if (i2c_dev->is_dvc) 902 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 903 904 if (i2c_dev->is_curr_dma_xfer) { 905 if (i2c_dev->msg_read) 906 dmaengine_terminate_async(i2c_dev->rx_dma_chan); 907 else 908 dmaengine_terminate_async(i2c_dev->tx_dma_chan); 909 910 complete(&i2c_dev->dma_complete); 911 } 912 913 complete(&i2c_dev->msg_complete); 914 done: 915 return IRQ_HANDLED; 916 } 917 918 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 919 size_t len) 920 { 921 u32 val, reg; 922 u8 dma_burst; 923 struct dma_slave_config slv_config = {0}; 924 struct dma_chan *chan; 925 int ret; 926 unsigned long reg_offset; 927 928 if (i2c_dev->hw->has_mst_fifo) 929 reg = I2C_MST_FIFO_CONTROL; 930 else 931 reg = I2C_FIFO_CONTROL; 932 933 if (i2c_dev->is_curr_dma_xfer) { 934 if (len & 0xF) 935 dma_burst = 1; 936 else if (len & 0x10) 937 dma_burst = 4; 938 else 939 dma_burst = 8; 940 941 if (i2c_dev->msg_read) { 942 chan = i2c_dev->rx_dma_chan; 943 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 944 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 945 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 946 slv_config.src_maxburst = dma_burst; 947 948 if (i2c_dev->hw->has_mst_fifo) 949 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 950 else 951 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 952 } else { 953 chan = i2c_dev->tx_dma_chan; 954 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 955 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 956 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 957 slv_config.dst_maxburst = dma_burst; 958 959 if (i2c_dev->hw->has_mst_fifo) 960 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 961 else 962 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 963 } 964 965 slv_config.device_fc = true; 966 ret = dmaengine_slave_config(chan, &slv_config); 967 if (ret < 0) { 968 dev_err(i2c_dev->dev, "DMA slave config failed: %d\n", 969 ret); 970 dev_err(i2c_dev->dev, "falling back to PIO\n"); 971 tegra_i2c_release_dma(i2c_dev); 972 i2c_dev->is_curr_dma_xfer = false; 973 } else { 974 goto out; 975 } 976 } 977 978 if (i2c_dev->hw->has_mst_fifo) 979 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 980 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 981 else 982 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 983 I2C_FIFO_CONTROL_RX_TRIG(1); 984 out: 985 i2c_writel(i2c_dev, val, reg); 986 } 987 988 static unsigned long 989 tegra_i2c_poll_completion_timeout(struct tegra_i2c_dev *i2c_dev, 990 struct completion *complete, 991 unsigned int timeout_ms) 992 { 993 ktime_t ktime = ktime_get(); 994 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 995 996 do { 997 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 998 999 if (status) 1000 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1001 1002 if (completion_done(complete)) { 1003 s64 delta = ktime_ms_delta(ktimeout, ktime); 1004 1005 return msecs_to_jiffies(delta) ?: 1; 1006 } 1007 1008 ktime = ktime_get(); 1009 1010 } while (ktime_before(ktime, ktimeout)); 1011 1012 return 0; 1013 } 1014 1015 static unsigned long 1016 tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev *i2c_dev, 1017 struct completion *complete, 1018 unsigned int timeout_ms) 1019 { 1020 unsigned long ret; 1021 1022 if (i2c_dev->is_curr_atomic_xfer) { 1023 ret = tegra_i2c_poll_completion_timeout(i2c_dev, complete, 1024 timeout_ms); 1025 } else { 1026 enable_irq(i2c_dev->irq); 1027 ret = wait_for_completion_timeout(complete, 1028 msecs_to_jiffies(timeout_ms)); 1029 disable_irq(i2c_dev->irq); 1030 1031 /* 1032 * Under some rare circumstances (like running KASAN + 1033 * NFS root) CPU, which handles interrupt, may stuck in 1034 * uninterruptible state for a significant time. In this 1035 * case we will get timeout if I2C transfer is running on 1036 * a sibling CPU, despite of IRQ being raised. 1037 * 1038 * In order to handle this rare condition, the IRQ status 1039 * needs to be checked after timeout. 1040 */ 1041 if (ret == 0) 1042 ret = tegra_i2c_poll_completion_timeout(i2c_dev, 1043 complete, 0); 1044 } 1045 1046 return ret; 1047 } 1048 1049 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1050 { 1051 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1052 int err; 1053 unsigned long time_left; 1054 u32 reg; 1055 1056 reinit_completion(&i2c_dev->msg_complete); 1057 reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) | 1058 I2C_BC_STOP_COND | I2C_BC_TERMINATE; 1059 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG); 1060 if (i2c_dev->hw->has_config_load_reg) { 1061 err = tegra_i2c_wait_for_config_load(i2c_dev); 1062 if (err) 1063 return err; 1064 } 1065 1066 reg |= I2C_BC_ENABLE; 1067 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG); 1068 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1069 1070 time_left = tegra_i2c_wait_completion_timeout( 1071 i2c_dev, &i2c_dev->msg_complete, 50); 1072 if (time_left == 0) { 1073 dev_err(i2c_dev->dev, "timed out for bus clear\n"); 1074 return -ETIMEDOUT; 1075 } 1076 1077 reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1078 if (!(reg & I2C_BC_STATUS)) { 1079 dev_err(i2c_dev->dev, 1080 "un-recovered arbitration lost\n"); 1081 return -EIO; 1082 } 1083 1084 return -EAGAIN; 1085 } 1086 1087 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1088 struct i2c_msg *msg, 1089 enum msg_end_type end_state) 1090 { 1091 u32 packet_header; 1092 u32 int_mask; 1093 unsigned long time_left; 1094 size_t xfer_size; 1095 u32 *buffer = NULL; 1096 int err = 0; 1097 bool dma; 1098 u16 xfer_time = 100; 1099 1100 tegra_i2c_flush_fifos(i2c_dev); 1101 1102 i2c_dev->msg_buf = msg->buf; 1103 i2c_dev->msg_buf_remaining = msg->len; 1104 i2c_dev->msg_err = I2C_ERR_NONE; 1105 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 1106 reinit_completion(&i2c_dev->msg_complete); 1107 1108 if (i2c_dev->msg_read) 1109 xfer_size = msg->len; 1110 else 1111 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; 1112 1113 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1114 i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_PREFERRED_LEN) && 1115 i2c_dev->dma_buf && 1116 !i2c_dev->is_curr_atomic_xfer; 1117 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1118 dma = i2c_dev->is_curr_dma_xfer; 1119 /* 1120 * Transfer time in mSec = Total bits / transfer rate 1121 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1122 */ 1123 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1124 i2c_dev->bus_clk_rate); 1125 1126 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1127 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1128 if (dma) { 1129 if (i2c_dev->msg_read) { 1130 dma_sync_single_for_device(i2c_dev->dev, 1131 i2c_dev->dma_phys, 1132 xfer_size, 1133 DMA_FROM_DEVICE); 1134 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1135 if (err < 0) { 1136 dev_err(i2c_dev->dev, 1137 "starting RX DMA failed, err %d\n", 1138 err); 1139 return err; 1140 } 1141 1142 } else { 1143 dma_sync_single_for_cpu(i2c_dev->dev, 1144 i2c_dev->dma_phys, 1145 xfer_size, 1146 DMA_TO_DEVICE); 1147 buffer = i2c_dev->dma_buf; 1148 } 1149 } 1150 1151 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 1152 PACKET_HEADER0_PROTOCOL_I2C | 1153 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 1154 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 1155 if (dma && !i2c_dev->msg_read) 1156 *buffer++ = packet_header; 1157 else 1158 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1159 1160 packet_header = msg->len - 1; 1161 if (dma && !i2c_dev->msg_read) 1162 *buffer++ = packet_header; 1163 else 1164 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1165 1166 packet_header = I2C_HEADER_IE_ENABLE; 1167 if (end_state == MSG_END_CONTINUE) 1168 packet_header |= I2C_HEADER_CONTINUE_XFER; 1169 else if (end_state == MSG_END_REPEAT_START) 1170 packet_header |= I2C_HEADER_REPEAT_START; 1171 if (msg->flags & I2C_M_TEN) { 1172 packet_header |= msg->addr; 1173 packet_header |= I2C_HEADER_10BIT_ADDR; 1174 } else { 1175 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1176 } 1177 if (msg->flags & I2C_M_IGNORE_NAK) 1178 packet_header |= I2C_HEADER_CONT_ON_NAK; 1179 if (msg->flags & I2C_M_RD) 1180 packet_header |= I2C_HEADER_READ; 1181 if (dma && !i2c_dev->msg_read) 1182 *buffer++ = packet_header; 1183 else 1184 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1185 1186 if (!i2c_dev->msg_read) { 1187 if (dma) { 1188 memcpy(buffer, msg->buf, msg->len); 1189 dma_sync_single_for_device(i2c_dev->dev, 1190 i2c_dev->dma_phys, 1191 xfer_size, 1192 DMA_TO_DEVICE); 1193 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1194 if (err < 0) { 1195 dev_err(i2c_dev->dev, 1196 "starting TX DMA failed, err %d\n", 1197 err); 1198 return err; 1199 } 1200 } else { 1201 tegra_i2c_fill_tx_fifo(i2c_dev); 1202 } 1203 } 1204 1205 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1206 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1207 if (!dma) { 1208 if (msg->flags & I2C_M_RD) 1209 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1210 else if (i2c_dev->msg_buf_remaining) 1211 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1212 } 1213 1214 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1215 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 1216 i2c_readl(i2c_dev, I2C_INT_MASK)); 1217 1218 if (dma) { 1219 time_left = tegra_i2c_wait_completion_timeout( 1220 i2c_dev, &i2c_dev->dma_complete, xfer_time); 1221 1222 /* 1223 * Synchronize DMA first, since dmaengine_terminate_sync() 1224 * performs synchronization after the transfer's termination 1225 * and we want to get a completion if transfer succeeded. 1226 */ 1227 dmaengine_synchronize(i2c_dev->msg_read ? 1228 i2c_dev->rx_dma_chan : 1229 i2c_dev->tx_dma_chan); 1230 1231 dmaengine_terminate_sync(i2c_dev->msg_read ? 1232 i2c_dev->rx_dma_chan : 1233 i2c_dev->tx_dma_chan); 1234 1235 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1236 dev_err(i2c_dev->dev, "DMA transfer timeout\n"); 1237 tegra_i2c_init(i2c_dev, true); 1238 return -ETIMEDOUT; 1239 } 1240 1241 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1242 dma_sync_single_for_cpu(i2c_dev->dev, 1243 i2c_dev->dma_phys, 1244 xfer_size, 1245 DMA_FROM_DEVICE); 1246 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, 1247 msg->len); 1248 } 1249 } 1250 1251 time_left = tegra_i2c_wait_completion_timeout( 1252 i2c_dev, &i2c_dev->msg_complete, xfer_time); 1253 1254 tegra_i2c_mask_irq(i2c_dev, int_mask); 1255 1256 if (time_left == 0) { 1257 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 1258 tegra_i2c_init(i2c_dev, true); 1259 return -ETIMEDOUT; 1260 } 1261 1262 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1263 time_left, completion_done(&i2c_dev->msg_complete), 1264 i2c_dev->msg_err); 1265 1266 i2c_dev->is_curr_dma_xfer = false; 1267 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 1268 return 0; 1269 1270 tegra_i2c_init(i2c_dev, true); 1271 /* start recovery upon arbitration loss in single master mode */ 1272 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1273 if (!i2c_dev->is_multimaster_mode) 1274 return i2c_recover_bus(&i2c_dev->adapter); 1275 return -EAGAIN; 1276 } 1277 1278 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1279 if (msg->flags & I2C_M_IGNORE_NAK) 1280 return 0; 1281 return -EREMOTEIO; 1282 } 1283 1284 return -EIO; 1285 } 1286 1287 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1288 int num) 1289 { 1290 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1291 int i; 1292 int ret; 1293 1294 ret = pm_runtime_get_sync(i2c_dev->dev); 1295 if (ret < 0) { 1296 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1297 return ret; 1298 } 1299 1300 for (i = 0; i < num; i++) { 1301 enum msg_end_type end_type = MSG_END_STOP; 1302 1303 if (i < (num - 1)) { 1304 if (msgs[i + 1].flags & I2C_M_NOSTART) 1305 end_type = MSG_END_CONTINUE; 1306 else 1307 end_type = MSG_END_REPEAT_START; 1308 } 1309 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1310 if (ret) 1311 break; 1312 } 1313 1314 pm_runtime_put(i2c_dev->dev); 1315 1316 return ret ?: i; 1317 } 1318 1319 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1320 struct i2c_msg msgs[], int num) 1321 { 1322 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1323 int ret; 1324 1325 i2c_dev->is_curr_atomic_xfer = true; 1326 ret = tegra_i2c_xfer(adap, msgs, num); 1327 i2c_dev->is_curr_atomic_xfer = false; 1328 1329 return ret; 1330 } 1331 1332 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1333 { 1334 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1335 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1336 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1337 1338 if (i2c_dev->hw->has_continue_xfer_support) 1339 ret |= I2C_FUNC_NOSTART; 1340 return ret; 1341 } 1342 1343 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1344 { 1345 struct device_node *np = i2c_dev->dev->of_node; 1346 int ret; 1347 bool multi_mode; 1348 1349 ret = of_property_read_u32(np, "clock-frequency", 1350 &i2c_dev->bus_clk_rate); 1351 if (ret) 1352 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */ 1353 1354 multi_mode = of_property_read_bool(np, "multi-master"); 1355 i2c_dev->is_multimaster_mode = multi_mode; 1356 } 1357 1358 static const struct i2c_algorithm tegra_i2c_algo = { 1359 .master_xfer = tegra_i2c_xfer, 1360 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1361 .functionality = tegra_i2c_func, 1362 }; 1363 1364 /* payload size is only 12 bit */ 1365 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1366 .flags = I2C_AQ_NO_ZERO_LEN, 1367 .max_read_len = SZ_4K, 1368 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1369 }; 1370 1371 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1372 .flags = I2C_AQ_NO_ZERO_LEN, 1373 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1374 }; 1375 1376 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1377 .recover_bus = tegra_i2c_issue_bus_clear, 1378 }; 1379 1380 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1381 .has_continue_xfer_support = false, 1382 .has_per_pkt_xfer_complete_irq = false, 1383 .has_single_clk_source = false, 1384 .clk_divisor_hs_mode = 3, 1385 .clk_divisor_std_mode = 0, 1386 .clk_divisor_fast_mode = 0, 1387 .clk_divisor_fast_plus_mode = 0, 1388 .has_config_load_reg = false, 1389 .has_multi_master_mode = false, 1390 .has_slcg_override_reg = false, 1391 .has_mst_fifo = false, 1392 .quirks = &tegra_i2c_quirks, 1393 .supports_bus_clear = false, 1394 .has_apb_dma = true, 1395 .tlow_std_mode = 0x4, 1396 .thigh_std_mode = 0x2, 1397 .tlow_fast_fastplus_mode = 0x4, 1398 .thigh_fast_fastplus_mode = 0x2, 1399 .setup_hold_time_std_mode = 0x0, 1400 .setup_hold_time_fast_fast_plus_mode = 0x0, 1401 .setup_hold_time_hs_mode = 0x0, 1402 .has_interface_timing_reg = false, 1403 }; 1404 1405 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1406 .has_continue_xfer_support = true, 1407 .has_per_pkt_xfer_complete_irq = false, 1408 .has_single_clk_source = false, 1409 .clk_divisor_hs_mode = 3, 1410 .clk_divisor_std_mode = 0, 1411 .clk_divisor_fast_mode = 0, 1412 .clk_divisor_fast_plus_mode = 0, 1413 .has_config_load_reg = false, 1414 .has_multi_master_mode = false, 1415 .has_slcg_override_reg = false, 1416 .has_mst_fifo = false, 1417 .quirks = &tegra_i2c_quirks, 1418 .supports_bus_clear = false, 1419 .has_apb_dma = true, 1420 .tlow_std_mode = 0x4, 1421 .thigh_std_mode = 0x2, 1422 .tlow_fast_fastplus_mode = 0x4, 1423 .thigh_fast_fastplus_mode = 0x2, 1424 .setup_hold_time_std_mode = 0x0, 1425 .setup_hold_time_fast_fast_plus_mode = 0x0, 1426 .setup_hold_time_hs_mode = 0x0, 1427 .has_interface_timing_reg = false, 1428 }; 1429 1430 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1431 .has_continue_xfer_support = true, 1432 .has_per_pkt_xfer_complete_irq = true, 1433 .has_single_clk_source = true, 1434 .clk_divisor_hs_mode = 1, 1435 .clk_divisor_std_mode = 0x19, 1436 .clk_divisor_fast_mode = 0x19, 1437 .clk_divisor_fast_plus_mode = 0x10, 1438 .has_config_load_reg = false, 1439 .has_multi_master_mode = false, 1440 .has_slcg_override_reg = false, 1441 .has_mst_fifo = false, 1442 .quirks = &tegra_i2c_quirks, 1443 .supports_bus_clear = true, 1444 .has_apb_dma = true, 1445 .tlow_std_mode = 0x4, 1446 .thigh_std_mode = 0x2, 1447 .tlow_fast_fastplus_mode = 0x4, 1448 .thigh_fast_fastplus_mode = 0x2, 1449 .setup_hold_time_std_mode = 0x0, 1450 .setup_hold_time_fast_fast_plus_mode = 0x0, 1451 .setup_hold_time_hs_mode = 0x0, 1452 .has_interface_timing_reg = false, 1453 }; 1454 1455 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1456 .has_continue_xfer_support = true, 1457 .has_per_pkt_xfer_complete_irq = true, 1458 .has_single_clk_source = true, 1459 .clk_divisor_hs_mode = 1, 1460 .clk_divisor_std_mode = 0x19, 1461 .clk_divisor_fast_mode = 0x19, 1462 .clk_divisor_fast_plus_mode = 0x10, 1463 .has_config_load_reg = true, 1464 .has_multi_master_mode = false, 1465 .has_slcg_override_reg = true, 1466 .has_mst_fifo = false, 1467 .quirks = &tegra_i2c_quirks, 1468 .supports_bus_clear = true, 1469 .has_apb_dma = true, 1470 .tlow_std_mode = 0x4, 1471 .thigh_std_mode = 0x2, 1472 .tlow_fast_fastplus_mode = 0x4, 1473 .thigh_fast_fastplus_mode = 0x2, 1474 .setup_hold_time_std_mode = 0x0, 1475 .setup_hold_time_fast_fast_plus_mode = 0x0, 1476 .setup_hold_time_hs_mode = 0x0, 1477 .has_interface_timing_reg = true, 1478 }; 1479 1480 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1481 .has_continue_xfer_support = true, 1482 .has_per_pkt_xfer_complete_irq = true, 1483 .has_single_clk_source = true, 1484 .clk_divisor_hs_mode = 1, 1485 .clk_divisor_std_mode = 0x19, 1486 .clk_divisor_fast_mode = 0x19, 1487 .clk_divisor_fast_plus_mode = 0x10, 1488 .has_config_load_reg = true, 1489 .has_multi_master_mode = false, 1490 .has_slcg_override_reg = true, 1491 .has_mst_fifo = false, 1492 .quirks = &tegra_i2c_quirks, 1493 .supports_bus_clear = true, 1494 .has_apb_dma = true, 1495 .tlow_std_mode = 0x4, 1496 .thigh_std_mode = 0x2, 1497 .tlow_fast_fastplus_mode = 0x4, 1498 .thigh_fast_fastplus_mode = 0x2, 1499 .setup_hold_time_std_mode = 0, 1500 .setup_hold_time_fast_fast_plus_mode = 0, 1501 .setup_hold_time_hs_mode = 0, 1502 .has_interface_timing_reg = true, 1503 }; 1504 1505 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1506 .has_continue_xfer_support = true, 1507 .has_per_pkt_xfer_complete_irq = true, 1508 .has_single_clk_source = true, 1509 .clk_divisor_hs_mode = 1, 1510 .clk_divisor_std_mode = 0x16, 1511 .clk_divisor_fast_mode = 0x19, 1512 .clk_divisor_fast_plus_mode = 0x10, 1513 .has_config_load_reg = true, 1514 .has_multi_master_mode = false, 1515 .has_slcg_override_reg = true, 1516 .has_mst_fifo = false, 1517 .quirks = &tegra_i2c_quirks, 1518 .supports_bus_clear = true, 1519 .has_apb_dma = false, 1520 .tlow_std_mode = 0x4, 1521 .thigh_std_mode = 0x3, 1522 .tlow_fast_fastplus_mode = 0x4, 1523 .thigh_fast_fastplus_mode = 0x2, 1524 .setup_hold_time_std_mode = 0, 1525 .setup_hold_time_fast_fast_plus_mode = 0, 1526 .setup_hold_time_hs_mode = 0, 1527 .has_interface_timing_reg = true, 1528 }; 1529 1530 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1531 .has_continue_xfer_support = true, 1532 .has_per_pkt_xfer_complete_irq = true, 1533 .has_single_clk_source = true, 1534 .clk_divisor_hs_mode = 1, 1535 .clk_divisor_std_mode = 0x4f, 1536 .clk_divisor_fast_mode = 0x3c, 1537 .clk_divisor_fast_plus_mode = 0x16, 1538 .has_config_load_reg = true, 1539 .has_multi_master_mode = true, 1540 .has_slcg_override_reg = true, 1541 .has_mst_fifo = true, 1542 .quirks = &tegra194_i2c_quirks, 1543 .supports_bus_clear = true, 1544 .has_apb_dma = false, 1545 .tlow_std_mode = 0x8, 1546 .thigh_std_mode = 0x7, 1547 .tlow_fast_fastplus_mode = 0x2, 1548 .thigh_fast_fastplus_mode = 0x2, 1549 .setup_hold_time_std_mode = 0x08080808, 1550 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1551 .setup_hold_time_hs_mode = 0x090909, 1552 .has_interface_timing_reg = true, 1553 }; 1554 1555 /* Match table for of_platform binding */ 1556 static const struct of_device_id tegra_i2c_of_match[] = { 1557 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1558 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1559 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1560 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1561 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1562 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1563 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1564 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1565 {}, 1566 }; 1567 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1568 1569 static int tegra_i2c_probe(struct platform_device *pdev) 1570 { 1571 struct tegra_i2c_dev *i2c_dev; 1572 struct resource *res; 1573 struct clk *div_clk; 1574 struct clk *fast_clk; 1575 void __iomem *base; 1576 phys_addr_t base_phys; 1577 int irq; 1578 int ret; 1579 1580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1581 base_phys = res->start; 1582 base = devm_ioremap_resource(&pdev->dev, res); 1583 if (IS_ERR(base)) 1584 return PTR_ERR(base); 1585 1586 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1587 if (!res) { 1588 dev_err(&pdev->dev, "no irq resource\n"); 1589 return -EINVAL; 1590 } 1591 irq = res->start; 1592 1593 div_clk = devm_clk_get(&pdev->dev, "div-clk"); 1594 if (IS_ERR(div_clk)) { 1595 if (PTR_ERR(div_clk) != -EPROBE_DEFER) 1596 dev_err(&pdev->dev, "missing controller clock\n"); 1597 1598 return PTR_ERR(div_clk); 1599 } 1600 1601 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1602 if (!i2c_dev) 1603 return -ENOMEM; 1604 1605 i2c_dev->base = base; 1606 i2c_dev->base_phys = base_phys; 1607 i2c_dev->div_clk = div_clk; 1608 i2c_dev->adapter.algo = &tegra_i2c_algo; 1609 i2c_dev->adapter.retries = 1; 1610 i2c_dev->adapter.timeout = 6 * HZ; 1611 i2c_dev->irq = irq; 1612 i2c_dev->cont_id = pdev->id; 1613 i2c_dev->dev = &pdev->dev; 1614 1615 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); 1616 if (IS_ERR(i2c_dev->rst)) { 1617 dev_err(&pdev->dev, "missing controller reset\n"); 1618 return PTR_ERR(i2c_dev->rst); 1619 } 1620 1621 tegra_i2c_parse_dt(i2c_dev); 1622 1623 i2c_dev->hw = of_device_get_match_data(&pdev->dev); 1624 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 1625 "nvidia,tegra20-i2c-dvc"); 1626 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1627 i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len + 1628 I2C_PACKET_HEADER_SIZE; 1629 init_completion(&i2c_dev->msg_complete); 1630 init_completion(&i2c_dev->dma_complete); 1631 1632 if (!i2c_dev->hw->has_single_clk_source) { 1633 fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); 1634 if (IS_ERR(fast_clk)) { 1635 dev_err(&pdev->dev, "missing fast clock\n"); 1636 return PTR_ERR(fast_clk); 1637 } 1638 i2c_dev->fast_clk = fast_clk; 1639 } 1640 1641 platform_set_drvdata(pdev, i2c_dev); 1642 1643 if (!i2c_dev->hw->has_single_clk_source) { 1644 ret = clk_prepare(i2c_dev->fast_clk); 1645 if (ret < 0) { 1646 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 1647 return ret; 1648 } 1649 } 1650 1651 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ && 1652 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ) 1653 i2c_dev->clk_divisor_non_hs_mode = 1654 i2c_dev->hw->clk_divisor_fast_plus_mode; 1655 else if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ && 1656 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ) 1657 i2c_dev->clk_divisor_non_hs_mode = 1658 i2c_dev->hw->clk_divisor_fast_mode; 1659 else 1660 i2c_dev->clk_divisor_non_hs_mode = 1661 i2c_dev->hw->clk_divisor_std_mode; 1662 1663 ret = clk_prepare(i2c_dev->div_clk); 1664 if (ret < 0) { 1665 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 1666 goto unprepare_fast_clk; 1667 } 1668 1669 pm_runtime_irq_safe(&pdev->dev); 1670 pm_runtime_enable(&pdev->dev); 1671 if (!pm_runtime_enabled(&pdev->dev)) { 1672 ret = tegra_i2c_runtime_resume(&pdev->dev); 1673 if (ret < 0) { 1674 dev_err(&pdev->dev, "runtime resume failed\n"); 1675 goto unprepare_div_clk; 1676 } 1677 } else { 1678 ret = pm_runtime_get_sync(i2c_dev->dev); 1679 if (ret < 0) { 1680 dev_err(&pdev->dev, "runtime resume failed\n"); 1681 goto disable_rpm; 1682 } 1683 } 1684 1685 if (i2c_dev->is_multimaster_mode) { 1686 ret = clk_enable(i2c_dev->div_clk); 1687 if (ret < 0) { 1688 dev_err(i2c_dev->dev, "div_clk enable failed %d\n", 1689 ret); 1690 goto put_rpm; 1691 } 1692 } 1693 1694 if (i2c_dev->hw->supports_bus_clear) 1695 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1696 1697 ret = tegra_i2c_init_dma(i2c_dev); 1698 if (ret < 0) 1699 goto disable_div_clk; 1700 1701 ret = tegra_i2c_init(i2c_dev, false); 1702 if (ret) { 1703 dev_err(&pdev->dev, "Failed to initialize i2c controller\n"); 1704 goto release_dma; 1705 } 1706 1707 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1708 1709 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 1710 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); 1711 if (ret) { 1712 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 1713 goto release_dma; 1714 } 1715 1716 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1717 i2c_dev->adapter.owner = THIS_MODULE; 1718 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1719 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev), 1720 sizeof(i2c_dev->adapter.name)); 1721 i2c_dev->adapter.dev.parent = &pdev->dev; 1722 i2c_dev->adapter.nr = pdev->id; 1723 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 1724 1725 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 1726 if (ret) 1727 goto release_dma; 1728 1729 pm_runtime_put(&pdev->dev); 1730 1731 return 0; 1732 1733 release_dma: 1734 tegra_i2c_release_dma(i2c_dev); 1735 1736 disable_div_clk: 1737 if (i2c_dev->is_multimaster_mode) 1738 clk_disable(i2c_dev->div_clk); 1739 1740 put_rpm: 1741 if (pm_runtime_enabled(&pdev->dev)) 1742 pm_runtime_put_sync(&pdev->dev); 1743 else 1744 tegra_i2c_runtime_suspend(&pdev->dev); 1745 1746 disable_rpm: 1747 if (pm_runtime_enabled(&pdev->dev)) 1748 pm_runtime_disable(&pdev->dev); 1749 1750 unprepare_div_clk: 1751 clk_unprepare(i2c_dev->div_clk); 1752 1753 unprepare_fast_clk: 1754 if (!i2c_dev->hw->has_single_clk_source) 1755 clk_unprepare(i2c_dev->fast_clk); 1756 1757 return ret; 1758 } 1759 1760 static int tegra_i2c_remove(struct platform_device *pdev) 1761 { 1762 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1763 1764 i2c_del_adapter(&i2c_dev->adapter); 1765 1766 if (i2c_dev->is_multimaster_mode) 1767 clk_disable(i2c_dev->div_clk); 1768 1769 pm_runtime_disable(&pdev->dev); 1770 if (!pm_runtime_status_suspended(&pdev->dev)) 1771 tegra_i2c_runtime_suspend(&pdev->dev); 1772 1773 clk_unprepare(i2c_dev->div_clk); 1774 if (!i2c_dev->hw->has_single_clk_source) 1775 clk_unprepare(i2c_dev->fast_clk); 1776 1777 tegra_i2c_release_dma(i2c_dev); 1778 return 0; 1779 } 1780 1781 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1782 { 1783 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1784 int err; 1785 1786 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1787 1788 err = pm_runtime_force_suspend(dev); 1789 if (err < 0) 1790 return err; 1791 1792 return 0; 1793 } 1794 1795 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1796 { 1797 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1798 int err; 1799 1800 err = tegra_i2c_runtime_resume(dev); 1801 if (err) 1802 return err; 1803 1804 err = tegra_i2c_init(i2c_dev, false); 1805 if (err) 1806 return err; 1807 1808 err = tegra_i2c_runtime_suspend(dev); 1809 if (err) 1810 return err; 1811 1812 err = pm_runtime_force_resume(dev); 1813 if (err < 0) 1814 return err; 1815 1816 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1817 1818 return 0; 1819 } 1820 1821 static const struct dev_pm_ops tegra_i2c_pm = { 1822 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1823 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1824 NULL) 1825 }; 1826 1827 static struct platform_driver tegra_i2c_driver = { 1828 .probe = tegra_i2c_probe, 1829 .remove = tegra_i2c_remove, 1830 .driver = { 1831 .name = "tegra-i2c", 1832 .of_match_table = tegra_i2c_of_match, 1833 .pm = &tegra_i2c_pm, 1834 }, 1835 }; 1836 1837 module_platform_driver(tegra_i2c_driver); 1838 1839 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 1840 MODULE_AUTHOR("Colin Cross"); 1841 MODULE_LICENSE("GPL v2"); 1842