xref: /openbmc/linux/drivers/i2c/busses/i2c-tegra.c (revision ae213c44)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * drivers/i2c/busses/i2c-tegra.c
4  *
5  * Copyright (C) 2010 Google, Inc.
6  * Author: Colin Cross <ccross@android.com>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/reset.h>
26 
27 #define BYTES_PER_FIFO_WORD 4
28 
29 #define I2C_CNFG				0x000
30 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT		12
31 #define I2C_CNFG_PACKET_MODE_EN			BIT(10)
32 #define I2C_CNFG_NEW_MASTER_FSM			BIT(11)
33 #define I2C_CNFG_MULTI_MASTER_MODE		BIT(17)
34 #define I2C_STATUS				0x01C
35 #define I2C_SL_CNFG				0x020
36 #define I2C_SL_CNFG_NACK			BIT(1)
37 #define I2C_SL_CNFG_NEWSL			BIT(2)
38 #define I2C_SL_ADDR1				0x02c
39 #define I2C_SL_ADDR2				0x030
40 #define I2C_TX_FIFO				0x050
41 #define I2C_RX_FIFO				0x054
42 #define I2C_PACKET_TRANSFER_STATUS		0x058
43 #define I2C_FIFO_CONTROL			0x05c
44 #define I2C_FIFO_CONTROL_TX_FLUSH		BIT(1)
45 #define I2C_FIFO_CONTROL_RX_FLUSH		BIT(0)
46 #define I2C_FIFO_CONTROL_TX_TRIG(x)		(((x) - 1) << 5)
47 #define I2C_FIFO_CONTROL_RX_TRIG(x)		(((x) - 1) << 2)
48 #define I2C_FIFO_STATUS				0x060
49 #define I2C_FIFO_STATUS_TX_MASK			0xF0
50 #define I2C_FIFO_STATUS_TX_SHIFT		4
51 #define I2C_FIFO_STATUS_RX_MASK			0x0F
52 #define I2C_FIFO_STATUS_RX_SHIFT		0
53 #define I2C_INT_MASK				0x064
54 #define I2C_INT_STATUS				0x068
55 #define I2C_INT_BUS_CLR_DONE			BIT(11)
56 #define I2C_INT_PACKET_XFER_COMPLETE		BIT(7)
57 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE	BIT(6)
58 #define I2C_INT_TX_FIFO_OVERFLOW		BIT(5)
59 #define I2C_INT_RX_FIFO_UNDERFLOW		BIT(4)
60 #define I2C_INT_NO_ACK				BIT(3)
61 #define I2C_INT_ARBITRATION_LOST		BIT(2)
62 #define I2C_INT_TX_FIFO_DATA_REQ		BIT(1)
63 #define I2C_INT_RX_FIFO_DATA_REQ		BIT(0)
64 #define I2C_CLK_DIVISOR				0x06c
65 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT	16
66 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE	8
67 
68 #define DVC_CTRL_REG1				0x000
69 #define DVC_CTRL_REG1_INTR_EN			BIT(10)
70 #define DVC_CTRL_REG2				0x004
71 #define DVC_CTRL_REG3				0x008
72 #define DVC_CTRL_REG3_SW_PROG			BIT(26)
73 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN		BIT(30)
74 #define DVC_STATUS				0x00c
75 #define DVC_STATUS_I2C_DONE_INTR		BIT(30)
76 
77 #define I2C_ERR_NONE				0x00
78 #define I2C_ERR_NO_ACK				0x01
79 #define I2C_ERR_ARBITRATION_LOST		0x02
80 #define I2C_ERR_UNKNOWN_INTERRUPT		0x04
81 
82 #define PACKET_HEADER0_HEADER_SIZE_SHIFT	28
83 #define PACKET_HEADER0_PACKET_ID_SHIFT		16
84 #define PACKET_HEADER0_CONT_ID_SHIFT		12
85 #define PACKET_HEADER0_PROTOCOL_I2C		BIT(4)
86 
87 #define I2C_HEADER_HIGHSPEED_MODE		BIT(22)
88 #define I2C_HEADER_CONT_ON_NAK			BIT(21)
89 #define I2C_HEADER_SEND_START_BYTE		BIT(20)
90 #define I2C_HEADER_READ				BIT(19)
91 #define I2C_HEADER_10BIT_ADDR			BIT(18)
92 #define I2C_HEADER_IE_ENABLE			BIT(17)
93 #define I2C_HEADER_REPEAT_START			BIT(16)
94 #define I2C_HEADER_CONTINUE_XFER		BIT(15)
95 #define I2C_HEADER_MASTER_ADDR_SHIFT		12
96 #define I2C_HEADER_SLAVE_ADDR_SHIFT		1
97 
98 #define I2C_BUS_CLEAR_CNFG			0x084
99 #define I2C_BC_SCLK_THRESHOLD			9
100 #define I2C_BC_SCLK_THRESHOLD_SHIFT		16
101 #define I2C_BC_STOP_COND			BIT(2)
102 #define I2C_BC_TERMINATE			BIT(1)
103 #define I2C_BC_ENABLE				BIT(0)
104 #define I2C_BUS_CLEAR_STATUS			0x088
105 #define I2C_BC_STATUS				BIT(0)
106 
107 #define I2C_CONFIG_LOAD				0x08C
108 #define I2C_MSTR_CONFIG_LOAD			BIT(0)
109 #define I2C_SLV_CONFIG_LOAD			BIT(1)
110 #define I2C_TIMEOUT_CONFIG_LOAD			BIT(2)
111 
112 #define I2C_CLKEN_OVERRIDE			0x090
113 #define I2C_MST_CORE_CLKEN_OVR			BIT(0)
114 
115 #define I2C_CONFIG_LOAD_TIMEOUT			1000000
116 
117 #define I2C_MST_FIFO_CONTROL			0x0b4
118 #define I2C_MST_FIFO_CONTROL_RX_FLUSH		BIT(0)
119 #define I2C_MST_FIFO_CONTROL_TX_FLUSH		BIT(1)
120 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x)		(((x) - 1) <<  4)
121 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x)		(((x) - 1) << 16)
122 
123 #define I2C_MST_FIFO_STATUS			0x0b8
124 #define I2C_MST_FIFO_STATUS_RX_MASK		0xff
125 #define I2C_MST_FIFO_STATUS_RX_SHIFT		0
126 #define I2C_MST_FIFO_STATUS_TX_MASK		0xff0000
127 #define I2C_MST_FIFO_STATUS_TX_SHIFT		16
128 
129 #define I2C_INTERFACE_TIMING_0			0x94
130 #define I2C_THIGH_SHIFT				8
131 #define I2C_INTERFACE_TIMING_1			0x98
132 
133 #define I2C_STANDARD_MODE			100000
134 #define I2C_FAST_MODE				400000
135 #define I2C_FAST_PLUS_MODE			1000000
136 #define I2C_HS_MODE				3500000
137 
138 /* Packet header size in bytes */
139 #define I2C_PACKET_HEADER_SIZE			12
140 
141 /*
142  * Upto I2C_PIO_MODE_MAX_LEN bytes, controller will use PIO mode,
143  * above this, controller will use DMA to fill FIFO.
144  * MAX PIO len is 20 bytes excluding packet header.
145  */
146 #define I2C_PIO_MODE_MAX_LEN			32
147 
148 /*
149  * msg_end_type: The bus control which need to be send at end of transfer.
150  * @MSG_END_STOP: Send stop pulse at end of transfer.
151  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
152  * @MSG_END_CONTINUE: The following on message is coming and so do not send
153  *		stop or repeat start.
154  */
155 enum msg_end_type {
156 	MSG_END_STOP,
157 	MSG_END_REPEAT_START,
158 	MSG_END_CONTINUE,
159 };
160 
161 /**
162  * struct tegra_i2c_hw_feature : Different HW support on Tegra
163  * @has_continue_xfer_support: Continue transfer supports.
164  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
165  *		complete interrupt per packet basis.
166  * @has_single_clk_source: The I2C controller has single clock source. Tegra30
167  *		and earlier SoCs have two clock sources i.e. div-clk and
168  *		fast-clk.
169  * @has_config_load_reg: Has the config load register to load the new
170  *		configuration.
171  * @clk_divisor_hs_mode: Clock divisor in HS mode.
172  * @clk_divisor_std_mode: Clock divisor in standard mode. It is
173  *		applicable if there is no fast clock source i.e. single clock
174  *		source.
175  * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
176  *		applicable if there is no fast clock source i.e. single clock
177  *		source.
178  * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
179  *		applicable if there is no fast clock source (i.e. single
180  *		clock source).
181  * @has_multi_master_mode: The I2C controller supports running in single-master
182  *		or multi-master mode.
183  * @has_slcg_override_reg: The I2C controller supports a register that
184  *		overrides the second level clock gating.
185  * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
186  *		provides additional features and allows for longer messages to
187  *		be transferred in one go.
188  * @quirks: i2c adapter quirks for limiting write/read transfer size and not
189  *		allowing 0 length transfers.
190  * @supports_bus_clear: Bus Clear support to recover from bus hang during
191  *		SDA stuck low from device for some unknown reasons.
192  * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
193  * @tlow_std_mode: Low period of the clock in standard mode.
194  * @thigh_std_mode: High period of the clock in standard mode.
195  * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
196  * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
197  * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
198  *		in standard mode.
199  * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
200  *		conditions in fast/fast-plus modes.
201  * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
202  *		in HS mode.
203  * @has_interface_timing_reg: Has interface timing register to program the tuned
204  *		timing settings.
205  */
206 struct tegra_i2c_hw_feature {
207 	bool has_continue_xfer_support;
208 	bool has_per_pkt_xfer_complete_irq;
209 	bool has_single_clk_source;
210 	bool has_config_load_reg;
211 	int clk_divisor_hs_mode;
212 	int clk_divisor_std_mode;
213 	int clk_divisor_fast_mode;
214 	u16 clk_divisor_fast_plus_mode;
215 	bool has_multi_master_mode;
216 	bool has_slcg_override_reg;
217 	bool has_mst_fifo;
218 	const struct i2c_adapter_quirks *quirks;
219 	bool supports_bus_clear;
220 	bool has_apb_dma;
221 	u8 tlow_std_mode;
222 	u8 thigh_std_mode;
223 	u8 tlow_fast_fastplus_mode;
224 	u8 thigh_fast_fastplus_mode;
225 	u32 setup_hold_time_std_mode;
226 	u32 setup_hold_time_fast_fast_plus_mode;
227 	u32 setup_hold_time_hs_mode;
228 	bool has_interface_timing_reg;
229 };
230 
231 /**
232  * struct tegra_i2c_dev - per device I2C context
233  * @dev: device reference for power management
234  * @hw: Tegra I2C HW feature
235  * @adapter: core I2C layer adapter information
236  * @div_clk: clock reference for div clock of I2C controller
237  * @fast_clk: clock reference for fast clock of I2C controller
238  * @rst: reset control for the I2C controller
239  * @base: ioremapped registers cookie
240  * @base_phys: physical base address of the I2C controller
241  * @cont_id: I2C controller ID, used for packet header
242  * @irq: IRQ number of transfer complete interrupt
243  * @irq_disabled: used to track whether or not the interrupt is enabled
244  * @is_dvc: identifies the DVC I2C controller, has a different register layout
245  * @msg_complete: transfer completion notifier
246  * @msg_err: error code for completed message
247  * @msg_buf: pointer to current message data
248  * @msg_buf_remaining: size of unsent data in the message buffer
249  * @msg_read: identifies read transfers
250  * @bus_clk_rate: current I2C bus clock rate
251  * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
252  * @is_multimaster_mode: track if I2C controller is in multi-master mode
253  * @xfer_lock: lock to serialize transfer submission and processing
254  * @tx_dma_chan: DMA transmit channel
255  * @rx_dma_chan: DMA receive channel
256  * @dma_phys: handle to DMA resources
257  * @dma_buf: pointer to allocated DMA buffer
258  * @dma_buf_size: DMA buffer size
259  * @is_curr_dma_xfer: indicates active DMA transfer
260  * @dma_complete: DMA completion notifier
261  */
262 struct tegra_i2c_dev {
263 	struct device *dev;
264 	const struct tegra_i2c_hw_feature *hw;
265 	struct i2c_adapter adapter;
266 	struct clk *div_clk;
267 	struct clk *fast_clk;
268 	struct reset_control *rst;
269 	void __iomem *base;
270 	phys_addr_t base_phys;
271 	int cont_id;
272 	int irq;
273 	bool irq_disabled;
274 	int is_dvc;
275 	struct completion msg_complete;
276 	int msg_err;
277 	u8 *msg_buf;
278 	size_t msg_buf_remaining;
279 	int msg_read;
280 	u32 bus_clk_rate;
281 	u16 clk_divisor_non_hs_mode;
282 	bool is_multimaster_mode;
283 	spinlock_t xfer_lock;
284 	struct dma_chan *tx_dma_chan;
285 	struct dma_chan *rx_dma_chan;
286 	dma_addr_t dma_phys;
287 	u32 *dma_buf;
288 	unsigned int dma_buf_size;
289 	bool is_curr_dma_xfer;
290 	struct completion dma_complete;
291 };
292 
293 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
294 		       unsigned long reg)
295 {
296 	writel(val, i2c_dev->base + reg);
297 }
298 
299 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
300 {
301 	return readl(i2c_dev->base + reg);
302 }
303 
304 /*
305  * i2c_writel and i2c_readl will offset the register if necessary to talk
306  * to the I2C block inside the DVC block
307  */
308 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
309 	unsigned long reg)
310 {
311 	if (i2c_dev->is_dvc)
312 		reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
313 	return reg;
314 }
315 
316 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
317 	unsigned long reg)
318 {
319 	writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
320 
321 	/* Read back register to make sure that register writes completed */
322 	if (reg != I2C_TX_FIFO)
323 		readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
324 }
325 
326 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
327 {
328 	return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
329 }
330 
331 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
332 	unsigned long reg, int len)
333 {
334 	writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
335 }
336 
337 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
338 	unsigned long reg, int len)
339 {
340 	readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
341 }
342 
343 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
344 {
345 	u32 int_mask;
346 
347 	int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
348 	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
349 }
350 
351 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
352 {
353 	u32 int_mask;
354 
355 	int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
356 	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
357 }
358 
359 static void tegra_i2c_dma_complete(void *args)
360 {
361 	struct tegra_i2c_dev *i2c_dev = args;
362 
363 	complete(&i2c_dev->dma_complete);
364 }
365 
366 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
367 {
368 	struct dma_async_tx_descriptor *dma_desc;
369 	enum dma_transfer_direction dir;
370 	struct dma_chan *chan;
371 
372 	dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
373 	reinit_completion(&i2c_dev->dma_complete);
374 	dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
375 	chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
376 	dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
377 					       len, dir, DMA_PREP_INTERRUPT |
378 					       DMA_CTRL_ACK);
379 	if (!dma_desc) {
380 		dev_err(i2c_dev->dev, "failed to get DMA descriptor\n");
381 		return -EINVAL;
382 	}
383 
384 	dma_desc->callback = tegra_i2c_dma_complete;
385 	dma_desc->callback_param = i2c_dev;
386 	dmaengine_submit(dma_desc);
387 	dma_async_issue_pending(chan);
388 	return 0;
389 }
390 
391 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
392 {
393 	if (i2c_dev->dma_buf) {
394 		dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
395 				  i2c_dev->dma_buf, i2c_dev->dma_phys);
396 		i2c_dev->dma_buf = NULL;
397 	}
398 
399 	if (i2c_dev->tx_dma_chan) {
400 		dma_release_channel(i2c_dev->tx_dma_chan);
401 		i2c_dev->tx_dma_chan = NULL;
402 	}
403 
404 	if (i2c_dev->rx_dma_chan) {
405 		dma_release_channel(i2c_dev->rx_dma_chan);
406 		i2c_dev->rx_dma_chan = NULL;
407 	}
408 }
409 
410 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
411 {
412 	struct dma_chan *chan;
413 	u32 *dma_buf;
414 	dma_addr_t dma_phys;
415 	int err;
416 
417 	if (!i2c_dev->hw->has_apb_dma)
418 		return 0;
419 
420 	if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
421 		dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n");
422 		return 0;
423 	}
424 
425 	chan = dma_request_slave_channel_reason(i2c_dev->dev, "rx");
426 	if (IS_ERR(chan)) {
427 		err = PTR_ERR(chan);
428 		goto err_out;
429 	}
430 
431 	i2c_dev->rx_dma_chan = chan;
432 
433 	chan = dma_request_slave_channel_reason(i2c_dev->dev, "tx");
434 	if (IS_ERR(chan)) {
435 		err = PTR_ERR(chan);
436 		goto err_out;
437 	}
438 
439 	i2c_dev->tx_dma_chan = chan;
440 
441 	dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
442 				     &dma_phys, GFP_KERNEL | __GFP_NOWARN);
443 	if (!dma_buf) {
444 		dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n");
445 		err = -ENOMEM;
446 		goto err_out;
447 	}
448 
449 	i2c_dev->dma_buf = dma_buf;
450 	i2c_dev->dma_phys = dma_phys;
451 	return 0;
452 
453 err_out:
454 	tegra_i2c_release_dma(i2c_dev);
455 	if (err != -EPROBE_DEFER) {
456 		dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
457 		dev_err(i2c_dev->dev, "falling back to PIO\n");
458 		return 0;
459 	}
460 
461 	return err;
462 }
463 
464 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
465 {
466 	unsigned long timeout = jiffies + HZ;
467 	unsigned int offset;
468 	u32 mask, val;
469 
470 	if (i2c_dev->hw->has_mst_fifo) {
471 		mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
472 		       I2C_MST_FIFO_CONTROL_RX_FLUSH;
473 		offset = I2C_MST_FIFO_CONTROL;
474 	} else {
475 		mask = I2C_FIFO_CONTROL_TX_FLUSH |
476 		       I2C_FIFO_CONTROL_RX_FLUSH;
477 		offset = I2C_FIFO_CONTROL;
478 	}
479 
480 	val = i2c_readl(i2c_dev, offset);
481 	val |= mask;
482 	i2c_writel(i2c_dev, val, offset);
483 
484 	while (i2c_readl(i2c_dev, offset) & mask) {
485 		if (time_after(jiffies, timeout)) {
486 			dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
487 			return -ETIMEDOUT;
488 		}
489 		msleep(1);
490 	}
491 	return 0;
492 }
493 
494 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
495 {
496 	u32 val;
497 	int rx_fifo_avail;
498 	u8 *buf = i2c_dev->msg_buf;
499 	size_t buf_remaining = i2c_dev->msg_buf_remaining;
500 	int words_to_transfer;
501 
502 	if (i2c_dev->hw->has_mst_fifo) {
503 		val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
504 		rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >>
505 			I2C_MST_FIFO_STATUS_RX_SHIFT;
506 	} else {
507 		val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
508 		rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
509 			I2C_FIFO_STATUS_RX_SHIFT;
510 	}
511 
512 	/* Rounds down to not include partial word at the end of buf */
513 	words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
514 	if (words_to_transfer > rx_fifo_avail)
515 		words_to_transfer = rx_fifo_avail;
516 
517 	i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
518 
519 	buf += words_to_transfer * BYTES_PER_FIFO_WORD;
520 	buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
521 	rx_fifo_avail -= words_to_transfer;
522 
523 	/*
524 	 * If there is a partial word at the end of buf, handle it manually to
525 	 * prevent overwriting past the end of buf
526 	 */
527 	if (rx_fifo_avail > 0 && buf_remaining > 0) {
528 		BUG_ON(buf_remaining > 3);
529 		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
530 		val = cpu_to_le32(val);
531 		memcpy(buf, &val, buf_remaining);
532 		buf_remaining = 0;
533 		rx_fifo_avail--;
534 	}
535 
536 	BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
537 	i2c_dev->msg_buf_remaining = buf_remaining;
538 	i2c_dev->msg_buf = buf;
539 
540 	return 0;
541 }
542 
543 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
544 {
545 	u32 val;
546 	int tx_fifo_avail;
547 	u8 *buf = i2c_dev->msg_buf;
548 	size_t buf_remaining = i2c_dev->msg_buf_remaining;
549 	int words_to_transfer;
550 
551 	if (i2c_dev->hw->has_mst_fifo) {
552 		val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
553 		tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >>
554 			I2C_MST_FIFO_STATUS_TX_SHIFT;
555 	} else {
556 		val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
557 		tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
558 			I2C_FIFO_STATUS_TX_SHIFT;
559 	}
560 
561 	/* Rounds down to not include partial word at the end of buf */
562 	words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
563 
564 	/* It's very common to have < 4 bytes, so optimize that case. */
565 	if (words_to_transfer) {
566 		if (words_to_transfer > tx_fifo_avail)
567 			words_to_transfer = tx_fifo_avail;
568 
569 		/*
570 		 * Update state before writing to FIFO.  If this casues us
571 		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
572 		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
573 		 * not maskable).  We need to make sure that the isr sees
574 		 * buf_remaining as 0 and doesn't call us back re-entrantly.
575 		 */
576 		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
577 		tx_fifo_avail -= words_to_transfer;
578 		i2c_dev->msg_buf_remaining = buf_remaining;
579 		i2c_dev->msg_buf = buf +
580 			words_to_transfer * BYTES_PER_FIFO_WORD;
581 		barrier();
582 
583 		i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
584 
585 		buf += words_to_transfer * BYTES_PER_FIFO_WORD;
586 	}
587 
588 	/*
589 	 * If there is a partial word at the end of buf, handle it manually to
590 	 * prevent reading past the end of buf, which could cross a page
591 	 * boundary and fault.
592 	 */
593 	if (tx_fifo_avail > 0 && buf_remaining > 0) {
594 		BUG_ON(buf_remaining > 3);
595 		memcpy(&val, buf, buf_remaining);
596 		val = le32_to_cpu(val);
597 
598 		/* Again update before writing to FIFO to make sure isr sees. */
599 		i2c_dev->msg_buf_remaining = 0;
600 		i2c_dev->msg_buf = NULL;
601 		barrier();
602 
603 		i2c_writel(i2c_dev, val, I2C_TX_FIFO);
604 	}
605 
606 	return 0;
607 }
608 
609 /*
610  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
611  * block.  This block is identical to the rest of the I2C blocks, except that
612  * it only supports master mode, it has registers moved around, and it needs
613  * some extra init to get it into I2C mode.  The register moves are handled
614  * by i2c_readl and i2c_writel
615  */
616 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
617 {
618 	u32 val;
619 
620 	val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
621 	val |= DVC_CTRL_REG3_SW_PROG;
622 	val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
623 	dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
624 
625 	val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
626 	val |= DVC_CTRL_REG1_INTR_EN;
627 	dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
628 }
629 
630 static int tegra_i2c_runtime_resume(struct device *dev)
631 {
632 	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
633 	int ret;
634 
635 	ret = pinctrl_pm_select_default_state(i2c_dev->dev);
636 	if (ret)
637 		return ret;
638 
639 	if (!i2c_dev->hw->has_single_clk_source) {
640 		ret = clk_enable(i2c_dev->fast_clk);
641 		if (ret < 0) {
642 			dev_err(i2c_dev->dev,
643 				"Enabling fast clk failed, err %d\n", ret);
644 			return ret;
645 		}
646 	}
647 
648 	ret = clk_enable(i2c_dev->div_clk);
649 	if (ret < 0) {
650 		dev_err(i2c_dev->dev,
651 			"Enabling div clk failed, err %d\n", ret);
652 		clk_disable(i2c_dev->fast_clk);
653 		return ret;
654 	}
655 
656 	return 0;
657 }
658 
659 static int tegra_i2c_runtime_suspend(struct device *dev)
660 {
661 	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
662 
663 	clk_disable(i2c_dev->div_clk);
664 	if (!i2c_dev->hw->has_single_clk_source)
665 		clk_disable(i2c_dev->fast_clk);
666 
667 	return pinctrl_pm_select_idle_state(i2c_dev->dev);
668 }
669 
670 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
671 {
672 	unsigned long reg_offset;
673 	void __iomem *addr;
674 	u32 val;
675 	int err;
676 
677 	if (i2c_dev->hw->has_config_load_reg) {
678 		reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
679 		addr = i2c_dev->base + reg_offset;
680 		i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
681 		if (in_interrupt())
682 			err = readl_poll_timeout_atomic(addr, val, val == 0,
683 					1000, I2C_CONFIG_LOAD_TIMEOUT);
684 		else
685 			err = readl_poll_timeout(addr, val, val == 0,
686 					1000, I2C_CONFIG_LOAD_TIMEOUT);
687 
688 		if (err) {
689 			dev_warn(i2c_dev->dev,
690 				 "timeout waiting for config load\n");
691 			return err;
692 		}
693 	}
694 
695 	return 0;
696 }
697 
698 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
699 {
700 	u32 val;
701 	int err;
702 	u32 clk_divisor, clk_multiplier;
703 	u32 tsu_thd = 0;
704 	u8 tlow, thigh;
705 
706 	err = pm_runtime_get_sync(i2c_dev->dev);
707 	if (err < 0) {
708 		dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
709 		return err;
710 	}
711 
712 	reset_control_assert(i2c_dev->rst);
713 	udelay(2);
714 	reset_control_deassert(i2c_dev->rst);
715 
716 	if (i2c_dev->is_dvc)
717 		tegra_dvc_init(i2c_dev);
718 
719 	val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
720 		(0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
721 
722 	if (i2c_dev->hw->has_multi_master_mode)
723 		val |= I2C_CNFG_MULTI_MASTER_MODE;
724 
725 	i2c_writel(i2c_dev, val, I2C_CNFG);
726 	i2c_writel(i2c_dev, 0, I2C_INT_MASK);
727 
728 	/* Make sure clock divisor programmed correctly */
729 	clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
730 	clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
731 					I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
732 	i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
733 
734 	if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
735 	    i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) {
736 		tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
737 		thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
738 		tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
739 	} else {
740 		tlow = i2c_dev->hw->tlow_std_mode;
741 		thigh = i2c_dev->hw->thigh_std_mode;
742 		tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
743 	}
744 
745 	if (i2c_dev->hw->has_interface_timing_reg) {
746 		val = (thigh << I2C_THIGH_SHIFT) | tlow;
747 		i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
748 	}
749 
750 	/*
751 	 * configure setup and hold times only when tsu_thd is non-zero.
752 	 * otherwise, preserve the chip default values
753 	 */
754 	if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
755 		i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
756 
757 	if (!clk_reinit) {
758 		clk_multiplier = (tlow + thigh + 2);
759 		clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
760 		err = clk_set_rate(i2c_dev->div_clk,
761 				   i2c_dev->bus_clk_rate * clk_multiplier);
762 		if (err) {
763 			dev_err(i2c_dev->dev,
764 				"failed changing clock rate: %d\n", err);
765 			goto err;
766 		}
767 	}
768 
769 	if (!i2c_dev->is_dvc) {
770 		u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
771 
772 		sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
773 		i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
774 		i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
775 		i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
776 	}
777 
778 	err = tegra_i2c_flush_fifos(i2c_dev);
779 	if (err)
780 		goto err;
781 
782 	if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
783 		i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
784 
785 	err = tegra_i2c_wait_for_config_load(i2c_dev);
786 	if (err)
787 		goto err;
788 
789 	if (i2c_dev->irq_disabled) {
790 		i2c_dev->irq_disabled = false;
791 		enable_irq(i2c_dev->irq);
792 	}
793 
794 err:
795 	pm_runtime_put(i2c_dev->dev);
796 	return err;
797 }
798 
799 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
800 {
801 	u32 cnfg;
802 
803 	/*
804 	 * NACK interrupt is generated before the I2C controller generates
805 	 * the STOP condition on the bus. So wait for 2 clock periods
806 	 * before disabling the controller so that the STOP condition has
807 	 * been delivered properly.
808 	 */
809 	udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
810 
811 	cnfg = i2c_readl(i2c_dev, I2C_CNFG);
812 	if (cnfg & I2C_CNFG_PACKET_MODE_EN)
813 		i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
814 
815 	return tegra_i2c_wait_for_config_load(i2c_dev);
816 }
817 
818 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
819 {
820 	u32 status;
821 	const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
822 	struct tegra_i2c_dev *i2c_dev = dev_id;
823 
824 	status = i2c_readl(i2c_dev, I2C_INT_STATUS);
825 
826 	spin_lock(&i2c_dev->xfer_lock);
827 	if (status == 0) {
828 		dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
829 			 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
830 			 i2c_readl(i2c_dev, I2C_STATUS),
831 			 i2c_readl(i2c_dev, I2C_CNFG));
832 		i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
833 
834 		if (!i2c_dev->irq_disabled) {
835 			disable_irq_nosync(i2c_dev->irq);
836 			i2c_dev->irq_disabled = true;
837 		}
838 		goto err;
839 	}
840 
841 	if (unlikely(status & status_err)) {
842 		tegra_i2c_disable_packet_mode(i2c_dev);
843 		if (status & I2C_INT_NO_ACK)
844 			i2c_dev->msg_err |= I2C_ERR_NO_ACK;
845 		if (status & I2C_INT_ARBITRATION_LOST)
846 			i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
847 		goto err;
848 	}
849 
850 	/*
851 	 * I2C transfer is terminated during the bus clear so skip
852 	 * processing the other interrupts.
853 	 */
854 	if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
855 		goto err;
856 
857 	if (!i2c_dev->is_curr_dma_xfer) {
858 		if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
859 			if (i2c_dev->msg_buf_remaining)
860 				tegra_i2c_empty_rx_fifo(i2c_dev);
861 			else
862 				BUG();
863 		}
864 
865 		if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
866 			if (i2c_dev->msg_buf_remaining)
867 				tegra_i2c_fill_tx_fifo(i2c_dev);
868 			else
869 				tegra_i2c_mask_irq(i2c_dev,
870 						   I2C_INT_TX_FIFO_DATA_REQ);
871 		}
872 	}
873 
874 	i2c_writel(i2c_dev, status, I2C_INT_STATUS);
875 	if (i2c_dev->is_dvc)
876 		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
877 
878 	/*
879 	 * During message read XFER_COMPLETE interrupt is triggered prior to
880 	 * DMA completion and during message write XFER_COMPLETE interrupt is
881 	 * triggered after DMA completion.
882 	 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer.
883 	 * so forcing msg_buf_remaining to 0 in DMA mode.
884 	 */
885 	if (status & I2C_INT_PACKET_XFER_COMPLETE) {
886 		if (i2c_dev->is_curr_dma_xfer)
887 			i2c_dev->msg_buf_remaining = 0;
888 		BUG_ON(i2c_dev->msg_buf_remaining);
889 		complete(&i2c_dev->msg_complete);
890 	}
891 	goto done;
892 err:
893 	/* An error occurred, mask all interrupts */
894 	tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
895 		I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
896 		I2C_INT_RX_FIFO_DATA_REQ);
897 	if (i2c_dev->hw->supports_bus_clear)
898 		tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
899 	i2c_writel(i2c_dev, status, I2C_INT_STATUS);
900 	if (i2c_dev->is_dvc)
901 		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
902 
903 	if (i2c_dev->is_curr_dma_xfer) {
904 		if (i2c_dev->msg_read)
905 			dmaengine_terminate_async(i2c_dev->rx_dma_chan);
906 		else
907 			dmaengine_terminate_async(i2c_dev->tx_dma_chan);
908 
909 		complete(&i2c_dev->dma_complete);
910 	}
911 
912 	complete(&i2c_dev->msg_complete);
913 done:
914 	spin_unlock(&i2c_dev->xfer_lock);
915 	return IRQ_HANDLED;
916 }
917 
918 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
919 				       size_t len)
920 {
921 	u32 val, reg;
922 	u8 dma_burst;
923 	struct dma_slave_config slv_config = {0};
924 	struct dma_chan *chan;
925 	int ret;
926 	unsigned long reg_offset;
927 
928 	if (i2c_dev->hw->has_mst_fifo)
929 		reg = I2C_MST_FIFO_CONTROL;
930 	else
931 		reg = I2C_FIFO_CONTROL;
932 
933 	if (i2c_dev->is_curr_dma_xfer) {
934 		if (len & 0xF)
935 			dma_burst = 1;
936 		else if (len & 0x10)
937 			dma_burst = 4;
938 		else
939 			dma_burst = 8;
940 
941 		if (i2c_dev->msg_read) {
942 			chan = i2c_dev->rx_dma_chan;
943 			reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
944 			slv_config.src_addr = i2c_dev->base_phys + reg_offset;
945 			slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
946 			slv_config.src_maxburst = dma_burst;
947 
948 			if (i2c_dev->hw->has_mst_fifo)
949 				val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
950 			else
951 				val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
952 		} else {
953 			chan = i2c_dev->tx_dma_chan;
954 			reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
955 			slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
956 			slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
957 			slv_config.dst_maxburst = dma_burst;
958 
959 			if (i2c_dev->hw->has_mst_fifo)
960 				val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
961 			else
962 				val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
963 		}
964 
965 		slv_config.device_fc = true;
966 		ret = dmaengine_slave_config(chan, &slv_config);
967 		if (ret < 0) {
968 			dev_err(i2c_dev->dev, "DMA slave config failed: %d\n",
969 				ret);
970 			dev_err(i2c_dev->dev, "falling back to PIO\n");
971 			tegra_i2c_release_dma(i2c_dev);
972 			i2c_dev->is_curr_dma_xfer = false;
973 		} else {
974 			goto out;
975 		}
976 	}
977 
978 	if (i2c_dev->hw->has_mst_fifo)
979 		val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
980 		      I2C_MST_FIFO_CONTROL_RX_TRIG(1);
981 	else
982 		val = I2C_FIFO_CONTROL_TX_TRIG(8) |
983 		      I2C_FIFO_CONTROL_RX_TRIG(1);
984 out:
985 	i2c_writel(i2c_dev, val, reg);
986 }
987 
988 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
989 {
990 	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
991 	int err;
992 	unsigned long time_left;
993 	u32 reg;
994 
995 	reinit_completion(&i2c_dev->msg_complete);
996 	reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) |
997 	      I2C_BC_STOP_COND | I2C_BC_TERMINATE;
998 	i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
999 	if (i2c_dev->hw->has_config_load_reg) {
1000 		err = tegra_i2c_wait_for_config_load(i2c_dev);
1001 		if (err)
1002 			return err;
1003 	}
1004 
1005 	reg |= I2C_BC_ENABLE;
1006 	i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1007 	tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1008 
1009 	time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
1010 						msecs_to_jiffies(50));
1011 	if (time_left == 0) {
1012 		dev_err(i2c_dev->dev, "timed out for bus clear\n");
1013 		return -ETIMEDOUT;
1014 	}
1015 
1016 	reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1017 	if (!(reg & I2C_BC_STATUS)) {
1018 		dev_err(i2c_dev->dev,
1019 			"un-recovered arbitration lost\n");
1020 		return -EIO;
1021 	}
1022 
1023 	return -EAGAIN;
1024 }
1025 
1026 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1027 	struct i2c_msg *msg, enum msg_end_type end_state)
1028 {
1029 	u32 packet_header;
1030 	u32 int_mask;
1031 	unsigned long time_left;
1032 	unsigned long flags;
1033 	size_t xfer_size;
1034 	u32 *buffer = NULL;
1035 	int err = 0;
1036 	bool dma;
1037 	u16 xfer_time = 100;
1038 
1039 	tegra_i2c_flush_fifos(i2c_dev);
1040 
1041 	i2c_dev->msg_buf = msg->buf;
1042 	i2c_dev->msg_buf_remaining = msg->len;
1043 	i2c_dev->msg_err = I2C_ERR_NONE;
1044 	i2c_dev->msg_read = (msg->flags & I2C_M_RD);
1045 	reinit_completion(&i2c_dev->msg_complete);
1046 
1047 	if (i2c_dev->msg_read)
1048 		xfer_size = msg->len;
1049 	else
1050 		xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1051 
1052 	xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1053 	i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_MAX_LEN) &&
1054 				    i2c_dev->dma_buf;
1055 	tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1056 	dma = i2c_dev->is_curr_dma_xfer;
1057 	/*
1058 	 * Transfer time in mSec = Total bits / transfer rate
1059 	 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1060 	 */
1061 	xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1062 					i2c_dev->bus_clk_rate);
1063 	spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
1064 
1065 	int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1066 	tegra_i2c_unmask_irq(i2c_dev, int_mask);
1067 	if (dma) {
1068 		if (i2c_dev->msg_read) {
1069 			dma_sync_single_for_device(i2c_dev->dev,
1070 						   i2c_dev->dma_phys,
1071 						   xfer_size,
1072 						   DMA_FROM_DEVICE);
1073 			err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1074 			if (err < 0) {
1075 				dev_err(i2c_dev->dev,
1076 					"starting RX DMA failed, err %d\n",
1077 					err);
1078 				goto unlock;
1079 			}
1080 
1081 		} else {
1082 			dma_sync_single_for_cpu(i2c_dev->dev,
1083 						i2c_dev->dma_phys,
1084 						xfer_size,
1085 						DMA_TO_DEVICE);
1086 			buffer = i2c_dev->dma_buf;
1087 		}
1088 	}
1089 
1090 	packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
1091 			PACKET_HEADER0_PROTOCOL_I2C |
1092 			(i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
1093 			(1 << PACKET_HEADER0_PACKET_ID_SHIFT);
1094 	if (dma && !i2c_dev->msg_read)
1095 		*buffer++ = packet_header;
1096 	else
1097 		i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1098 
1099 	packet_header = msg->len - 1;
1100 	if (dma && !i2c_dev->msg_read)
1101 		*buffer++ = packet_header;
1102 	else
1103 		i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1104 
1105 	packet_header = I2C_HEADER_IE_ENABLE;
1106 	if (end_state == MSG_END_CONTINUE)
1107 		packet_header |= I2C_HEADER_CONTINUE_XFER;
1108 	else if (end_state == MSG_END_REPEAT_START)
1109 		packet_header |= I2C_HEADER_REPEAT_START;
1110 	if (msg->flags & I2C_M_TEN) {
1111 		packet_header |= msg->addr;
1112 		packet_header |= I2C_HEADER_10BIT_ADDR;
1113 	} else {
1114 		packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1115 	}
1116 	if (msg->flags & I2C_M_IGNORE_NAK)
1117 		packet_header |= I2C_HEADER_CONT_ON_NAK;
1118 	if (msg->flags & I2C_M_RD)
1119 		packet_header |= I2C_HEADER_READ;
1120 	if (dma && !i2c_dev->msg_read)
1121 		*buffer++ = packet_header;
1122 	else
1123 		i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1124 
1125 	if (!i2c_dev->msg_read) {
1126 		if (dma) {
1127 			memcpy(buffer, msg->buf, msg->len);
1128 			dma_sync_single_for_device(i2c_dev->dev,
1129 						   i2c_dev->dma_phys,
1130 						   xfer_size,
1131 						   DMA_TO_DEVICE);
1132 			err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1133 			if (err < 0) {
1134 				dev_err(i2c_dev->dev,
1135 					"starting TX DMA failed, err %d\n",
1136 					err);
1137 				goto unlock;
1138 			}
1139 		} else {
1140 			tegra_i2c_fill_tx_fifo(i2c_dev);
1141 		}
1142 	}
1143 
1144 	if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1145 		int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1146 	if (!dma) {
1147 		if (msg->flags & I2C_M_RD)
1148 			int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1149 		else if (i2c_dev->msg_buf_remaining)
1150 			int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1151 	}
1152 
1153 	tegra_i2c_unmask_irq(i2c_dev, int_mask);
1154 	dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1155 		i2c_readl(i2c_dev, I2C_INT_MASK));
1156 
1157 unlock:
1158 	spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
1159 
1160 	if (dma) {
1161 		if (err)
1162 			return err;
1163 
1164 		time_left = wait_for_completion_timeout(
1165 						&i2c_dev->dma_complete,
1166 						msecs_to_jiffies(xfer_time));
1167 		if (time_left == 0) {
1168 			dev_err(i2c_dev->dev, "DMA transfer timeout\n");
1169 			dmaengine_terminate_sync(i2c_dev->msg_read ?
1170 						 i2c_dev->rx_dma_chan :
1171 						 i2c_dev->tx_dma_chan);
1172 			tegra_i2c_init(i2c_dev, true);
1173 			return -ETIMEDOUT;
1174 		}
1175 
1176 		if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1177 			dma_sync_single_for_cpu(i2c_dev->dev,
1178 						i2c_dev->dma_phys,
1179 						xfer_size,
1180 						DMA_FROM_DEVICE);
1181 			memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf,
1182 			       msg->len);
1183 		}
1184 
1185 		if (i2c_dev->msg_err != I2C_ERR_NONE)
1186 			dmaengine_synchronize(i2c_dev->msg_read ?
1187 					      i2c_dev->rx_dma_chan :
1188 					      i2c_dev->tx_dma_chan);
1189 	}
1190 
1191 	time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
1192 						msecs_to_jiffies(xfer_time));
1193 	tegra_i2c_mask_irq(i2c_dev, int_mask);
1194 
1195 	if (time_left == 0) {
1196 		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
1197 
1198 		tegra_i2c_init(i2c_dev, true);
1199 		return -ETIMEDOUT;
1200 	}
1201 
1202 	dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1203 		time_left, completion_done(&i2c_dev->msg_complete),
1204 		i2c_dev->msg_err);
1205 
1206 	i2c_dev->is_curr_dma_xfer = false;
1207 	if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
1208 		return 0;
1209 
1210 	tegra_i2c_init(i2c_dev, true);
1211 	/* start recovery upon arbitration loss in single master mode */
1212 	if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1213 		if (!i2c_dev->is_multimaster_mode)
1214 			return i2c_recover_bus(&i2c_dev->adapter);
1215 		return -EAGAIN;
1216 	}
1217 
1218 	if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1219 		if (msg->flags & I2C_M_IGNORE_NAK)
1220 			return 0;
1221 		return -EREMOTEIO;
1222 	}
1223 
1224 	return -EIO;
1225 }
1226 
1227 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1228 	int num)
1229 {
1230 	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1231 	int i;
1232 	int ret = 0;
1233 
1234 	ret = pm_runtime_get_sync(i2c_dev->dev);
1235 	if (ret < 0) {
1236 		dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1237 		return ret;
1238 	}
1239 
1240 	for (i = 0; i < num; i++) {
1241 		enum msg_end_type end_type = MSG_END_STOP;
1242 
1243 		if (i < (num - 1)) {
1244 			if (msgs[i + 1].flags & I2C_M_NOSTART)
1245 				end_type = MSG_END_CONTINUE;
1246 			else
1247 				end_type = MSG_END_REPEAT_START;
1248 		}
1249 		ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1250 		if (ret)
1251 			break;
1252 	}
1253 
1254 	pm_runtime_put(i2c_dev->dev);
1255 
1256 	return ret ?: i;
1257 }
1258 
1259 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1260 {
1261 	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1262 	u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1263 		  I2C_FUNC_10BIT_ADDR |	I2C_FUNC_PROTOCOL_MANGLING;
1264 
1265 	if (i2c_dev->hw->has_continue_xfer_support)
1266 		ret |= I2C_FUNC_NOSTART;
1267 	return ret;
1268 }
1269 
1270 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1271 {
1272 	struct device_node *np = i2c_dev->dev->of_node;
1273 	int ret;
1274 
1275 	ret = of_property_read_u32(np, "clock-frequency",
1276 			&i2c_dev->bus_clk_rate);
1277 	if (ret)
1278 		i2c_dev->bus_clk_rate = 100000; /* default clock rate */
1279 
1280 	i2c_dev->is_multimaster_mode = of_property_read_bool(np,
1281 			"multi-master");
1282 }
1283 
1284 static const struct i2c_algorithm tegra_i2c_algo = {
1285 	.master_xfer	= tegra_i2c_xfer,
1286 	.functionality	= tegra_i2c_func,
1287 };
1288 
1289 /* payload size is only 12 bit */
1290 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1291 	.flags = I2C_AQ_NO_ZERO_LEN,
1292 	.max_read_len = SZ_4K,
1293 	.max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1294 };
1295 
1296 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1297 	.flags = I2C_AQ_NO_ZERO_LEN,
1298 	.max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1299 };
1300 
1301 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1302 	.recover_bus = tegra_i2c_issue_bus_clear,
1303 };
1304 
1305 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1306 	.has_continue_xfer_support = false,
1307 	.has_per_pkt_xfer_complete_irq = false,
1308 	.has_single_clk_source = false,
1309 	.clk_divisor_hs_mode = 3,
1310 	.clk_divisor_std_mode = 0,
1311 	.clk_divisor_fast_mode = 0,
1312 	.clk_divisor_fast_plus_mode = 0,
1313 	.has_config_load_reg = false,
1314 	.has_multi_master_mode = false,
1315 	.has_slcg_override_reg = false,
1316 	.has_mst_fifo = false,
1317 	.quirks = &tegra_i2c_quirks,
1318 	.supports_bus_clear = false,
1319 	.has_apb_dma = true,
1320 	.tlow_std_mode = 0x4,
1321 	.thigh_std_mode = 0x2,
1322 	.tlow_fast_fastplus_mode = 0x4,
1323 	.thigh_fast_fastplus_mode = 0x2,
1324 	.setup_hold_time_std_mode = 0x0,
1325 	.setup_hold_time_fast_fast_plus_mode = 0x0,
1326 	.setup_hold_time_hs_mode = 0x0,
1327 	.has_interface_timing_reg = false,
1328 };
1329 
1330 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1331 	.has_continue_xfer_support = true,
1332 	.has_per_pkt_xfer_complete_irq = false,
1333 	.has_single_clk_source = false,
1334 	.clk_divisor_hs_mode = 3,
1335 	.clk_divisor_std_mode = 0,
1336 	.clk_divisor_fast_mode = 0,
1337 	.clk_divisor_fast_plus_mode = 0,
1338 	.has_config_load_reg = false,
1339 	.has_multi_master_mode = false,
1340 	.has_slcg_override_reg = false,
1341 	.has_mst_fifo = false,
1342 	.quirks = &tegra_i2c_quirks,
1343 	.supports_bus_clear = false,
1344 	.has_apb_dma = true,
1345 	.tlow_std_mode = 0x4,
1346 	.thigh_std_mode = 0x2,
1347 	.tlow_fast_fastplus_mode = 0x4,
1348 	.thigh_fast_fastplus_mode = 0x2,
1349 	.setup_hold_time_std_mode = 0x0,
1350 	.setup_hold_time_fast_fast_plus_mode = 0x0,
1351 	.setup_hold_time_hs_mode = 0x0,
1352 	.has_interface_timing_reg = false,
1353 };
1354 
1355 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1356 	.has_continue_xfer_support = true,
1357 	.has_per_pkt_xfer_complete_irq = true,
1358 	.has_single_clk_source = true,
1359 	.clk_divisor_hs_mode = 1,
1360 	.clk_divisor_std_mode = 0x19,
1361 	.clk_divisor_fast_mode = 0x19,
1362 	.clk_divisor_fast_plus_mode = 0x10,
1363 	.has_config_load_reg = false,
1364 	.has_multi_master_mode = false,
1365 	.has_slcg_override_reg = false,
1366 	.has_mst_fifo = false,
1367 	.quirks = &tegra_i2c_quirks,
1368 	.supports_bus_clear = true,
1369 	.has_apb_dma = true,
1370 	.tlow_std_mode = 0x4,
1371 	.thigh_std_mode = 0x2,
1372 	.tlow_fast_fastplus_mode = 0x4,
1373 	.thigh_fast_fastplus_mode = 0x2,
1374 	.setup_hold_time_std_mode = 0x0,
1375 	.setup_hold_time_fast_fast_plus_mode = 0x0,
1376 	.setup_hold_time_hs_mode = 0x0,
1377 	.has_interface_timing_reg = false,
1378 };
1379 
1380 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1381 	.has_continue_xfer_support = true,
1382 	.has_per_pkt_xfer_complete_irq = true,
1383 	.has_single_clk_source = true,
1384 	.clk_divisor_hs_mode = 1,
1385 	.clk_divisor_std_mode = 0x19,
1386 	.clk_divisor_fast_mode = 0x19,
1387 	.clk_divisor_fast_plus_mode = 0x10,
1388 	.has_config_load_reg = true,
1389 	.has_multi_master_mode = false,
1390 	.has_slcg_override_reg = true,
1391 	.has_mst_fifo = false,
1392 	.quirks = &tegra_i2c_quirks,
1393 	.supports_bus_clear = true,
1394 	.has_apb_dma = true,
1395 	.tlow_std_mode = 0x4,
1396 	.thigh_std_mode = 0x2,
1397 	.tlow_fast_fastplus_mode = 0x4,
1398 	.thigh_fast_fastplus_mode = 0x2,
1399 	.setup_hold_time_std_mode = 0x0,
1400 	.setup_hold_time_fast_fast_plus_mode = 0x0,
1401 	.setup_hold_time_hs_mode = 0x0,
1402 	.has_interface_timing_reg = true,
1403 };
1404 
1405 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1406 	.has_continue_xfer_support = true,
1407 	.has_per_pkt_xfer_complete_irq = true,
1408 	.has_single_clk_source = true,
1409 	.clk_divisor_hs_mode = 1,
1410 	.clk_divisor_std_mode = 0x19,
1411 	.clk_divisor_fast_mode = 0x19,
1412 	.clk_divisor_fast_plus_mode = 0x10,
1413 	.has_config_load_reg = true,
1414 	.has_multi_master_mode = false,
1415 	.has_slcg_override_reg = true,
1416 	.has_mst_fifo = false,
1417 	.quirks = &tegra_i2c_quirks,
1418 	.supports_bus_clear = true,
1419 	.has_apb_dma = true,
1420 	.tlow_std_mode = 0x4,
1421 	.thigh_std_mode = 0x2,
1422 	.tlow_fast_fastplus_mode = 0x4,
1423 	.thigh_fast_fastplus_mode = 0x2,
1424 	.setup_hold_time_std_mode = 0,
1425 	.setup_hold_time_fast_fast_plus_mode = 0,
1426 	.setup_hold_time_hs_mode = 0,
1427 	.has_interface_timing_reg = true,
1428 };
1429 
1430 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1431 	.has_continue_xfer_support = true,
1432 	.has_per_pkt_xfer_complete_irq = true,
1433 	.has_single_clk_source = true,
1434 	.clk_divisor_hs_mode = 1,
1435 	.clk_divisor_std_mode = 0x16,
1436 	.clk_divisor_fast_mode = 0x19,
1437 	.clk_divisor_fast_plus_mode = 0x10,
1438 	.has_config_load_reg = true,
1439 	.has_multi_master_mode = false,
1440 	.has_slcg_override_reg = true,
1441 	.has_mst_fifo = false,
1442 	.quirks = &tegra_i2c_quirks,
1443 	.supports_bus_clear = true,
1444 	.has_apb_dma = false,
1445 	.tlow_std_mode = 0x4,
1446 	.thigh_std_mode = 0x3,
1447 	.tlow_fast_fastplus_mode = 0x4,
1448 	.thigh_fast_fastplus_mode = 0x2,
1449 	.setup_hold_time_std_mode = 0,
1450 	.setup_hold_time_fast_fast_plus_mode = 0,
1451 	.setup_hold_time_hs_mode = 0,
1452 	.has_interface_timing_reg = true,
1453 };
1454 
1455 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1456 	.has_continue_xfer_support = true,
1457 	.has_per_pkt_xfer_complete_irq = true,
1458 	.has_single_clk_source = true,
1459 	.clk_divisor_hs_mode = 1,
1460 	.clk_divisor_std_mode = 0x4f,
1461 	.clk_divisor_fast_mode = 0x3c,
1462 	.clk_divisor_fast_plus_mode = 0x16,
1463 	.has_config_load_reg = true,
1464 	.has_multi_master_mode = true,
1465 	.has_slcg_override_reg = true,
1466 	.has_mst_fifo = true,
1467 	.quirks = &tegra194_i2c_quirks,
1468 	.supports_bus_clear = true,
1469 	.has_apb_dma = false,
1470 	.tlow_std_mode = 0x8,
1471 	.thigh_std_mode = 0x7,
1472 	.tlow_fast_fastplus_mode = 0x2,
1473 	.thigh_fast_fastplus_mode = 0x2,
1474 	.setup_hold_time_std_mode = 0x08080808,
1475 	.setup_hold_time_fast_fast_plus_mode = 0x02020202,
1476 	.setup_hold_time_hs_mode = 0x090909,
1477 	.has_interface_timing_reg = true,
1478 };
1479 
1480 /* Match table for of_platform binding */
1481 static const struct of_device_id tegra_i2c_of_match[] = {
1482 	{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1483 	{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1484 	{ .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1485 	{ .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1486 	{ .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1487 	{ .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1488 	{ .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1489 	{ .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1490 	{},
1491 };
1492 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1493 
1494 static int tegra_i2c_probe(struct platform_device *pdev)
1495 {
1496 	struct tegra_i2c_dev *i2c_dev;
1497 	struct resource *res;
1498 	struct clk *div_clk;
1499 	struct clk *fast_clk;
1500 	void __iomem *base;
1501 	phys_addr_t base_phys;
1502 	int irq;
1503 	int ret = 0;
1504 
1505 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1506 	base_phys = res->start;
1507 	base = devm_ioremap_resource(&pdev->dev, res);
1508 	if (IS_ERR(base))
1509 		return PTR_ERR(base);
1510 
1511 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1512 	if (!res) {
1513 		dev_err(&pdev->dev, "no irq resource\n");
1514 		return -EINVAL;
1515 	}
1516 	irq = res->start;
1517 
1518 	div_clk = devm_clk_get(&pdev->dev, "div-clk");
1519 	if (IS_ERR(div_clk)) {
1520 		dev_err(&pdev->dev, "missing controller clock\n");
1521 		return PTR_ERR(div_clk);
1522 	}
1523 
1524 	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1525 	if (!i2c_dev)
1526 		return -ENOMEM;
1527 
1528 	i2c_dev->base = base;
1529 	i2c_dev->base_phys = base_phys;
1530 	i2c_dev->div_clk = div_clk;
1531 	i2c_dev->adapter.algo = &tegra_i2c_algo;
1532 	i2c_dev->adapter.retries = 1;
1533 	i2c_dev->adapter.timeout = 6 * HZ;
1534 	i2c_dev->irq = irq;
1535 	i2c_dev->cont_id = pdev->id;
1536 	i2c_dev->dev = &pdev->dev;
1537 
1538 	i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
1539 	if (IS_ERR(i2c_dev->rst)) {
1540 		dev_err(&pdev->dev, "missing controller reset\n");
1541 		return PTR_ERR(i2c_dev->rst);
1542 	}
1543 
1544 	tegra_i2c_parse_dt(i2c_dev);
1545 
1546 	i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1547 	i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1548 						  "nvidia,tegra20-i2c-dvc");
1549 	i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1550 	i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len +
1551 				I2C_PACKET_HEADER_SIZE;
1552 	init_completion(&i2c_dev->msg_complete);
1553 	init_completion(&i2c_dev->dma_complete);
1554 	spin_lock_init(&i2c_dev->xfer_lock);
1555 
1556 	if (!i2c_dev->hw->has_single_clk_source) {
1557 		fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1558 		if (IS_ERR(fast_clk)) {
1559 			dev_err(&pdev->dev, "missing fast clock\n");
1560 			return PTR_ERR(fast_clk);
1561 		}
1562 		i2c_dev->fast_clk = fast_clk;
1563 	}
1564 
1565 	platform_set_drvdata(pdev, i2c_dev);
1566 
1567 	if (!i2c_dev->hw->has_single_clk_source) {
1568 		ret = clk_prepare(i2c_dev->fast_clk);
1569 		if (ret < 0) {
1570 			dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1571 			return ret;
1572 		}
1573 	}
1574 
1575 	if (i2c_dev->bus_clk_rate > I2C_FAST_MODE &&
1576 	    i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE)
1577 		i2c_dev->clk_divisor_non_hs_mode =
1578 				i2c_dev->hw->clk_divisor_fast_plus_mode;
1579 	else if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
1580 		 i2c_dev->bus_clk_rate <= I2C_FAST_MODE)
1581 		i2c_dev->clk_divisor_non_hs_mode =
1582 				i2c_dev->hw->clk_divisor_fast_mode;
1583 	else
1584 		i2c_dev->clk_divisor_non_hs_mode =
1585 				i2c_dev->hw->clk_divisor_std_mode;
1586 
1587 	ret = clk_prepare(i2c_dev->div_clk);
1588 	if (ret < 0) {
1589 		dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1590 		goto unprepare_fast_clk;
1591 	}
1592 
1593 	pm_runtime_enable(&pdev->dev);
1594 	if (!pm_runtime_enabled(&pdev->dev)) {
1595 		ret = tegra_i2c_runtime_resume(&pdev->dev);
1596 		if (ret < 0) {
1597 			dev_err(&pdev->dev, "runtime resume failed\n");
1598 			goto unprepare_div_clk;
1599 		}
1600 	}
1601 
1602 	if (i2c_dev->is_multimaster_mode) {
1603 		ret = clk_enable(i2c_dev->div_clk);
1604 		if (ret < 0) {
1605 			dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
1606 				ret);
1607 			goto disable_rpm;
1608 		}
1609 	}
1610 
1611 	if (i2c_dev->hw->supports_bus_clear)
1612 		i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1613 
1614 	ret = tegra_i2c_init_dma(i2c_dev);
1615 	if (ret < 0)
1616 		goto disable_div_clk;
1617 
1618 	ret = tegra_i2c_init(i2c_dev, false);
1619 	if (ret) {
1620 		dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1621 		goto release_dma;
1622 	}
1623 
1624 	ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1625 			tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
1626 	if (ret) {
1627 		dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1628 		goto release_dma;
1629 	}
1630 
1631 	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1632 	i2c_dev->adapter.owner = THIS_MODULE;
1633 	i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1634 	strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1635 		sizeof(i2c_dev->adapter.name));
1636 	i2c_dev->adapter.dev.parent = &pdev->dev;
1637 	i2c_dev->adapter.nr = pdev->id;
1638 	i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1639 
1640 	ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1641 	if (ret)
1642 		goto release_dma;
1643 
1644 	return 0;
1645 
1646 release_dma:
1647 	tegra_i2c_release_dma(i2c_dev);
1648 
1649 disable_div_clk:
1650 	if (i2c_dev->is_multimaster_mode)
1651 		clk_disable(i2c_dev->div_clk);
1652 
1653 disable_rpm:
1654 	pm_runtime_disable(&pdev->dev);
1655 	if (!pm_runtime_status_suspended(&pdev->dev))
1656 		tegra_i2c_runtime_suspend(&pdev->dev);
1657 
1658 unprepare_div_clk:
1659 	clk_unprepare(i2c_dev->div_clk);
1660 
1661 unprepare_fast_clk:
1662 	if (!i2c_dev->hw->has_single_clk_source)
1663 		clk_unprepare(i2c_dev->fast_clk);
1664 
1665 	return ret;
1666 }
1667 
1668 static int tegra_i2c_remove(struct platform_device *pdev)
1669 {
1670 	struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1671 
1672 	i2c_del_adapter(&i2c_dev->adapter);
1673 
1674 	if (i2c_dev->is_multimaster_mode)
1675 		clk_disable(i2c_dev->div_clk);
1676 
1677 	pm_runtime_disable(&pdev->dev);
1678 	if (!pm_runtime_status_suspended(&pdev->dev))
1679 		tegra_i2c_runtime_suspend(&pdev->dev);
1680 
1681 	clk_unprepare(i2c_dev->div_clk);
1682 	if (!i2c_dev->hw->has_single_clk_source)
1683 		clk_unprepare(i2c_dev->fast_clk);
1684 
1685 	tegra_i2c_release_dma(i2c_dev);
1686 	return 0;
1687 }
1688 
1689 #ifdef CONFIG_PM_SLEEP
1690 static const struct dev_pm_ops tegra_i2c_pm = {
1691 	SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1692 			   NULL)
1693 };
1694 #define TEGRA_I2C_PM	(&tegra_i2c_pm)
1695 #else
1696 #define TEGRA_I2C_PM	NULL
1697 #endif
1698 
1699 static struct platform_driver tegra_i2c_driver = {
1700 	.probe   = tegra_i2c_probe,
1701 	.remove  = tegra_i2c_remove,
1702 	.driver  = {
1703 		.name  = "tegra-i2c",
1704 		.of_match_table = tegra_i2c_of_match,
1705 		.pm    = TEGRA_I2C_PM,
1706 	},
1707 };
1708 
1709 module_platform_driver(tegra_i2c_driver);
1710 
1711 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1712 MODULE_AUTHOR("Colin Cross");
1713 MODULE_LICENSE("GPL v2");
1714