1 /* 2 * drivers/i2c/busses/i2c-tegra.c 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * Author: Colin Cross <ccross@android.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/err.h> 23 #include <linux/i2c.h> 24 #include <linux/io.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 #include <linux/of_device.h> 29 #include <linux/module.h> 30 #include <linux/reset.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/iopoll.h> 34 35 #include <asm/unaligned.h> 36 37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 38 #define BYTES_PER_FIFO_WORD 4 39 40 #define I2C_CNFG 0x000 41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 42 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 43 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 44 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 45 #define I2C_STATUS 0x01C 46 #define I2C_SL_CNFG 0x020 47 #define I2C_SL_CNFG_NACK BIT(1) 48 #define I2C_SL_CNFG_NEWSL BIT(2) 49 #define I2C_SL_ADDR1 0x02c 50 #define I2C_SL_ADDR2 0x030 51 #define I2C_TX_FIFO 0x050 52 #define I2C_RX_FIFO 0x054 53 #define I2C_PACKET_TRANSFER_STATUS 0x058 54 #define I2C_FIFO_CONTROL 0x05c 55 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 56 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 59 #define I2C_FIFO_STATUS 0x060 60 #define I2C_FIFO_STATUS_TX_MASK 0xF0 61 #define I2C_FIFO_STATUS_TX_SHIFT 4 62 #define I2C_FIFO_STATUS_RX_MASK 0x0F 63 #define I2C_FIFO_STATUS_RX_SHIFT 0 64 #define I2C_INT_MASK 0x064 65 #define I2C_INT_STATUS 0x068 66 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6) 68 #define I2C_INT_TX_FIFO_OVERFLOW BIT(5) 69 #define I2C_INT_RX_FIFO_UNDERFLOW BIT(4) 70 #define I2C_INT_NO_ACK BIT(3) 71 #define I2C_INT_ARBITRATION_LOST BIT(2) 72 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 73 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 74 #define I2C_CLK_DIVISOR 0x06c 75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 77 78 #define DVC_CTRL_REG1 0x000 79 #define DVC_CTRL_REG1_INTR_EN BIT(10) 80 #define DVC_CTRL_REG2 0x004 81 #define DVC_CTRL_REG3 0x008 82 #define DVC_CTRL_REG3_SW_PROG BIT(26) 83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 84 #define DVC_STATUS 0x00c 85 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 86 87 #define I2C_ERR_NONE 0x00 88 #define I2C_ERR_NO_ACK 0x01 89 #define I2C_ERR_ARBITRATION_LOST 0x02 90 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 91 92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 93 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 94 #define PACKET_HEADER0_CONT_ID_SHIFT 12 95 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4) 96 97 #define I2C_HEADER_HIGHSPEED_MODE BIT(22) 98 #define I2C_HEADER_CONT_ON_NAK BIT(21) 99 #define I2C_HEADER_SEND_START_BYTE BIT(20) 100 #define I2C_HEADER_READ BIT(19) 101 #define I2C_HEADER_10BIT_ADDR BIT(18) 102 #define I2C_HEADER_IE_ENABLE BIT(17) 103 #define I2C_HEADER_REPEAT_START BIT(16) 104 #define I2C_HEADER_CONTINUE_XFER BIT(15) 105 #define I2C_HEADER_MASTER_ADDR_SHIFT 12 106 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 107 108 #define I2C_CONFIG_LOAD 0x08C 109 #define I2C_MSTR_CONFIG_LOAD BIT(0) 110 #define I2C_SLV_CONFIG_LOAD BIT(1) 111 #define I2C_TIMEOUT_CONFIG_LOAD BIT(2) 112 113 #define I2C_CLKEN_OVERRIDE 0x090 114 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 115 116 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 117 118 /* 119 * msg_end_type: The bus control which need to be send at end of transfer. 120 * @MSG_END_STOP: Send stop pulse at end of transfer. 121 * @MSG_END_REPEAT_START: Send repeat start at end of transfer. 122 * @MSG_END_CONTINUE: The following on message is coming and so do not send 123 * stop or repeat start. 124 */ 125 enum msg_end_type { 126 MSG_END_STOP, 127 MSG_END_REPEAT_START, 128 MSG_END_CONTINUE, 129 }; 130 131 /** 132 * struct tegra_i2c_hw_feature : Different HW support on Tegra 133 * @has_continue_xfer_support: Continue transfer supports. 134 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 135 * complete interrupt per packet basis. 136 * @has_single_clk_source: The i2c controller has single clock source. Tegra30 137 * and earlier Socs has two clock sources i.e. div-clk and 138 * fast-clk. 139 * @has_config_load_reg: Has the config load register to load the new 140 * configuration. 141 * @clk_divisor_hs_mode: Clock divisor in HS mode. 142 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is 143 * applicable if there is no fast clock source i.e. single clock 144 * source. 145 */ 146 147 struct tegra_i2c_hw_feature { 148 bool has_continue_xfer_support; 149 bool has_per_pkt_xfer_complete_irq; 150 bool has_single_clk_source; 151 bool has_config_load_reg; 152 int clk_divisor_hs_mode; 153 int clk_divisor_std_fast_mode; 154 u16 clk_divisor_fast_plus_mode; 155 bool has_multi_master_mode; 156 bool has_slcg_override_reg; 157 }; 158 159 /** 160 * struct tegra_i2c_dev - per device i2c context 161 * @dev: device reference for power management 162 * @hw: Tegra i2c hw feature. 163 * @adapter: core i2c layer adapter information 164 * @div_clk: clock reference for div clock of i2c controller. 165 * @fast_clk: clock reference for fast clock of i2c controller. 166 * @base: ioremapped registers cookie 167 * @cont_id: i2c controller id, used for for packet header 168 * @irq: irq number of transfer complete interrupt 169 * @is_dvc: identifies the DVC i2c controller, has a different register layout 170 * @msg_complete: transfer completion notifier 171 * @msg_err: error code for completed message 172 * @msg_buf: pointer to current message data 173 * @msg_buf_remaining: size of unsent data in the message buffer 174 * @msg_read: identifies read transfers 175 * @bus_clk_rate: current i2c bus clock rate 176 */ 177 struct tegra_i2c_dev { 178 struct device *dev; 179 const struct tegra_i2c_hw_feature *hw; 180 struct i2c_adapter adapter; 181 struct clk *div_clk; 182 struct clk *fast_clk; 183 struct reset_control *rst; 184 void __iomem *base; 185 int cont_id; 186 int irq; 187 bool irq_disabled; 188 int is_dvc; 189 struct completion msg_complete; 190 int msg_err; 191 u8 *msg_buf; 192 size_t msg_buf_remaining; 193 int msg_read; 194 u32 bus_clk_rate; 195 u16 clk_divisor_non_hs_mode; 196 bool is_multimaster_mode; 197 spinlock_t xfer_lock; 198 }; 199 200 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 201 unsigned long reg) 202 { 203 writel(val, i2c_dev->base + reg); 204 } 205 206 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 207 { 208 return readl(i2c_dev->base + reg); 209 } 210 211 /* 212 * i2c_writel and i2c_readl will offset the register if necessary to talk 213 * to the I2C block inside the DVC block 214 */ 215 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 216 unsigned long reg) 217 { 218 if (i2c_dev->is_dvc) 219 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 220 return reg; 221 } 222 223 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 224 unsigned long reg) 225 { 226 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 227 228 /* Read back register to make sure that register writes completed */ 229 if (reg != I2C_TX_FIFO) 230 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 231 } 232 233 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 234 { 235 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 236 } 237 238 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 239 unsigned long reg, int len) 240 { 241 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 242 } 243 244 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 245 unsigned long reg, int len) 246 { 247 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 248 } 249 250 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 251 { 252 u32 int_mask; 253 254 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 255 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 256 } 257 258 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 259 { 260 u32 int_mask; 261 262 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 263 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 264 } 265 266 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 267 { 268 unsigned long timeout = jiffies + HZ; 269 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); 270 271 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; 272 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 273 274 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & 275 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { 276 if (time_after(jiffies, timeout)) { 277 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 278 return -ETIMEDOUT; 279 } 280 msleep(1); 281 } 282 return 0; 283 } 284 285 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 286 { 287 u32 val; 288 int rx_fifo_avail; 289 u8 *buf = i2c_dev->msg_buf; 290 size_t buf_remaining = i2c_dev->msg_buf_remaining; 291 int words_to_transfer; 292 293 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 294 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 295 I2C_FIFO_STATUS_RX_SHIFT; 296 297 /* Rounds down to not include partial word at the end of buf */ 298 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 299 if (words_to_transfer > rx_fifo_avail) 300 words_to_transfer = rx_fifo_avail; 301 302 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 303 304 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 305 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 306 rx_fifo_avail -= words_to_transfer; 307 308 /* 309 * If there is a partial word at the end of buf, handle it manually to 310 * prevent overwriting past the end of buf 311 */ 312 if (rx_fifo_avail > 0 && buf_remaining > 0) { 313 BUG_ON(buf_remaining > 3); 314 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 315 val = cpu_to_le32(val); 316 memcpy(buf, &val, buf_remaining); 317 buf_remaining = 0; 318 rx_fifo_avail--; 319 } 320 321 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); 322 i2c_dev->msg_buf_remaining = buf_remaining; 323 i2c_dev->msg_buf = buf; 324 return 0; 325 } 326 327 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 328 { 329 u32 val; 330 int tx_fifo_avail; 331 u8 *buf = i2c_dev->msg_buf; 332 size_t buf_remaining = i2c_dev->msg_buf_remaining; 333 int words_to_transfer; 334 335 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 336 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 337 I2C_FIFO_STATUS_TX_SHIFT; 338 339 /* Rounds down to not include partial word at the end of buf */ 340 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 341 342 /* It's very common to have < 4 bytes, so optimize that case. */ 343 if (words_to_transfer) { 344 if (words_to_transfer > tx_fifo_avail) 345 words_to_transfer = tx_fifo_avail; 346 347 /* 348 * Update state before writing to FIFO. If this casues us 349 * to finish writing all bytes (AKA buf_remaining goes to 0) we 350 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 351 * not maskable). We need to make sure that the isr sees 352 * buf_remaining as 0 and doesn't call us back re-entrantly. 353 */ 354 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 355 tx_fifo_avail -= words_to_transfer; 356 i2c_dev->msg_buf_remaining = buf_remaining; 357 i2c_dev->msg_buf = buf + 358 words_to_transfer * BYTES_PER_FIFO_WORD; 359 barrier(); 360 361 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 362 363 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 364 } 365 366 /* 367 * If there is a partial word at the end of buf, handle it manually to 368 * prevent reading past the end of buf, which could cross a page 369 * boundary and fault. 370 */ 371 if (tx_fifo_avail > 0 && buf_remaining > 0) { 372 BUG_ON(buf_remaining > 3); 373 memcpy(&val, buf, buf_remaining); 374 val = le32_to_cpu(val); 375 376 /* Again update before writing to FIFO to make sure isr sees. */ 377 i2c_dev->msg_buf_remaining = 0; 378 i2c_dev->msg_buf = NULL; 379 barrier(); 380 381 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 382 } 383 384 return 0; 385 } 386 387 /* 388 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 389 * block. This block is identical to the rest of the I2C blocks, except that 390 * it only supports master mode, it has registers moved around, and it needs 391 * some extra init to get it into I2C mode. The register moves are handled 392 * by i2c_readl and i2c_writel 393 */ 394 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 395 { 396 u32 val; 397 398 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 399 val |= DVC_CTRL_REG3_SW_PROG; 400 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 401 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 402 403 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 404 val |= DVC_CTRL_REG1_INTR_EN; 405 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 406 } 407 408 static int tegra_i2c_runtime_resume(struct device *dev) 409 { 410 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 411 int ret; 412 413 ret = pinctrl_pm_select_default_state(i2c_dev->dev); 414 if (ret) 415 return ret; 416 417 if (!i2c_dev->hw->has_single_clk_source) { 418 ret = clk_enable(i2c_dev->fast_clk); 419 if (ret < 0) { 420 dev_err(i2c_dev->dev, 421 "Enabling fast clk failed, err %d\n", ret); 422 return ret; 423 } 424 } 425 426 ret = clk_enable(i2c_dev->div_clk); 427 if (ret < 0) { 428 dev_err(i2c_dev->dev, 429 "Enabling div clk failed, err %d\n", ret); 430 clk_disable(i2c_dev->fast_clk); 431 return ret; 432 } 433 434 return 0; 435 } 436 437 static int tegra_i2c_runtime_suspend(struct device *dev) 438 { 439 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 440 441 clk_disable(i2c_dev->div_clk); 442 if (!i2c_dev->hw->has_single_clk_source) 443 clk_disable(i2c_dev->fast_clk); 444 445 return pinctrl_pm_select_idle_state(i2c_dev->dev); 446 } 447 448 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 449 { 450 unsigned long reg_offset; 451 void __iomem *addr; 452 u32 val; 453 int err; 454 455 if (i2c_dev->hw->has_config_load_reg) { 456 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); 457 addr = i2c_dev->base + reg_offset; 458 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 459 if (in_interrupt()) 460 err = readl_poll_timeout_atomic(addr, val, val == 0, 461 1000, I2C_CONFIG_LOAD_TIMEOUT); 462 else 463 err = readl_poll_timeout(addr, val, val == 0, 464 1000, I2C_CONFIG_LOAD_TIMEOUT); 465 466 if (err) { 467 dev_warn(i2c_dev->dev, 468 "timeout waiting for config load\n"); 469 return err; 470 } 471 } 472 473 return 0; 474 } 475 476 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 477 { 478 u32 val; 479 int err; 480 u32 clk_divisor; 481 482 err = pm_runtime_get_sync(i2c_dev->dev); 483 if (err < 0) { 484 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err); 485 return err; 486 } 487 488 reset_control_assert(i2c_dev->rst); 489 udelay(2); 490 reset_control_deassert(i2c_dev->rst); 491 492 if (i2c_dev->is_dvc) 493 tegra_dvc_init(i2c_dev); 494 495 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 496 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 497 498 if (i2c_dev->hw->has_multi_master_mode) 499 val |= I2C_CNFG_MULTI_MASTER_MODE; 500 501 i2c_writel(i2c_dev, val, I2C_CNFG); 502 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 503 504 /* Make sure clock divisor programmed correctly */ 505 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; 506 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << 507 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; 508 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 509 510 if (!i2c_dev->is_dvc) { 511 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 512 513 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 514 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 515 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 516 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 517 } 518 519 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | 520 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; 521 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 522 523 err = tegra_i2c_flush_fifos(i2c_dev); 524 if (err) 525 goto err; 526 527 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 528 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 529 530 err = tegra_i2c_wait_for_config_load(i2c_dev); 531 if (err) 532 goto err; 533 534 if (i2c_dev->irq_disabled) { 535 i2c_dev->irq_disabled = false; 536 enable_irq(i2c_dev->irq); 537 } 538 539 err: 540 pm_runtime_put(i2c_dev->dev); 541 return err; 542 } 543 544 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 545 { 546 u32 cnfg; 547 548 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 549 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 550 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 551 552 return tegra_i2c_wait_for_config_load(i2c_dev); 553 } 554 555 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 556 { 557 u32 status; 558 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 559 struct tegra_i2c_dev *i2c_dev = dev_id; 560 unsigned long flags; 561 562 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 563 564 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); 565 if (status == 0) { 566 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 567 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 568 i2c_readl(i2c_dev, I2C_STATUS), 569 i2c_readl(i2c_dev, I2C_CNFG)); 570 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 571 572 if (!i2c_dev->irq_disabled) { 573 disable_irq_nosync(i2c_dev->irq); 574 i2c_dev->irq_disabled = true; 575 } 576 goto err; 577 } 578 579 if (unlikely(status & status_err)) { 580 tegra_i2c_disable_packet_mode(i2c_dev); 581 if (status & I2C_INT_NO_ACK) 582 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 583 if (status & I2C_INT_ARBITRATION_LOST) 584 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 585 goto err; 586 } 587 588 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 589 if (i2c_dev->msg_buf_remaining) 590 tegra_i2c_empty_rx_fifo(i2c_dev); 591 else 592 BUG(); 593 } 594 595 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 596 if (i2c_dev->msg_buf_remaining) 597 tegra_i2c_fill_tx_fifo(i2c_dev); 598 else 599 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); 600 } 601 602 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 603 if (i2c_dev->is_dvc) 604 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 605 606 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 607 BUG_ON(i2c_dev->msg_buf_remaining); 608 complete(&i2c_dev->msg_complete); 609 } 610 goto done; 611 err: 612 /* An error occurred, mask all interrupts */ 613 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 614 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 615 I2C_INT_RX_FIFO_DATA_REQ); 616 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 617 if (i2c_dev->is_dvc) 618 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 619 620 complete(&i2c_dev->msg_complete); 621 done: 622 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); 623 return IRQ_HANDLED; 624 } 625 626 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 627 struct i2c_msg *msg, enum msg_end_type end_state) 628 { 629 u32 packet_header; 630 u32 int_mask; 631 unsigned long time_left; 632 unsigned long flags; 633 634 tegra_i2c_flush_fifos(i2c_dev); 635 636 if (msg->len == 0) 637 return -EINVAL; 638 639 i2c_dev->msg_buf = msg->buf; 640 i2c_dev->msg_buf_remaining = msg->len; 641 i2c_dev->msg_err = I2C_ERR_NONE; 642 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 643 reinit_completion(&i2c_dev->msg_complete); 644 645 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); 646 647 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 648 tegra_i2c_unmask_irq(i2c_dev, int_mask); 649 650 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 651 PACKET_HEADER0_PROTOCOL_I2C | 652 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 653 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 654 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 655 656 packet_header = msg->len - 1; 657 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 658 659 packet_header = I2C_HEADER_IE_ENABLE; 660 if (end_state == MSG_END_CONTINUE) 661 packet_header |= I2C_HEADER_CONTINUE_XFER; 662 else if (end_state == MSG_END_REPEAT_START) 663 packet_header |= I2C_HEADER_REPEAT_START; 664 if (msg->flags & I2C_M_TEN) { 665 packet_header |= msg->addr; 666 packet_header |= I2C_HEADER_10BIT_ADDR; 667 } else { 668 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 669 } 670 if (msg->flags & I2C_M_IGNORE_NAK) 671 packet_header |= I2C_HEADER_CONT_ON_NAK; 672 if (msg->flags & I2C_M_RD) 673 packet_header |= I2C_HEADER_READ; 674 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 675 676 if (!(msg->flags & I2C_M_RD)) 677 tegra_i2c_fill_tx_fifo(i2c_dev); 678 679 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 680 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 681 if (msg->flags & I2C_M_RD) 682 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 683 else if (i2c_dev->msg_buf_remaining) 684 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 685 686 tegra_i2c_unmask_irq(i2c_dev, int_mask); 687 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); 688 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 689 i2c_readl(i2c_dev, I2C_INT_MASK)); 690 691 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 692 TEGRA_I2C_TIMEOUT); 693 tegra_i2c_mask_irq(i2c_dev, int_mask); 694 695 if (time_left == 0) { 696 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 697 698 tegra_i2c_init(i2c_dev); 699 return -ETIMEDOUT; 700 } 701 702 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 703 time_left, completion_done(&i2c_dev->msg_complete), 704 i2c_dev->msg_err); 705 706 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 707 return 0; 708 709 /* 710 * NACK interrupt is generated before the I2C controller generates 711 * the STOP condition on the bus. So wait for 2 clock periods 712 * before resetting the controller so that the STOP condition has 713 * been delivered properly. 714 */ 715 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) 716 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 717 718 tegra_i2c_init(i2c_dev); 719 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 720 if (msg->flags & I2C_M_IGNORE_NAK) 721 return 0; 722 return -EREMOTEIO; 723 } 724 725 return -EIO; 726 } 727 728 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 729 int num) 730 { 731 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 732 int i; 733 int ret = 0; 734 735 ret = pm_runtime_get_sync(i2c_dev->dev); 736 if (ret < 0) { 737 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 738 return ret; 739 } 740 741 for (i = 0; i < num; i++) { 742 enum msg_end_type end_type = MSG_END_STOP; 743 744 if (i < (num - 1)) { 745 if (msgs[i + 1].flags & I2C_M_NOSTART) 746 end_type = MSG_END_CONTINUE; 747 else 748 end_type = MSG_END_REPEAT_START; 749 } 750 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 751 if (ret) 752 break; 753 } 754 755 pm_runtime_put(i2c_dev->dev); 756 757 return ret ?: i; 758 } 759 760 static u32 tegra_i2c_func(struct i2c_adapter *adap) 761 { 762 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 763 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 764 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 765 766 if (i2c_dev->hw->has_continue_xfer_support) 767 ret |= I2C_FUNC_NOSTART; 768 return ret; 769 } 770 771 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 772 { 773 struct device_node *np = i2c_dev->dev->of_node; 774 int ret; 775 776 ret = of_property_read_u32(np, "clock-frequency", 777 &i2c_dev->bus_clk_rate); 778 if (ret) 779 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ 780 781 i2c_dev->is_multimaster_mode = of_property_read_bool(np, 782 "multi-master"); 783 } 784 785 static const struct i2c_algorithm tegra_i2c_algo = { 786 .master_xfer = tegra_i2c_xfer, 787 .functionality = tegra_i2c_func, 788 }; 789 790 /* payload size is only 12 bit */ 791 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 792 .max_read_len = 4096, 793 .max_write_len = 4096, 794 }; 795 796 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 797 .has_continue_xfer_support = false, 798 .has_per_pkt_xfer_complete_irq = false, 799 .has_single_clk_source = false, 800 .clk_divisor_hs_mode = 3, 801 .clk_divisor_std_fast_mode = 0, 802 .clk_divisor_fast_plus_mode = 0, 803 .has_config_load_reg = false, 804 .has_multi_master_mode = false, 805 .has_slcg_override_reg = false, 806 }; 807 808 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 809 .has_continue_xfer_support = true, 810 .has_per_pkt_xfer_complete_irq = false, 811 .has_single_clk_source = false, 812 .clk_divisor_hs_mode = 3, 813 .clk_divisor_std_fast_mode = 0, 814 .clk_divisor_fast_plus_mode = 0, 815 .has_config_load_reg = false, 816 .has_multi_master_mode = false, 817 .has_slcg_override_reg = false, 818 }; 819 820 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 821 .has_continue_xfer_support = true, 822 .has_per_pkt_xfer_complete_irq = true, 823 .has_single_clk_source = true, 824 .clk_divisor_hs_mode = 1, 825 .clk_divisor_std_fast_mode = 0x19, 826 .clk_divisor_fast_plus_mode = 0x10, 827 .has_config_load_reg = false, 828 .has_multi_master_mode = false, 829 .has_slcg_override_reg = false, 830 }; 831 832 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 833 .has_continue_xfer_support = true, 834 .has_per_pkt_xfer_complete_irq = true, 835 .has_single_clk_source = true, 836 .clk_divisor_hs_mode = 1, 837 .clk_divisor_std_fast_mode = 0x19, 838 .clk_divisor_fast_plus_mode = 0x10, 839 .has_config_load_reg = true, 840 .has_multi_master_mode = false, 841 .has_slcg_override_reg = true, 842 }; 843 844 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 845 .has_continue_xfer_support = true, 846 .has_per_pkt_xfer_complete_irq = true, 847 .has_single_clk_source = true, 848 .clk_divisor_hs_mode = 1, 849 .clk_divisor_std_fast_mode = 0x19, 850 .clk_divisor_fast_plus_mode = 0x10, 851 .has_config_load_reg = true, 852 .has_multi_master_mode = true, 853 .has_slcg_override_reg = true, 854 }; 855 856 /* Match table for of_platform binding */ 857 static const struct of_device_id tegra_i2c_of_match[] = { 858 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 859 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 860 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 861 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 862 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 863 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 864 {}, 865 }; 866 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 867 868 static int tegra_i2c_probe(struct platform_device *pdev) 869 { 870 struct tegra_i2c_dev *i2c_dev; 871 struct resource *res; 872 struct clk *div_clk; 873 struct clk *fast_clk; 874 void __iomem *base; 875 int irq; 876 int ret = 0; 877 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE; 878 879 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 880 base = devm_ioremap_resource(&pdev->dev, res); 881 if (IS_ERR(base)) 882 return PTR_ERR(base); 883 884 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 885 if (!res) { 886 dev_err(&pdev->dev, "no irq resource\n"); 887 return -EINVAL; 888 } 889 irq = res->start; 890 891 div_clk = devm_clk_get(&pdev->dev, "div-clk"); 892 if (IS_ERR(div_clk)) { 893 dev_err(&pdev->dev, "missing controller clock\n"); 894 return PTR_ERR(div_clk); 895 } 896 897 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 898 if (!i2c_dev) 899 return -ENOMEM; 900 901 i2c_dev->base = base; 902 i2c_dev->div_clk = div_clk; 903 i2c_dev->adapter.algo = &tegra_i2c_algo; 904 i2c_dev->adapter.quirks = &tegra_i2c_quirks; 905 i2c_dev->irq = irq; 906 i2c_dev->cont_id = pdev->id; 907 i2c_dev->dev = &pdev->dev; 908 909 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); 910 if (IS_ERR(i2c_dev->rst)) { 911 dev_err(&pdev->dev, "missing controller reset\n"); 912 return PTR_ERR(i2c_dev->rst); 913 } 914 915 tegra_i2c_parse_dt(i2c_dev); 916 917 i2c_dev->hw = of_device_get_match_data(&pdev->dev); 918 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 919 "nvidia,tegra20-i2c-dvc"); 920 init_completion(&i2c_dev->msg_complete); 921 spin_lock_init(&i2c_dev->xfer_lock); 922 923 if (!i2c_dev->hw->has_single_clk_source) { 924 fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); 925 if (IS_ERR(fast_clk)) { 926 dev_err(&pdev->dev, "missing fast clock\n"); 927 return PTR_ERR(fast_clk); 928 } 929 i2c_dev->fast_clk = fast_clk; 930 } 931 932 platform_set_drvdata(pdev, i2c_dev); 933 934 if (!i2c_dev->hw->has_single_clk_source) { 935 ret = clk_prepare(i2c_dev->fast_clk); 936 if (ret < 0) { 937 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 938 return ret; 939 } 940 } 941 942 i2c_dev->clk_divisor_non_hs_mode = 943 i2c_dev->hw->clk_divisor_std_fast_mode; 944 if (i2c_dev->hw->clk_divisor_fast_plus_mode && 945 (i2c_dev->bus_clk_rate == 1000000)) 946 i2c_dev->clk_divisor_non_hs_mode = 947 i2c_dev->hw->clk_divisor_fast_plus_mode; 948 949 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); 950 ret = clk_set_rate(i2c_dev->div_clk, 951 i2c_dev->bus_clk_rate * clk_multiplier); 952 if (ret) { 953 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret); 954 goto unprepare_fast_clk; 955 } 956 957 ret = clk_prepare(i2c_dev->div_clk); 958 if (ret < 0) { 959 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 960 goto unprepare_fast_clk; 961 } 962 963 pm_runtime_enable(&pdev->dev); 964 if (!pm_runtime_enabled(&pdev->dev)) { 965 ret = tegra_i2c_runtime_resume(&pdev->dev); 966 if (ret < 0) { 967 dev_err(&pdev->dev, "runtime resume failed\n"); 968 goto unprepare_div_clk; 969 } 970 } 971 972 if (i2c_dev->is_multimaster_mode) { 973 ret = clk_enable(i2c_dev->div_clk); 974 if (ret < 0) { 975 dev_err(i2c_dev->dev, "div_clk enable failed %d\n", 976 ret); 977 goto disable_rpm; 978 } 979 } 980 981 ret = tegra_i2c_init(i2c_dev); 982 if (ret) { 983 dev_err(&pdev->dev, "Failed to initialize i2c controller\n"); 984 goto disable_div_clk; 985 } 986 987 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 988 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); 989 if (ret) { 990 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 991 goto disable_div_clk; 992 } 993 994 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 995 i2c_dev->adapter.owner = THIS_MODULE; 996 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 997 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev), 998 sizeof(i2c_dev->adapter.name)); 999 i2c_dev->adapter.dev.parent = &pdev->dev; 1000 i2c_dev->adapter.nr = pdev->id; 1001 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 1002 1003 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 1004 if (ret) 1005 goto disable_div_clk; 1006 1007 return 0; 1008 1009 disable_div_clk: 1010 if (i2c_dev->is_multimaster_mode) 1011 clk_disable(i2c_dev->div_clk); 1012 1013 disable_rpm: 1014 pm_runtime_disable(&pdev->dev); 1015 if (!pm_runtime_status_suspended(&pdev->dev)) 1016 tegra_i2c_runtime_suspend(&pdev->dev); 1017 1018 unprepare_div_clk: 1019 clk_unprepare(i2c_dev->div_clk); 1020 1021 unprepare_fast_clk: 1022 if (!i2c_dev->hw->has_single_clk_source) 1023 clk_unprepare(i2c_dev->fast_clk); 1024 1025 return ret; 1026 } 1027 1028 static int tegra_i2c_remove(struct platform_device *pdev) 1029 { 1030 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1031 1032 i2c_del_adapter(&i2c_dev->adapter); 1033 1034 if (i2c_dev->is_multimaster_mode) 1035 clk_disable(i2c_dev->div_clk); 1036 1037 pm_runtime_disable(&pdev->dev); 1038 if (!pm_runtime_status_suspended(&pdev->dev)) 1039 tegra_i2c_runtime_suspend(&pdev->dev); 1040 1041 clk_unprepare(i2c_dev->div_clk); 1042 if (!i2c_dev->hw->has_single_clk_source) 1043 clk_unprepare(i2c_dev->fast_clk); 1044 1045 return 0; 1046 } 1047 1048 #ifdef CONFIG_PM_SLEEP 1049 static const struct dev_pm_ops tegra_i2c_pm = { 1050 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1051 NULL) 1052 }; 1053 #define TEGRA_I2C_PM (&tegra_i2c_pm) 1054 #else 1055 #define TEGRA_I2C_PM NULL 1056 #endif 1057 1058 static struct platform_driver tegra_i2c_driver = { 1059 .probe = tegra_i2c_probe, 1060 .remove = tegra_i2c_remove, 1061 .driver = { 1062 .name = "tegra-i2c", 1063 .of_match_table = tegra_i2c_of_match, 1064 .pm = TEGRA_I2C_PM, 1065 }, 1066 }; 1067 1068 static int __init tegra_i2c_init_driver(void) 1069 { 1070 return platform_driver_register(&tegra_i2c_driver); 1071 } 1072 1073 static void __exit tegra_i2c_exit_driver(void) 1074 { 1075 platform_driver_unregister(&tegra_i2c_driver); 1076 } 1077 1078 subsys_initcall(tegra_i2c_init_driver); 1079 module_exit(tegra_i2c_exit_driver); 1080 1081 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 1082 MODULE_AUTHOR("Colin Cross"); 1083 MODULE_LICENSE("GPL v2"); 1084