1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/kernel.h> 23 #include <linux/ktime.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/reset.h> 30 31 #define BYTES_PER_FIFO_WORD 4 32 33 #define I2C_CNFG 0x000 34 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 35 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 36 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 37 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 38 #define I2C_STATUS 0x01c 39 #define I2C_SL_CNFG 0x020 40 #define I2C_SL_CNFG_NACK BIT(1) 41 #define I2C_SL_CNFG_NEWSL BIT(2) 42 #define I2C_SL_ADDR1 0x02c 43 #define I2C_SL_ADDR2 0x030 44 #define I2C_TLOW_SEXT 0x034 45 #define I2C_TX_FIFO 0x050 46 #define I2C_RX_FIFO 0x054 47 #define I2C_PACKET_TRANSFER_STATUS 0x058 48 #define I2C_FIFO_CONTROL 0x05c 49 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 50 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 53 #define I2C_FIFO_STATUS 0x060 54 #define I2C_FIFO_STATUS_TX GENMASK(7, 4) 55 #define I2C_FIFO_STATUS_RX GENMASK(3, 0) 56 #define I2C_INT_MASK 0x064 57 #define I2C_INT_STATUS 0x068 58 #define I2C_INT_BUS_CLR_DONE BIT(11) 59 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 60 #define I2C_INT_NO_ACK BIT(3) 61 #define I2C_INT_ARBITRATION_LOST BIT(2) 62 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 63 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 64 #define I2C_CLK_DIVISOR 0x06c 65 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 66 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 67 68 #define DVC_CTRL_REG1 0x000 69 #define DVC_CTRL_REG1_INTR_EN BIT(10) 70 #define DVC_CTRL_REG3 0x008 71 #define DVC_CTRL_REG3_SW_PROG BIT(26) 72 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 73 #define DVC_STATUS 0x00c 74 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 75 76 #define I2C_ERR_NONE 0x00 77 #define I2C_ERR_NO_ACK BIT(0) 78 #define I2C_ERR_ARBITRATION_LOST BIT(1) 79 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 80 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 81 82 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28) 83 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16) 84 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12) 85 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 86 #define PACKET_HEADER0_PROTOCOL_I2C 1 87 88 #define I2C_HEADER_CONT_ON_NAK BIT(21) 89 #define I2C_HEADER_READ BIT(19) 90 #define I2C_HEADER_10BIT_ADDR BIT(18) 91 #define I2C_HEADER_IE_ENABLE BIT(17) 92 #define I2C_HEADER_REPEAT_START BIT(16) 93 #define I2C_HEADER_CONTINUE_XFER BIT(15) 94 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 95 96 #define I2C_BUS_CLEAR_CNFG 0x084 97 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 98 #define I2C_BC_STOP_COND BIT(2) 99 #define I2C_BC_TERMINATE BIT(1) 100 #define I2C_BC_ENABLE BIT(0) 101 #define I2C_BUS_CLEAR_STATUS 0x088 102 #define I2C_BC_STATUS BIT(0) 103 104 #define I2C_CONFIG_LOAD 0x08c 105 #define I2C_MSTR_CONFIG_LOAD BIT(0) 106 107 #define I2C_CLKEN_OVERRIDE 0x090 108 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 109 110 #define I2C_INTERFACE_TIMING_0 0x094 111 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 112 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 113 #define I2C_INTERFACE_TIMING_1 0x098 114 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 115 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 116 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 117 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 118 119 #define I2C_HS_INTERFACE_TIMING_0 0x09c 120 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 121 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 122 #define I2C_HS_INTERFACE_TIMING_1 0x0a0 123 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 124 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 125 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 126 127 #define I2C_MST_FIFO_CONTROL 0x0b4 128 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 129 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 132 133 #define I2C_MST_FIFO_STATUS 0x0b8 134 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 135 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 136 137 /* configuration load timeout in microseconds */ 138 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 139 140 /* packet header size in bytes */ 141 #define I2C_PACKET_HEADER_SIZE 12 142 143 /* 144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 145 * avoid DMA overhead, otherwise external APB DMA controller will be used. 146 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 147 * I2C_PACKET_HEADER_SIZE. 148 */ 149 #define I2C_PIO_MODE_PREFERRED_LEN 32 150 151 /* 152 * msg_end_type: The bus control which needs to be sent at end of transfer. 153 * @MSG_END_STOP: Send stop pulse. 154 * @MSG_END_REPEAT_START: Send repeat-start. 155 * @MSG_END_CONTINUE: Don't send stop or repeat-start. 156 */ 157 enum msg_end_type { 158 MSG_END_STOP, 159 MSG_END_REPEAT_START, 160 MSG_END_CONTINUE, 161 }; 162 163 /** 164 * struct tegra_i2c_hw_feature : per hardware generation features 165 * @has_continue_xfer_support: continue-transfer supported 166 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 167 * completion interrupt on per packet basis. 168 * @has_config_load_reg: Has the config load register to load the new 169 * configuration. 170 * @clk_divisor_hs_mode: Clock divisor in HS mode. 171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 172 * applicable if there is no fast clock source i.e. single clock 173 * source. 174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 175 * applicable if there is no fast clock source i.e. single clock 176 * source. 177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 178 * applicable if there is no fast clock source (i.e. single 179 * clock source). 180 * @has_multi_master_mode: The I2C controller supports running in single-master 181 * or multi-master mode. 182 * @has_slcg_override_reg: The I2C controller supports a register that 183 * overrides the second level clock gating. 184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 185 * provides additional features and allows for longer messages to 186 * be transferred in one go. 187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not 188 * allowing 0 length transfers. 189 * @supports_bus_clear: Bus Clear support to recover from bus hang during 190 * SDA stuck low from device for some unknown reasons. 191 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 192 * @tlow_std_mode: Low period of the clock in standard mode. 193 * @thigh_std_mode: High period of the clock in standard mode. 194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 196 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 197 * in standard mode. 198 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 199 * conditions in fast/fast-plus modes. 200 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 201 * in HS mode. 202 * @has_interface_timing_reg: Has interface timing register to program the tuned 203 * timing settings. 204 */ 205 struct tegra_i2c_hw_feature { 206 bool has_continue_xfer_support; 207 bool has_per_pkt_xfer_complete_irq; 208 bool has_config_load_reg; 209 u32 clk_divisor_hs_mode; 210 u32 clk_divisor_std_mode; 211 u32 clk_divisor_fast_mode; 212 u32 clk_divisor_fast_plus_mode; 213 bool has_multi_master_mode; 214 bool has_slcg_override_reg; 215 bool has_mst_fifo; 216 const struct i2c_adapter_quirks *quirks; 217 bool supports_bus_clear; 218 bool has_apb_dma; 219 u32 tlow_std_mode; 220 u32 thigh_std_mode; 221 u32 tlow_fast_fastplus_mode; 222 u32 thigh_fast_fastplus_mode; 223 u32 setup_hold_time_std_mode; 224 u32 setup_hold_time_fast_fast_plus_mode; 225 u32 setup_hold_time_hs_mode; 226 bool has_interface_timing_reg; 227 }; 228 229 /** 230 * struct tegra_i2c_dev - per device I2C context 231 * @dev: device reference for power management 232 * @hw: Tegra I2C HW feature 233 * @adapter: core I2C layer adapter information 234 * @div_clk: clock reference for div clock of I2C controller 235 * @clocks: array of I2C controller clocks 236 * @nclocks: number of clocks in the array 237 * @rst: reset control for the I2C controller 238 * @base: ioremapped registers cookie 239 * @base_phys: physical base address of the I2C controller 240 * @cont_id: I2C controller ID, used for packet header 241 * @irq: IRQ number of transfer complete interrupt 242 * @is_dvc: identifies the DVC I2C controller, has a different register layout 243 * @is_vi: identifies the VI I2C controller, has a different register layout 244 * @msg_complete: transfer completion notifier 245 * @msg_err: error code for completed message 246 * @msg_buf: pointer to current message data 247 * @msg_buf_remaining: size of unsent data in the message buffer 248 * @msg_read: indicates that the transfer is a read access 249 * @timings: i2c timings information like bus frequency 250 * @multimaster_mode: indicates that I2C controller is in multi-master mode 251 * @tx_dma_chan: DMA transmit channel 252 * @rx_dma_chan: DMA receive channel 253 * @dma_phys: handle to DMA resources 254 * @dma_buf: pointer to allocated DMA buffer 255 * @dma_buf_size: DMA buffer size 256 * @dma_mode: indicates active DMA transfer 257 * @dma_complete: DMA completion notifier 258 * @atomic_mode: indicates active atomic transfer 259 */ 260 struct tegra_i2c_dev { 261 struct device *dev; 262 struct i2c_adapter adapter; 263 264 const struct tegra_i2c_hw_feature *hw; 265 struct reset_control *rst; 266 unsigned int cont_id; 267 unsigned int irq; 268 269 phys_addr_t base_phys; 270 void __iomem *base; 271 272 struct clk_bulk_data clocks[2]; 273 unsigned int nclocks; 274 275 struct clk *div_clk; 276 struct i2c_timings timings; 277 278 struct completion msg_complete; 279 size_t msg_buf_remaining; 280 int msg_err; 281 u8 *msg_buf; 282 283 struct completion dma_complete; 284 struct dma_chan *tx_dma_chan; 285 struct dma_chan *rx_dma_chan; 286 unsigned int dma_buf_size; 287 struct device *dma_dev; 288 dma_addr_t dma_phys; 289 void *dma_buf; 290 291 bool multimaster_mode; 292 bool atomic_mode; 293 bool dma_mode; 294 bool msg_read; 295 bool is_dvc; 296 bool is_vi; 297 }; 298 299 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 300 unsigned int reg) 301 { 302 writel_relaxed(val, i2c_dev->base + reg); 303 } 304 305 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 306 { 307 return readl_relaxed(i2c_dev->base + reg); 308 } 309 310 /* 311 * If necessary, i2c_writel() and i2c_readl() will offset the register 312 * in order to talk to the I2C block inside the DVC block. 313 */ 314 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 315 { 316 if (i2c_dev->is_dvc) 317 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 318 else if (i2c_dev->is_vi) 319 reg = 0xc00 + (reg << 2); 320 321 return reg; 322 } 323 324 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 325 { 326 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 327 328 /* read back register to make sure that register writes completed */ 329 if (reg != I2C_TX_FIFO) 330 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 331 else if (i2c_dev->is_vi) 332 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 333 } 334 335 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 336 { 337 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 338 } 339 340 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 341 unsigned int reg, unsigned int len) 342 { 343 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 344 } 345 346 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, 347 unsigned int reg, unsigned int len) 348 { 349 u32 *data32 = data; 350 351 /* 352 * VI I2C controller has known hardware bug where writes get stuck 353 * when immediate multiple writes happen to TX_FIFO register. 354 * Recommended software work around is to read I2C register after 355 * each write to TX_FIFO register to flush out the data. 356 */ 357 while (len--) 358 i2c_writel(i2c_dev, *data32++, reg); 359 } 360 361 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 362 unsigned int reg, unsigned int len) 363 { 364 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 365 } 366 367 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 368 { 369 u32 int_mask; 370 371 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 372 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 373 } 374 375 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 376 { 377 u32 int_mask; 378 379 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 380 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 381 } 382 383 static void tegra_i2c_dma_complete(void *args) 384 { 385 struct tegra_i2c_dev *i2c_dev = args; 386 387 complete(&i2c_dev->dma_complete); 388 } 389 390 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 391 { 392 struct dma_async_tx_descriptor *dma_desc; 393 enum dma_transfer_direction dir; 394 struct dma_chan *chan; 395 396 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 397 398 reinit_completion(&i2c_dev->dma_complete); 399 400 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 401 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; 402 403 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, 404 len, dir, DMA_PREP_INTERRUPT | 405 DMA_CTRL_ACK); 406 if (!dma_desc) { 407 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", 408 i2c_dev->msg_read ? "RX" : "TX"); 409 return -EINVAL; 410 } 411 412 dma_desc->callback = tegra_i2c_dma_complete; 413 dma_desc->callback_param = i2c_dev; 414 415 dmaengine_submit(dma_desc); 416 dma_async_issue_pending(chan); 417 418 return 0; 419 } 420 421 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 422 { 423 if (i2c_dev->dma_buf) { 424 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 425 i2c_dev->dma_buf, i2c_dev->dma_phys); 426 i2c_dev->dma_buf = NULL; 427 } 428 429 if (i2c_dev->tx_dma_chan) { 430 dma_release_channel(i2c_dev->tx_dma_chan); 431 i2c_dev->tx_dma_chan = NULL; 432 } 433 434 if (i2c_dev->rx_dma_chan) { 435 dma_release_channel(i2c_dev->rx_dma_chan); 436 i2c_dev->rx_dma_chan = NULL; 437 } 438 } 439 440 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 441 { 442 struct dma_chan *chan; 443 dma_addr_t dma_phys; 444 u32 *dma_buf; 445 int err; 446 447 if (i2c_dev->is_vi) 448 return 0; 449 450 if (!i2c_dev->hw->has_apb_dma) { 451 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 452 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); 453 return 0; 454 } 455 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) { 456 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); 457 return 0; 458 } 459 460 chan = dma_request_chan(i2c_dev->dev, "rx"); 461 if (IS_ERR(chan)) { 462 err = PTR_ERR(chan); 463 goto err_out; 464 } 465 466 i2c_dev->rx_dma_chan = chan; 467 468 chan = dma_request_chan(i2c_dev->dev, "tx"); 469 if (IS_ERR(chan)) { 470 err = PTR_ERR(chan); 471 goto err_out; 472 } 473 474 i2c_dev->tx_dma_chan = chan; 475 476 WARN_ON(i2c_dev->tx_dma_chan->device != i2c_dev->rx_dma_chan->device); 477 i2c_dev->dma_dev = chan->device->dev; 478 479 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + 480 I2C_PACKET_HEADER_SIZE; 481 482 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 483 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 484 if (!dma_buf) { 485 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); 486 err = -ENOMEM; 487 goto err_out; 488 } 489 490 i2c_dev->dma_buf = dma_buf; 491 i2c_dev->dma_phys = dma_phys; 492 493 return 0; 494 495 err_out: 496 tegra_i2c_release_dma(i2c_dev); 497 if (err != -EPROBE_DEFER) { 498 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 499 dev_err(i2c_dev->dev, "falling back to PIO\n"); 500 return 0; 501 } 502 503 return err; 504 } 505 506 /* 507 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 508 * block. This block is identical to the rest of the I2C blocks, except that 509 * it only supports master mode, it has registers moved around, and it needs 510 * some extra init to get it into I2C mode. The register moves are handled 511 * by i2c_readl() and i2c_writel(). 512 */ 513 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 514 { 515 u32 val; 516 517 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 518 val |= DVC_CTRL_REG3_SW_PROG; 519 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 520 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 521 522 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 523 val |= DVC_CTRL_REG1_INTR_EN; 524 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 525 } 526 527 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) 528 { 529 u32 value; 530 531 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 532 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 533 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 534 535 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 536 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 537 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 538 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 539 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 540 541 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 542 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 543 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 544 545 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 546 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 547 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 548 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 549 550 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 551 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 552 553 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 554 } 555 556 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 557 u32 reg, u32 mask, u32 delay_us, 558 u32 timeout_us) 559 { 560 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 561 u32 val; 562 563 if (!i2c_dev->atomic_mode) 564 return readl_relaxed_poll_timeout(addr, val, !(val & mask), 565 delay_us, timeout_us); 566 567 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), 568 delay_us, timeout_us); 569 } 570 571 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 572 { 573 u32 mask, val, offset; 574 int err; 575 576 if (i2c_dev->hw->has_mst_fifo) { 577 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 578 I2C_MST_FIFO_CONTROL_RX_FLUSH; 579 offset = I2C_MST_FIFO_CONTROL; 580 } else { 581 mask = I2C_FIFO_CONTROL_TX_FLUSH | 582 I2C_FIFO_CONTROL_RX_FLUSH; 583 offset = I2C_FIFO_CONTROL; 584 } 585 586 val = i2c_readl(i2c_dev, offset); 587 val |= mask; 588 i2c_writel(i2c_dev, val, offset); 589 590 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000); 591 if (err) { 592 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); 593 return err; 594 } 595 596 return 0; 597 } 598 599 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 600 { 601 int err; 602 603 if (!i2c_dev->hw->has_config_load_reg) 604 return 0; 605 606 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 607 608 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 609 1000, I2C_CONFIG_LOAD_TIMEOUT); 610 if (err) { 611 dev_err(i2c_dev->dev, "failed to load config\n"); 612 return err; 613 } 614 615 return 0; 616 } 617 618 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 619 { 620 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 621 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); 622 struct i2c_timings *t = &i2c_dev->timings; 623 int err; 624 625 /* 626 * The reset shouldn't ever fail in practice. The failure will be a 627 * sign of a severe problem that needs to be resolved. Still we don't 628 * want to fail the initialization completely because this may break 629 * kernel boot up since voltage regulators use I2C. Hence, we will 630 * emit a noisy warning on error, which won't stay unnoticed and 631 * won't hose machine entirely. 632 */ 633 if (handle) 634 err = acpi_evaluate_object(handle, "_RST", NULL, NULL); 635 else 636 err = reset_control_reset(i2c_dev->rst); 637 638 WARN_ON_ONCE(err); 639 640 if (i2c_dev->is_dvc) 641 tegra_dvc_init(i2c_dev); 642 643 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 644 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); 645 646 if (i2c_dev->hw->has_multi_master_mode) 647 val |= I2C_CNFG_MULTI_MASTER_MODE; 648 649 i2c_writel(i2c_dev, val, I2C_CNFG); 650 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 651 652 if (i2c_dev->is_vi) 653 tegra_i2c_vi_init(i2c_dev); 654 655 switch (t->bus_freq_hz) { 656 case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 657 default: 658 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 659 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 660 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 661 662 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 663 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 664 else 665 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 666 break; 667 668 case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 669 tlow = i2c_dev->hw->tlow_std_mode; 670 thigh = i2c_dev->hw->thigh_std_mode; 671 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 672 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 673 break; 674 } 675 676 /* make sure clock divisor programmed correctly */ 677 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 678 i2c_dev->hw->clk_divisor_hs_mode) | 679 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 680 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 681 682 if (i2c_dev->hw->has_interface_timing_reg) { 683 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 684 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 685 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 686 } 687 688 /* 689 * Configure setup and hold times only when tsu_thd is non-zero. 690 * Otherwise, preserve the chip default values. 691 */ 692 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 693 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 694 695 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 696 697 err = clk_set_rate(i2c_dev->div_clk, 698 t->bus_freq_hz * clk_multiplier); 699 if (err) { 700 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); 701 return err; 702 } 703 704 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) { 705 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 706 707 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 708 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 709 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 710 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 711 } 712 713 err = tegra_i2c_flush_fifos(i2c_dev); 714 if (err) 715 return err; 716 717 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 718 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 719 720 err = tegra_i2c_wait_for_config_load(i2c_dev); 721 if (err) 722 return err; 723 724 return 0; 725 } 726 727 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 728 { 729 u32 cnfg; 730 731 /* 732 * NACK interrupt is generated before the I2C controller generates 733 * the STOP condition on the bus. So, wait for 2 clock periods 734 * before disabling the controller so that the STOP condition has 735 * been delivered properly. 736 */ 737 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); 738 739 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 740 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 741 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 742 743 return tegra_i2c_wait_for_config_load(i2c_dev); 744 } 745 746 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 747 { 748 size_t buf_remaining = i2c_dev->msg_buf_remaining; 749 unsigned int words_to_transfer, rx_fifo_avail; 750 u8 *buf = i2c_dev->msg_buf; 751 u32 val; 752 753 /* 754 * Catch overflow due to message fully sent before the check for 755 * RX FIFO availability. 756 */ 757 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 758 return -EINVAL; 759 760 if (i2c_dev->hw->has_mst_fifo) { 761 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 762 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 763 } else { 764 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 765 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 766 } 767 768 /* round down to exclude partial word at the end of buffer */ 769 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 770 if (words_to_transfer > rx_fifo_avail) 771 words_to_transfer = rx_fifo_avail; 772 773 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 774 775 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 776 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 777 rx_fifo_avail -= words_to_transfer; 778 779 /* 780 * If there is a partial word at the end of buffer, handle it 781 * manually to prevent overwriting past the end of buffer. 782 */ 783 if (rx_fifo_avail > 0 && buf_remaining > 0) { 784 /* 785 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 786 * when (words_to_transfer was > rx_fifo_avail) earlier 787 * in this function. 788 */ 789 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 790 val = cpu_to_le32(val); 791 memcpy(buf, &val, buf_remaining); 792 buf_remaining = 0; 793 rx_fifo_avail--; 794 } 795 796 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 797 if (WARN_ON_ONCE(rx_fifo_avail)) 798 return -EINVAL; 799 800 i2c_dev->msg_buf_remaining = buf_remaining; 801 i2c_dev->msg_buf = buf; 802 803 return 0; 804 } 805 806 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 807 { 808 size_t buf_remaining = i2c_dev->msg_buf_remaining; 809 unsigned int words_to_transfer, tx_fifo_avail; 810 u8 *buf = i2c_dev->msg_buf; 811 u32 val; 812 813 if (i2c_dev->hw->has_mst_fifo) { 814 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 815 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 816 } else { 817 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 818 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 819 } 820 821 /* round down to exclude partial word at the end of buffer */ 822 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 823 824 /* 825 * This hunk pushes 4 bytes at a time into the TX FIFO. 826 * 827 * It's very common to have < 4 bytes, hence there is no word 828 * to push if we have less than 4 bytes to transfer. 829 */ 830 if (words_to_transfer) { 831 if (words_to_transfer > tx_fifo_avail) 832 words_to_transfer = tx_fifo_avail; 833 834 /* 835 * Update state before writing to FIFO. Note that this may 836 * cause us to finish writing all bytes (AKA buf_remaining 837 * goes to 0), hence we have a potential for an interrupt 838 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt 839 * is disabled at this point. 840 */ 841 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 842 tx_fifo_avail -= words_to_transfer; 843 844 i2c_dev->msg_buf_remaining = buf_remaining; 845 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 846 847 if (i2c_dev->is_vi) 848 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 849 else 850 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 851 852 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 853 } 854 855 /* 856 * If there is a partial word at the end of buffer, handle it manually 857 * to prevent reading past the end of buffer, which could cross a page 858 * boundary and fault. 859 */ 860 if (tx_fifo_avail > 0 && buf_remaining > 0) { 861 /* 862 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 863 * when (words_to_transfer was > tx_fifo_avail) earlier 864 * in this function for non-zero words_to_transfer. 865 */ 866 memcpy(&val, buf, buf_remaining); 867 val = le32_to_cpu(val); 868 869 i2c_dev->msg_buf_remaining = 0; 870 i2c_dev->msg_buf = NULL; 871 872 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 873 } 874 875 return 0; 876 } 877 878 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 879 { 880 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 881 struct tegra_i2c_dev *i2c_dev = dev_id; 882 u32 status; 883 884 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 885 886 if (status == 0) { 887 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 888 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 889 i2c_readl(i2c_dev, I2C_STATUS), 890 i2c_readl(i2c_dev, I2C_CNFG)); 891 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 892 goto err; 893 } 894 895 if (status & status_err) { 896 tegra_i2c_disable_packet_mode(i2c_dev); 897 if (status & I2C_INT_NO_ACK) 898 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 899 if (status & I2C_INT_ARBITRATION_LOST) 900 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 901 goto err; 902 } 903 904 /* 905 * I2C transfer is terminated during the bus clear, so skip 906 * processing the other interrupts. 907 */ 908 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 909 goto err; 910 911 if (!i2c_dev->dma_mode) { 912 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 913 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 914 /* 915 * Overflow error condition: message fully sent, 916 * with no XFER_COMPLETE interrupt but hardware 917 * asks to transfer more. 918 */ 919 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 920 goto err; 921 } 922 } 923 924 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 925 if (i2c_dev->msg_buf_remaining) 926 tegra_i2c_fill_tx_fifo(i2c_dev); 927 else 928 tegra_i2c_mask_irq(i2c_dev, 929 I2C_INT_TX_FIFO_DATA_REQ); 930 } 931 } 932 933 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 934 if (i2c_dev->is_dvc) 935 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 936 937 /* 938 * During message read XFER_COMPLETE interrupt is triggered prior to 939 * DMA completion and during message write XFER_COMPLETE interrupt is 940 * triggered after DMA completion. 941 * 942 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer, 943 * so forcing msg_buf_remaining to 0 in DMA mode. 944 */ 945 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 946 if (i2c_dev->dma_mode) 947 i2c_dev->msg_buf_remaining = 0; 948 /* 949 * Underflow error condition: XFER_COMPLETE before message 950 * fully sent. 951 */ 952 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 953 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 954 goto err; 955 } 956 complete(&i2c_dev->msg_complete); 957 } 958 goto done; 959 err: 960 /* mask all interrupts on error */ 961 tegra_i2c_mask_irq(i2c_dev, 962 I2C_INT_NO_ACK | 963 I2C_INT_ARBITRATION_LOST | 964 I2C_INT_PACKET_XFER_COMPLETE | 965 I2C_INT_TX_FIFO_DATA_REQ | 966 I2C_INT_RX_FIFO_DATA_REQ); 967 968 if (i2c_dev->hw->supports_bus_clear) 969 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 970 971 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 972 973 if (i2c_dev->is_dvc) 974 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 975 976 if (i2c_dev->dma_mode) { 977 if (i2c_dev->msg_read) 978 dmaengine_terminate_async(i2c_dev->rx_dma_chan); 979 else 980 dmaengine_terminate_async(i2c_dev->tx_dma_chan); 981 982 complete(&i2c_dev->dma_complete); 983 } 984 985 complete(&i2c_dev->msg_complete); 986 done: 987 return IRQ_HANDLED; 988 } 989 990 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 991 size_t len) 992 { 993 struct dma_slave_config slv_config = {0}; 994 u32 val, reg, dma_burst, reg_offset; 995 struct dma_chan *chan; 996 int err; 997 998 if (i2c_dev->hw->has_mst_fifo) 999 reg = I2C_MST_FIFO_CONTROL; 1000 else 1001 reg = I2C_FIFO_CONTROL; 1002 1003 if (i2c_dev->dma_mode) { 1004 if (len & 0xF) 1005 dma_burst = 1; 1006 else if (len & 0x10) 1007 dma_burst = 4; 1008 else 1009 dma_burst = 8; 1010 1011 if (i2c_dev->msg_read) { 1012 chan = i2c_dev->rx_dma_chan; 1013 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 1014 1015 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 1016 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1017 slv_config.src_maxburst = dma_burst; 1018 1019 if (i2c_dev->hw->has_mst_fifo) 1020 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 1021 else 1022 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1023 } else { 1024 chan = i2c_dev->tx_dma_chan; 1025 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1026 1027 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1028 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1029 slv_config.dst_maxburst = dma_burst; 1030 1031 if (i2c_dev->hw->has_mst_fifo) 1032 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 1033 else 1034 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 1035 } 1036 1037 slv_config.device_fc = true; 1038 err = dmaengine_slave_config(chan, &slv_config); 1039 if (err) { 1040 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); 1041 dev_err(i2c_dev->dev, "falling back to PIO\n"); 1042 1043 tegra_i2c_release_dma(i2c_dev); 1044 i2c_dev->dma_mode = false; 1045 } else { 1046 goto out; 1047 } 1048 } 1049 1050 if (i2c_dev->hw->has_mst_fifo) 1051 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 1052 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 1053 else 1054 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 1055 I2C_FIFO_CONTROL_RX_TRIG(1); 1056 out: 1057 i2c_writel(i2c_dev, val, reg); 1058 } 1059 1060 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev, 1061 struct completion *complete, 1062 unsigned int timeout_ms) 1063 { 1064 ktime_t ktime = ktime_get(); 1065 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1066 1067 do { 1068 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1069 1070 if (status) 1071 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1072 1073 if (completion_done(complete)) { 1074 s64 delta = ktime_ms_delta(ktimeout, ktime); 1075 1076 return msecs_to_jiffies(delta) ?: 1; 1077 } 1078 1079 ktime = ktime_get(); 1080 1081 } while (ktime_before(ktime, ktimeout)); 1082 1083 return 0; 1084 } 1085 1086 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev, 1087 struct completion *complete, 1088 unsigned int timeout_ms) 1089 { 1090 unsigned long ret; 1091 1092 if (i2c_dev->atomic_mode) { 1093 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms); 1094 } else { 1095 enable_irq(i2c_dev->irq); 1096 ret = wait_for_completion_timeout(complete, 1097 msecs_to_jiffies(timeout_ms)); 1098 disable_irq(i2c_dev->irq); 1099 1100 /* 1101 * Under some rare circumstances (like running KASAN + 1102 * NFS root) CPU, which handles interrupt, may stuck in 1103 * uninterruptible state for a significant time. In this 1104 * case we will get timeout if I2C transfer is running on 1105 * a sibling CPU, despite of IRQ being raised. 1106 * 1107 * In order to handle this rare condition, the IRQ status 1108 * needs to be checked after timeout. 1109 */ 1110 if (ret == 0) 1111 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0); 1112 } 1113 1114 return ret; 1115 } 1116 1117 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1118 { 1119 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1120 u32 val, time_left; 1121 int err; 1122 1123 reinit_completion(&i2c_dev->msg_complete); 1124 1125 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1126 I2C_BC_TERMINATE; 1127 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1128 1129 err = tegra_i2c_wait_for_config_load(i2c_dev); 1130 if (err) 1131 return err; 1132 1133 val |= I2C_BC_ENABLE; 1134 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1135 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1136 1137 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); 1138 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1139 1140 if (time_left == 0) { 1141 dev_err(i2c_dev->dev, "failed to clear bus\n"); 1142 return -ETIMEDOUT; 1143 } 1144 1145 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1146 if (!(val & I2C_BC_STATUS)) { 1147 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1148 return -EIO; 1149 } 1150 1151 return -EAGAIN; 1152 } 1153 1154 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, 1155 struct i2c_msg *msg, 1156 enum msg_end_type end_state) 1157 { 1158 u32 *dma_buf = i2c_dev->dma_buf; 1159 u32 packet_header; 1160 1161 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) | 1162 FIELD_PREP(PACKET_HEADER0_PROTOCOL, 1163 PACKET_HEADER0_PROTOCOL_I2C) | 1164 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | 1165 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1); 1166 1167 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1168 *dma_buf++ = packet_header; 1169 else 1170 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1171 1172 packet_header = msg->len - 1; 1173 1174 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1175 *dma_buf++ = packet_header; 1176 else 1177 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1178 1179 packet_header = I2C_HEADER_IE_ENABLE; 1180 1181 if (end_state == MSG_END_CONTINUE) 1182 packet_header |= I2C_HEADER_CONTINUE_XFER; 1183 else if (end_state == MSG_END_REPEAT_START) 1184 packet_header |= I2C_HEADER_REPEAT_START; 1185 1186 if (msg->flags & I2C_M_TEN) { 1187 packet_header |= msg->addr; 1188 packet_header |= I2C_HEADER_10BIT_ADDR; 1189 } else { 1190 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1191 } 1192 1193 if (msg->flags & I2C_M_IGNORE_NAK) 1194 packet_header |= I2C_HEADER_CONT_ON_NAK; 1195 1196 if (msg->flags & I2C_M_RD) 1197 packet_header |= I2C_HEADER_READ; 1198 1199 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1200 *dma_buf++ = packet_header; 1201 else 1202 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1203 } 1204 1205 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, 1206 struct i2c_msg *msg) 1207 { 1208 if (i2c_dev->msg_err == I2C_ERR_NONE) 1209 return 0; 1210 1211 tegra_i2c_init(i2c_dev); 1212 1213 /* start recovery upon arbitration loss in single master mode */ 1214 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1215 if (!i2c_dev->multimaster_mode) 1216 return i2c_recover_bus(&i2c_dev->adapter); 1217 1218 return -EAGAIN; 1219 } 1220 1221 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1222 if (msg->flags & I2C_M_IGNORE_NAK) 1223 return 0; 1224 1225 return -EREMOTEIO; 1226 } 1227 1228 return -EIO; 1229 } 1230 1231 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1232 struct i2c_msg *msg, 1233 enum msg_end_type end_state) 1234 { 1235 unsigned long time_left, xfer_time = 100; 1236 size_t xfer_size; 1237 u32 int_mask; 1238 int err; 1239 1240 err = tegra_i2c_flush_fifos(i2c_dev); 1241 if (err) 1242 return err; 1243 1244 i2c_dev->msg_buf = msg->buf; 1245 1246 /* The condition true implies smbus block read and len is already read */ 1247 if (msg->flags & I2C_M_RECV_LEN && end_state != MSG_END_CONTINUE) 1248 i2c_dev->msg_buf = msg->buf + 1; 1249 1250 i2c_dev->msg_buf_remaining = msg->len; 1251 i2c_dev->msg_err = I2C_ERR_NONE; 1252 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); 1253 reinit_completion(&i2c_dev->msg_complete); 1254 1255 if (i2c_dev->msg_read) 1256 xfer_size = msg->len; 1257 else 1258 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; 1259 1260 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1261 1262 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && 1263 i2c_dev->dma_buf && !i2c_dev->atomic_mode; 1264 1265 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1266 1267 /* 1268 * Transfer time in mSec = Total bits / transfer rate 1269 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1270 */ 1271 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1272 i2c_dev->timings.bus_freq_hz); 1273 1274 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1275 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1276 1277 if (i2c_dev->dma_mode) { 1278 if (i2c_dev->msg_read) { 1279 dma_sync_single_for_device(i2c_dev->dma_dev, 1280 i2c_dev->dma_phys, 1281 xfer_size, DMA_FROM_DEVICE); 1282 1283 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1284 if (err) 1285 return err; 1286 } else { 1287 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1288 i2c_dev->dma_phys, 1289 xfer_size, DMA_TO_DEVICE); 1290 } 1291 } 1292 1293 tegra_i2c_push_packet_header(i2c_dev, msg, end_state); 1294 1295 if (!i2c_dev->msg_read) { 1296 if (i2c_dev->dma_mode) { 1297 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, 1298 msg->buf, msg->len); 1299 1300 dma_sync_single_for_device(i2c_dev->dma_dev, 1301 i2c_dev->dma_phys, 1302 xfer_size, DMA_TO_DEVICE); 1303 1304 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1305 if (err) 1306 return err; 1307 } else { 1308 tegra_i2c_fill_tx_fifo(i2c_dev); 1309 } 1310 } 1311 1312 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1313 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1314 1315 if (!i2c_dev->dma_mode) { 1316 if (msg->flags & I2C_M_RD) 1317 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1318 else if (i2c_dev->msg_buf_remaining) 1319 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1320 } 1321 1322 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1323 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1324 i2c_readl(i2c_dev, I2C_INT_MASK)); 1325 1326 if (i2c_dev->dma_mode) { 1327 time_left = tegra_i2c_wait_completion(i2c_dev, 1328 &i2c_dev->dma_complete, 1329 xfer_time); 1330 1331 /* 1332 * Synchronize DMA first, since dmaengine_terminate_sync() 1333 * performs synchronization after the transfer's termination 1334 * and we want to get a completion if transfer succeeded. 1335 */ 1336 dmaengine_synchronize(i2c_dev->msg_read ? 1337 i2c_dev->rx_dma_chan : 1338 i2c_dev->tx_dma_chan); 1339 1340 dmaengine_terminate_sync(i2c_dev->msg_read ? 1341 i2c_dev->rx_dma_chan : 1342 i2c_dev->tx_dma_chan); 1343 1344 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1345 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); 1346 tegra_i2c_init(i2c_dev); 1347 return -ETIMEDOUT; 1348 } 1349 1350 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1351 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1352 i2c_dev->dma_phys, 1353 xfer_size, DMA_FROM_DEVICE); 1354 1355 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len); 1356 } 1357 } 1358 1359 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 1360 xfer_time); 1361 1362 tegra_i2c_mask_irq(i2c_dev, int_mask); 1363 1364 if (time_left == 0) { 1365 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); 1366 tegra_i2c_init(i2c_dev); 1367 return -ETIMEDOUT; 1368 } 1369 1370 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1371 time_left, completion_done(&i2c_dev->msg_complete), 1372 i2c_dev->msg_err); 1373 1374 i2c_dev->dma_mode = false; 1375 1376 err = tegra_i2c_error_recover(i2c_dev, msg); 1377 if (err) 1378 return err; 1379 1380 return 0; 1381 } 1382 1383 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1384 int num) 1385 { 1386 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1387 int i, ret; 1388 1389 ret = pm_runtime_get_sync(i2c_dev->dev); 1390 if (ret < 0) { 1391 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1392 pm_runtime_put_noidle(i2c_dev->dev); 1393 return ret; 1394 } 1395 1396 for (i = 0; i < num; i++) { 1397 enum msg_end_type end_type = MSG_END_STOP; 1398 1399 if (i < (num - 1)) { 1400 /* check whether follow up message is coming */ 1401 if (msgs[i + 1].flags & I2C_M_NOSTART) 1402 end_type = MSG_END_CONTINUE; 1403 else 1404 end_type = MSG_END_REPEAT_START; 1405 } 1406 /* If M_RECV_LEN use ContinueXfer to read the first byte */ 1407 if (msgs[i].flags & I2C_M_RECV_LEN) { 1408 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE); 1409 if (ret) 1410 break; 1411 /* Set the read byte as msg len */ 1412 msgs[i].len = msgs[i].buf[0]; 1413 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); 1414 } 1415 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1416 if (ret) 1417 break; 1418 } 1419 1420 pm_runtime_put(i2c_dev->dev); 1421 1422 return ret ?: i; 1423 } 1424 1425 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1426 struct i2c_msg msgs[], int num) 1427 { 1428 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1429 int ret; 1430 1431 i2c_dev->atomic_mode = true; 1432 ret = tegra_i2c_xfer(adap, msgs, num); 1433 i2c_dev->atomic_mode = false; 1434 1435 return ret; 1436 } 1437 1438 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1439 { 1440 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1441 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1442 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1443 1444 if (i2c_dev->hw->has_continue_xfer_support) 1445 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1446 1447 return ret; 1448 } 1449 1450 static const struct i2c_algorithm tegra_i2c_algo = { 1451 .master_xfer = tegra_i2c_xfer, 1452 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1453 .functionality = tegra_i2c_func, 1454 }; 1455 1456 /* payload size is only 12 bit */ 1457 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1458 .flags = I2C_AQ_NO_ZERO_LEN, 1459 .max_read_len = SZ_4K, 1460 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1461 }; 1462 1463 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1464 .flags = I2C_AQ_NO_ZERO_LEN, 1465 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1466 }; 1467 1468 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1469 .recover_bus = tegra_i2c_issue_bus_clear, 1470 }; 1471 1472 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1473 .has_continue_xfer_support = false, 1474 .has_per_pkt_xfer_complete_irq = false, 1475 .clk_divisor_hs_mode = 3, 1476 .clk_divisor_std_mode = 0, 1477 .clk_divisor_fast_mode = 0, 1478 .clk_divisor_fast_plus_mode = 0, 1479 .has_config_load_reg = false, 1480 .has_multi_master_mode = false, 1481 .has_slcg_override_reg = false, 1482 .has_mst_fifo = false, 1483 .quirks = &tegra_i2c_quirks, 1484 .supports_bus_clear = false, 1485 .has_apb_dma = true, 1486 .tlow_std_mode = 0x4, 1487 .thigh_std_mode = 0x2, 1488 .tlow_fast_fastplus_mode = 0x4, 1489 .thigh_fast_fastplus_mode = 0x2, 1490 .setup_hold_time_std_mode = 0x0, 1491 .setup_hold_time_fast_fast_plus_mode = 0x0, 1492 .setup_hold_time_hs_mode = 0x0, 1493 .has_interface_timing_reg = false, 1494 }; 1495 1496 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1497 .has_continue_xfer_support = true, 1498 .has_per_pkt_xfer_complete_irq = false, 1499 .clk_divisor_hs_mode = 3, 1500 .clk_divisor_std_mode = 0, 1501 .clk_divisor_fast_mode = 0, 1502 .clk_divisor_fast_plus_mode = 0, 1503 .has_config_load_reg = false, 1504 .has_multi_master_mode = false, 1505 .has_slcg_override_reg = false, 1506 .has_mst_fifo = false, 1507 .quirks = &tegra_i2c_quirks, 1508 .supports_bus_clear = false, 1509 .has_apb_dma = true, 1510 .tlow_std_mode = 0x4, 1511 .thigh_std_mode = 0x2, 1512 .tlow_fast_fastplus_mode = 0x4, 1513 .thigh_fast_fastplus_mode = 0x2, 1514 .setup_hold_time_std_mode = 0x0, 1515 .setup_hold_time_fast_fast_plus_mode = 0x0, 1516 .setup_hold_time_hs_mode = 0x0, 1517 .has_interface_timing_reg = false, 1518 }; 1519 1520 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1521 .has_continue_xfer_support = true, 1522 .has_per_pkt_xfer_complete_irq = true, 1523 .clk_divisor_hs_mode = 1, 1524 .clk_divisor_std_mode = 0x19, 1525 .clk_divisor_fast_mode = 0x19, 1526 .clk_divisor_fast_plus_mode = 0x10, 1527 .has_config_load_reg = false, 1528 .has_multi_master_mode = false, 1529 .has_slcg_override_reg = false, 1530 .has_mst_fifo = false, 1531 .quirks = &tegra_i2c_quirks, 1532 .supports_bus_clear = true, 1533 .has_apb_dma = true, 1534 .tlow_std_mode = 0x4, 1535 .thigh_std_mode = 0x2, 1536 .tlow_fast_fastplus_mode = 0x4, 1537 .thigh_fast_fastplus_mode = 0x2, 1538 .setup_hold_time_std_mode = 0x0, 1539 .setup_hold_time_fast_fast_plus_mode = 0x0, 1540 .setup_hold_time_hs_mode = 0x0, 1541 .has_interface_timing_reg = false, 1542 }; 1543 1544 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1545 .has_continue_xfer_support = true, 1546 .has_per_pkt_xfer_complete_irq = true, 1547 .clk_divisor_hs_mode = 1, 1548 .clk_divisor_std_mode = 0x19, 1549 .clk_divisor_fast_mode = 0x19, 1550 .clk_divisor_fast_plus_mode = 0x10, 1551 .has_config_load_reg = true, 1552 .has_multi_master_mode = false, 1553 .has_slcg_override_reg = true, 1554 .has_mst_fifo = false, 1555 .quirks = &tegra_i2c_quirks, 1556 .supports_bus_clear = true, 1557 .has_apb_dma = true, 1558 .tlow_std_mode = 0x4, 1559 .thigh_std_mode = 0x2, 1560 .tlow_fast_fastplus_mode = 0x4, 1561 .thigh_fast_fastplus_mode = 0x2, 1562 .setup_hold_time_std_mode = 0x0, 1563 .setup_hold_time_fast_fast_plus_mode = 0x0, 1564 .setup_hold_time_hs_mode = 0x0, 1565 .has_interface_timing_reg = true, 1566 }; 1567 1568 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1569 .has_continue_xfer_support = true, 1570 .has_per_pkt_xfer_complete_irq = true, 1571 .clk_divisor_hs_mode = 1, 1572 .clk_divisor_std_mode = 0x19, 1573 .clk_divisor_fast_mode = 0x19, 1574 .clk_divisor_fast_plus_mode = 0x10, 1575 .has_config_load_reg = true, 1576 .has_multi_master_mode = false, 1577 .has_slcg_override_reg = true, 1578 .has_mst_fifo = false, 1579 .quirks = &tegra_i2c_quirks, 1580 .supports_bus_clear = true, 1581 .has_apb_dma = true, 1582 .tlow_std_mode = 0x4, 1583 .thigh_std_mode = 0x2, 1584 .tlow_fast_fastplus_mode = 0x4, 1585 .thigh_fast_fastplus_mode = 0x2, 1586 .setup_hold_time_std_mode = 0, 1587 .setup_hold_time_fast_fast_plus_mode = 0, 1588 .setup_hold_time_hs_mode = 0, 1589 .has_interface_timing_reg = true, 1590 }; 1591 1592 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1593 .has_continue_xfer_support = true, 1594 .has_per_pkt_xfer_complete_irq = true, 1595 .clk_divisor_hs_mode = 1, 1596 .clk_divisor_std_mode = 0x16, 1597 .clk_divisor_fast_mode = 0x19, 1598 .clk_divisor_fast_plus_mode = 0x10, 1599 .has_config_load_reg = true, 1600 .has_multi_master_mode = false, 1601 .has_slcg_override_reg = true, 1602 .has_mst_fifo = false, 1603 .quirks = &tegra_i2c_quirks, 1604 .supports_bus_clear = true, 1605 .has_apb_dma = false, 1606 .tlow_std_mode = 0x4, 1607 .thigh_std_mode = 0x3, 1608 .tlow_fast_fastplus_mode = 0x4, 1609 .thigh_fast_fastplus_mode = 0x2, 1610 .setup_hold_time_std_mode = 0, 1611 .setup_hold_time_fast_fast_plus_mode = 0, 1612 .setup_hold_time_hs_mode = 0, 1613 .has_interface_timing_reg = true, 1614 }; 1615 1616 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1617 .has_continue_xfer_support = true, 1618 .has_per_pkt_xfer_complete_irq = true, 1619 .clk_divisor_hs_mode = 1, 1620 .clk_divisor_std_mode = 0x4f, 1621 .clk_divisor_fast_mode = 0x3c, 1622 .clk_divisor_fast_plus_mode = 0x16, 1623 .has_config_load_reg = true, 1624 .has_multi_master_mode = true, 1625 .has_slcg_override_reg = true, 1626 .has_mst_fifo = true, 1627 .quirks = &tegra194_i2c_quirks, 1628 .supports_bus_clear = true, 1629 .has_apb_dma = false, 1630 .tlow_std_mode = 0x8, 1631 .thigh_std_mode = 0x7, 1632 .tlow_fast_fastplus_mode = 0x2, 1633 .thigh_fast_fastplus_mode = 0x2, 1634 .setup_hold_time_std_mode = 0x08080808, 1635 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1636 .setup_hold_time_hs_mode = 0x090909, 1637 .has_interface_timing_reg = true, 1638 }; 1639 1640 static const struct of_device_id tegra_i2c_of_match[] = { 1641 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1642 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1643 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1644 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1645 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1646 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1647 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1648 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1649 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1650 {}, 1651 }; 1652 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1653 1654 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1655 { 1656 struct device_node *np = i2c_dev->dev->of_node; 1657 bool multi_mode; 1658 1659 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); 1660 1661 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); 1662 i2c_dev->multimaster_mode = multi_mode; 1663 1664 if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 1665 i2c_dev->is_dvc = true; 1666 1667 if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 1668 i2c_dev->is_vi = true; 1669 } 1670 1671 static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) 1672 { 1673 if (ACPI_HANDLE(i2c_dev->dev)) 1674 return 0; 1675 1676 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); 1677 if (IS_ERR(i2c_dev->rst)) 1678 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), 1679 "failed to get reset control\n"); 1680 1681 return 0; 1682 } 1683 1684 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) 1685 { 1686 int err; 1687 1688 if (ACPI_HANDLE(i2c_dev->dev)) 1689 return 0; 1690 1691 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; 1692 1693 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) 1694 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; 1695 1696 if (i2c_dev->is_vi) 1697 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; 1698 1699 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, 1700 i2c_dev->clocks); 1701 if (err) 1702 return err; 1703 1704 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); 1705 if (err) 1706 return err; 1707 1708 i2c_dev->div_clk = i2c_dev->clocks[0].clk; 1709 1710 if (!i2c_dev->multimaster_mode) 1711 return 0; 1712 1713 err = clk_enable(i2c_dev->div_clk); 1714 if (err) { 1715 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); 1716 goto unprepare_clocks; 1717 } 1718 1719 return 0; 1720 1721 unprepare_clocks: 1722 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1723 1724 return err; 1725 } 1726 1727 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev) 1728 { 1729 if (i2c_dev->multimaster_mode) 1730 clk_disable(i2c_dev->div_clk); 1731 1732 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1733 } 1734 1735 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev) 1736 { 1737 int ret; 1738 1739 ret = pm_runtime_get_sync(i2c_dev->dev); 1740 if (ret < 0) 1741 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); 1742 else 1743 ret = tegra_i2c_init(i2c_dev); 1744 1745 pm_runtime_put_sync(i2c_dev->dev); 1746 1747 return ret; 1748 } 1749 1750 static int tegra_i2c_probe(struct platform_device *pdev) 1751 { 1752 struct tegra_i2c_dev *i2c_dev; 1753 struct resource *res; 1754 int err; 1755 1756 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1757 if (!i2c_dev) 1758 return -ENOMEM; 1759 1760 platform_set_drvdata(pdev, i2c_dev); 1761 1762 init_completion(&i2c_dev->msg_complete); 1763 init_completion(&i2c_dev->dma_complete); 1764 1765 i2c_dev->hw = device_get_match_data(&pdev->dev); 1766 i2c_dev->cont_id = pdev->id; 1767 i2c_dev->dev = &pdev->dev; 1768 1769 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1770 if (IS_ERR(i2c_dev->base)) 1771 return PTR_ERR(i2c_dev->base); 1772 1773 i2c_dev->base_phys = res->start; 1774 1775 err = platform_get_irq(pdev, 0); 1776 if (err < 0) 1777 return err; 1778 1779 i2c_dev->irq = err; 1780 1781 /* interrupt will be enabled during of transfer time */ 1782 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1783 1784 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, 1785 NULL, tegra_i2c_isr, 1786 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1787 dev_name(i2c_dev->dev), i2c_dev); 1788 if (err) 1789 return err; 1790 1791 tegra_i2c_parse_dt(i2c_dev); 1792 1793 err = tegra_i2c_init_reset(i2c_dev); 1794 if (err) 1795 return err; 1796 1797 err = tegra_i2c_init_clocks(i2c_dev); 1798 if (err) 1799 return err; 1800 1801 err = tegra_i2c_init_dma(i2c_dev); 1802 if (err) 1803 goto release_clocks; 1804 1805 /* 1806 * VI I2C is in VE power domain which is not always ON and not 1807 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a 1808 * non IRQ-safe domain because this prevents powering off the power 1809 * domain. 1810 * 1811 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't 1812 * be used for atomic transfers. 1813 */ 1814 if (!i2c_dev->is_vi) 1815 pm_runtime_irq_safe(i2c_dev->dev); 1816 1817 pm_runtime_enable(i2c_dev->dev); 1818 1819 err = tegra_i2c_init_hardware(i2c_dev); 1820 if (err) 1821 goto release_rpm; 1822 1823 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1824 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1825 i2c_dev->adapter.dev.parent = i2c_dev->dev; 1826 i2c_dev->adapter.retries = 1; 1827 i2c_dev->adapter.timeout = 6 * HZ; 1828 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1829 i2c_dev->adapter.owner = THIS_MODULE; 1830 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1831 i2c_dev->adapter.algo = &tegra_i2c_algo; 1832 i2c_dev->adapter.nr = pdev->id; 1833 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1834 1835 if (i2c_dev->hw->supports_bus_clear) 1836 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1837 1838 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1839 sizeof(i2c_dev->adapter.name)); 1840 1841 err = i2c_add_numbered_adapter(&i2c_dev->adapter); 1842 if (err) 1843 goto release_rpm; 1844 1845 return 0; 1846 1847 release_rpm: 1848 pm_runtime_disable(i2c_dev->dev); 1849 1850 tegra_i2c_release_dma(i2c_dev); 1851 release_clocks: 1852 tegra_i2c_release_clocks(i2c_dev); 1853 1854 return err; 1855 } 1856 1857 static int tegra_i2c_remove(struct platform_device *pdev) 1858 { 1859 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1860 1861 i2c_del_adapter(&i2c_dev->adapter); 1862 pm_runtime_force_suspend(i2c_dev->dev); 1863 1864 tegra_i2c_release_dma(i2c_dev); 1865 tegra_i2c_release_clocks(i2c_dev); 1866 1867 return 0; 1868 } 1869 1870 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 1871 { 1872 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1873 int err; 1874 1875 err = pinctrl_pm_select_default_state(dev); 1876 if (err) 1877 return err; 1878 1879 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); 1880 if (err) 1881 return err; 1882 1883 /* 1884 * VI I2C device is attached to VE power domain which goes through 1885 * power ON/OFF during runtime PM resume/suspend, meaning that 1886 * controller needs to be re-initialized after power ON. 1887 */ 1888 if (i2c_dev->is_vi) { 1889 err = tegra_i2c_init(i2c_dev); 1890 if (err) 1891 goto disable_clocks; 1892 } 1893 1894 return 0; 1895 1896 disable_clocks: 1897 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1898 1899 return err; 1900 } 1901 1902 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 1903 { 1904 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1905 1906 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1907 1908 return pinctrl_pm_select_idle_state(dev); 1909 } 1910 1911 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1912 { 1913 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1914 int err; 1915 1916 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1917 1918 if (!pm_runtime_status_suspended(dev)) { 1919 err = tegra_i2c_runtime_suspend(dev); 1920 if (err) 1921 return err; 1922 } 1923 1924 return 0; 1925 } 1926 1927 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1928 { 1929 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1930 int err; 1931 1932 /* 1933 * We need to ensure that clocks are enabled so that registers can be 1934 * restored in tegra_i2c_init(). 1935 */ 1936 err = tegra_i2c_runtime_resume(dev); 1937 if (err) 1938 return err; 1939 1940 err = tegra_i2c_init(i2c_dev); 1941 if (err) 1942 return err; 1943 1944 /* 1945 * In case we are runtime suspended, disable clocks again so that we 1946 * don't unbalance the clock reference counts during the next runtime 1947 * resume transition. 1948 */ 1949 if (pm_runtime_status_suspended(dev)) { 1950 err = tegra_i2c_runtime_suspend(dev); 1951 if (err) 1952 return err; 1953 } 1954 1955 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1956 1957 return 0; 1958 } 1959 1960 static const struct dev_pm_ops tegra_i2c_pm = { 1961 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1962 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1963 NULL) 1964 }; 1965 1966 static const struct acpi_device_id tegra_i2c_acpi_match[] = { 1967 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 1968 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 1969 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 1970 { } 1971 }; 1972 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); 1973 1974 static struct platform_driver tegra_i2c_driver = { 1975 .probe = tegra_i2c_probe, 1976 .remove = tegra_i2c_remove, 1977 .driver = { 1978 .name = "tegra-i2c", 1979 .of_match_table = tegra_i2c_of_match, 1980 .acpi_match_table = tegra_i2c_acpi_match, 1981 .pm = &tegra_i2c_pm, 1982 }, 1983 }; 1984 module_platform_driver(tegra_i2c_driver); 1985 1986 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver"); 1987 MODULE_AUTHOR("Colin Cross"); 1988 MODULE_LICENSE("GPL v2"); 1989