1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/kernel.h> 23 #include <linux/ktime.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/reset.h> 30 31 #define BYTES_PER_FIFO_WORD 4 32 33 #define I2C_CNFG 0x000 34 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 35 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 36 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 37 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 38 #define I2C_STATUS 0x01c 39 #define I2C_SL_CNFG 0x020 40 #define I2C_SL_CNFG_NACK BIT(1) 41 #define I2C_SL_CNFG_NEWSL BIT(2) 42 #define I2C_SL_ADDR1 0x02c 43 #define I2C_SL_ADDR2 0x030 44 #define I2C_TLOW_SEXT 0x034 45 #define I2C_TX_FIFO 0x050 46 #define I2C_RX_FIFO 0x054 47 #define I2C_PACKET_TRANSFER_STATUS 0x058 48 #define I2C_FIFO_CONTROL 0x05c 49 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 50 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 53 #define I2C_FIFO_STATUS 0x060 54 #define I2C_FIFO_STATUS_TX GENMASK(7, 4) 55 #define I2C_FIFO_STATUS_RX GENMASK(3, 0) 56 #define I2C_INT_MASK 0x064 57 #define I2C_INT_STATUS 0x068 58 #define I2C_INT_BUS_CLR_DONE BIT(11) 59 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 60 #define I2C_INT_NO_ACK BIT(3) 61 #define I2C_INT_ARBITRATION_LOST BIT(2) 62 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 63 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 64 #define I2C_CLK_DIVISOR 0x06c 65 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 66 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 67 68 #define DVC_CTRL_REG1 0x000 69 #define DVC_CTRL_REG1_INTR_EN BIT(10) 70 #define DVC_CTRL_REG3 0x008 71 #define DVC_CTRL_REG3_SW_PROG BIT(26) 72 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 73 #define DVC_STATUS 0x00c 74 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 75 76 #define I2C_ERR_NONE 0x00 77 #define I2C_ERR_NO_ACK BIT(0) 78 #define I2C_ERR_ARBITRATION_LOST BIT(1) 79 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 80 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 81 82 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28) 83 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16) 84 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12) 85 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 86 #define PACKET_HEADER0_PROTOCOL_I2C 1 87 88 #define I2C_HEADER_CONT_ON_NAK BIT(21) 89 #define I2C_HEADER_READ BIT(19) 90 #define I2C_HEADER_10BIT_ADDR BIT(18) 91 #define I2C_HEADER_IE_ENABLE BIT(17) 92 #define I2C_HEADER_REPEAT_START BIT(16) 93 #define I2C_HEADER_CONTINUE_XFER BIT(15) 94 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 95 96 #define I2C_BUS_CLEAR_CNFG 0x084 97 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 98 #define I2C_BC_STOP_COND BIT(2) 99 #define I2C_BC_TERMINATE BIT(1) 100 #define I2C_BC_ENABLE BIT(0) 101 #define I2C_BUS_CLEAR_STATUS 0x088 102 #define I2C_BC_STATUS BIT(0) 103 104 #define I2C_CONFIG_LOAD 0x08c 105 #define I2C_MSTR_CONFIG_LOAD BIT(0) 106 107 #define I2C_CLKEN_OVERRIDE 0x090 108 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 109 110 #define I2C_INTERFACE_TIMING_0 0x094 111 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 112 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 113 #define I2C_INTERFACE_TIMING_1 0x098 114 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 115 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 116 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 117 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 118 119 #define I2C_HS_INTERFACE_TIMING_0 0x09c 120 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 121 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 122 #define I2C_HS_INTERFACE_TIMING_1 0x0a0 123 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 124 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 125 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 126 127 #define I2C_MST_FIFO_CONTROL 0x0b4 128 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 129 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 132 133 #define I2C_MST_FIFO_STATUS 0x0b8 134 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 135 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 136 137 /* configuration load timeout in microseconds */ 138 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 139 140 /* packet header size in bytes */ 141 #define I2C_PACKET_HEADER_SIZE 12 142 143 /* 144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 145 * avoid DMA overhead, otherwise external APB DMA controller will be used. 146 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 147 * I2C_PACKET_HEADER_SIZE. 148 */ 149 #define I2C_PIO_MODE_PREFERRED_LEN 32 150 151 /* 152 * msg_end_type: The bus control which needs to be sent at end of transfer. 153 * @MSG_END_STOP: Send stop pulse. 154 * @MSG_END_REPEAT_START: Send repeat-start. 155 * @MSG_END_CONTINUE: Don't send stop or repeat-start. 156 */ 157 enum msg_end_type { 158 MSG_END_STOP, 159 MSG_END_REPEAT_START, 160 MSG_END_CONTINUE, 161 }; 162 163 /** 164 * struct tegra_i2c_hw_feature : per hardware generation features 165 * @has_continue_xfer_support: continue-transfer supported 166 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 167 * completion interrupt on per packet basis. 168 * @has_config_load_reg: Has the config load register to load the new 169 * configuration. 170 * @clk_divisor_hs_mode: Clock divisor in HS mode. 171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 172 * applicable if there is no fast clock source i.e. single clock 173 * source. 174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 175 * applicable if there is no fast clock source i.e. single clock 176 * source. 177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 178 * applicable if there is no fast clock source (i.e. single 179 * clock source). 180 * @has_multi_master_mode: The I2C controller supports running in single-master 181 * or multi-master mode. 182 * @has_slcg_override_reg: The I2C controller supports a register that 183 * overrides the second level clock gating. 184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 185 * provides additional features and allows for longer messages to 186 * be transferred in one go. 187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not 188 * allowing 0 length transfers. 189 * @supports_bus_clear: Bus Clear support to recover from bus hang during 190 * SDA stuck low from device for some unknown reasons. 191 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 192 * @tlow_std_mode: Low period of the clock in standard mode. 193 * @thigh_std_mode: High period of the clock in standard mode. 194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 196 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 197 * in standard mode. 198 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 199 * conditions in fast/fast-plus modes. 200 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 201 * in HS mode. 202 * @has_interface_timing_reg: Has interface timing register to program the tuned 203 * timing settings. 204 */ 205 struct tegra_i2c_hw_feature { 206 bool has_continue_xfer_support; 207 bool has_per_pkt_xfer_complete_irq; 208 bool has_config_load_reg; 209 u32 clk_divisor_hs_mode; 210 u32 clk_divisor_std_mode; 211 u32 clk_divisor_fast_mode; 212 u32 clk_divisor_fast_plus_mode; 213 bool has_multi_master_mode; 214 bool has_slcg_override_reg; 215 bool has_mst_fifo; 216 const struct i2c_adapter_quirks *quirks; 217 bool supports_bus_clear; 218 bool has_apb_dma; 219 u32 tlow_std_mode; 220 u32 thigh_std_mode; 221 u32 tlow_fast_fastplus_mode; 222 u32 thigh_fast_fastplus_mode; 223 u32 setup_hold_time_std_mode; 224 u32 setup_hold_time_fast_fast_plus_mode; 225 u32 setup_hold_time_hs_mode; 226 bool has_interface_timing_reg; 227 }; 228 229 /** 230 * struct tegra_i2c_dev - per device I2C context 231 * @dev: device reference for power management 232 * @hw: Tegra I2C HW feature 233 * @adapter: core I2C layer adapter information 234 * @div_clk: clock reference for div clock of I2C controller 235 * @clocks: array of I2C controller clocks 236 * @nclocks: number of clocks in the array 237 * @rst: reset control for the I2C controller 238 * @base: ioremapped registers cookie 239 * @base_phys: physical base address of the I2C controller 240 * @cont_id: I2C controller ID, used for packet header 241 * @irq: IRQ number of transfer complete interrupt 242 * @is_dvc: identifies the DVC I2C controller, has a different register layout 243 * @is_vi: identifies the VI I2C controller, has a different register layout 244 * @msg_complete: transfer completion notifier 245 * @msg_buf_remaining: size of unsent data in the message buffer 246 * @msg_len: length of message in current transfer 247 * @msg_err: error code for completed message 248 * @msg_buf: pointer to current message data 249 * @msg_read: indicates that the transfer is a read access 250 * @timings: i2c timings information like bus frequency 251 * @multimaster_mode: indicates that I2C controller is in multi-master mode 252 * @tx_dma_chan: DMA transmit channel 253 * @rx_dma_chan: DMA receive channel 254 * @dma_phys: handle to DMA resources 255 * @dma_buf: pointer to allocated DMA buffer 256 * @dma_buf_size: DMA buffer size 257 * @dma_mode: indicates active DMA transfer 258 * @dma_complete: DMA completion notifier 259 * @atomic_mode: indicates active atomic transfer 260 */ 261 struct tegra_i2c_dev { 262 struct device *dev; 263 struct i2c_adapter adapter; 264 265 const struct tegra_i2c_hw_feature *hw; 266 struct reset_control *rst; 267 unsigned int cont_id; 268 unsigned int irq; 269 270 phys_addr_t base_phys; 271 void __iomem *base; 272 273 struct clk_bulk_data clocks[2]; 274 unsigned int nclocks; 275 276 struct clk *div_clk; 277 struct i2c_timings timings; 278 279 struct completion msg_complete; 280 size_t msg_buf_remaining; 281 unsigned int msg_len; 282 int msg_err; 283 u8 *msg_buf; 284 285 struct completion dma_complete; 286 struct dma_chan *tx_dma_chan; 287 struct dma_chan *rx_dma_chan; 288 unsigned int dma_buf_size; 289 struct device *dma_dev; 290 dma_addr_t dma_phys; 291 void *dma_buf; 292 293 bool multimaster_mode; 294 bool atomic_mode; 295 bool dma_mode; 296 bool msg_read; 297 bool is_dvc; 298 bool is_vi; 299 }; 300 301 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 302 unsigned int reg) 303 { 304 writel_relaxed(val, i2c_dev->base + reg); 305 } 306 307 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 308 { 309 return readl_relaxed(i2c_dev->base + reg); 310 } 311 312 /* 313 * If necessary, i2c_writel() and i2c_readl() will offset the register 314 * in order to talk to the I2C block inside the DVC block. 315 */ 316 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 317 { 318 if (i2c_dev->is_dvc) 319 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 320 else if (i2c_dev->is_vi) 321 reg = 0xc00 + (reg << 2); 322 323 return reg; 324 } 325 326 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 327 { 328 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 329 330 /* read back register to make sure that register writes completed */ 331 if (reg != I2C_TX_FIFO) 332 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 333 else if (i2c_dev->is_vi) 334 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 335 } 336 337 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 338 { 339 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 340 } 341 342 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 343 unsigned int reg, unsigned int len) 344 { 345 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 346 } 347 348 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, 349 unsigned int reg, unsigned int len) 350 { 351 u32 *data32 = data; 352 353 /* 354 * VI I2C controller has known hardware bug where writes get stuck 355 * when immediate multiple writes happen to TX_FIFO register. 356 * Recommended software work around is to read I2C register after 357 * each write to TX_FIFO register to flush out the data. 358 */ 359 while (len--) 360 i2c_writel(i2c_dev, *data32++, reg); 361 } 362 363 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 364 unsigned int reg, unsigned int len) 365 { 366 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 367 } 368 369 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 370 { 371 u32 int_mask; 372 373 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 374 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 375 } 376 377 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 378 { 379 u32 int_mask; 380 381 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 382 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 383 } 384 385 static void tegra_i2c_dma_complete(void *args) 386 { 387 struct tegra_i2c_dev *i2c_dev = args; 388 389 complete(&i2c_dev->dma_complete); 390 } 391 392 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 393 { 394 struct dma_async_tx_descriptor *dma_desc; 395 enum dma_transfer_direction dir; 396 struct dma_chan *chan; 397 398 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 399 400 reinit_completion(&i2c_dev->dma_complete); 401 402 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 403 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; 404 405 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, 406 len, dir, DMA_PREP_INTERRUPT | 407 DMA_CTRL_ACK); 408 if (!dma_desc) { 409 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", 410 i2c_dev->msg_read ? "RX" : "TX"); 411 return -EINVAL; 412 } 413 414 dma_desc->callback = tegra_i2c_dma_complete; 415 dma_desc->callback_param = i2c_dev; 416 417 dmaengine_submit(dma_desc); 418 dma_async_issue_pending(chan); 419 420 return 0; 421 } 422 423 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 424 { 425 if (i2c_dev->dma_buf) { 426 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 427 i2c_dev->dma_buf, i2c_dev->dma_phys); 428 i2c_dev->dma_buf = NULL; 429 } 430 431 if (i2c_dev->tx_dma_chan) { 432 dma_release_channel(i2c_dev->tx_dma_chan); 433 i2c_dev->tx_dma_chan = NULL; 434 } 435 436 if (i2c_dev->rx_dma_chan) { 437 dma_release_channel(i2c_dev->rx_dma_chan); 438 i2c_dev->rx_dma_chan = NULL; 439 } 440 } 441 442 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 443 { 444 struct dma_chan *chan; 445 dma_addr_t dma_phys; 446 u32 *dma_buf; 447 int err; 448 449 if (i2c_dev->is_vi) 450 return 0; 451 452 if (!i2c_dev->hw->has_apb_dma) { 453 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 454 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); 455 return 0; 456 } 457 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) { 458 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); 459 return 0; 460 } 461 462 chan = dma_request_chan(i2c_dev->dev, "rx"); 463 if (IS_ERR(chan)) { 464 err = PTR_ERR(chan); 465 goto err_out; 466 } 467 468 i2c_dev->rx_dma_chan = chan; 469 470 chan = dma_request_chan(i2c_dev->dev, "tx"); 471 if (IS_ERR(chan)) { 472 err = PTR_ERR(chan); 473 goto err_out; 474 } 475 476 i2c_dev->tx_dma_chan = chan; 477 478 WARN_ON(i2c_dev->tx_dma_chan->device != i2c_dev->rx_dma_chan->device); 479 i2c_dev->dma_dev = chan->device->dev; 480 481 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + 482 I2C_PACKET_HEADER_SIZE; 483 484 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 485 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 486 if (!dma_buf) { 487 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); 488 err = -ENOMEM; 489 goto err_out; 490 } 491 492 i2c_dev->dma_buf = dma_buf; 493 i2c_dev->dma_phys = dma_phys; 494 495 return 0; 496 497 err_out: 498 tegra_i2c_release_dma(i2c_dev); 499 if (err != -EPROBE_DEFER) { 500 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 501 dev_err(i2c_dev->dev, "falling back to PIO\n"); 502 return 0; 503 } 504 505 return err; 506 } 507 508 /* 509 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 510 * block. This block is identical to the rest of the I2C blocks, except that 511 * it only supports master mode, it has registers moved around, and it needs 512 * some extra init to get it into I2C mode. The register moves are handled 513 * by i2c_readl() and i2c_writel(). 514 */ 515 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 516 { 517 u32 val; 518 519 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 520 val |= DVC_CTRL_REG3_SW_PROG; 521 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 522 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 523 524 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 525 val |= DVC_CTRL_REG1_INTR_EN; 526 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 527 } 528 529 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) 530 { 531 u32 value; 532 533 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 534 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 535 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 536 537 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 538 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 539 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 540 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 541 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 542 543 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 544 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 545 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 546 547 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 548 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 549 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 550 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 551 552 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 553 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 554 555 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 556 } 557 558 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 559 u32 reg, u32 mask, u32 delay_us, 560 u32 timeout_us) 561 { 562 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 563 u32 val; 564 565 if (!i2c_dev->atomic_mode) 566 return readl_relaxed_poll_timeout(addr, val, !(val & mask), 567 delay_us, timeout_us); 568 569 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), 570 delay_us, timeout_us); 571 } 572 573 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 574 { 575 u32 mask, val, offset; 576 int err; 577 578 if (i2c_dev->hw->has_mst_fifo) { 579 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 580 I2C_MST_FIFO_CONTROL_RX_FLUSH; 581 offset = I2C_MST_FIFO_CONTROL; 582 } else { 583 mask = I2C_FIFO_CONTROL_TX_FLUSH | 584 I2C_FIFO_CONTROL_RX_FLUSH; 585 offset = I2C_FIFO_CONTROL; 586 } 587 588 val = i2c_readl(i2c_dev, offset); 589 val |= mask; 590 i2c_writel(i2c_dev, val, offset); 591 592 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000); 593 if (err) { 594 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); 595 return err; 596 } 597 598 return 0; 599 } 600 601 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 602 { 603 int err; 604 605 if (!i2c_dev->hw->has_config_load_reg) 606 return 0; 607 608 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 609 610 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 611 1000, I2C_CONFIG_LOAD_TIMEOUT); 612 if (err) { 613 dev_err(i2c_dev->dev, "failed to load config\n"); 614 return err; 615 } 616 617 return 0; 618 } 619 620 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 621 { 622 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 623 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); 624 struct i2c_timings *t = &i2c_dev->timings; 625 int err; 626 627 /* 628 * The reset shouldn't ever fail in practice. The failure will be a 629 * sign of a severe problem that needs to be resolved. Still we don't 630 * want to fail the initialization completely because this may break 631 * kernel boot up since voltage regulators use I2C. Hence, we will 632 * emit a noisy warning on error, which won't stay unnoticed and 633 * won't hose machine entirely. 634 */ 635 if (handle) 636 err = acpi_evaluate_object(handle, "_RST", NULL, NULL); 637 else 638 err = reset_control_reset(i2c_dev->rst); 639 640 WARN_ON_ONCE(err); 641 642 if (i2c_dev->is_dvc) 643 tegra_dvc_init(i2c_dev); 644 645 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 646 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); 647 648 if (i2c_dev->hw->has_multi_master_mode) 649 val |= I2C_CNFG_MULTI_MASTER_MODE; 650 651 i2c_writel(i2c_dev, val, I2C_CNFG); 652 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 653 654 if (i2c_dev->is_vi) 655 tegra_i2c_vi_init(i2c_dev); 656 657 switch (t->bus_freq_hz) { 658 case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 659 default: 660 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 661 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 662 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 663 664 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 665 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 666 else 667 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 668 break; 669 670 case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 671 tlow = i2c_dev->hw->tlow_std_mode; 672 thigh = i2c_dev->hw->thigh_std_mode; 673 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 674 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 675 break; 676 } 677 678 /* make sure clock divisor programmed correctly */ 679 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 680 i2c_dev->hw->clk_divisor_hs_mode) | 681 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 682 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 683 684 if (i2c_dev->hw->has_interface_timing_reg) { 685 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 686 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 687 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 688 } 689 690 /* 691 * Configure setup and hold times only when tsu_thd is non-zero. 692 * Otherwise, preserve the chip default values. 693 */ 694 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 695 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 696 697 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 698 699 err = clk_set_rate(i2c_dev->div_clk, 700 t->bus_freq_hz * clk_multiplier); 701 if (err) { 702 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); 703 return err; 704 } 705 706 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) { 707 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 708 709 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 710 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 711 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 712 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 713 } 714 715 err = tegra_i2c_flush_fifos(i2c_dev); 716 if (err) 717 return err; 718 719 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 720 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 721 722 err = tegra_i2c_wait_for_config_load(i2c_dev); 723 if (err) 724 return err; 725 726 return 0; 727 } 728 729 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 730 { 731 u32 cnfg; 732 733 /* 734 * NACK interrupt is generated before the I2C controller generates 735 * the STOP condition on the bus. So, wait for 2 clock periods 736 * before disabling the controller so that the STOP condition has 737 * been delivered properly. 738 */ 739 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); 740 741 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 742 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 743 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 744 745 return tegra_i2c_wait_for_config_load(i2c_dev); 746 } 747 748 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 749 { 750 size_t buf_remaining = i2c_dev->msg_buf_remaining; 751 unsigned int words_to_transfer, rx_fifo_avail; 752 u8 *buf = i2c_dev->msg_buf; 753 u32 val; 754 755 /* 756 * Catch overflow due to message fully sent before the check for 757 * RX FIFO availability. 758 */ 759 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 760 return -EINVAL; 761 762 if (i2c_dev->hw->has_mst_fifo) { 763 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 764 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 765 } else { 766 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 767 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 768 } 769 770 /* round down to exclude partial word at the end of buffer */ 771 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 772 if (words_to_transfer > rx_fifo_avail) 773 words_to_transfer = rx_fifo_avail; 774 775 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 776 777 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 778 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 779 rx_fifo_avail -= words_to_transfer; 780 781 /* 782 * If there is a partial word at the end of buffer, handle it 783 * manually to prevent overwriting past the end of buffer. 784 */ 785 if (rx_fifo_avail > 0 && buf_remaining > 0) { 786 /* 787 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 788 * when (words_to_transfer was > rx_fifo_avail) earlier 789 * in this function. 790 */ 791 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 792 val = cpu_to_le32(val); 793 memcpy(buf, &val, buf_remaining); 794 buf_remaining = 0; 795 rx_fifo_avail--; 796 } 797 798 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 799 if (WARN_ON_ONCE(rx_fifo_avail)) 800 return -EINVAL; 801 802 i2c_dev->msg_buf_remaining = buf_remaining; 803 i2c_dev->msg_buf = buf; 804 805 return 0; 806 } 807 808 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 809 { 810 size_t buf_remaining = i2c_dev->msg_buf_remaining; 811 unsigned int words_to_transfer, tx_fifo_avail; 812 u8 *buf = i2c_dev->msg_buf; 813 u32 val; 814 815 if (i2c_dev->hw->has_mst_fifo) { 816 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 817 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 818 } else { 819 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 820 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 821 } 822 823 /* round down to exclude partial word at the end of buffer */ 824 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 825 826 /* 827 * This hunk pushes 4 bytes at a time into the TX FIFO. 828 * 829 * It's very common to have < 4 bytes, hence there is no word 830 * to push if we have less than 4 bytes to transfer. 831 */ 832 if (words_to_transfer) { 833 if (words_to_transfer > tx_fifo_avail) 834 words_to_transfer = tx_fifo_avail; 835 836 /* 837 * Update state before writing to FIFO. Note that this may 838 * cause us to finish writing all bytes (AKA buf_remaining 839 * goes to 0), hence we have a potential for an interrupt 840 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt 841 * is disabled at this point. 842 */ 843 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 844 tx_fifo_avail -= words_to_transfer; 845 846 i2c_dev->msg_buf_remaining = buf_remaining; 847 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 848 849 if (i2c_dev->is_vi) 850 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 851 else 852 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 853 854 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 855 } 856 857 /* 858 * If there is a partial word at the end of buffer, handle it manually 859 * to prevent reading past the end of buffer, which could cross a page 860 * boundary and fault. 861 */ 862 if (tx_fifo_avail > 0 && buf_remaining > 0) { 863 /* 864 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 865 * when (words_to_transfer was > tx_fifo_avail) earlier 866 * in this function for non-zero words_to_transfer. 867 */ 868 memcpy(&val, buf, buf_remaining); 869 val = le32_to_cpu(val); 870 871 i2c_dev->msg_buf_remaining = 0; 872 i2c_dev->msg_buf = NULL; 873 874 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 875 } 876 877 return 0; 878 } 879 880 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 881 { 882 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 883 struct tegra_i2c_dev *i2c_dev = dev_id; 884 u32 status; 885 886 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 887 888 if (status == 0) { 889 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 890 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 891 i2c_readl(i2c_dev, I2C_STATUS), 892 i2c_readl(i2c_dev, I2C_CNFG)); 893 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 894 goto err; 895 } 896 897 if (status & status_err) { 898 tegra_i2c_disable_packet_mode(i2c_dev); 899 if (status & I2C_INT_NO_ACK) 900 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 901 if (status & I2C_INT_ARBITRATION_LOST) 902 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 903 goto err; 904 } 905 906 /* 907 * I2C transfer is terminated during the bus clear, so skip 908 * processing the other interrupts. 909 */ 910 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 911 goto err; 912 913 if (!i2c_dev->dma_mode) { 914 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 915 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 916 /* 917 * Overflow error condition: message fully sent, 918 * with no XFER_COMPLETE interrupt but hardware 919 * asks to transfer more. 920 */ 921 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 922 goto err; 923 } 924 } 925 926 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 927 if (i2c_dev->msg_buf_remaining) 928 tegra_i2c_fill_tx_fifo(i2c_dev); 929 else 930 tegra_i2c_mask_irq(i2c_dev, 931 I2C_INT_TX_FIFO_DATA_REQ); 932 } 933 } 934 935 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 936 if (i2c_dev->is_dvc) 937 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 938 939 /* 940 * During message read XFER_COMPLETE interrupt is triggered prior to 941 * DMA completion and during message write XFER_COMPLETE interrupt is 942 * triggered after DMA completion. 943 * 944 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer, 945 * so forcing msg_buf_remaining to 0 in DMA mode. 946 */ 947 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 948 if (i2c_dev->dma_mode) 949 i2c_dev->msg_buf_remaining = 0; 950 /* 951 * Underflow error condition: XFER_COMPLETE before message 952 * fully sent. 953 */ 954 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 955 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 956 goto err; 957 } 958 complete(&i2c_dev->msg_complete); 959 } 960 goto done; 961 err: 962 /* mask all interrupts on error */ 963 tegra_i2c_mask_irq(i2c_dev, 964 I2C_INT_NO_ACK | 965 I2C_INT_ARBITRATION_LOST | 966 I2C_INT_PACKET_XFER_COMPLETE | 967 I2C_INT_TX_FIFO_DATA_REQ | 968 I2C_INT_RX_FIFO_DATA_REQ); 969 970 if (i2c_dev->hw->supports_bus_clear) 971 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 972 973 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 974 975 if (i2c_dev->is_dvc) 976 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 977 978 if (i2c_dev->dma_mode) { 979 if (i2c_dev->msg_read) 980 dmaengine_terminate_async(i2c_dev->rx_dma_chan); 981 else 982 dmaengine_terminate_async(i2c_dev->tx_dma_chan); 983 984 complete(&i2c_dev->dma_complete); 985 } 986 987 complete(&i2c_dev->msg_complete); 988 done: 989 return IRQ_HANDLED; 990 } 991 992 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 993 size_t len) 994 { 995 struct dma_slave_config slv_config = {0}; 996 u32 val, reg, dma_burst, reg_offset; 997 struct dma_chan *chan; 998 int err; 999 1000 if (i2c_dev->hw->has_mst_fifo) 1001 reg = I2C_MST_FIFO_CONTROL; 1002 else 1003 reg = I2C_FIFO_CONTROL; 1004 1005 if (i2c_dev->dma_mode) { 1006 if (len & 0xF) 1007 dma_burst = 1; 1008 else if (len & 0x10) 1009 dma_burst = 4; 1010 else 1011 dma_burst = 8; 1012 1013 if (i2c_dev->msg_read) { 1014 chan = i2c_dev->rx_dma_chan; 1015 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 1016 1017 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 1018 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1019 slv_config.src_maxburst = dma_burst; 1020 1021 if (i2c_dev->hw->has_mst_fifo) 1022 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 1023 else 1024 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1025 } else { 1026 chan = i2c_dev->tx_dma_chan; 1027 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1028 1029 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1030 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1031 slv_config.dst_maxburst = dma_burst; 1032 1033 if (i2c_dev->hw->has_mst_fifo) 1034 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 1035 else 1036 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 1037 } 1038 1039 slv_config.device_fc = true; 1040 err = dmaengine_slave_config(chan, &slv_config); 1041 if (err) { 1042 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); 1043 dev_err(i2c_dev->dev, "falling back to PIO\n"); 1044 1045 tegra_i2c_release_dma(i2c_dev); 1046 i2c_dev->dma_mode = false; 1047 } else { 1048 goto out; 1049 } 1050 } 1051 1052 if (i2c_dev->hw->has_mst_fifo) 1053 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 1054 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 1055 else 1056 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 1057 I2C_FIFO_CONTROL_RX_TRIG(1); 1058 out: 1059 i2c_writel(i2c_dev, val, reg); 1060 } 1061 1062 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev, 1063 struct completion *complete, 1064 unsigned int timeout_ms) 1065 { 1066 ktime_t ktime = ktime_get(); 1067 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1068 1069 do { 1070 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1071 1072 if (status) 1073 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1074 1075 if (completion_done(complete)) { 1076 s64 delta = ktime_ms_delta(ktimeout, ktime); 1077 1078 return msecs_to_jiffies(delta) ?: 1; 1079 } 1080 1081 ktime = ktime_get(); 1082 1083 } while (ktime_before(ktime, ktimeout)); 1084 1085 return 0; 1086 } 1087 1088 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev, 1089 struct completion *complete, 1090 unsigned int timeout_ms) 1091 { 1092 unsigned long ret; 1093 1094 if (i2c_dev->atomic_mode) { 1095 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms); 1096 } else { 1097 enable_irq(i2c_dev->irq); 1098 ret = wait_for_completion_timeout(complete, 1099 msecs_to_jiffies(timeout_ms)); 1100 disable_irq(i2c_dev->irq); 1101 1102 /* 1103 * Under some rare circumstances (like running KASAN + 1104 * NFS root) CPU, which handles interrupt, may stuck in 1105 * uninterruptible state for a significant time. In this 1106 * case we will get timeout if I2C transfer is running on 1107 * a sibling CPU, despite of IRQ being raised. 1108 * 1109 * In order to handle this rare condition, the IRQ status 1110 * needs to be checked after timeout. 1111 */ 1112 if (ret == 0) 1113 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0); 1114 } 1115 1116 return ret; 1117 } 1118 1119 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1120 { 1121 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1122 u32 val, time_left; 1123 int err; 1124 1125 reinit_completion(&i2c_dev->msg_complete); 1126 1127 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1128 I2C_BC_TERMINATE; 1129 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1130 1131 err = tegra_i2c_wait_for_config_load(i2c_dev); 1132 if (err) 1133 return err; 1134 1135 val |= I2C_BC_ENABLE; 1136 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1137 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1138 1139 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); 1140 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1141 1142 if (time_left == 0) { 1143 dev_err(i2c_dev->dev, "failed to clear bus\n"); 1144 return -ETIMEDOUT; 1145 } 1146 1147 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1148 if (!(val & I2C_BC_STATUS)) { 1149 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1150 return -EIO; 1151 } 1152 1153 return -EAGAIN; 1154 } 1155 1156 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, 1157 struct i2c_msg *msg, 1158 enum msg_end_type end_state) 1159 { 1160 u32 *dma_buf = i2c_dev->dma_buf; 1161 u32 packet_header; 1162 1163 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) | 1164 FIELD_PREP(PACKET_HEADER0_PROTOCOL, 1165 PACKET_HEADER0_PROTOCOL_I2C) | 1166 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | 1167 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1); 1168 1169 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1170 *dma_buf++ = packet_header; 1171 else 1172 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1173 1174 packet_header = i2c_dev->msg_len - 1; 1175 1176 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1177 *dma_buf++ = packet_header; 1178 else 1179 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1180 1181 packet_header = I2C_HEADER_IE_ENABLE; 1182 1183 if (end_state == MSG_END_CONTINUE) 1184 packet_header |= I2C_HEADER_CONTINUE_XFER; 1185 else if (end_state == MSG_END_REPEAT_START) 1186 packet_header |= I2C_HEADER_REPEAT_START; 1187 1188 if (msg->flags & I2C_M_TEN) { 1189 packet_header |= msg->addr; 1190 packet_header |= I2C_HEADER_10BIT_ADDR; 1191 } else { 1192 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1193 } 1194 1195 if (msg->flags & I2C_M_IGNORE_NAK) 1196 packet_header |= I2C_HEADER_CONT_ON_NAK; 1197 1198 if (msg->flags & I2C_M_RD) 1199 packet_header |= I2C_HEADER_READ; 1200 1201 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1202 *dma_buf++ = packet_header; 1203 else 1204 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1205 } 1206 1207 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, 1208 struct i2c_msg *msg) 1209 { 1210 if (i2c_dev->msg_err == I2C_ERR_NONE) 1211 return 0; 1212 1213 tegra_i2c_init(i2c_dev); 1214 1215 /* start recovery upon arbitration loss in single master mode */ 1216 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1217 if (!i2c_dev->multimaster_mode) 1218 return i2c_recover_bus(&i2c_dev->adapter); 1219 1220 return -EAGAIN; 1221 } 1222 1223 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1224 if (msg->flags & I2C_M_IGNORE_NAK) 1225 return 0; 1226 1227 return -EREMOTEIO; 1228 } 1229 1230 return -EIO; 1231 } 1232 1233 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1234 struct i2c_msg *msg, 1235 enum msg_end_type end_state) 1236 { 1237 unsigned long time_left, xfer_time = 100; 1238 size_t xfer_size; 1239 u32 int_mask; 1240 int err; 1241 1242 err = tegra_i2c_flush_fifos(i2c_dev); 1243 if (err) 1244 return err; 1245 1246 i2c_dev->msg_buf = msg->buf; 1247 i2c_dev->msg_len = msg->len; 1248 1249 i2c_dev->msg_err = I2C_ERR_NONE; 1250 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); 1251 reinit_completion(&i2c_dev->msg_complete); 1252 1253 /* 1254 * For SMBUS block read command, read only 1 byte in the first transfer. 1255 * Adjust that 1 byte for the next transfer in the msg buffer and msg 1256 * length. 1257 */ 1258 if (msg->flags & I2C_M_RECV_LEN) { 1259 if (end_state == MSG_END_CONTINUE) { 1260 i2c_dev->msg_len = 1; 1261 } else { 1262 i2c_dev->msg_buf += 1; 1263 i2c_dev->msg_len -= 1; 1264 } 1265 } 1266 1267 i2c_dev->msg_buf_remaining = i2c_dev->msg_len; 1268 1269 if (i2c_dev->msg_read) 1270 xfer_size = i2c_dev->msg_len; 1271 else 1272 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE; 1273 1274 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1275 1276 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && 1277 i2c_dev->dma_buf && !i2c_dev->atomic_mode; 1278 1279 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1280 1281 /* 1282 * Transfer time in mSec = Total bits / transfer rate 1283 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1284 */ 1285 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1286 i2c_dev->timings.bus_freq_hz); 1287 1288 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1289 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1290 1291 if (i2c_dev->dma_mode) { 1292 if (i2c_dev->msg_read) { 1293 dma_sync_single_for_device(i2c_dev->dma_dev, 1294 i2c_dev->dma_phys, 1295 xfer_size, DMA_FROM_DEVICE); 1296 1297 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1298 if (err) 1299 return err; 1300 } else { 1301 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1302 i2c_dev->dma_phys, 1303 xfer_size, DMA_TO_DEVICE); 1304 } 1305 } 1306 1307 tegra_i2c_push_packet_header(i2c_dev, msg, end_state); 1308 1309 if (!i2c_dev->msg_read) { 1310 if (i2c_dev->dma_mode) { 1311 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, 1312 msg->buf, i2c_dev->msg_len); 1313 1314 dma_sync_single_for_device(i2c_dev->dma_dev, 1315 i2c_dev->dma_phys, 1316 xfer_size, DMA_TO_DEVICE); 1317 1318 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1319 if (err) 1320 return err; 1321 } else { 1322 tegra_i2c_fill_tx_fifo(i2c_dev); 1323 } 1324 } 1325 1326 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1327 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1328 1329 if (!i2c_dev->dma_mode) { 1330 if (msg->flags & I2C_M_RD) 1331 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1332 else if (i2c_dev->msg_buf_remaining) 1333 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1334 } 1335 1336 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1337 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1338 i2c_readl(i2c_dev, I2C_INT_MASK)); 1339 1340 if (i2c_dev->dma_mode) { 1341 time_left = tegra_i2c_wait_completion(i2c_dev, 1342 &i2c_dev->dma_complete, 1343 xfer_time); 1344 1345 /* 1346 * Synchronize DMA first, since dmaengine_terminate_sync() 1347 * performs synchronization after the transfer's termination 1348 * and we want to get a completion if transfer succeeded. 1349 */ 1350 dmaengine_synchronize(i2c_dev->msg_read ? 1351 i2c_dev->rx_dma_chan : 1352 i2c_dev->tx_dma_chan); 1353 1354 dmaengine_terminate_sync(i2c_dev->msg_read ? 1355 i2c_dev->rx_dma_chan : 1356 i2c_dev->tx_dma_chan); 1357 1358 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1359 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); 1360 tegra_i2c_init(i2c_dev); 1361 return -ETIMEDOUT; 1362 } 1363 1364 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1365 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1366 i2c_dev->dma_phys, 1367 xfer_size, DMA_FROM_DEVICE); 1368 1369 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len); 1370 } 1371 } 1372 1373 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 1374 xfer_time); 1375 1376 tegra_i2c_mask_irq(i2c_dev, int_mask); 1377 1378 if (time_left == 0) { 1379 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); 1380 tegra_i2c_init(i2c_dev); 1381 return -ETIMEDOUT; 1382 } 1383 1384 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1385 time_left, completion_done(&i2c_dev->msg_complete), 1386 i2c_dev->msg_err); 1387 1388 i2c_dev->dma_mode = false; 1389 1390 err = tegra_i2c_error_recover(i2c_dev, msg); 1391 if (err) 1392 return err; 1393 1394 return 0; 1395 } 1396 1397 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1398 int num) 1399 { 1400 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1401 int i, ret; 1402 1403 ret = pm_runtime_get_sync(i2c_dev->dev); 1404 if (ret < 0) { 1405 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1406 pm_runtime_put_noidle(i2c_dev->dev); 1407 return ret; 1408 } 1409 1410 for (i = 0; i < num; i++) { 1411 enum msg_end_type end_type = MSG_END_STOP; 1412 1413 if (i < (num - 1)) { 1414 /* check whether follow up message is coming */ 1415 if (msgs[i + 1].flags & I2C_M_NOSTART) 1416 end_type = MSG_END_CONTINUE; 1417 else 1418 end_type = MSG_END_REPEAT_START; 1419 } 1420 /* If M_RECV_LEN use ContinueXfer to read the first byte */ 1421 if (msgs[i].flags & I2C_M_RECV_LEN) { 1422 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE); 1423 if (ret) 1424 break; 1425 /* Set the msg length from first byte */ 1426 msgs[i].len += msgs[i].buf[0]; 1427 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); 1428 } 1429 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1430 if (ret) 1431 break; 1432 } 1433 1434 pm_runtime_put(i2c_dev->dev); 1435 1436 return ret ?: i; 1437 } 1438 1439 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1440 struct i2c_msg msgs[], int num) 1441 { 1442 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1443 int ret; 1444 1445 i2c_dev->atomic_mode = true; 1446 ret = tegra_i2c_xfer(adap, msgs, num); 1447 i2c_dev->atomic_mode = false; 1448 1449 return ret; 1450 } 1451 1452 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1453 { 1454 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1455 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1456 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1457 1458 if (i2c_dev->hw->has_continue_xfer_support) 1459 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1460 1461 return ret; 1462 } 1463 1464 static const struct i2c_algorithm tegra_i2c_algo = { 1465 .master_xfer = tegra_i2c_xfer, 1466 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1467 .functionality = tegra_i2c_func, 1468 }; 1469 1470 /* payload size is only 12 bit */ 1471 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1472 .flags = I2C_AQ_NO_ZERO_LEN, 1473 .max_read_len = SZ_4K, 1474 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1475 }; 1476 1477 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1478 .flags = I2C_AQ_NO_ZERO_LEN, 1479 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1480 }; 1481 1482 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1483 .recover_bus = tegra_i2c_issue_bus_clear, 1484 }; 1485 1486 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1487 .has_continue_xfer_support = false, 1488 .has_per_pkt_xfer_complete_irq = false, 1489 .clk_divisor_hs_mode = 3, 1490 .clk_divisor_std_mode = 0, 1491 .clk_divisor_fast_mode = 0, 1492 .clk_divisor_fast_plus_mode = 0, 1493 .has_config_load_reg = false, 1494 .has_multi_master_mode = false, 1495 .has_slcg_override_reg = false, 1496 .has_mst_fifo = false, 1497 .quirks = &tegra_i2c_quirks, 1498 .supports_bus_clear = false, 1499 .has_apb_dma = true, 1500 .tlow_std_mode = 0x4, 1501 .thigh_std_mode = 0x2, 1502 .tlow_fast_fastplus_mode = 0x4, 1503 .thigh_fast_fastplus_mode = 0x2, 1504 .setup_hold_time_std_mode = 0x0, 1505 .setup_hold_time_fast_fast_plus_mode = 0x0, 1506 .setup_hold_time_hs_mode = 0x0, 1507 .has_interface_timing_reg = false, 1508 }; 1509 1510 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1511 .has_continue_xfer_support = true, 1512 .has_per_pkt_xfer_complete_irq = false, 1513 .clk_divisor_hs_mode = 3, 1514 .clk_divisor_std_mode = 0, 1515 .clk_divisor_fast_mode = 0, 1516 .clk_divisor_fast_plus_mode = 0, 1517 .has_config_load_reg = false, 1518 .has_multi_master_mode = false, 1519 .has_slcg_override_reg = false, 1520 .has_mst_fifo = false, 1521 .quirks = &tegra_i2c_quirks, 1522 .supports_bus_clear = false, 1523 .has_apb_dma = true, 1524 .tlow_std_mode = 0x4, 1525 .thigh_std_mode = 0x2, 1526 .tlow_fast_fastplus_mode = 0x4, 1527 .thigh_fast_fastplus_mode = 0x2, 1528 .setup_hold_time_std_mode = 0x0, 1529 .setup_hold_time_fast_fast_plus_mode = 0x0, 1530 .setup_hold_time_hs_mode = 0x0, 1531 .has_interface_timing_reg = false, 1532 }; 1533 1534 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1535 .has_continue_xfer_support = true, 1536 .has_per_pkt_xfer_complete_irq = true, 1537 .clk_divisor_hs_mode = 1, 1538 .clk_divisor_std_mode = 0x19, 1539 .clk_divisor_fast_mode = 0x19, 1540 .clk_divisor_fast_plus_mode = 0x10, 1541 .has_config_load_reg = false, 1542 .has_multi_master_mode = false, 1543 .has_slcg_override_reg = false, 1544 .has_mst_fifo = false, 1545 .quirks = &tegra_i2c_quirks, 1546 .supports_bus_clear = true, 1547 .has_apb_dma = true, 1548 .tlow_std_mode = 0x4, 1549 .thigh_std_mode = 0x2, 1550 .tlow_fast_fastplus_mode = 0x4, 1551 .thigh_fast_fastplus_mode = 0x2, 1552 .setup_hold_time_std_mode = 0x0, 1553 .setup_hold_time_fast_fast_plus_mode = 0x0, 1554 .setup_hold_time_hs_mode = 0x0, 1555 .has_interface_timing_reg = false, 1556 }; 1557 1558 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1559 .has_continue_xfer_support = true, 1560 .has_per_pkt_xfer_complete_irq = true, 1561 .clk_divisor_hs_mode = 1, 1562 .clk_divisor_std_mode = 0x19, 1563 .clk_divisor_fast_mode = 0x19, 1564 .clk_divisor_fast_plus_mode = 0x10, 1565 .has_config_load_reg = true, 1566 .has_multi_master_mode = false, 1567 .has_slcg_override_reg = true, 1568 .has_mst_fifo = false, 1569 .quirks = &tegra_i2c_quirks, 1570 .supports_bus_clear = true, 1571 .has_apb_dma = true, 1572 .tlow_std_mode = 0x4, 1573 .thigh_std_mode = 0x2, 1574 .tlow_fast_fastplus_mode = 0x4, 1575 .thigh_fast_fastplus_mode = 0x2, 1576 .setup_hold_time_std_mode = 0x0, 1577 .setup_hold_time_fast_fast_plus_mode = 0x0, 1578 .setup_hold_time_hs_mode = 0x0, 1579 .has_interface_timing_reg = true, 1580 }; 1581 1582 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1583 .has_continue_xfer_support = true, 1584 .has_per_pkt_xfer_complete_irq = true, 1585 .clk_divisor_hs_mode = 1, 1586 .clk_divisor_std_mode = 0x19, 1587 .clk_divisor_fast_mode = 0x19, 1588 .clk_divisor_fast_plus_mode = 0x10, 1589 .has_config_load_reg = true, 1590 .has_multi_master_mode = false, 1591 .has_slcg_override_reg = true, 1592 .has_mst_fifo = false, 1593 .quirks = &tegra_i2c_quirks, 1594 .supports_bus_clear = true, 1595 .has_apb_dma = true, 1596 .tlow_std_mode = 0x4, 1597 .thigh_std_mode = 0x2, 1598 .tlow_fast_fastplus_mode = 0x4, 1599 .thigh_fast_fastplus_mode = 0x2, 1600 .setup_hold_time_std_mode = 0, 1601 .setup_hold_time_fast_fast_plus_mode = 0, 1602 .setup_hold_time_hs_mode = 0, 1603 .has_interface_timing_reg = true, 1604 }; 1605 1606 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1607 .has_continue_xfer_support = true, 1608 .has_per_pkt_xfer_complete_irq = true, 1609 .clk_divisor_hs_mode = 1, 1610 .clk_divisor_std_mode = 0x16, 1611 .clk_divisor_fast_mode = 0x19, 1612 .clk_divisor_fast_plus_mode = 0x10, 1613 .has_config_load_reg = true, 1614 .has_multi_master_mode = false, 1615 .has_slcg_override_reg = true, 1616 .has_mst_fifo = false, 1617 .quirks = &tegra_i2c_quirks, 1618 .supports_bus_clear = true, 1619 .has_apb_dma = false, 1620 .tlow_std_mode = 0x4, 1621 .thigh_std_mode = 0x3, 1622 .tlow_fast_fastplus_mode = 0x4, 1623 .thigh_fast_fastplus_mode = 0x2, 1624 .setup_hold_time_std_mode = 0, 1625 .setup_hold_time_fast_fast_plus_mode = 0, 1626 .setup_hold_time_hs_mode = 0, 1627 .has_interface_timing_reg = true, 1628 }; 1629 1630 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1631 .has_continue_xfer_support = true, 1632 .has_per_pkt_xfer_complete_irq = true, 1633 .clk_divisor_hs_mode = 1, 1634 .clk_divisor_std_mode = 0x4f, 1635 .clk_divisor_fast_mode = 0x3c, 1636 .clk_divisor_fast_plus_mode = 0x16, 1637 .has_config_load_reg = true, 1638 .has_multi_master_mode = true, 1639 .has_slcg_override_reg = true, 1640 .has_mst_fifo = true, 1641 .quirks = &tegra194_i2c_quirks, 1642 .supports_bus_clear = true, 1643 .has_apb_dma = false, 1644 .tlow_std_mode = 0x8, 1645 .thigh_std_mode = 0x7, 1646 .tlow_fast_fastplus_mode = 0x2, 1647 .thigh_fast_fastplus_mode = 0x2, 1648 .setup_hold_time_std_mode = 0x08080808, 1649 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1650 .setup_hold_time_hs_mode = 0x090909, 1651 .has_interface_timing_reg = true, 1652 }; 1653 1654 static const struct of_device_id tegra_i2c_of_match[] = { 1655 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1656 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1657 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1658 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1659 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1660 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1661 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1662 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1663 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1664 {}, 1665 }; 1666 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1667 1668 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1669 { 1670 struct device_node *np = i2c_dev->dev->of_node; 1671 bool multi_mode; 1672 1673 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); 1674 1675 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); 1676 i2c_dev->multimaster_mode = multi_mode; 1677 1678 if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 1679 i2c_dev->is_dvc = true; 1680 1681 if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 1682 i2c_dev->is_vi = true; 1683 } 1684 1685 static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) 1686 { 1687 if (ACPI_HANDLE(i2c_dev->dev)) 1688 return 0; 1689 1690 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); 1691 if (IS_ERR(i2c_dev->rst)) 1692 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), 1693 "failed to get reset control\n"); 1694 1695 return 0; 1696 } 1697 1698 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) 1699 { 1700 int err; 1701 1702 if (ACPI_HANDLE(i2c_dev->dev)) 1703 return 0; 1704 1705 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; 1706 1707 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) 1708 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; 1709 1710 if (i2c_dev->is_vi) 1711 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; 1712 1713 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, 1714 i2c_dev->clocks); 1715 if (err) 1716 return err; 1717 1718 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); 1719 if (err) 1720 return err; 1721 1722 i2c_dev->div_clk = i2c_dev->clocks[0].clk; 1723 1724 if (!i2c_dev->multimaster_mode) 1725 return 0; 1726 1727 err = clk_enable(i2c_dev->div_clk); 1728 if (err) { 1729 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); 1730 goto unprepare_clocks; 1731 } 1732 1733 return 0; 1734 1735 unprepare_clocks: 1736 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1737 1738 return err; 1739 } 1740 1741 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev) 1742 { 1743 if (i2c_dev->multimaster_mode) 1744 clk_disable(i2c_dev->div_clk); 1745 1746 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1747 } 1748 1749 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev) 1750 { 1751 int ret; 1752 1753 ret = pm_runtime_get_sync(i2c_dev->dev); 1754 if (ret < 0) 1755 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); 1756 else 1757 ret = tegra_i2c_init(i2c_dev); 1758 1759 pm_runtime_put_sync(i2c_dev->dev); 1760 1761 return ret; 1762 } 1763 1764 static int tegra_i2c_probe(struct platform_device *pdev) 1765 { 1766 struct tegra_i2c_dev *i2c_dev; 1767 struct resource *res; 1768 int err; 1769 1770 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1771 if (!i2c_dev) 1772 return -ENOMEM; 1773 1774 platform_set_drvdata(pdev, i2c_dev); 1775 1776 init_completion(&i2c_dev->msg_complete); 1777 init_completion(&i2c_dev->dma_complete); 1778 1779 i2c_dev->hw = device_get_match_data(&pdev->dev); 1780 i2c_dev->cont_id = pdev->id; 1781 i2c_dev->dev = &pdev->dev; 1782 1783 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1784 if (IS_ERR(i2c_dev->base)) 1785 return PTR_ERR(i2c_dev->base); 1786 1787 i2c_dev->base_phys = res->start; 1788 1789 err = platform_get_irq(pdev, 0); 1790 if (err < 0) 1791 return err; 1792 1793 i2c_dev->irq = err; 1794 1795 /* interrupt will be enabled during of transfer time */ 1796 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1797 1798 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, 1799 NULL, tegra_i2c_isr, 1800 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1801 dev_name(i2c_dev->dev), i2c_dev); 1802 if (err) 1803 return err; 1804 1805 tegra_i2c_parse_dt(i2c_dev); 1806 1807 err = tegra_i2c_init_reset(i2c_dev); 1808 if (err) 1809 return err; 1810 1811 err = tegra_i2c_init_clocks(i2c_dev); 1812 if (err) 1813 return err; 1814 1815 err = tegra_i2c_init_dma(i2c_dev); 1816 if (err) 1817 goto release_clocks; 1818 1819 /* 1820 * VI I2C is in VE power domain which is not always ON and not 1821 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a 1822 * non IRQ-safe domain because this prevents powering off the power 1823 * domain. 1824 * 1825 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't 1826 * be used for atomic transfers. 1827 */ 1828 if (!i2c_dev->is_vi) 1829 pm_runtime_irq_safe(i2c_dev->dev); 1830 1831 pm_runtime_enable(i2c_dev->dev); 1832 1833 err = tegra_i2c_init_hardware(i2c_dev); 1834 if (err) 1835 goto release_rpm; 1836 1837 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1838 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1839 i2c_dev->adapter.dev.parent = i2c_dev->dev; 1840 i2c_dev->adapter.retries = 1; 1841 i2c_dev->adapter.timeout = 6 * HZ; 1842 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1843 i2c_dev->adapter.owner = THIS_MODULE; 1844 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1845 i2c_dev->adapter.algo = &tegra_i2c_algo; 1846 i2c_dev->adapter.nr = pdev->id; 1847 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1848 1849 if (i2c_dev->hw->supports_bus_clear) 1850 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1851 1852 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1853 sizeof(i2c_dev->adapter.name)); 1854 1855 err = i2c_add_numbered_adapter(&i2c_dev->adapter); 1856 if (err) 1857 goto release_rpm; 1858 1859 return 0; 1860 1861 release_rpm: 1862 pm_runtime_disable(i2c_dev->dev); 1863 1864 tegra_i2c_release_dma(i2c_dev); 1865 release_clocks: 1866 tegra_i2c_release_clocks(i2c_dev); 1867 1868 return err; 1869 } 1870 1871 static int tegra_i2c_remove(struct platform_device *pdev) 1872 { 1873 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1874 1875 i2c_del_adapter(&i2c_dev->adapter); 1876 pm_runtime_force_suspend(i2c_dev->dev); 1877 1878 tegra_i2c_release_dma(i2c_dev); 1879 tegra_i2c_release_clocks(i2c_dev); 1880 1881 return 0; 1882 } 1883 1884 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 1885 { 1886 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1887 int err; 1888 1889 err = pinctrl_pm_select_default_state(dev); 1890 if (err) 1891 return err; 1892 1893 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); 1894 if (err) 1895 return err; 1896 1897 /* 1898 * VI I2C device is attached to VE power domain which goes through 1899 * power ON/OFF during runtime PM resume/suspend, meaning that 1900 * controller needs to be re-initialized after power ON. 1901 */ 1902 if (i2c_dev->is_vi) { 1903 err = tegra_i2c_init(i2c_dev); 1904 if (err) 1905 goto disable_clocks; 1906 } 1907 1908 return 0; 1909 1910 disable_clocks: 1911 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1912 1913 return err; 1914 } 1915 1916 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 1917 { 1918 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1919 1920 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1921 1922 return pinctrl_pm_select_idle_state(dev); 1923 } 1924 1925 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1926 { 1927 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1928 int err; 1929 1930 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1931 1932 if (!pm_runtime_status_suspended(dev)) { 1933 err = tegra_i2c_runtime_suspend(dev); 1934 if (err) 1935 return err; 1936 } 1937 1938 return 0; 1939 } 1940 1941 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1942 { 1943 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1944 int err; 1945 1946 /* 1947 * We need to ensure that clocks are enabled so that registers can be 1948 * restored in tegra_i2c_init(). 1949 */ 1950 err = tegra_i2c_runtime_resume(dev); 1951 if (err) 1952 return err; 1953 1954 err = tegra_i2c_init(i2c_dev); 1955 if (err) 1956 return err; 1957 1958 /* 1959 * In case we are runtime suspended, disable clocks again so that we 1960 * don't unbalance the clock reference counts during the next runtime 1961 * resume transition. 1962 */ 1963 if (pm_runtime_status_suspended(dev)) { 1964 err = tegra_i2c_runtime_suspend(dev); 1965 if (err) 1966 return err; 1967 } 1968 1969 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1970 1971 return 0; 1972 } 1973 1974 static const struct dev_pm_ops tegra_i2c_pm = { 1975 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1976 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1977 NULL) 1978 }; 1979 1980 static const struct acpi_device_id tegra_i2c_acpi_match[] = { 1981 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 1982 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 1983 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 1984 { } 1985 }; 1986 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); 1987 1988 static struct platform_driver tegra_i2c_driver = { 1989 .probe = tegra_i2c_probe, 1990 .remove = tegra_i2c_remove, 1991 .driver = { 1992 .name = "tegra-i2c", 1993 .of_match_table = tegra_i2c_of_match, 1994 .acpi_match_table = tegra_i2c_acpi_match, 1995 .pm = &tegra_i2c_pm, 1996 }, 1997 }; 1998 module_platform_driver(tegra_i2c_driver); 1999 2000 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver"); 2001 MODULE_AUTHOR("Colin Cross"); 2002 MODULE_LICENSE("GPL v2"); 2003