1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/platform_device.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/i2c.h> 15 #include <linux/io.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/of_device.h> 20 #include <linux/module.h> 21 #include <linux/reset.h> 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/iopoll.h> 25 26 #include <asm/unaligned.h> 27 28 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 29 #define BYTES_PER_FIFO_WORD 4 30 31 #define I2C_CNFG 0x000 32 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 33 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 34 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 35 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 36 #define I2C_STATUS 0x01C 37 #define I2C_SL_CNFG 0x020 38 #define I2C_SL_CNFG_NACK BIT(1) 39 #define I2C_SL_CNFG_NEWSL BIT(2) 40 #define I2C_SL_ADDR1 0x02c 41 #define I2C_SL_ADDR2 0x030 42 #define I2C_TX_FIFO 0x050 43 #define I2C_RX_FIFO 0x054 44 #define I2C_PACKET_TRANSFER_STATUS 0x058 45 #define I2C_FIFO_CONTROL 0x05c 46 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 47 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 48 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 49 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 50 #define I2C_FIFO_STATUS 0x060 51 #define I2C_FIFO_STATUS_TX_MASK 0xF0 52 #define I2C_FIFO_STATUS_TX_SHIFT 4 53 #define I2C_FIFO_STATUS_RX_MASK 0x0F 54 #define I2C_FIFO_STATUS_RX_SHIFT 0 55 #define I2C_INT_MASK 0x064 56 #define I2C_INT_STATUS 0x068 57 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 58 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6) 59 #define I2C_INT_TX_FIFO_OVERFLOW BIT(5) 60 #define I2C_INT_RX_FIFO_UNDERFLOW BIT(4) 61 #define I2C_INT_NO_ACK BIT(3) 62 #define I2C_INT_ARBITRATION_LOST BIT(2) 63 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 64 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 65 #define I2C_CLK_DIVISOR 0x06c 66 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 67 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 68 69 #define DVC_CTRL_REG1 0x000 70 #define DVC_CTRL_REG1_INTR_EN BIT(10) 71 #define DVC_CTRL_REG2 0x004 72 #define DVC_CTRL_REG3 0x008 73 #define DVC_CTRL_REG3_SW_PROG BIT(26) 74 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 75 #define DVC_STATUS 0x00c 76 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 77 78 #define I2C_ERR_NONE 0x00 79 #define I2C_ERR_NO_ACK 0x01 80 #define I2C_ERR_ARBITRATION_LOST 0x02 81 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 82 83 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 84 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 85 #define PACKET_HEADER0_CONT_ID_SHIFT 12 86 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4) 87 88 #define I2C_HEADER_HIGHSPEED_MODE BIT(22) 89 #define I2C_HEADER_CONT_ON_NAK BIT(21) 90 #define I2C_HEADER_SEND_START_BYTE BIT(20) 91 #define I2C_HEADER_READ BIT(19) 92 #define I2C_HEADER_10BIT_ADDR BIT(18) 93 #define I2C_HEADER_IE_ENABLE BIT(17) 94 #define I2C_HEADER_REPEAT_START BIT(16) 95 #define I2C_HEADER_CONTINUE_XFER BIT(15) 96 #define I2C_HEADER_MASTER_ADDR_SHIFT 12 97 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 98 99 #define I2C_CONFIG_LOAD 0x08C 100 #define I2C_MSTR_CONFIG_LOAD BIT(0) 101 #define I2C_SLV_CONFIG_LOAD BIT(1) 102 #define I2C_TIMEOUT_CONFIG_LOAD BIT(2) 103 104 #define I2C_CLKEN_OVERRIDE 0x090 105 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 106 107 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 108 109 #define I2C_MST_FIFO_CONTROL 0x0b4 110 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 111 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 112 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 113 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 114 115 #define I2C_MST_FIFO_STATUS 0x0b8 116 #define I2C_MST_FIFO_STATUS_RX_MASK 0xff 117 #define I2C_MST_FIFO_STATUS_RX_SHIFT 0 118 #define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000 119 #define I2C_MST_FIFO_STATUS_TX_SHIFT 16 120 121 /* 122 * msg_end_type: The bus control which need to be send at end of transfer. 123 * @MSG_END_STOP: Send stop pulse at end of transfer. 124 * @MSG_END_REPEAT_START: Send repeat start at end of transfer. 125 * @MSG_END_CONTINUE: The following on message is coming and so do not send 126 * stop or repeat start. 127 */ 128 enum msg_end_type { 129 MSG_END_STOP, 130 MSG_END_REPEAT_START, 131 MSG_END_CONTINUE, 132 }; 133 134 /** 135 * struct tegra_i2c_hw_feature : Different HW support on Tegra 136 * @has_continue_xfer_support: Continue transfer supports. 137 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 138 * complete interrupt per packet basis. 139 * @has_single_clk_source: The I2C controller has single clock source. Tegra30 140 * and earlier SoCs have two clock sources i.e. div-clk and 141 * fast-clk. 142 * @has_config_load_reg: Has the config load register to load the new 143 * configuration. 144 * @clk_divisor_hs_mode: Clock divisor in HS mode. 145 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is 146 * applicable if there is no fast clock source i.e. single clock 147 * source. 148 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 149 * applicable if there is no fast clock source (i.e. single 150 * clock source). 151 * @has_multi_master_mode: The I2C controller supports running in single-master 152 * or multi-master mode. 153 * @has_slcg_override_reg: The I2C controller supports a register that 154 * overrides the second level clock gating. 155 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 156 * provides additional features and allows for longer messages to 157 * be transferred in one go. 158 */ 159 struct tegra_i2c_hw_feature { 160 bool has_continue_xfer_support; 161 bool has_per_pkt_xfer_complete_irq; 162 bool has_single_clk_source; 163 bool has_config_load_reg; 164 int clk_divisor_hs_mode; 165 int clk_divisor_std_fast_mode; 166 u16 clk_divisor_fast_plus_mode; 167 bool has_multi_master_mode; 168 bool has_slcg_override_reg; 169 bool has_mst_fifo; 170 }; 171 172 /** 173 * struct tegra_i2c_dev - per device I2C context 174 * @dev: device reference for power management 175 * @hw: Tegra I2C HW feature 176 * @adapter: core I2C layer adapter information 177 * @div_clk: clock reference for div clock of I2C controller 178 * @fast_clk: clock reference for fast clock of I2C controller 179 * @rst: reset control for the I2C controller 180 * @base: ioremapped registers cookie 181 * @cont_id: I2C controller ID, used for packet header 182 * @irq: IRQ number of transfer complete interrupt 183 * @irq_disabled: used to track whether or not the interrupt is enabled 184 * @is_dvc: identifies the DVC I2C controller, has a different register layout 185 * @msg_complete: transfer completion notifier 186 * @msg_err: error code for completed message 187 * @msg_buf: pointer to current message data 188 * @msg_buf_remaining: size of unsent data in the message buffer 189 * @msg_read: identifies read transfers 190 * @bus_clk_rate: current I2C bus clock rate 191 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes 192 * @is_multimaster_mode: track if I2C controller is in multi-master mode 193 * @xfer_lock: lock to serialize transfer submission and processing 194 */ 195 struct tegra_i2c_dev { 196 struct device *dev; 197 const struct tegra_i2c_hw_feature *hw; 198 struct i2c_adapter adapter; 199 struct clk *div_clk; 200 struct clk *fast_clk; 201 struct reset_control *rst; 202 void __iomem *base; 203 int cont_id; 204 int irq; 205 bool irq_disabled; 206 int is_dvc; 207 struct completion msg_complete; 208 int msg_err; 209 u8 *msg_buf; 210 size_t msg_buf_remaining; 211 int msg_read; 212 u32 bus_clk_rate; 213 u16 clk_divisor_non_hs_mode; 214 bool is_multimaster_mode; 215 spinlock_t xfer_lock; 216 }; 217 218 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 219 unsigned long reg) 220 { 221 writel(val, i2c_dev->base + reg); 222 } 223 224 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 225 { 226 return readl(i2c_dev->base + reg); 227 } 228 229 /* 230 * i2c_writel and i2c_readl will offset the register if necessary to talk 231 * to the I2C block inside the DVC block 232 */ 233 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 234 unsigned long reg) 235 { 236 if (i2c_dev->is_dvc) 237 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 238 return reg; 239 } 240 241 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 242 unsigned long reg) 243 { 244 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 245 246 /* Read back register to make sure that register writes completed */ 247 if (reg != I2C_TX_FIFO) 248 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 249 } 250 251 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 252 { 253 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 254 } 255 256 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 257 unsigned long reg, int len) 258 { 259 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 260 } 261 262 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 263 unsigned long reg, int len) 264 { 265 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 266 } 267 268 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 269 { 270 u32 int_mask; 271 272 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 273 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 274 } 275 276 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 277 { 278 u32 int_mask; 279 280 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 281 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 282 } 283 284 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 285 { 286 unsigned long timeout = jiffies + HZ; 287 unsigned int offset; 288 u32 mask, val; 289 290 if (i2c_dev->hw->has_mst_fifo) { 291 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 292 I2C_MST_FIFO_CONTROL_RX_FLUSH; 293 offset = I2C_MST_FIFO_CONTROL; 294 } else { 295 mask = I2C_FIFO_CONTROL_TX_FLUSH | 296 I2C_FIFO_CONTROL_RX_FLUSH; 297 offset = I2C_FIFO_CONTROL; 298 } 299 300 val = i2c_readl(i2c_dev, offset); 301 val |= mask; 302 i2c_writel(i2c_dev, val, offset); 303 304 while (i2c_readl(i2c_dev, offset) & mask) { 305 if (time_after(jiffies, timeout)) { 306 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 307 return -ETIMEDOUT; 308 } 309 msleep(1); 310 } 311 return 0; 312 } 313 314 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 315 { 316 u32 val; 317 int rx_fifo_avail; 318 u8 *buf = i2c_dev->msg_buf; 319 size_t buf_remaining = i2c_dev->msg_buf_remaining; 320 int words_to_transfer; 321 322 if (i2c_dev->hw->has_mst_fifo) { 323 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 324 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >> 325 I2C_MST_FIFO_STATUS_RX_SHIFT; 326 } else { 327 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 328 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 329 I2C_FIFO_STATUS_RX_SHIFT; 330 } 331 332 /* Rounds down to not include partial word at the end of buf */ 333 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 334 if (words_to_transfer > rx_fifo_avail) 335 words_to_transfer = rx_fifo_avail; 336 337 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 338 339 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 340 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 341 rx_fifo_avail -= words_to_transfer; 342 343 /* 344 * If there is a partial word at the end of buf, handle it manually to 345 * prevent overwriting past the end of buf 346 */ 347 if (rx_fifo_avail > 0 && buf_remaining > 0) { 348 BUG_ON(buf_remaining > 3); 349 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 350 val = cpu_to_le32(val); 351 memcpy(buf, &val, buf_remaining); 352 buf_remaining = 0; 353 rx_fifo_avail--; 354 } 355 356 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); 357 i2c_dev->msg_buf_remaining = buf_remaining; 358 i2c_dev->msg_buf = buf; 359 360 return 0; 361 } 362 363 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 364 { 365 u32 val; 366 int tx_fifo_avail; 367 u8 *buf = i2c_dev->msg_buf; 368 size_t buf_remaining = i2c_dev->msg_buf_remaining; 369 int words_to_transfer; 370 371 if (i2c_dev->hw->has_mst_fifo) { 372 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 373 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >> 374 I2C_MST_FIFO_STATUS_TX_SHIFT; 375 } else { 376 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 377 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 378 I2C_FIFO_STATUS_TX_SHIFT; 379 } 380 381 /* Rounds down to not include partial word at the end of buf */ 382 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 383 384 /* It's very common to have < 4 bytes, so optimize that case. */ 385 if (words_to_transfer) { 386 if (words_to_transfer > tx_fifo_avail) 387 words_to_transfer = tx_fifo_avail; 388 389 /* 390 * Update state before writing to FIFO. If this casues us 391 * to finish writing all bytes (AKA buf_remaining goes to 0) we 392 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 393 * not maskable). We need to make sure that the isr sees 394 * buf_remaining as 0 and doesn't call us back re-entrantly. 395 */ 396 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 397 tx_fifo_avail -= words_to_transfer; 398 i2c_dev->msg_buf_remaining = buf_remaining; 399 i2c_dev->msg_buf = buf + 400 words_to_transfer * BYTES_PER_FIFO_WORD; 401 barrier(); 402 403 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 404 405 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 406 } 407 408 /* 409 * If there is a partial word at the end of buf, handle it manually to 410 * prevent reading past the end of buf, which could cross a page 411 * boundary and fault. 412 */ 413 if (tx_fifo_avail > 0 && buf_remaining > 0) { 414 BUG_ON(buf_remaining > 3); 415 memcpy(&val, buf, buf_remaining); 416 val = le32_to_cpu(val); 417 418 /* Again update before writing to FIFO to make sure isr sees. */ 419 i2c_dev->msg_buf_remaining = 0; 420 i2c_dev->msg_buf = NULL; 421 barrier(); 422 423 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 424 } 425 426 return 0; 427 } 428 429 /* 430 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 431 * block. This block is identical to the rest of the I2C blocks, except that 432 * it only supports master mode, it has registers moved around, and it needs 433 * some extra init to get it into I2C mode. The register moves are handled 434 * by i2c_readl and i2c_writel 435 */ 436 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 437 { 438 u32 val; 439 440 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 441 val |= DVC_CTRL_REG3_SW_PROG; 442 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 443 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 444 445 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 446 val |= DVC_CTRL_REG1_INTR_EN; 447 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 448 } 449 450 static int tegra_i2c_runtime_resume(struct device *dev) 451 { 452 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 453 int ret; 454 455 ret = pinctrl_pm_select_default_state(i2c_dev->dev); 456 if (ret) 457 return ret; 458 459 if (!i2c_dev->hw->has_single_clk_source) { 460 ret = clk_enable(i2c_dev->fast_clk); 461 if (ret < 0) { 462 dev_err(i2c_dev->dev, 463 "Enabling fast clk failed, err %d\n", ret); 464 return ret; 465 } 466 } 467 468 ret = clk_enable(i2c_dev->div_clk); 469 if (ret < 0) { 470 dev_err(i2c_dev->dev, 471 "Enabling div clk failed, err %d\n", ret); 472 clk_disable(i2c_dev->fast_clk); 473 return ret; 474 } 475 476 return 0; 477 } 478 479 static int tegra_i2c_runtime_suspend(struct device *dev) 480 { 481 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 482 483 clk_disable(i2c_dev->div_clk); 484 if (!i2c_dev->hw->has_single_clk_source) 485 clk_disable(i2c_dev->fast_clk); 486 487 return pinctrl_pm_select_idle_state(i2c_dev->dev); 488 } 489 490 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 491 { 492 unsigned long reg_offset; 493 void __iomem *addr; 494 u32 val; 495 int err; 496 497 if (i2c_dev->hw->has_config_load_reg) { 498 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); 499 addr = i2c_dev->base + reg_offset; 500 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 501 if (in_interrupt()) 502 err = readl_poll_timeout_atomic(addr, val, val == 0, 503 1000, I2C_CONFIG_LOAD_TIMEOUT); 504 else 505 err = readl_poll_timeout(addr, val, val == 0, 506 1000, I2C_CONFIG_LOAD_TIMEOUT); 507 508 if (err) { 509 dev_warn(i2c_dev->dev, 510 "timeout waiting for config load\n"); 511 return err; 512 } 513 } 514 515 return 0; 516 } 517 518 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 519 { 520 u32 val; 521 int err; 522 u32 clk_divisor; 523 524 err = pm_runtime_get_sync(i2c_dev->dev); 525 if (err < 0) { 526 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err); 527 return err; 528 } 529 530 reset_control_assert(i2c_dev->rst); 531 udelay(2); 532 reset_control_deassert(i2c_dev->rst); 533 534 if (i2c_dev->is_dvc) 535 tegra_dvc_init(i2c_dev); 536 537 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 538 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 539 540 if (i2c_dev->hw->has_multi_master_mode) 541 val |= I2C_CNFG_MULTI_MASTER_MODE; 542 543 i2c_writel(i2c_dev, val, I2C_CNFG); 544 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 545 546 /* Make sure clock divisor programmed correctly */ 547 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; 548 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << 549 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; 550 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 551 552 if (!i2c_dev->is_dvc) { 553 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 554 555 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 556 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 557 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 558 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 559 } 560 561 if (i2c_dev->hw->has_mst_fifo) { 562 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 563 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 564 i2c_writel(i2c_dev, val, I2C_MST_FIFO_CONTROL); 565 } else { 566 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | 567 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; 568 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 569 } 570 571 err = tegra_i2c_flush_fifos(i2c_dev); 572 if (err) 573 goto err; 574 575 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 576 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 577 578 err = tegra_i2c_wait_for_config_load(i2c_dev); 579 if (err) 580 goto err; 581 582 if (i2c_dev->irq_disabled) { 583 i2c_dev->irq_disabled = false; 584 enable_irq(i2c_dev->irq); 585 } 586 587 err: 588 pm_runtime_put(i2c_dev->dev); 589 return err; 590 } 591 592 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 593 { 594 u32 cnfg; 595 596 /* 597 * NACK interrupt is generated before the I2C controller generates 598 * the STOP condition on the bus. So wait for 2 clock periods 599 * before disabling the controller so that the STOP condition has 600 * been delivered properly. 601 */ 602 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 603 604 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 605 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 606 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 607 608 return tegra_i2c_wait_for_config_load(i2c_dev); 609 } 610 611 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 612 { 613 u32 status; 614 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 615 struct tegra_i2c_dev *i2c_dev = dev_id; 616 617 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 618 619 spin_lock(&i2c_dev->xfer_lock); 620 if (status == 0) { 621 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 622 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 623 i2c_readl(i2c_dev, I2C_STATUS), 624 i2c_readl(i2c_dev, I2C_CNFG)); 625 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 626 627 if (!i2c_dev->irq_disabled) { 628 disable_irq_nosync(i2c_dev->irq); 629 i2c_dev->irq_disabled = true; 630 } 631 goto err; 632 } 633 634 if (unlikely(status & status_err)) { 635 tegra_i2c_disable_packet_mode(i2c_dev); 636 if (status & I2C_INT_NO_ACK) 637 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 638 if (status & I2C_INT_ARBITRATION_LOST) 639 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 640 goto err; 641 } 642 643 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 644 if (i2c_dev->msg_buf_remaining) 645 tegra_i2c_empty_rx_fifo(i2c_dev); 646 else 647 BUG(); 648 } 649 650 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 651 if (i2c_dev->msg_buf_remaining) 652 tegra_i2c_fill_tx_fifo(i2c_dev); 653 else 654 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); 655 } 656 657 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 658 if (i2c_dev->is_dvc) 659 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 660 661 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 662 BUG_ON(i2c_dev->msg_buf_remaining); 663 complete(&i2c_dev->msg_complete); 664 } 665 goto done; 666 err: 667 /* An error occurred, mask all interrupts */ 668 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 669 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 670 I2C_INT_RX_FIFO_DATA_REQ); 671 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 672 if (i2c_dev->is_dvc) 673 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 674 675 complete(&i2c_dev->msg_complete); 676 done: 677 spin_unlock(&i2c_dev->xfer_lock); 678 return IRQ_HANDLED; 679 } 680 681 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 682 struct i2c_msg *msg, enum msg_end_type end_state) 683 { 684 u32 packet_header; 685 u32 int_mask; 686 unsigned long time_left; 687 unsigned long flags; 688 689 tegra_i2c_flush_fifos(i2c_dev); 690 691 i2c_dev->msg_buf = msg->buf; 692 i2c_dev->msg_buf_remaining = msg->len; 693 i2c_dev->msg_err = I2C_ERR_NONE; 694 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 695 reinit_completion(&i2c_dev->msg_complete); 696 697 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); 698 699 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 700 tegra_i2c_unmask_irq(i2c_dev, int_mask); 701 702 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 703 PACKET_HEADER0_PROTOCOL_I2C | 704 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 705 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 706 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 707 708 packet_header = msg->len - 1; 709 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 710 711 packet_header = I2C_HEADER_IE_ENABLE; 712 if (end_state == MSG_END_CONTINUE) 713 packet_header |= I2C_HEADER_CONTINUE_XFER; 714 else if (end_state == MSG_END_REPEAT_START) 715 packet_header |= I2C_HEADER_REPEAT_START; 716 if (msg->flags & I2C_M_TEN) { 717 packet_header |= msg->addr; 718 packet_header |= I2C_HEADER_10BIT_ADDR; 719 } else { 720 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 721 } 722 if (msg->flags & I2C_M_IGNORE_NAK) 723 packet_header |= I2C_HEADER_CONT_ON_NAK; 724 if (msg->flags & I2C_M_RD) 725 packet_header |= I2C_HEADER_READ; 726 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 727 728 if (!(msg->flags & I2C_M_RD)) 729 tegra_i2c_fill_tx_fifo(i2c_dev); 730 731 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 732 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 733 if (msg->flags & I2C_M_RD) 734 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 735 else if (i2c_dev->msg_buf_remaining) 736 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 737 738 tegra_i2c_unmask_irq(i2c_dev, int_mask); 739 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); 740 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 741 i2c_readl(i2c_dev, I2C_INT_MASK)); 742 743 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 744 TEGRA_I2C_TIMEOUT); 745 tegra_i2c_mask_irq(i2c_dev, int_mask); 746 747 if (time_left == 0) { 748 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 749 750 tegra_i2c_init(i2c_dev); 751 return -ETIMEDOUT; 752 } 753 754 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 755 time_left, completion_done(&i2c_dev->msg_complete), 756 i2c_dev->msg_err); 757 758 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 759 return 0; 760 761 tegra_i2c_init(i2c_dev); 762 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 763 if (msg->flags & I2C_M_IGNORE_NAK) 764 return 0; 765 return -EREMOTEIO; 766 } 767 768 return -EIO; 769 } 770 771 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 772 int num) 773 { 774 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 775 int i; 776 int ret = 0; 777 778 ret = pm_runtime_get_sync(i2c_dev->dev); 779 if (ret < 0) { 780 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 781 return ret; 782 } 783 784 for (i = 0; i < num; i++) { 785 enum msg_end_type end_type = MSG_END_STOP; 786 787 if (i < (num - 1)) { 788 if (msgs[i + 1].flags & I2C_M_NOSTART) 789 end_type = MSG_END_CONTINUE; 790 else 791 end_type = MSG_END_REPEAT_START; 792 } 793 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 794 if (ret) 795 break; 796 } 797 798 pm_runtime_put(i2c_dev->dev); 799 800 return ret ?: i; 801 } 802 803 static u32 tegra_i2c_func(struct i2c_adapter *adap) 804 { 805 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 806 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 807 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 808 809 if (i2c_dev->hw->has_continue_xfer_support) 810 ret |= I2C_FUNC_NOSTART; 811 return ret; 812 } 813 814 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 815 { 816 struct device_node *np = i2c_dev->dev->of_node; 817 int ret; 818 819 ret = of_property_read_u32(np, "clock-frequency", 820 &i2c_dev->bus_clk_rate); 821 if (ret) 822 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ 823 824 i2c_dev->is_multimaster_mode = of_property_read_bool(np, 825 "multi-master"); 826 } 827 828 static const struct i2c_algorithm tegra_i2c_algo = { 829 .master_xfer = tegra_i2c_xfer, 830 .functionality = tegra_i2c_func, 831 }; 832 833 /* payload size is only 12 bit */ 834 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 835 .flags = I2C_AQ_NO_ZERO_LEN, 836 .max_read_len = 4096, 837 .max_write_len = 4096, 838 }; 839 840 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 841 .has_continue_xfer_support = false, 842 .has_per_pkt_xfer_complete_irq = false, 843 .has_single_clk_source = false, 844 .clk_divisor_hs_mode = 3, 845 .clk_divisor_std_fast_mode = 0, 846 .clk_divisor_fast_plus_mode = 0, 847 .has_config_load_reg = false, 848 .has_multi_master_mode = false, 849 .has_slcg_override_reg = false, 850 .has_mst_fifo = false, 851 }; 852 853 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 854 .has_continue_xfer_support = true, 855 .has_per_pkt_xfer_complete_irq = false, 856 .has_single_clk_source = false, 857 .clk_divisor_hs_mode = 3, 858 .clk_divisor_std_fast_mode = 0, 859 .clk_divisor_fast_plus_mode = 0, 860 .has_config_load_reg = false, 861 .has_multi_master_mode = false, 862 .has_slcg_override_reg = false, 863 .has_mst_fifo = false, 864 }; 865 866 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 867 .has_continue_xfer_support = true, 868 .has_per_pkt_xfer_complete_irq = true, 869 .has_single_clk_source = true, 870 .clk_divisor_hs_mode = 1, 871 .clk_divisor_std_fast_mode = 0x19, 872 .clk_divisor_fast_plus_mode = 0x10, 873 .has_config_load_reg = false, 874 .has_multi_master_mode = false, 875 .has_slcg_override_reg = false, 876 .has_mst_fifo = false, 877 }; 878 879 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 880 .has_continue_xfer_support = true, 881 .has_per_pkt_xfer_complete_irq = true, 882 .has_single_clk_source = true, 883 .clk_divisor_hs_mode = 1, 884 .clk_divisor_std_fast_mode = 0x19, 885 .clk_divisor_fast_plus_mode = 0x10, 886 .has_config_load_reg = true, 887 .has_multi_master_mode = false, 888 .has_slcg_override_reg = true, 889 .has_mst_fifo = false, 890 }; 891 892 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 893 .has_continue_xfer_support = true, 894 .has_per_pkt_xfer_complete_irq = true, 895 .has_single_clk_source = true, 896 .clk_divisor_hs_mode = 1, 897 .clk_divisor_std_fast_mode = 0x19, 898 .clk_divisor_fast_plus_mode = 0x10, 899 .has_config_load_reg = true, 900 .has_multi_master_mode = true, 901 .has_slcg_override_reg = true, 902 .has_mst_fifo = false, 903 }; 904 905 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 906 .has_continue_xfer_support = true, 907 .has_per_pkt_xfer_complete_irq = true, 908 .has_single_clk_source = true, 909 .clk_divisor_hs_mode = 1, 910 .clk_divisor_std_fast_mode = 0x19, 911 .clk_divisor_fast_plus_mode = 0x10, 912 .has_config_load_reg = true, 913 .has_multi_master_mode = true, 914 .has_slcg_override_reg = true, 915 .has_mst_fifo = true, 916 }; 917 918 /* Match table for of_platform binding */ 919 static const struct of_device_id tegra_i2c_of_match[] = { 920 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 921 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 922 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 923 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 924 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 925 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 926 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 927 {}, 928 }; 929 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 930 931 static int tegra_i2c_probe(struct platform_device *pdev) 932 { 933 struct tegra_i2c_dev *i2c_dev; 934 struct resource *res; 935 struct clk *div_clk; 936 struct clk *fast_clk; 937 void __iomem *base; 938 int irq; 939 int ret = 0; 940 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE; 941 942 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 943 base = devm_ioremap_resource(&pdev->dev, res); 944 if (IS_ERR(base)) 945 return PTR_ERR(base); 946 947 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 948 if (!res) { 949 dev_err(&pdev->dev, "no irq resource\n"); 950 return -EINVAL; 951 } 952 irq = res->start; 953 954 div_clk = devm_clk_get(&pdev->dev, "div-clk"); 955 if (IS_ERR(div_clk)) { 956 dev_err(&pdev->dev, "missing controller clock\n"); 957 return PTR_ERR(div_clk); 958 } 959 960 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 961 if (!i2c_dev) 962 return -ENOMEM; 963 964 i2c_dev->base = base; 965 i2c_dev->div_clk = div_clk; 966 i2c_dev->adapter.algo = &tegra_i2c_algo; 967 i2c_dev->adapter.quirks = &tegra_i2c_quirks; 968 i2c_dev->irq = irq; 969 i2c_dev->cont_id = pdev->id; 970 i2c_dev->dev = &pdev->dev; 971 972 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); 973 if (IS_ERR(i2c_dev->rst)) { 974 dev_err(&pdev->dev, "missing controller reset\n"); 975 return PTR_ERR(i2c_dev->rst); 976 } 977 978 tegra_i2c_parse_dt(i2c_dev); 979 980 i2c_dev->hw = of_device_get_match_data(&pdev->dev); 981 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 982 "nvidia,tegra20-i2c-dvc"); 983 init_completion(&i2c_dev->msg_complete); 984 spin_lock_init(&i2c_dev->xfer_lock); 985 986 if (!i2c_dev->hw->has_single_clk_source) { 987 fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); 988 if (IS_ERR(fast_clk)) { 989 dev_err(&pdev->dev, "missing fast clock\n"); 990 return PTR_ERR(fast_clk); 991 } 992 i2c_dev->fast_clk = fast_clk; 993 } 994 995 platform_set_drvdata(pdev, i2c_dev); 996 997 if (!i2c_dev->hw->has_single_clk_source) { 998 ret = clk_prepare(i2c_dev->fast_clk); 999 if (ret < 0) { 1000 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 1001 return ret; 1002 } 1003 } 1004 1005 i2c_dev->clk_divisor_non_hs_mode = 1006 i2c_dev->hw->clk_divisor_std_fast_mode; 1007 if (i2c_dev->hw->clk_divisor_fast_plus_mode && 1008 (i2c_dev->bus_clk_rate == 1000000)) 1009 i2c_dev->clk_divisor_non_hs_mode = 1010 i2c_dev->hw->clk_divisor_fast_plus_mode; 1011 1012 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); 1013 ret = clk_set_rate(i2c_dev->div_clk, 1014 i2c_dev->bus_clk_rate * clk_multiplier); 1015 if (ret) { 1016 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret); 1017 goto unprepare_fast_clk; 1018 } 1019 1020 ret = clk_prepare(i2c_dev->div_clk); 1021 if (ret < 0) { 1022 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 1023 goto unprepare_fast_clk; 1024 } 1025 1026 pm_runtime_enable(&pdev->dev); 1027 if (!pm_runtime_enabled(&pdev->dev)) { 1028 ret = tegra_i2c_runtime_resume(&pdev->dev); 1029 if (ret < 0) { 1030 dev_err(&pdev->dev, "runtime resume failed\n"); 1031 goto unprepare_div_clk; 1032 } 1033 } 1034 1035 if (i2c_dev->is_multimaster_mode) { 1036 ret = clk_enable(i2c_dev->div_clk); 1037 if (ret < 0) { 1038 dev_err(i2c_dev->dev, "div_clk enable failed %d\n", 1039 ret); 1040 goto disable_rpm; 1041 } 1042 } 1043 1044 ret = tegra_i2c_init(i2c_dev); 1045 if (ret) { 1046 dev_err(&pdev->dev, "Failed to initialize i2c controller\n"); 1047 goto disable_div_clk; 1048 } 1049 1050 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 1051 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); 1052 if (ret) { 1053 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 1054 goto disable_div_clk; 1055 } 1056 1057 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1058 i2c_dev->adapter.owner = THIS_MODULE; 1059 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1060 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev), 1061 sizeof(i2c_dev->adapter.name)); 1062 i2c_dev->adapter.dev.parent = &pdev->dev; 1063 i2c_dev->adapter.nr = pdev->id; 1064 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 1065 1066 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 1067 if (ret) 1068 goto disable_div_clk; 1069 1070 return 0; 1071 1072 disable_div_clk: 1073 if (i2c_dev->is_multimaster_mode) 1074 clk_disable(i2c_dev->div_clk); 1075 1076 disable_rpm: 1077 pm_runtime_disable(&pdev->dev); 1078 if (!pm_runtime_status_suspended(&pdev->dev)) 1079 tegra_i2c_runtime_suspend(&pdev->dev); 1080 1081 unprepare_div_clk: 1082 clk_unprepare(i2c_dev->div_clk); 1083 1084 unprepare_fast_clk: 1085 if (!i2c_dev->hw->has_single_clk_source) 1086 clk_unprepare(i2c_dev->fast_clk); 1087 1088 return ret; 1089 } 1090 1091 static int tegra_i2c_remove(struct platform_device *pdev) 1092 { 1093 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1094 1095 i2c_del_adapter(&i2c_dev->adapter); 1096 1097 if (i2c_dev->is_multimaster_mode) 1098 clk_disable(i2c_dev->div_clk); 1099 1100 pm_runtime_disable(&pdev->dev); 1101 if (!pm_runtime_status_suspended(&pdev->dev)) 1102 tegra_i2c_runtime_suspend(&pdev->dev); 1103 1104 clk_unprepare(i2c_dev->div_clk); 1105 if (!i2c_dev->hw->has_single_clk_source) 1106 clk_unprepare(i2c_dev->fast_clk); 1107 1108 return 0; 1109 } 1110 1111 #ifdef CONFIG_PM_SLEEP 1112 static const struct dev_pm_ops tegra_i2c_pm = { 1113 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1114 NULL) 1115 }; 1116 #define TEGRA_I2C_PM (&tegra_i2c_pm) 1117 #else 1118 #define TEGRA_I2C_PM NULL 1119 #endif 1120 1121 static struct platform_driver tegra_i2c_driver = { 1122 .probe = tegra_i2c_probe, 1123 .remove = tegra_i2c_remove, 1124 .driver = { 1125 .name = "tegra-i2c", 1126 .of_match_table = tegra_i2c_of_match, 1127 .pm = TEGRA_I2C_PM, 1128 }, 1129 }; 1130 1131 static int __init tegra_i2c_init_driver(void) 1132 { 1133 return platform_driver_register(&tegra_i2c_driver); 1134 } 1135 1136 static void __exit tegra_i2c_exit_driver(void) 1137 { 1138 platform_driver_unregister(&tegra_i2c_driver); 1139 } 1140 1141 subsys_initcall(tegra_i2c_init_driver); 1142 module_exit(tegra_i2c_exit_driver); 1143 1144 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 1145 MODULE_AUTHOR("Colin Cross"); 1146 MODULE_LICENSE("GPL v2"); 1147