1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2012 FUJITSU SEMICONDUCTOR LIMITED
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/i2c.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21
22 #define WAIT_PCLK(n, rate) \
23 ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10)
24
25 /* I2C register address definitions */
26 #define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status
27 #define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control
28 #define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
29 #define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address
30 #define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data
31 #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
32 #define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
33 #define SYNQUACER_I2C_REG_BC2R (0x07 << 2) // Bus Control 2
34
35 /* I2C register bit definitions */
36 #define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer
37 #define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address
38 #define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave
39 #define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive
40 #define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit
41 #define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost
42 #define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond.
43 #define SYNQUACER_I2C_BSR_BB BIT(7) // Bus Busy
44
45 #define SYNQUACER_I2C_BCR_INT BIT(0) // Interrupt
46 #define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable
47 #define SYNQUACER_I2C_BCR_GCAA BIT(2) // Gen. Call Access Ack.
48 #define SYNQUACER_I2C_BCR_ACK BIT(3) // Acknowledge
49 #define SYNQUACER_I2C_BCR_MSS BIT(4) // Master Slave Select
50 #define SYNQUACER_I2C_BCR_SCC BIT(5) // Start Condition Cont.
51 #define SYNQUACER_I2C_BCR_BEIE BIT(6) // Bus Error Int Enable
52 #define SYNQUACER_I2C_BCR_BER BIT(7) // Bus Error
53
54 #define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
55 #define SYNQUACER_I2C_CCR_EN BIT(5) // Enable
56 #define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select
57
58 #define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
59
60 #define SYNQUACER_I2C_BC2R_SCLL BIT(0) // SCL Low Drive
61 #define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive
62 #define SYNQUACER_I2C_BC2R_SCLS BIT(4) // SCL Status
63 #define SYNQUACER_I2C_BC2R_SDAS BIT(5) // SDA Status
64
65 /* PCLK frequency */
66 #define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
67
68 /* STANDARD MODE frequency */
69 #define SYNQUACER_I2C_CLK_MASTER_STD(rate) \
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
71 /* FAST MODE frequency */
72 #define SYNQUACER_I2C_CLK_MASTER_FAST(rate) \
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
74
75 /* (clkrate <= 18000000) */
76 /* calculate the value of CS bits in CCR register on standard mode */
77 #define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate) \
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
79 & SYNQUACER_I2C_CCR_CS_MASK)
80
81 /* calculate the value of CS bits in CSR register on standard mode */
82 #define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate) 0x00
83
84 /* calculate the value of CS bits in CCR register on fast mode */
85 #define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate) \
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
87 & SYNQUACER_I2C_CCR_CS_MASK)
88
89 /* calculate the value of CS bits in CSR register on fast mode */
90 #define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00
91
92 /* (clkrate > 18000000) */
93 /* calculate the value of CS bits in CCR register on standard mode */
94 #define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate) \
95 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
96 & SYNQUACER_I2C_CCR_CS_MASK)
97
98 /* calculate the value of CS bits in CSR register on standard mode */
99 #define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate) \
100 (((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \
101 & SYNQUACER_I2C_CSR_CS_MASK)
102
103 /* calculate the value of CS bits in CCR register on fast mode */
104 #define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate) \
105 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
106 & SYNQUACER_I2C_CCR_CS_MASK)
107
108 /* calculate the value of CS bits in CSR register on fast mode */
109 #define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate) \
110 (((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5) \
111 & SYNQUACER_I2C_CSR_CS_MASK)
112
113 /* min I2C clock frequency 14M */
114 #define SYNQUACER_I2C_MIN_CLK_RATE (14 * 1000000)
115 /* max I2C clock frequency 200M */
116 #define SYNQUACER_I2C_MAX_CLK_RATE (200 * 1000000)
117 /* I2C clock frequency 18M */
118 #define SYNQUACER_I2C_CLK_RATE_18M (18 * 1000000)
119
120 #define SYNQUACER_I2C_SPEED_FM 400 // Fast Mode
121 #define SYNQUACER_I2C_SPEED_SM 100 // Standard Mode
122
123 enum i2c_state {
124 STATE_IDLE,
125 STATE_START,
126 STATE_READ,
127 STATE_WRITE
128 };
129
130 struct synquacer_i2c {
131 struct completion completion;
132
133 struct i2c_msg *msg;
134 u32 msg_num;
135 u32 msg_idx;
136 u32 msg_ptr;
137
138 int irq;
139 struct device *dev;
140 void __iomem *base;
141 u32 pclkrate;
142 u32 speed_khz;
143 u32 timeout_ms;
144 enum i2c_state state;
145 struct i2c_adapter adapter;
146 };
147
is_lastmsg(struct synquacer_i2c * i2c)148 static inline int is_lastmsg(struct synquacer_i2c *i2c)
149 {
150 return i2c->msg_idx >= (i2c->msg_num - 1);
151 }
152
is_msglast(struct synquacer_i2c * i2c)153 static inline int is_msglast(struct synquacer_i2c *i2c)
154 {
155 return i2c->msg_ptr == (i2c->msg->len - 1);
156 }
157
is_msgend(struct synquacer_i2c * i2c)158 static inline int is_msgend(struct synquacer_i2c *i2c)
159 {
160 return i2c->msg_ptr >= i2c->msg->len;
161 }
162
calc_timeout_ms(struct synquacer_i2c * i2c,struct i2c_msg * msgs,int num)163 static inline unsigned long calc_timeout_ms(struct synquacer_i2c *i2c,
164 struct i2c_msg *msgs,
165 int num)
166 {
167 unsigned long bit_count = 0;
168 int i;
169
170 for (i = 0; i < num; i++, msgs++)
171 bit_count += msgs->len;
172
173 return DIV_ROUND_UP((bit_count * 9 + num * 10) * 3, 200) + 10;
174 }
175
synquacer_i2c_stop(struct synquacer_i2c * i2c,int ret)176 static void synquacer_i2c_stop(struct synquacer_i2c *i2c, int ret)
177 {
178 /*
179 * clear IRQ (INT=0, BER=0)
180 * set Stop Condition (MSS=0)
181 * Interrupt Disable
182 */
183 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
184
185 i2c->state = STATE_IDLE;
186
187 i2c->msg_ptr = 0;
188 i2c->msg = NULL;
189 i2c->msg_idx++;
190 i2c->msg_num = 0;
191 if (ret)
192 i2c->msg_idx = ret;
193
194 complete(&i2c->completion);
195 }
196
synquacer_i2c_hw_init(struct synquacer_i2c * i2c)197 static void synquacer_i2c_hw_init(struct synquacer_i2c *i2c)
198 {
199 unsigned char ccr_cs, csr_cs;
200 u32 rt = i2c->pclkrate;
201
202 /* Set own Address */
203 writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR);
204
205 /* Set PCLK frequency */
206 writeb(SYNQUACER_I2C_BUS_CLK_FR(i2c->pclkrate),
207 i2c->base + SYNQUACER_I2C_REG_FSR);
208
209 switch (i2c->speed_khz) {
210 case SYNQUACER_I2C_SPEED_FM:
211 if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
212 ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rt);
213 csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rt);
214 } else {
215 ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rt);
216 csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rt);
217 }
218
219 /* Set Clock and enable, Set fast mode */
220 writeb(ccr_cs | SYNQUACER_I2C_CCR_FM |
221 SYNQUACER_I2C_CCR_EN,
222 i2c->base + SYNQUACER_I2C_REG_CCR);
223 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
224 break;
225 case SYNQUACER_I2C_SPEED_SM:
226 if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
227 ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rt);
228 csr_cs = SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rt);
229 } else {
230 ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rt);
231 csr_cs = SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rt);
232 }
233
234 /* Set Clock and enable, Set standard mode */
235 writeb(ccr_cs | SYNQUACER_I2C_CCR_EN,
236 i2c->base + SYNQUACER_I2C_REG_CCR);
237 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
238 break;
239 default:
240 WARN_ON(1);
241 }
242
243 /* clear IRQ (INT=0, BER=0), Interrupt Disable */
244 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
245 writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R);
246 }
247
synquacer_i2c_hw_reset(struct synquacer_i2c * i2c)248 static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
249 {
250 /* Disable clock */
251 writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR);
252 writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR);
253
254 WAIT_PCLK(100, i2c->pclkrate);
255 }
256
synquacer_i2c_master_start(struct synquacer_i2c * i2c,struct i2c_msg * pmsg)257 static int synquacer_i2c_master_start(struct synquacer_i2c *i2c,
258 struct i2c_msg *pmsg)
259 {
260 unsigned char bsr, bcr;
261
262 writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR);
263
264 dev_dbg(i2c->dev, "slave:0x%02x\n", pmsg->addr);
265
266 /* Generate Start Condition */
267 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
268 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
269 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
270
271 if ((bsr & SYNQUACER_I2C_BSR_BB) &&
272 !(bcr & SYNQUACER_I2C_BCR_MSS)) {
273 dev_dbg(i2c->dev, "bus is busy");
274 return -EBUSY;
275 }
276
277 if (bsr & SYNQUACER_I2C_BSR_BB) { /* Bus is busy */
278 dev_dbg(i2c->dev, "Continuous Start");
279 writeb(bcr | SYNQUACER_I2C_BCR_SCC,
280 i2c->base + SYNQUACER_I2C_REG_BCR);
281 } else {
282 if (bcr & SYNQUACER_I2C_BCR_MSS) {
283 dev_dbg(i2c->dev, "not in master mode");
284 return -EAGAIN;
285 }
286 dev_dbg(i2c->dev, "Start Condition");
287 /* Start Condition + Enable Interrupts */
288 writeb(bcr | SYNQUACER_I2C_BCR_MSS |
289 SYNQUACER_I2C_BCR_INTE | SYNQUACER_I2C_BCR_BEIE,
290 i2c->base + SYNQUACER_I2C_REG_BCR);
291 }
292
293 WAIT_PCLK(10, i2c->pclkrate);
294
295 /* get BSR & BCR registers */
296 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
297 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
298 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
299
300 if ((bsr & SYNQUACER_I2C_BSR_AL) ||
301 !(bcr & SYNQUACER_I2C_BCR_MSS)) {
302 dev_dbg(i2c->dev, "arbitration lost\n");
303 return -EAGAIN;
304 }
305
306 return 0;
307 }
308
synquacer_i2c_doxfer(struct synquacer_i2c * i2c,struct i2c_msg * msgs,int num)309 static int synquacer_i2c_doxfer(struct synquacer_i2c *i2c,
310 struct i2c_msg *msgs, int num)
311 {
312 unsigned char bsr;
313 unsigned long timeout;
314 int ret;
315
316 synquacer_i2c_hw_init(i2c);
317 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
318 if (bsr & SYNQUACER_I2C_BSR_BB) {
319 dev_err(i2c->dev, "cannot get bus (bus busy)\n");
320 return -EBUSY;
321 }
322
323 reinit_completion(&i2c->completion);
324
325 i2c->msg = msgs;
326 i2c->msg_num = num;
327 i2c->msg_ptr = 0;
328 i2c->msg_idx = 0;
329 i2c->state = STATE_START;
330
331 ret = synquacer_i2c_master_start(i2c, i2c->msg);
332 if (ret < 0) {
333 dev_dbg(i2c->dev, "Address failed: (%d)\n", ret);
334 return ret;
335 }
336
337 timeout = wait_for_completion_timeout(&i2c->completion,
338 msecs_to_jiffies(i2c->timeout_ms));
339 if (timeout == 0) {
340 dev_dbg(i2c->dev, "timeout\n");
341 return -EAGAIN;
342 }
343
344 ret = i2c->msg_idx;
345 if (ret != num) {
346 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
347 return -EAGAIN;
348 }
349
350 /* wait 2 clock periods to ensure the stop has been through the bus */
351 udelay(DIV_ROUND_UP(2 * 1000, i2c->speed_khz));
352
353 return ret;
354 }
355
synquacer_i2c_isr(int irq,void * dev_id)356 static irqreturn_t synquacer_i2c_isr(int irq, void *dev_id)
357 {
358 struct synquacer_i2c *i2c = dev_id;
359
360 unsigned char byte;
361 unsigned char bsr, bcr;
362 int ret;
363
364 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
365 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
366 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
367
368 if (bcr & SYNQUACER_I2C_BCR_BER) {
369 dev_err(i2c->dev, "bus error\n");
370 synquacer_i2c_stop(i2c, -EAGAIN);
371 goto out;
372 }
373 if ((bsr & SYNQUACER_I2C_BSR_AL) ||
374 !(bcr & SYNQUACER_I2C_BCR_MSS)) {
375 dev_dbg(i2c->dev, "arbitration lost\n");
376 synquacer_i2c_stop(i2c, -EAGAIN);
377 goto out;
378 }
379
380 switch (i2c->state) {
381 case STATE_START:
382 if (bsr & SYNQUACER_I2C_BSR_LRB) {
383 dev_dbg(i2c->dev, "ack was not received\n");
384 synquacer_i2c_stop(i2c, -EAGAIN);
385 goto out;
386 }
387
388 if (i2c->msg->flags & I2C_M_RD)
389 i2c->state = STATE_READ;
390 else
391 i2c->state = STATE_WRITE;
392
393 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
394 synquacer_i2c_stop(i2c, 0);
395 goto out;
396 }
397
398 if (i2c->state == STATE_READ)
399 goto prepare_read;
400 fallthrough;
401
402 case STATE_WRITE:
403 if (bsr & SYNQUACER_I2C_BSR_LRB) {
404 dev_dbg(i2c->dev, "WRITE: No Ack\n");
405 synquacer_i2c_stop(i2c, -EAGAIN);
406 goto out;
407 }
408
409 if (!is_msgend(i2c)) {
410 writeb(i2c->msg->buf[i2c->msg_ptr++],
411 i2c->base + SYNQUACER_I2C_REG_DAR);
412
413 /* clear IRQ, and continue */
414 writeb(SYNQUACER_I2C_BCR_BEIE |
415 SYNQUACER_I2C_BCR_MSS |
416 SYNQUACER_I2C_BCR_INTE,
417 i2c->base + SYNQUACER_I2C_REG_BCR);
418 break;
419 }
420 if (is_lastmsg(i2c)) {
421 synquacer_i2c_stop(i2c, 0);
422 break;
423 }
424 dev_dbg(i2c->dev, "WRITE: Next Message\n");
425
426 i2c->msg_ptr = 0;
427 i2c->msg_idx++;
428 i2c->msg++;
429
430 /* send the new start */
431 ret = synquacer_i2c_master_start(i2c, i2c->msg);
432 if (ret < 0) {
433 dev_dbg(i2c->dev, "restart error (%d)\n", ret);
434 synquacer_i2c_stop(i2c, -EAGAIN);
435 break;
436 }
437 i2c->state = STATE_START;
438 break;
439
440 case STATE_READ:
441 byte = readb(i2c->base + SYNQUACER_I2C_REG_DAR);
442 if (!(bsr & SYNQUACER_I2C_BSR_FBT)) /* data */
443 i2c->msg->buf[i2c->msg_ptr++] = byte;
444 else /* address */
445 dev_dbg(i2c->dev, "address:0x%02x. ignore it.\n", byte);
446
447 prepare_read:
448 if (is_msglast(i2c)) {
449 writeb(SYNQUACER_I2C_BCR_MSS |
450 SYNQUACER_I2C_BCR_BEIE |
451 SYNQUACER_I2C_BCR_INTE,
452 i2c->base + SYNQUACER_I2C_REG_BCR);
453 break;
454 }
455 if (!is_msgend(i2c)) {
456 writeb(SYNQUACER_I2C_BCR_MSS |
457 SYNQUACER_I2C_BCR_BEIE |
458 SYNQUACER_I2C_BCR_INTE |
459 SYNQUACER_I2C_BCR_ACK,
460 i2c->base + SYNQUACER_I2C_REG_BCR);
461 break;
462 }
463 if (is_lastmsg(i2c)) {
464 /* last message, send stop and complete */
465 dev_dbg(i2c->dev, "READ: Send Stop\n");
466 synquacer_i2c_stop(i2c, 0);
467 break;
468 }
469 dev_dbg(i2c->dev, "READ: Next Transfer\n");
470
471 i2c->msg_ptr = 0;
472 i2c->msg_idx++;
473 i2c->msg++;
474
475 ret = synquacer_i2c_master_start(i2c, i2c->msg);
476 if (ret < 0) {
477 dev_dbg(i2c->dev, "restart error (%d)\n", ret);
478 synquacer_i2c_stop(i2c, -EAGAIN);
479 } else {
480 i2c->state = STATE_START;
481 }
482 break;
483 default:
484 dev_err(i2c->dev, "called in err STATE (%d)\n", i2c->state);
485 break;
486 }
487
488 out:
489 WAIT_PCLK(10, i2c->pclkrate);
490 return IRQ_HANDLED;
491 }
492
synquacer_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)493 static int synquacer_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
494 int num)
495 {
496 struct synquacer_i2c *i2c;
497 int retry;
498 int ret;
499
500 i2c = i2c_get_adapdata(adap);
501 i2c->timeout_ms = calc_timeout_ms(i2c, msgs, num);
502
503 dev_dbg(i2c->dev, "calculated timeout %d ms\n", i2c->timeout_ms);
504
505 for (retry = 0; retry <= adap->retries; retry++) {
506 ret = synquacer_i2c_doxfer(i2c, msgs, num);
507 if (ret != -EAGAIN)
508 return ret;
509
510 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
511
512 synquacer_i2c_hw_reset(i2c);
513 }
514 return -EIO;
515 }
516
synquacer_i2c_functionality(struct i2c_adapter * adap)517 static u32 synquacer_i2c_functionality(struct i2c_adapter *adap)
518 {
519 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
520 }
521
522 static const struct i2c_algorithm synquacer_i2c_algo = {
523 .master_xfer = synquacer_i2c_xfer,
524 .functionality = synquacer_i2c_functionality,
525 };
526
527 static const struct i2c_adapter synquacer_i2c_ops = {
528 .owner = THIS_MODULE,
529 .name = "synquacer_i2c-adapter",
530 .algo = &synquacer_i2c_algo,
531 .retries = 5,
532 };
533
synquacer_i2c_probe(struct platform_device * pdev)534 static int synquacer_i2c_probe(struct platform_device *pdev)
535 {
536 struct synquacer_i2c *i2c;
537 struct clk *pclk;
538 u32 bus_speed;
539 int ret;
540
541 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
542 if (!i2c)
543 return -ENOMEM;
544
545 bus_speed = i2c_acpi_find_bus_speed(&pdev->dev);
546 if (!bus_speed)
547 device_property_read_u32(&pdev->dev, "clock-frequency",
548 &bus_speed);
549
550 device_property_read_u32(&pdev->dev, "socionext,pclk-rate",
551 &i2c->pclkrate);
552
553 pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
554 if (IS_ERR(pclk))
555 return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
556 "failed to get and enable clock\n");
557
558 if (pclk)
559 i2c->pclkrate = clk_get_rate(pclk);
560
561 if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE ||
562 i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE)
563 return dev_err_probe(&pdev->dev, -EINVAL,
564 "PCLK missing or out of range (%d)\n",
565 i2c->pclkrate);
566
567 i2c->base = devm_platform_ioremap_resource(pdev, 0);
568 if (IS_ERR(i2c->base))
569 return PTR_ERR(i2c->base);
570
571 i2c->irq = platform_get_irq(pdev, 0);
572 if (i2c->irq < 0)
573 return i2c->irq;
574
575 ret = devm_request_irq(&pdev->dev, i2c->irq, synquacer_i2c_isr,
576 0, dev_name(&pdev->dev), i2c);
577 if (ret < 0)
578 return dev_err_probe(&pdev->dev, ret, "cannot claim IRQ %d\n", i2c->irq);
579
580 i2c->state = STATE_IDLE;
581 i2c->dev = &pdev->dev;
582 i2c->adapter = synquacer_i2c_ops;
583 i2c_set_adapdata(&i2c->adapter, i2c);
584 i2c->adapter.dev.parent = &pdev->dev;
585 i2c->adapter.dev.of_node = pdev->dev.of_node;
586 ACPI_COMPANION_SET(&i2c->adapter.dev, ACPI_COMPANION(&pdev->dev));
587 i2c->adapter.nr = pdev->id;
588 init_completion(&i2c->completion);
589
590 if (bus_speed < I2C_MAX_FAST_MODE_FREQ)
591 i2c->speed_khz = SYNQUACER_I2C_SPEED_SM;
592 else
593 i2c->speed_khz = SYNQUACER_I2C_SPEED_FM;
594
595 synquacer_i2c_hw_init(i2c);
596
597 ret = i2c_add_numbered_adapter(&i2c->adapter);
598 if (ret)
599 return dev_err_probe(&pdev->dev, ret, "failed to add bus to i2c core\n");
600
601 platform_set_drvdata(pdev, i2c);
602
603 dev_info(&pdev->dev, "%s: synquacer_i2c adapter\n",
604 dev_name(&i2c->adapter.dev));
605
606 return 0;
607 }
608
synquacer_i2c_remove(struct platform_device * pdev)609 static void synquacer_i2c_remove(struct platform_device *pdev)
610 {
611 struct synquacer_i2c *i2c = platform_get_drvdata(pdev);
612
613 i2c_del_adapter(&i2c->adapter);
614 };
615
616 static const struct of_device_id synquacer_i2c_dt_ids[] __maybe_unused = {
617 { .compatible = "socionext,synquacer-i2c" },
618 { /* sentinel */ }
619 };
620 MODULE_DEVICE_TABLE(of, synquacer_i2c_dt_ids);
621
622 #ifdef CONFIG_ACPI
623 static const struct acpi_device_id synquacer_i2c_acpi_ids[] = {
624 { "SCX0003" },
625 { /* sentinel */ }
626 };
627 MODULE_DEVICE_TABLE(acpi, synquacer_i2c_acpi_ids);
628 #endif
629
630 static struct platform_driver synquacer_i2c_driver = {
631 .probe = synquacer_i2c_probe,
632 .remove_new = synquacer_i2c_remove,
633 .driver = {
634 .name = "synquacer_i2c",
635 .of_match_table = of_match_ptr(synquacer_i2c_dt_ids),
636 .acpi_match_table = ACPI_PTR(synquacer_i2c_acpi_ids),
637 },
638 };
639 module_platform_driver(synquacer_i2c_driver);
640
641 MODULE_AUTHOR("Fujitsu Semiconductor Ltd");
642 MODULE_DESCRIPTION("Socionext SynQuacer I2C Driver");
643 MODULE_LICENSE("GPL v2");
644