1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/i2c-smbus.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/pm_wakeirq.h> 34 #include <linux/regmap.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 38 #include "i2c-stm32.h" 39 40 /* STM32F7 I2C registers */ 41 #define STM32F7_I2C_CR1 0x00 42 #define STM32F7_I2C_CR2 0x04 43 #define STM32F7_I2C_OAR1 0x08 44 #define STM32F7_I2C_OAR2 0x0C 45 #define STM32F7_I2C_PECR 0x20 46 #define STM32F7_I2C_TIMINGR 0x10 47 #define STM32F7_I2C_ISR 0x18 48 #define STM32F7_I2C_ICR 0x1C 49 #define STM32F7_I2C_RXDR 0x24 50 #define STM32F7_I2C_TXDR 0x28 51 52 /* STM32F7 I2C control 1 */ 53 #define STM32F7_I2C_CR1_PECEN BIT(23) 54 #define STM32F7_I2C_CR1_ALERTEN BIT(22) 55 #define STM32F7_I2C_CR1_SMBHEN BIT(20) 56 #define STM32F7_I2C_CR1_WUPEN BIT(18) 57 #define STM32F7_I2C_CR1_SBC BIT(16) 58 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 59 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 60 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 61 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8) 62 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8) 63 #define STM32F7_I2C_CR1_ERRIE BIT(7) 64 #define STM32F7_I2C_CR1_TCIE BIT(6) 65 #define STM32F7_I2C_CR1_STOPIE BIT(5) 66 #define STM32F7_I2C_CR1_NACKIE BIT(4) 67 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 68 #define STM32F7_I2C_CR1_RXIE BIT(2) 69 #define STM32F7_I2C_CR1_TXIE BIT(1) 70 #define STM32F7_I2C_CR1_PE BIT(0) 71 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 72 | STM32F7_I2C_CR1_TCIE \ 73 | STM32F7_I2C_CR1_STOPIE \ 74 | STM32F7_I2C_CR1_NACKIE \ 75 | STM32F7_I2C_CR1_RXIE \ 76 | STM32F7_I2C_CR1_TXIE) 77 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 78 | STM32F7_I2C_CR1_STOPIE \ 79 | STM32F7_I2C_CR1_NACKIE \ 80 | STM32F7_I2C_CR1_RXIE \ 81 | STM32F7_I2C_CR1_TXIE) 82 83 /* STM32F7 I2C control 2 */ 84 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 85 #define STM32F7_I2C_CR2_RELOAD BIT(24) 86 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 87 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 88 #define STM32F7_I2C_CR2_NACK BIT(15) 89 #define STM32F7_I2C_CR2_STOP BIT(14) 90 #define STM32F7_I2C_CR2_START BIT(13) 91 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 92 #define STM32F7_I2C_CR2_ADD10 BIT(11) 93 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 94 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 95 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 96 STM32F7_I2C_CR2_SADD10_MASK)) 97 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 98 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 99 100 /* STM32F7 I2C Own Address 1 */ 101 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 102 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 103 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 104 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 105 STM32F7_I2C_OAR1_OA1_10_MASK)) 106 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 107 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 108 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 109 | STM32F7_I2C_OAR1_OA1_10_MASK \ 110 | STM32F7_I2C_OAR1_OA1EN \ 111 | STM32F7_I2C_OAR1_OA1MODE) 112 113 /* STM32F7 I2C Own Address 2 */ 114 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 115 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 116 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 117 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 118 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 119 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 120 | STM32F7_I2C_OAR2_OA2_7_MASK \ 121 | STM32F7_I2C_OAR2_OA2EN) 122 123 /* STM32F7 I2C Interrupt Status */ 124 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 127 #define STM32F7_I2C_ISR_DIR BIT(16) 128 #define STM32F7_I2C_ISR_BUSY BIT(15) 129 #define STM32F7_I2C_ISR_ALERT BIT(13) 130 #define STM32F7_I2C_ISR_PECERR BIT(11) 131 #define STM32F7_I2C_ISR_ARLO BIT(9) 132 #define STM32F7_I2C_ISR_BERR BIT(8) 133 #define STM32F7_I2C_ISR_TCR BIT(7) 134 #define STM32F7_I2C_ISR_TC BIT(6) 135 #define STM32F7_I2C_ISR_STOPF BIT(5) 136 #define STM32F7_I2C_ISR_NACKF BIT(4) 137 #define STM32F7_I2C_ISR_ADDR BIT(3) 138 #define STM32F7_I2C_ISR_RXNE BIT(2) 139 #define STM32F7_I2C_ISR_TXIS BIT(1) 140 #define STM32F7_I2C_ISR_TXE BIT(0) 141 142 /* STM32F7 I2C Interrupt Clear */ 143 #define STM32F7_I2C_ICR_ALERTCF BIT(13) 144 #define STM32F7_I2C_ICR_PECCF BIT(11) 145 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 146 #define STM32F7_I2C_ICR_BERRCF BIT(8) 147 #define STM32F7_I2C_ICR_STOPCF BIT(5) 148 #define STM32F7_I2C_ICR_NACKCF BIT(4) 149 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 150 151 /* STM32F7 I2C Timing */ 152 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 153 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 154 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 155 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 156 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 157 158 #define STM32F7_I2C_MAX_LEN 0xff 159 #define STM32F7_I2C_DMA_LEN_MIN 0x16 160 enum { 161 STM32F7_SLAVE_HOSTNOTIFY, 162 STM32F7_SLAVE_7_10_BITS_ADDR, 163 STM32F7_SLAVE_7_BITS_ADDR, 164 STM32F7_I2C_MAX_SLAVE 165 }; 166 167 #define STM32F7_I2C_DNF_DEFAULT 0 168 #define STM32F7_I2C_DNF_MAX 15 169 170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 172 173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 175 176 #define STM32F7_PRESC_MAX BIT(4) 177 #define STM32F7_SCLDEL_MAX BIT(4) 178 #define STM32F7_SDADEL_MAX BIT(4) 179 #define STM32F7_SCLH_MAX BIT(8) 180 #define STM32F7_SCLL_MAX BIT(8) 181 182 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 183 184 /** 185 * struct stm32f7_i2c_regs - i2c f7 registers backup 186 * @cr1: Control register 1 187 * @cr2: Control register 2 188 * @oar1: Own address 1 register 189 * @oar2: Own address 2 register 190 * @tmgr: Timing register 191 */ 192 struct stm32f7_i2c_regs { 193 u32 cr1; 194 u32 cr2; 195 u32 oar1; 196 u32 oar2; 197 u32 tmgr; 198 }; 199 200 /** 201 * struct stm32f7_i2c_spec - private i2c specification timing 202 * @rate: I2C bus speed (Hz) 203 * @fall_max: Max fall time of both SDA and SCL signals (ns) 204 * @rise_max: Max rise time of both SDA and SCL signals (ns) 205 * @hddat_min: Min data hold time (ns) 206 * @vddat_max: Max data valid time (ns) 207 * @sudat_min: Min data setup time (ns) 208 * @l_min: Min low period of the SCL clock (ns) 209 * @h_min: Min high period of the SCL clock (ns) 210 */ 211 struct stm32f7_i2c_spec { 212 u32 rate; 213 u32 fall_max; 214 u32 rise_max; 215 u32 hddat_min; 216 u32 vddat_max; 217 u32 sudat_min; 218 u32 l_min; 219 u32 h_min; 220 }; 221 222 /** 223 * struct stm32f7_i2c_setup - private I2C timing setup parameters 224 * @speed_freq: I2C speed frequency (Hz) 225 * @clock_src: I2C clock source frequency (Hz) 226 * @rise_time: Rise time (ns) 227 * @fall_time: Fall time (ns) 228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 229 */ 230 struct stm32f7_i2c_setup { 231 u32 speed_freq; 232 u32 clock_src; 233 u32 rise_time; 234 u32 fall_time; 235 u32 fmp_clr_offset; 236 }; 237 238 /** 239 * struct stm32f7_i2c_timings - private I2C output parameters 240 * @node: List entry 241 * @presc: Prescaler value 242 * @scldel: Data setup time 243 * @sdadel: Data hold time 244 * @sclh: SCL high period (master mode) 245 * @scll: SCL low period (master mode) 246 */ 247 struct stm32f7_i2c_timings { 248 struct list_head node; 249 u8 presc; 250 u8 scldel; 251 u8 sdadel; 252 u8 sclh; 253 u8 scll; 254 }; 255 256 /** 257 * struct stm32f7_i2c_msg - client specific data 258 * @addr: 8-bit or 10-bit slave addr, including r/w bit 259 * @count: number of bytes to be transferred 260 * @buf: data buffer 261 * @result: result of the transfer 262 * @stop: last I2C msg to be sent, i.e. STOP to be generated 263 * @smbus: boolean to know if the I2C IP is used in SMBus mode 264 * @size: type of SMBus protocol 265 * @read_write: direction of SMBus protocol 266 * SMBus block read and SMBus block write - block read process call protocols 267 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 268 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 269 * This buffer has to be 32-bit aligned to be compliant with memory address 270 * register in DMA mode. 271 */ 272 struct stm32f7_i2c_msg { 273 u16 addr; 274 u32 count; 275 u8 *buf; 276 int result; 277 bool stop; 278 bool smbus; 279 int size; 280 char read_write; 281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 282 }; 283 284 /** 285 * struct stm32f7_i2c_alert - SMBus alert specific data 286 * @setup: platform data for the smbus_alert i2c client 287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert 288 * Response Address 289 */ 290 struct stm32f7_i2c_alert { 291 struct i2c_smbus_alert_setup setup; 292 struct i2c_client *ara; 293 }; 294 295 /** 296 * struct stm32f7_i2c_dev - private data of the controller 297 * @adap: I2C adapter for this controller 298 * @dev: device for this controller 299 * @base: virtual memory area 300 * @complete: completion of I2C message 301 * @clk: hw i2c clock 302 * @bus_rate: I2C clock frequency of the controller 303 * @msg: Pointer to data to be written 304 * @msg_num: number of I2C messages to be executed 305 * @msg_id: message identifiant 306 * @f7_msg: customized i2c msg for driver usage 307 * @setup: I2C timing input setup 308 * @timing: I2C computed timings 309 * @slave: list of slave devices registered on the I2C bus 310 * @slave_running: slave device currently used 311 * @backup_regs: backup of i2c controller registers (for suspend/resume) 312 * @slave_dir: transfer direction for the current slave device 313 * @master_mode: boolean to know in which mode the I2C is running (master or 314 * slave) 315 * @dma: dma data 316 * @use_dma: boolean to know if dma is used in the current transfer 317 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 318 * @fmp_sreg: register address for setting Fast Mode Plus bits 319 * @fmp_creg: register address for clearing Fast Mode Plus bits 320 * @fmp_mask: mask for Fast Mode Plus bits in set register 321 * @wakeup_src: boolean to know if the device is a wakeup source 322 * @smbus_mode: states that the controller is configured in SMBus mode 323 * @host_notify_client: SMBus host-notify client 324 * @analog_filter: boolean to indicate enabling of the analog filter 325 * @dnf_dt: value of digital filter requested via dt 326 * @dnf: value of digital filter to apply 327 * @alert: SMBus alert specific data 328 */ 329 struct stm32f7_i2c_dev { 330 struct i2c_adapter adap; 331 struct device *dev; 332 void __iomem *base; 333 struct completion complete; 334 struct clk *clk; 335 unsigned int bus_rate; 336 struct i2c_msg *msg; 337 unsigned int msg_num; 338 unsigned int msg_id; 339 struct stm32f7_i2c_msg f7_msg; 340 struct stm32f7_i2c_setup setup; 341 struct stm32f7_i2c_timings timing; 342 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 343 struct i2c_client *slave_running; 344 struct stm32f7_i2c_regs backup_regs; 345 u32 slave_dir; 346 bool master_mode; 347 struct stm32_i2c_dma *dma; 348 bool use_dma; 349 struct regmap *regmap; 350 u32 fmp_sreg; 351 u32 fmp_creg; 352 u32 fmp_mask; 353 bool wakeup_src; 354 bool smbus_mode; 355 struct i2c_client *host_notify_client; 356 bool analog_filter; 357 u32 dnf_dt; 358 u32 dnf; 359 struct stm32f7_i2c_alert *alert; 360 }; 361 362 /* 363 * All these values are coming from I2C Specification, Version 6.0, 4th of 364 * April 2014. 365 * 366 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 367 * and Fast-mode Plus I2C-bus devices 368 */ 369 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = { 370 { 371 .rate = I2C_MAX_STANDARD_MODE_FREQ, 372 .fall_max = 300, 373 .rise_max = 1000, 374 .hddat_min = 0, 375 .vddat_max = 3450, 376 .sudat_min = 250, 377 .l_min = 4700, 378 .h_min = 4000, 379 }, 380 { 381 .rate = I2C_MAX_FAST_MODE_FREQ, 382 .fall_max = 300, 383 .rise_max = 300, 384 .hddat_min = 0, 385 .vddat_max = 900, 386 .sudat_min = 100, 387 .l_min = 1300, 388 .h_min = 600, 389 }, 390 { 391 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ, 392 .fall_max = 100, 393 .rise_max = 120, 394 .hddat_min = 0, 395 .vddat_max = 450, 396 .sudat_min = 50, 397 .l_min = 500, 398 .h_min = 260, 399 }, 400 }; 401 402 static const struct stm32f7_i2c_setup stm32f7_setup = { 403 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 404 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 405 }; 406 407 static const struct stm32f7_i2c_setup stm32mp15_setup = { 408 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 409 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 410 .fmp_clr_offset = 0x40, 411 }; 412 413 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 414 { 415 writel_relaxed(readl_relaxed(reg) | mask, reg); 416 } 417 418 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 419 { 420 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 421 } 422 423 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 424 { 425 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 426 } 427 428 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate) 429 { 430 int i; 431 432 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++) 433 if (rate <= stm32f7_i2c_specs[i].rate) 434 return &stm32f7_i2c_specs[i]; 435 436 return ERR_PTR(-EINVAL); 437 } 438 439 #define RATE_MIN(rate) ((rate) * 8 / 10) 440 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 441 struct stm32f7_i2c_setup *setup, 442 struct stm32f7_i2c_timings *output) 443 { 444 struct stm32f7_i2c_spec *specs; 445 u32 p_prev = STM32F7_PRESC_MAX; 446 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 447 setup->clock_src); 448 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 449 setup->speed_freq); 450 u32 clk_error_prev = i2cbus; 451 u32 tsync; 452 u32 af_delay_min, af_delay_max; 453 u32 dnf_delay; 454 u32 clk_min, clk_max; 455 int sdadel_min, sdadel_max; 456 int scldel_min; 457 struct stm32f7_i2c_timings *v, *_v, *s; 458 struct list_head solutions; 459 u16 p, l, a, h; 460 int ret = 0; 461 462 specs = stm32f7_get_specs(setup->speed_freq); 463 if (specs == ERR_PTR(-EINVAL)) { 464 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", 465 setup->speed_freq); 466 return -EINVAL; 467 } 468 469 if ((setup->rise_time > specs->rise_max) || 470 (setup->fall_time > specs->fall_max)) { 471 dev_err(i2c_dev->dev, 472 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 473 setup->rise_time, specs->rise_max, 474 setup->fall_time, specs->fall_max); 475 return -EINVAL; 476 } 477 478 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); 479 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { 480 dev_err(i2c_dev->dev, 481 "DNF out of bound %d/%d\n", 482 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); 483 return -EINVAL; 484 } 485 486 /* Analog and Digital Filters */ 487 af_delay_min = 488 (i2c_dev->analog_filter ? 489 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 490 af_delay_max = 491 (i2c_dev->analog_filter ? 492 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 493 dnf_delay = i2c_dev->dnf * i2cclk; 494 495 sdadel_min = specs->hddat_min + setup->fall_time - 496 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; 497 498 sdadel_max = specs->vddat_max - setup->rise_time - 499 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; 500 501 scldel_min = setup->rise_time + specs->sudat_min; 502 503 if (sdadel_min < 0) 504 sdadel_min = 0; 505 if (sdadel_max < 0) 506 sdadel_max = 0; 507 508 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 509 sdadel_min, sdadel_max, scldel_min); 510 511 INIT_LIST_HEAD(&solutions); 512 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 513 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 514 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 515 u32 scldel = (l + 1) * (p + 1) * i2cclk; 516 517 if (scldel < scldel_min) 518 continue; 519 520 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 521 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 522 523 if (((sdadel >= sdadel_min) && 524 (sdadel <= sdadel_max)) && 525 (p != p_prev)) { 526 v = kmalloc(sizeof(*v), GFP_KERNEL); 527 if (!v) { 528 ret = -ENOMEM; 529 goto exit; 530 } 531 532 v->presc = p; 533 v->scldel = l; 534 v->sdadel = a; 535 p_prev = p; 536 537 list_add_tail(&v->node, 538 &solutions); 539 break; 540 } 541 } 542 543 if (p_prev == p) 544 break; 545 } 546 } 547 548 if (list_empty(&solutions)) { 549 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 550 ret = -EPERM; 551 goto exit; 552 } 553 554 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 555 s = NULL; 556 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); 557 clk_min = NSEC_PER_SEC / setup->speed_freq; 558 559 /* 560 * Among Prescaler possibilities discovered above figures out SCL Low 561 * and High Period. Provided: 562 * - SCL Low Period has to be higher than SCL Clock Low Period 563 * defined by I2C Specification. I2C Clock has to be lower than 564 * (SCL Low Period - Analog/Digital filters) / 4. 565 * - SCL High Period has to be lower than SCL Clock High Period 566 * defined by I2C Specification 567 * - I2C Clock has to be lower than SCL High Period 568 */ 569 list_for_each_entry(v, &solutions, node) { 570 u32 prescaler = (v->presc + 1) * i2cclk; 571 572 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 573 u32 tscl_l = (l + 1) * prescaler + tsync; 574 575 if ((tscl_l < specs->l_min) || 576 (i2cclk >= 577 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 578 continue; 579 } 580 581 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 582 u32 tscl_h = (h + 1) * prescaler + tsync; 583 u32 tscl = tscl_l + tscl_h + 584 setup->rise_time + setup->fall_time; 585 586 if ((tscl >= clk_min) && (tscl <= clk_max) && 587 (tscl_h >= specs->h_min) && 588 (i2cclk < tscl_h)) { 589 int clk_error = tscl - i2cbus; 590 591 if (clk_error < 0) 592 clk_error = -clk_error; 593 594 if (clk_error < clk_error_prev) { 595 clk_error_prev = clk_error; 596 v->scll = l; 597 v->sclh = h; 598 s = v; 599 } 600 } 601 } 602 } 603 } 604 605 if (!s) { 606 dev_err(i2c_dev->dev, "no solution at all\n"); 607 ret = -EPERM; 608 goto exit; 609 } 610 611 output->presc = s->presc; 612 output->scldel = s->scldel; 613 output->sdadel = s->sdadel; 614 output->scll = s->scll; 615 output->sclh = s->sclh; 616 617 dev_dbg(i2c_dev->dev, 618 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 619 output->presc, 620 output->scldel, output->sdadel, 621 output->scll, output->sclh); 622 623 exit: 624 /* Release list and memory */ 625 list_for_each_entry_safe(v, _v, &solutions, node) { 626 list_del(&v->node); 627 kfree(v); 628 } 629 630 return ret; 631 } 632 633 static u32 stm32f7_get_lower_rate(u32 rate) 634 { 635 int i = ARRAY_SIZE(stm32f7_i2c_specs); 636 637 while (--i) 638 if (stm32f7_i2c_specs[i].rate < rate) 639 break; 640 641 return stm32f7_i2c_specs[i].rate; 642 } 643 644 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 645 struct stm32f7_i2c_setup *setup) 646 { 647 struct i2c_timings timings, *t = &timings; 648 int ret = 0; 649 650 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 651 t->scl_rise_ns = i2c_dev->setup.rise_time; 652 t->scl_fall_ns = i2c_dev->setup.fall_time; 653 654 i2c_parse_fw_timings(i2c_dev->dev, t, false); 655 656 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { 657 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", 658 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); 659 return -EINVAL; 660 } 661 662 setup->speed_freq = t->bus_freq_hz; 663 i2c_dev->setup.rise_time = t->scl_rise_ns; 664 i2c_dev->setup.fall_time = t->scl_fall_ns; 665 i2c_dev->dnf_dt = t->digital_filter_width_ns; 666 setup->clock_src = clk_get_rate(i2c_dev->clk); 667 668 if (!setup->clock_src) { 669 dev_err(i2c_dev->dev, "clock rate is 0\n"); 670 return -EINVAL; 671 } 672 673 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) 674 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; 675 676 do { 677 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 678 &i2c_dev->timing); 679 if (ret) { 680 dev_err(i2c_dev->dev, 681 "failed to compute I2C timings.\n"); 682 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) 683 break; 684 setup->speed_freq = 685 stm32f7_get_lower_rate(setup->speed_freq); 686 dev_warn(i2c_dev->dev, 687 "downgrade I2C Speed Freq to (%i)\n", 688 setup->speed_freq); 689 } 690 } while (ret); 691 692 if (ret) { 693 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 694 return ret; 695 } 696 697 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, 698 "i2c-analog-filter"); 699 700 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 701 setup->speed_freq, setup->clock_src); 702 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 703 setup->rise_time, setup->fall_time); 704 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 705 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); 706 707 i2c_dev->bus_rate = setup->speed_freq; 708 709 return 0; 710 } 711 712 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 713 { 714 void __iomem *base = i2c_dev->base; 715 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 716 717 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 718 } 719 720 static void stm32f7_i2c_dma_callback(void *arg) 721 { 722 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 723 struct stm32_i2c_dma *dma = i2c_dev->dma; 724 struct device *dev = dma->chan_using->device->dev; 725 726 stm32f7_i2c_disable_dma_req(i2c_dev); 727 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 728 complete(&dma->dma_complete); 729 } 730 731 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 732 { 733 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 734 u32 timing = 0; 735 736 /* Timing settings */ 737 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 738 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 739 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 740 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 741 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 742 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 743 744 /* Configure the Analog Filter */ 745 if (i2c_dev->analog_filter) 746 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 747 STM32F7_I2C_CR1_ANFOFF); 748 else 749 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 750 STM32F7_I2C_CR1_ANFOFF); 751 752 /* Program the Digital Filter */ 753 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 754 STM32F7_I2C_CR1_DNF_MASK); 755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 756 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); 757 758 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 759 STM32F7_I2C_CR1_PE); 760 } 761 762 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 763 { 764 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 765 void __iomem *base = i2c_dev->base; 766 767 if (f7_msg->count) { 768 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 769 f7_msg->count--; 770 } 771 } 772 773 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 774 { 775 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 776 void __iomem *base = i2c_dev->base; 777 778 if (f7_msg->count) { 779 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 780 f7_msg->count--; 781 } else { 782 /* Flush RX buffer has no data is expected */ 783 readb_relaxed(base + STM32F7_I2C_RXDR); 784 } 785 } 786 787 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 788 { 789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 790 u32 cr2; 791 792 if (i2c_dev->use_dma) 793 f7_msg->count -= STM32F7_I2C_MAX_LEN; 794 795 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 796 797 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 798 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 799 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 800 } else { 801 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 802 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 803 } 804 805 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 806 } 807 808 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 809 { 810 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 811 u32 cr2; 812 u8 *val; 813 814 /* 815 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 816 * data received inform us how many data will follow. 817 */ 818 stm32f7_i2c_read_rx_data(i2c_dev); 819 820 /* 821 * Update NBYTES with the value read to continue the transfer 822 */ 823 val = f7_msg->buf - sizeof(u8); 824 f7_msg->count = *val; 825 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 826 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 827 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 828 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 829 } 830 831 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 832 { 833 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 834 835 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 836 STM32F7_I2C_CR1_PE); 837 838 stm32f7_i2c_hw_config(i2c_dev); 839 } 840 841 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 842 { 843 u32 status; 844 int ret; 845 846 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 847 status, 848 !(status & STM32F7_I2C_ISR_BUSY), 849 10, 1000); 850 if (!ret) 851 return 0; 852 853 stm32f7_i2c_release_bus(&i2c_dev->adap); 854 855 return -EBUSY; 856 } 857 858 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 859 struct i2c_msg *msg) 860 { 861 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 862 void __iomem *base = i2c_dev->base; 863 u32 cr1, cr2; 864 int ret; 865 866 f7_msg->addr = msg->addr; 867 f7_msg->buf = msg->buf; 868 f7_msg->count = msg->len; 869 f7_msg->result = 0; 870 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 871 872 reinit_completion(&i2c_dev->complete); 873 874 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 875 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 876 877 /* Set transfer direction */ 878 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 879 if (msg->flags & I2C_M_RD) 880 cr2 |= STM32F7_I2C_CR2_RD_WRN; 881 882 /* Set slave address */ 883 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 884 if (msg->flags & I2C_M_TEN) { 885 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 886 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 887 cr2 |= STM32F7_I2C_CR2_ADD10; 888 } else { 889 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 890 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 891 } 892 893 /* Set nb bytes to transfer and reload if needed */ 894 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 895 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 896 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 897 cr2 |= STM32F7_I2C_CR2_RELOAD; 898 } else { 899 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 900 } 901 902 /* Enable NACK, STOP, error and transfer complete interrupts */ 903 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 904 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 905 906 /* Clear DMA req and TX/RX interrupt */ 907 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 908 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 909 910 /* Configure DMA or enable RX/TX interrupt */ 911 i2c_dev->use_dma = false; 912 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 913 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 914 msg->flags & I2C_M_RD, 915 f7_msg->count, f7_msg->buf, 916 stm32f7_i2c_dma_callback, 917 i2c_dev); 918 if (!ret) 919 i2c_dev->use_dma = true; 920 else 921 dev_warn(i2c_dev->dev, "can't use DMA\n"); 922 } 923 924 if (!i2c_dev->use_dma) { 925 if (msg->flags & I2C_M_RD) 926 cr1 |= STM32F7_I2C_CR1_RXIE; 927 else 928 cr1 |= STM32F7_I2C_CR1_TXIE; 929 } else { 930 if (msg->flags & I2C_M_RD) 931 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 932 else 933 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 934 } 935 936 /* Configure Start/Repeated Start */ 937 cr2 |= STM32F7_I2C_CR2_START; 938 939 i2c_dev->master_mode = true; 940 941 /* Write configurations registers */ 942 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 943 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 944 } 945 946 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 947 unsigned short flags, u8 command, 948 union i2c_smbus_data *data) 949 { 950 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 951 struct device *dev = i2c_dev->dev; 952 void __iomem *base = i2c_dev->base; 953 u32 cr1, cr2; 954 int i, ret; 955 956 f7_msg->result = 0; 957 reinit_completion(&i2c_dev->complete); 958 959 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 960 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 961 962 /* Set transfer direction */ 963 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 964 if (f7_msg->read_write) 965 cr2 |= STM32F7_I2C_CR2_RD_WRN; 966 967 /* Set slave address */ 968 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 969 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 970 971 f7_msg->smbus_buf[0] = command; 972 switch (f7_msg->size) { 973 case I2C_SMBUS_QUICK: 974 f7_msg->stop = true; 975 f7_msg->count = 0; 976 break; 977 case I2C_SMBUS_BYTE: 978 f7_msg->stop = true; 979 f7_msg->count = 1; 980 break; 981 case I2C_SMBUS_BYTE_DATA: 982 if (f7_msg->read_write) { 983 f7_msg->stop = false; 984 f7_msg->count = 1; 985 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 986 } else { 987 f7_msg->stop = true; 988 f7_msg->count = 2; 989 f7_msg->smbus_buf[1] = data->byte; 990 } 991 break; 992 case I2C_SMBUS_WORD_DATA: 993 if (f7_msg->read_write) { 994 f7_msg->stop = false; 995 f7_msg->count = 1; 996 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 997 } else { 998 f7_msg->stop = true; 999 f7_msg->count = 3; 1000 f7_msg->smbus_buf[1] = data->word & 0xff; 1001 f7_msg->smbus_buf[2] = data->word >> 8; 1002 } 1003 break; 1004 case I2C_SMBUS_BLOCK_DATA: 1005 if (f7_msg->read_write) { 1006 f7_msg->stop = false; 1007 f7_msg->count = 1; 1008 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1009 } else { 1010 f7_msg->stop = true; 1011 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 1012 !data->block[0]) { 1013 dev_err(dev, "Invalid block write size %d\n", 1014 data->block[0]); 1015 return -EINVAL; 1016 } 1017 f7_msg->count = data->block[0] + 2; 1018 for (i = 1; i < f7_msg->count; i++) 1019 f7_msg->smbus_buf[i] = data->block[i - 1]; 1020 } 1021 break; 1022 case I2C_SMBUS_PROC_CALL: 1023 f7_msg->stop = false; 1024 f7_msg->count = 3; 1025 f7_msg->smbus_buf[1] = data->word & 0xff; 1026 f7_msg->smbus_buf[2] = data->word >> 8; 1027 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1028 f7_msg->read_write = I2C_SMBUS_READ; 1029 break; 1030 case I2C_SMBUS_BLOCK_PROC_CALL: 1031 f7_msg->stop = false; 1032 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 1033 dev_err(dev, "Invalid block write size %d\n", 1034 data->block[0]); 1035 return -EINVAL; 1036 } 1037 f7_msg->count = data->block[0] + 2; 1038 for (i = 1; i < f7_msg->count; i++) 1039 f7_msg->smbus_buf[i] = data->block[i - 1]; 1040 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1041 f7_msg->read_write = I2C_SMBUS_READ; 1042 break; 1043 case I2C_SMBUS_I2C_BLOCK_DATA: 1044 /* Rely on emulated i2c transfer (through master_xfer) */ 1045 return -EOPNOTSUPP; 1046 default: 1047 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 1048 return -EOPNOTSUPP; 1049 } 1050 1051 f7_msg->buf = f7_msg->smbus_buf; 1052 1053 /* Configure PEC */ 1054 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 1055 cr1 |= STM32F7_I2C_CR1_PECEN; 1056 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1057 if (!f7_msg->read_write) 1058 f7_msg->count++; 1059 } else { 1060 cr1 &= ~STM32F7_I2C_CR1_PECEN; 1061 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 1062 } 1063 1064 /* Set number of bytes to be transferred */ 1065 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 1066 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1067 1068 /* Enable NACK, STOP, error and transfer complete interrupts */ 1069 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 1070 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 1071 1072 /* Clear DMA req and TX/RX interrupt */ 1073 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1074 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1075 1076 /* Configure DMA or enable RX/TX interrupt */ 1077 i2c_dev->use_dma = false; 1078 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 1079 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1080 cr2 & STM32F7_I2C_CR2_RD_WRN, 1081 f7_msg->count, f7_msg->buf, 1082 stm32f7_i2c_dma_callback, 1083 i2c_dev); 1084 if (!ret) 1085 i2c_dev->use_dma = true; 1086 else 1087 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1088 } 1089 1090 if (!i2c_dev->use_dma) { 1091 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1092 cr1 |= STM32F7_I2C_CR1_RXIE; 1093 else 1094 cr1 |= STM32F7_I2C_CR1_TXIE; 1095 } else { 1096 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1097 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1098 else 1099 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1100 } 1101 1102 /* Set Start bit */ 1103 cr2 |= STM32F7_I2C_CR2_START; 1104 1105 i2c_dev->master_mode = true; 1106 1107 /* Write configurations registers */ 1108 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1109 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1110 1111 return 0; 1112 } 1113 1114 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1115 { 1116 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1117 void __iomem *base = i2c_dev->base; 1118 u32 cr1, cr2; 1119 int ret; 1120 1121 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1122 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1123 1124 /* Set transfer direction */ 1125 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1126 1127 switch (f7_msg->size) { 1128 case I2C_SMBUS_BYTE_DATA: 1129 f7_msg->count = 1; 1130 break; 1131 case I2C_SMBUS_WORD_DATA: 1132 case I2C_SMBUS_PROC_CALL: 1133 f7_msg->count = 2; 1134 break; 1135 case I2C_SMBUS_BLOCK_DATA: 1136 case I2C_SMBUS_BLOCK_PROC_CALL: 1137 f7_msg->count = 1; 1138 cr2 |= STM32F7_I2C_CR2_RELOAD; 1139 break; 1140 } 1141 1142 f7_msg->buf = f7_msg->smbus_buf; 1143 f7_msg->stop = true; 1144 1145 /* Add one byte for PEC if needed */ 1146 if (cr1 & STM32F7_I2C_CR1_PECEN) 1147 f7_msg->count++; 1148 1149 /* Set number of bytes to be transferred */ 1150 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1151 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1152 1153 /* 1154 * Configure RX/TX interrupt: 1155 */ 1156 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1157 cr1 |= STM32F7_I2C_CR1_RXIE; 1158 1159 /* 1160 * Configure DMA or enable RX/TX interrupt: 1161 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1162 * dma as we don't know in advance how many data will be received 1163 */ 1164 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1165 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1166 1167 i2c_dev->use_dma = false; 1168 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1169 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1170 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1171 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1172 cr2 & STM32F7_I2C_CR2_RD_WRN, 1173 f7_msg->count, f7_msg->buf, 1174 stm32f7_i2c_dma_callback, 1175 i2c_dev); 1176 1177 if (!ret) 1178 i2c_dev->use_dma = true; 1179 else 1180 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1181 } 1182 1183 if (!i2c_dev->use_dma) 1184 cr1 |= STM32F7_I2C_CR1_RXIE; 1185 else 1186 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1187 1188 /* Configure Repeated Start */ 1189 cr2 |= STM32F7_I2C_CR2_START; 1190 1191 /* Write configurations registers */ 1192 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1193 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1194 } 1195 1196 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1197 { 1198 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1199 u8 count, internal_pec, received_pec; 1200 1201 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1202 1203 switch (f7_msg->size) { 1204 case I2C_SMBUS_BYTE: 1205 case I2C_SMBUS_BYTE_DATA: 1206 received_pec = f7_msg->smbus_buf[1]; 1207 break; 1208 case I2C_SMBUS_WORD_DATA: 1209 case I2C_SMBUS_PROC_CALL: 1210 received_pec = f7_msg->smbus_buf[2]; 1211 break; 1212 case I2C_SMBUS_BLOCK_DATA: 1213 case I2C_SMBUS_BLOCK_PROC_CALL: 1214 count = f7_msg->smbus_buf[0]; 1215 received_pec = f7_msg->smbus_buf[count]; 1216 break; 1217 default: 1218 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1219 return -EINVAL; 1220 } 1221 1222 if (internal_pec != received_pec) { 1223 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1224 internal_pec, received_pec); 1225 return -EBADMSG; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1232 { 1233 u32 addr; 1234 1235 if (!slave) 1236 return false; 1237 1238 if (slave->flags & I2C_CLIENT_TEN) { 1239 /* 1240 * For 10-bit addr, addcode = 11110XY with 1241 * X = Bit 9 of slave address 1242 * Y = Bit 8 of slave address 1243 */ 1244 addr = slave->addr >> 8; 1245 addr |= 0x78; 1246 if (addr == addcode) 1247 return true; 1248 } else { 1249 addr = slave->addr & 0x7f; 1250 if (addr == addcode) 1251 return true; 1252 } 1253 1254 return false; 1255 } 1256 1257 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1258 { 1259 struct i2c_client *slave = i2c_dev->slave_running; 1260 void __iomem *base = i2c_dev->base; 1261 u32 mask; 1262 u8 value = 0; 1263 1264 if (i2c_dev->slave_dir) { 1265 /* Notify i2c slave that new read transfer is starting */ 1266 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1267 1268 /* 1269 * Disable slave TX config in case of I2C combined message 1270 * (I2C Write followed by I2C Read) 1271 */ 1272 mask = STM32F7_I2C_CR2_RELOAD; 1273 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1274 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1275 STM32F7_I2C_CR1_TCIE; 1276 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1277 1278 /* Enable TX empty, STOP, NACK interrupts */ 1279 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1280 STM32F7_I2C_CR1_TXIE; 1281 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1282 1283 /* Write 1st data byte */ 1284 writel_relaxed(value, base + STM32F7_I2C_TXDR); 1285 } else { 1286 /* Notify i2c slave that new write transfer is starting */ 1287 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1288 1289 /* Set reload mode to be able to ACK/NACK each received byte */ 1290 mask = STM32F7_I2C_CR2_RELOAD; 1291 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1292 1293 /* 1294 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1295 * Set Slave Byte Control to be able to ACK/NACK each data 1296 * byte received 1297 */ 1298 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1299 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1300 STM32F7_I2C_CR1_TCIE; 1301 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1302 } 1303 } 1304 1305 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1306 { 1307 void __iomem *base = i2c_dev->base; 1308 u32 isr, addcode, dir, mask; 1309 int i; 1310 1311 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1312 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1313 dir = isr & STM32F7_I2C_ISR_DIR; 1314 1315 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1316 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1317 i2c_dev->slave_running = i2c_dev->slave[i]; 1318 i2c_dev->slave_dir = dir; 1319 1320 /* Start I2C slave processing */ 1321 stm32f7_i2c_slave_start(i2c_dev); 1322 1323 /* Clear ADDR flag */ 1324 mask = STM32F7_I2C_ICR_ADDRCF; 1325 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1326 break; 1327 } 1328 } 1329 } 1330 1331 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1332 struct i2c_client *slave, int *id) 1333 { 1334 int i; 1335 1336 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1337 if (i2c_dev->slave[i] == slave) { 1338 *id = i; 1339 return 0; 1340 } 1341 } 1342 1343 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1344 1345 return -ENODEV; 1346 } 1347 1348 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1349 struct i2c_client *slave, int *id) 1350 { 1351 struct device *dev = i2c_dev->dev; 1352 int i; 1353 1354 /* 1355 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8) 1356 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address 1357 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only 1358 */ 1359 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { 1360 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) 1361 goto fail; 1362 *id = STM32F7_SLAVE_HOSTNOTIFY; 1363 return 0; 1364 } 1365 1366 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { 1367 if ((i == STM32F7_SLAVE_7_BITS_ADDR) && 1368 (slave->flags & I2C_CLIENT_TEN)) 1369 continue; 1370 if (!i2c_dev->slave[i]) { 1371 *id = i; 1372 return 0; 1373 } 1374 } 1375 1376 fail: 1377 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1378 1379 return -EINVAL; 1380 } 1381 1382 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1383 { 1384 int i; 1385 1386 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1387 if (i2c_dev->slave[i]) 1388 return true; 1389 } 1390 1391 return false; 1392 } 1393 1394 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1395 { 1396 int i, busy; 1397 1398 busy = 0; 1399 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1400 if (i2c_dev->slave[i]) 1401 busy++; 1402 } 1403 1404 return i == busy; 1405 } 1406 1407 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev) 1408 { 1409 void __iomem *base = i2c_dev->base; 1410 u32 cr2, status, mask; 1411 u8 val; 1412 int ret; 1413 1414 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1415 1416 /* Slave transmitter mode */ 1417 if (status & STM32F7_I2C_ISR_TXIS) { 1418 i2c_slave_event(i2c_dev->slave_running, 1419 I2C_SLAVE_READ_PROCESSED, 1420 &val); 1421 1422 /* Write data byte */ 1423 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1424 } 1425 1426 /* Transfer Complete Reload for Slave receiver mode */ 1427 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1428 /* 1429 * Read data byte then set NBYTES to receive next byte or NACK 1430 * the current received byte 1431 */ 1432 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1433 ret = i2c_slave_event(i2c_dev->slave_running, 1434 I2C_SLAVE_WRITE_RECEIVED, 1435 &val); 1436 if (!ret) { 1437 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1438 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1439 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1440 } else { 1441 mask = STM32F7_I2C_CR2_NACK; 1442 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1443 } 1444 } 1445 1446 /* NACK received */ 1447 if (status & STM32F7_I2C_ISR_NACKF) { 1448 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1449 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1450 } 1451 1452 /* STOP received */ 1453 if (status & STM32F7_I2C_ISR_STOPF) { 1454 /* Disable interrupts */ 1455 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1456 1457 if (i2c_dev->slave_dir) { 1458 /* 1459 * Flush TX buffer in order to not used the byte in 1460 * TXDR for the next transfer 1461 */ 1462 mask = STM32F7_I2C_ISR_TXE; 1463 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1464 } 1465 1466 /* Clear STOP flag */ 1467 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1468 1469 /* Notify i2c slave that a STOP flag has been detected */ 1470 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1471 1472 i2c_dev->slave_running = NULL; 1473 } 1474 1475 /* Address match received */ 1476 if (status & STM32F7_I2C_ISR_ADDR) 1477 stm32f7_i2c_slave_addr(i2c_dev); 1478 1479 return IRQ_HANDLED; 1480 } 1481 1482 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1483 { 1484 struct stm32f7_i2c_dev *i2c_dev = data; 1485 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1486 struct stm32_i2c_dma *dma = i2c_dev->dma; 1487 void __iomem *base = i2c_dev->base; 1488 u32 status, mask; 1489 int ret = IRQ_HANDLED; 1490 1491 /* Check if the interrupt if for a slave device */ 1492 if (!i2c_dev->master_mode) { 1493 ret = stm32f7_i2c_slave_isr_event(i2c_dev); 1494 return ret; 1495 } 1496 1497 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1498 1499 /* Tx empty */ 1500 if (status & STM32F7_I2C_ISR_TXIS) 1501 stm32f7_i2c_write_tx_data(i2c_dev); 1502 1503 /* RX not empty */ 1504 if (status & STM32F7_I2C_ISR_RXNE) 1505 stm32f7_i2c_read_rx_data(i2c_dev); 1506 1507 /* NACK received */ 1508 if (status & STM32F7_I2C_ISR_NACKF) { 1509 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", 1510 __func__, f7_msg->addr); 1511 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1512 if (i2c_dev->use_dma) { 1513 stm32f7_i2c_disable_dma_req(i2c_dev); 1514 dmaengine_terminate_async(dma->chan_using); 1515 } 1516 f7_msg->result = -ENXIO; 1517 } 1518 1519 /* STOP detection flag */ 1520 if (status & STM32F7_I2C_ISR_STOPF) { 1521 /* Disable interrupts */ 1522 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1523 mask = STM32F7_I2C_XFER_IRQ_MASK; 1524 else 1525 mask = STM32F7_I2C_ALL_IRQ_MASK; 1526 stm32f7_i2c_disable_irq(i2c_dev, mask); 1527 1528 /* Clear STOP flag */ 1529 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1530 1531 if (i2c_dev->use_dma && !f7_msg->result) { 1532 ret = IRQ_WAKE_THREAD; 1533 } else { 1534 i2c_dev->master_mode = false; 1535 complete(&i2c_dev->complete); 1536 } 1537 } 1538 1539 /* Transfer complete */ 1540 if (status & STM32F7_I2C_ISR_TC) { 1541 if (f7_msg->stop) { 1542 mask = STM32F7_I2C_CR2_STOP; 1543 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1544 } else if (i2c_dev->use_dma && !f7_msg->result) { 1545 ret = IRQ_WAKE_THREAD; 1546 } else if (f7_msg->smbus) { 1547 stm32f7_i2c_smbus_rep_start(i2c_dev); 1548 } else { 1549 i2c_dev->msg_id++; 1550 i2c_dev->msg++; 1551 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1552 } 1553 } 1554 1555 if (status & STM32F7_I2C_ISR_TCR) { 1556 if (f7_msg->smbus) 1557 stm32f7_i2c_smbus_reload(i2c_dev); 1558 else 1559 stm32f7_i2c_reload(i2c_dev); 1560 } 1561 1562 return ret; 1563 } 1564 1565 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1566 { 1567 struct stm32f7_i2c_dev *i2c_dev = data; 1568 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1569 struct stm32_i2c_dma *dma = i2c_dev->dma; 1570 u32 status; 1571 int ret; 1572 1573 /* 1574 * Wait for dma transfer completion before sending next message or 1575 * notity the end of xfer to the client 1576 */ 1577 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1578 if (!ret) { 1579 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1580 stm32f7_i2c_disable_dma_req(i2c_dev); 1581 dmaengine_terminate_async(dma->chan_using); 1582 f7_msg->result = -ETIMEDOUT; 1583 } 1584 1585 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1586 1587 if (status & STM32F7_I2C_ISR_TC) { 1588 if (f7_msg->smbus) { 1589 stm32f7_i2c_smbus_rep_start(i2c_dev); 1590 } else { 1591 i2c_dev->msg_id++; 1592 i2c_dev->msg++; 1593 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1594 } 1595 } else { 1596 i2c_dev->master_mode = false; 1597 complete(&i2c_dev->complete); 1598 } 1599 1600 return IRQ_HANDLED; 1601 } 1602 1603 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data) 1604 { 1605 struct stm32f7_i2c_dev *i2c_dev = data; 1606 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1607 void __iomem *base = i2c_dev->base; 1608 struct device *dev = i2c_dev->dev; 1609 struct stm32_i2c_dma *dma = i2c_dev->dma; 1610 u32 status; 1611 1612 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1613 1614 /* Bus error */ 1615 if (status & STM32F7_I2C_ISR_BERR) { 1616 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n", 1617 __func__, f7_msg->addr); 1618 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1619 stm32f7_i2c_release_bus(&i2c_dev->adap); 1620 f7_msg->result = -EIO; 1621 } 1622 1623 /* Arbitration loss */ 1624 if (status & STM32F7_I2C_ISR_ARLO) { 1625 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n", 1626 __func__, f7_msg->addr); 1627 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1628 f7_msg->result = -EAGAIN; 1629 } 1630 1631 if (status & STM32F7_I2C_ISR_PECERR) { 1632 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n", 1633 __func__, f7_msg->addr); 1634 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1635 f7_msg->result = -EINVAL; 1636 } 1637 1638 if (status & STM32F7_I2C_ISR_ALERT) { 1639 dev_dbg(dev, "<%s>: SMBus alert received\n", __func__); 1640 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR); 1641 i2c_handle_smbus_alert(i2c_dev->alert->ara); 1642 return IRQ_HANDLED; 1643 } 1644 1645 if (!i2c_dev->slave_running) { 1646 u32 mask; 1647 /* Disable interrupts */ 1648 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1649 mask = STM32F7_I2C_XFER_IRQ_MASK; 1650 else 1651 mask = STM32F7_I2C_ALL_IRQ_MASK; 1652 stm32f7_i2c_disable_irq(i2c_dev, mask); 1653 } 1654 1655 /* Disable dma */ 1656 if (i2c_dev->use_dma) { 1657 stm32f7_i2c_disable_dma_req(i2c_dev); 1658 dmaengine_terminate_async(dma->chan_using); 1659 } 1660 1661 i2c_dev->master_mode = false; 1662 complete(&i2c_dev->complete); 1663 1664 return IRQ_HANDLED; 1665 } 1666 1667 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1668 struct i2c_msg msgs[], int num) 1669 { 1670 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1671 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1672 struct stm32_i2c_dma *dma = i2c_dev->dma; 1673 unsigned long time_left; 1674 int ret; 1675 1676 i2c_dev->msg = msgs; 1677 i2c_dev->msg_num = num; 1678 i2c_dev->msg_id = 0; 1679 f7_msg->smbus = false; 1680 1681 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1682 if (ret < 0) 1683 return ret; 1684 1685 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1686 if (ret) 1687 goto pm_free; 1688 1689 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1690 1691 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1692 i2c_dev->adap.timeout); 1693 ret = f7_msg->result; 1694 if (ret) { 1695 if (i2c_dev->use_dma) 1696 dmaengine_synchronize(dma->chan_using); 1697 1698 /* 1699 * It is possible that some unsent data have already been 1700 * written into TXDR. To avoid sending old data in a 1701 * further transfer, flush TXDR in case of any error 1702 */ 1703 writel_relaxed(STM32F7_I2C_ISR_TXE, 1704 i2c_dev->base + STM32F7_I2C_ISR); 1705 goto pm_free; 1706 } 1707 1708 if (!time_left) { 1709 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1710 i2c_dev->msg->addr); 1711 if (i2c_dev->use_dma) 1712 dmaengine_terminate_sync(dma->chan_using); 1713 stm32f7_i2c_wait_free_bus(i2c_dev); 1714 ret = -ETIMEDOUT; 1715 } 1716 1717 pm_free: 1718 pm_runtime_mark_last_busy(i2c_dev->dev); 1719 pm_runtime_put_autosuspend(i2c_dev->dev); 1720 1721 return (ret < 0) ? ret : num; 1722 } 1723 1724 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1725 unsigned short flags, char read_write, 1726 u8 command, int size, 1727 union i2c_smbus_data *data) 1728 { 1729 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1730 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1731 struct stm32_i2c_dma *dma = i2c_dev->dma; 1732 struct device *dev = i2c_dev->dev; 1733 unsigned long timeout; 1734 int i, ret; 1735 1736 f7_msg->addr = addr; 1737 f7_msg->size = size; 1738 f7_msg->read_write = read_write; 1739 f7_msg->smbus = true; 1740 1741 ret = pm_runtime_resume_and_get(dev); 1742 if (ret < 0) 1743 return ret; 1744 1745 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1746 if (ret) 1747 goto pm_free; 1748 1749 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1750 if (ret) 1751 goto pm_free; 1752 1753 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1754 i2c_dev->adap.timeout); 1755 ret = f7_msg->result; 1756 if (ret) { 1757 if (i2c_dev->use_dma) 1758 dmaengine_synchronize(dma->chan_using); 1759 1760 /* 1761 * It is possible that some unsent data have already been 1762 * written into TXDR. To avoid sending old data in a 1763 * further transfer, flush TXDR in case of any error 1764 */ 1765 writel_relaxed(STM32F7_I2C_ISR_TXE, 1766 i2c_dev->base + STM32F7_I2C_ISR); 1767 goto pm_free; 1768 } 1769 1770 if (!timeout) { 1771 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1772 if (i2c_dev->use_dma) 1773 dmaengine_terminate_sync(dma->chan_using); 1774 stm32f7_i2c_wait_free_bus(i2c_dev); 1775 ret = -ETIMEDOUT; 1776 goto pm_free; 1777 } 1778 1779 /* Check PEC */ 1780 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1781 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1782 if (ret) 1783 goto pm_free; 1784 } 1785 1786 if (read_write && size != I2C_SMBUS_QUICK) { 1787 switch (size) { 1788 case I2C_SMBUS_BYTE: 1789 case I2C_SMBUS_BYTE_DATA: 1790 data->byte = f7_msg->smbus_buf[0]; 1791 break; 1792 case I2C_SMBUS_WORD_DATA: 1793 case I2C_SMBUS_PROC_CALL: 1794 data->word = f7_msg->smbus_buf[0] | 1795 (f7_msg->smbus_buf[1] << 8); 1796 break; 1797 case I2C_SMBUS_BLOCK_DATA: 1798 case I2C_SMBUS_BLOCK_PROC_CALL: 1799 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1800 data->block[i] = f7_msg->smbus_buf[i]; 1801 break; 1802 default: 1803 dev_err(dev, "Unsupported smbus transaction\n"); 1804 ret = -EINVAL; 1805 } 1806 } 1807 1808 pm_free: 1809 pm_runtime_mark_last_busy(dev); 1810 pm_runtime_put_autosuspend(dev); 1811 return ret; 1812 } 1813 1814 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, 1815 bool enable) 1816 { 1817 void __iomem *base = i2c_dev->base; 1818 u32 mask = STM32F7_I2C_CR1_WUPEN; 1819 1820 if (!i2c_dev->wakeup_src) 1821 return; 1822 1823 if (enable) { 1824 device_set_wakeup_enable(i2c_dev->dev, true); 1825 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1826 } else { 1827 device_set_wakeup_enable(i2c_dev->dev, false); 1828 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1829 } 1830 } 1831 1832 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1833 { 1834 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1835 void __iomem *base = i2c_dev->base; 1836 struct device *dev = i2c_dev->dev; 1837 u32 oar1, oar2, mask; 1838 int id, ret; 1839 1840 if (slave->flags & I2C_CLIENT_PEC) { 1841 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1842 return -EINVAL; 1843 } 1844 1845 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1846 dev_err(dev, "Too much slave registered\n"); 1847 return -EBUSY; 1848 } 1849 1850 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1851 if (ret) 1852 return ret; 1853 1854 ret = pm_runtime_resume_and_get(dev); 1855 if (ret < 0) 1856 return ret; 1857 1858 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1859 stm32f7_i2c_enable_wakeup(i2c_dev, true); 1860 1861 switch (id) { 1862 case 0: 1863 /* Slave SMBus Host */ 1864 i2c_dev->slave[id] = slave; 1865 break; 1866 1867 case 1: 1868 /* Configure Own Address 1 */ 1869 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1870 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1871 if (slave->flags & I2C_CLIENT_TEN) { 1872 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1873 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1874 } else { 1875 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1876 } 1877 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1878 i2c_dev->slave[id] = slave; 1879 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1880 break; 1881 1882 case 2: 1883 /* Configure Own Address 2 */ 1884 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1885 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1886 if (slave->flags & I2C_CLIENT_TEN) { 1887 ret = -EOPNOTSUPP; 1888 goto pm_free; 1889 } 1890 1891 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1892 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1893 i2c_dev->slave[id] = slave; 1894 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1895 break; 1896 1897 default: 1898 dev_err(dev, "I2C slave id not supported\n"); 1899 ret = -ENODEV; 1900 goto pm_free; 1901 } 1902 1903 /* Enable ACK */ 1904 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1905 1906 /* Enable Address match interrupt, error interrupt and enable I2C */ 1907 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1908 STM32F7_I2C_CR1_PE; 1909 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1910 1911 ret = 0; 1912 pm_free: 1913 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1914 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1915 1916 pm_runtime_mark_last_busy(dev); 1917 pm_runtime_put_autosuspend(dev); 1918 1919 return ret; 1920 } 1921 1922 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1923 { 1924 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1925 void __iomem *base = i2c_dev->base; 1926 u32 mask; 1927 int id, ret; 1928 1929 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1930 if (ret) 1931 return ret; 1932 1933 WARN_ON(!i2c_dev->slave[id]); 1934 1935 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1936 if (ret < 0) 1937 return ret; 1938 1939 if (id == 1) { 1940 mask = STM32F7_I2C_OAR1_OA1EN; 1941 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1942 } else if (id == 2) { 1943 mask = STM32F7_I2C_OAR2_OA2EN; 1944 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1945 } 1946 1947 i2c_dev->slave[id] = NULL; 1948 1949 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 1950 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1951 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1952 } 1953 1954 pm_runtime_mark_last_busy(i2c_dev->dev); 1955 pm_runtime_put_autosuspend(i2c_dev->dev); 1956 1957 return 0; 1958 } 1959 1960 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, 1961 bool enable) 1962 { 1963 int ret; 1964 1965 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || 1966 IS_ERR_OR_NULL(i2c_dev->regmap)) 1967 /* Optional */ 1968 return 0; 1969 1970 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) 1971 ret = regmap_update_bits(i2c_dev->regmap, 1972 i2c_dev->fmp_sreg, 1973 i2c_dev->fmp_mask, 1974 enable ? i2c_dev->fmp_mask : 0); 1975 else 1976 ret = regmap_write(i2c_dev->regmap, 1977 enable ? i2c_dev->fmp_sreg : 1978 i2c_dev->fmp_creg, 1979 i2c_dev->fmp_mask); 1980 1981 return ret; 1982 } 1983 1984 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 1985 struct stm32f7_i2c_dev *i2c_dev) 1986 { 1987 struct device_node *np = pdev->dev.of_node; 1988 int ret; 1989 1990 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 1991 if (IS_ERR(i2c_dev->regmap)) 1992 /* Optional */ 1993 return 0; 1994 1995 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, 1996 &i2c_dev->fmp_sreg); 1997 if (ret) 1998 return ret; 1999 2000 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + 2001 i2c_dev->setup.fmp_clr_offset; 2002 2003 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, 2004 &i2c_dev->fmp_mask); 2005 } 2006 2007 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2008 { 2009 struct i2c_adapter *adap = &i2c_dev->adap; 2010 void __iomem *base = i2c_dev->base; 2011 struct i2c_client *client; 2012 2013 client = i2c_new_slave_host_notify_device(adap); 2014 if (IS_ERR(client)) 2015 return PTR_ERR(client); 2016 2017 i2c_dev->host_notify_client = client; 2018 2019 /* Enable SMBus Host address */ 2020 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN); 2021 2022 return 0; 2023 } 2024 2025 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2026 { 2027 void __iomem *base = i2c_dev->base; 2028 2029 if (i2c_dev->host_notify_client) { 2030 /* Disable SMBus Host address */ 2031 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2032 STM32F7_I2C_CR1_SMBHEN); 2033 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); 2034 } 2035 } 2036 2037 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2038 { 2039 struct stm32f7_i2c_alert *alert; 2040 struct i2c_adapter *adap = &i2c_dev->adap; 2041 struct device *dev = i2c_dev->dev; 2042 void __iomem *base = i2c_dev->base; 2043 2044 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL); 2045 if (!alert) 2046 return -ENOMEM; 2047 2048 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); 2049 if (IS_ERR(alert->ara)) 2050 return PTR_ERR(alert->ara); 2051 2052 i2c_dev->alert = alert; 2053 2054 /* Enable SMBus Alert */ 2055 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN); 2056 2057 return 0; 2058 } 2059 2060 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2061 { 2062 struct stm32f7_i2c_alert *alert = i2c_dev->alert; 2063 void __iomem *base = i2c_dev->base; 2064 2065 if (alert) { 2066 /* Disable SMBus Alert */ 2067 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2068 STM32F7_I2C_CR1_ALERTEN); 2069 i2c_unregister_device(alert->ara); 2070 } 2071 } 2072 2073 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 2074 { 2075 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 2076 2077 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 2078 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 2079 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 2080 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 2081 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 2082 I2C_FUNC_SMBUS_I2C_BLOCK; 2083 2084 if (i2c_dev->smbus_mode) 2085 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 2086 2087 return func; 2088 } 2089 2090 static const struct i2c_algorithm stm32f7_i2c_algo = { 2091 .master_xfer = stm32f7_i2c_xfer, 2092 .smbus_xfer = stm32f7_i2c_smbus_xfer, 2093 .functionality = stm32f7_i2c_func, 2094 .reg_slave = stm32f7_i2c_reg_slave, 2095 .unreg_slave = stm32f7_i2c_unreg_slave, 2096 }; 2097 2098 static int stm32f7_i2c_probe(struct platform_device *pdev) 2099 { 2100 struct stm32f7_i2c_dev *i2c_dev; 2101 const struct stm32f7_i2c_setup *setup; 2102 struct resource *res; 2103 struct i2c_adapter *adap; 2104 struct reset_control *rst; 2105 dma_addr_t phy_addr; 2106 int irq_error, irq_event, ret; 2107 2108 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 2109 if (!i2c_dev) 2110 return -ENOMEM; 2111 2112 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2113 if (IS_ERR(i2c_dev->base)) 2114 return PTR_ERR(i2c_dev->base); 2115 phy_addr = (dma_addr_t)res->start; 2116 2117 irq_event = platform_get_irq(pdev, 0); 2118 if (irq_event <= 0) 2119 return irq_event ? : -ENOENT; 2120 2121 irq_error = platform_get_irq(pdev, 1); 2122 if (irq_error <= 0) 2123 return irq_error ? : -ENOENT; 2124 2125 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, 2126 "wakeup-source"); 2127 2128 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 2129 if (IS_ERR(i2c_dev->clk)) 2130 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), 2131 "Failed to get controller clock\n"); 2132 2133 ret = clk_prepare_enable(i2c_dev->clk); 2134 if (ret) { 2135 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); 2136 return ret; 2137 } 2138 2139 rst = devm_reset_control_get(&pdev->dev, NULL); 2140 if (IS_ERR(rst)) { 2141 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), 2142 "Error: Missing reset ctrl\n"); 2143 goto clk_free; 2144 } 2145 reset_control_assert(rst); 2146 udelay(2); 2147 reset_control_deassert(rst); 2148 2149 i2c_dev->dev = &pdev->dev; 2150 2151 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 2152 stm32f7_i2c_isr_event, 2153 stm32f7_i2c_isr_event_thread, 2154 IRQF_ONESHOT, 2155 pdev->name, i2c_dev); 2156 if (ret) { 2157 dev_err(&pdev->dev, "Failed to request irq event %i\n", 2158 irq_event); 2159 goto clk_free; 2160 } 2161 2162 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, 2163 pdev->name, i2c_dev); 2164 if (ret) { 2165 dev_err(&pdev->dev, "Failed to request irq error %i\n", 2166 irq_error); 2167 goto clk_free; 2168 } 2169 2170 setup = of_device_get_match_data(&pdev->dev); 2171 if (!setup) { 2172 dev_err(&pdev->dev, "Can't get device data\n"); 2173 ret = -ENODEV; 2174 goto clk_free; 2175 } 2176 i2c_dev->setup = *setup; 2177 2178 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 2179 if (ret) 2180 goto clk_free; 2181 2182 /* Setup Fast mode plus if necessary */ 2183 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { 2184 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 2185 if (ret) 2186 goto clk_free; 2187 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2188 if (ret) 2189 goto clk_free; 2190 } 2191 2192 adap = &i2c_dev->adap; 2193 i2c_set_adapdata(adap, i2c_dev); 2194 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 2195 &res->start); 2196 adap->owner = THIS_MODULE; 2197 adap->timeout = 2 * HZ; 2198 adap->retries = 3; 2199 adap->algo = &stm32f7_i2c_algo; 2200 adap->dev.parent = &pdev->dev; 2201 adap->dev.of_node = pdev->dev.of_node; 2202 2203 init_completion(&i2c_dev->complete); 2204 2205 /* Init DMA config if supported */ 2206 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 2207 STM32F7_I2C_TXDR, 2208 STM32F7_I2C_RXDR); 2209 if (IS_ERR(i2c_dev->dma)) { 2210 ret = PTR_ERR(i2c_dev->dma); 2211 /* DMA support is optional, only report other errors */ 2212 if (ret != -ENODEV) 2213 goto fmp_clear; 2214 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); 2215 i2c_dev->dma = NULL; 2216 } 2217 2218 if (i2c_dev->wakeup_src) { 2219 device_set_wakeup_capable(i2c_dev->dev, true); 2220 2221 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); 2222 if (ret) { 2223 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); 2224 goto clr_wakeup_capable; 2225 } 2226 } 2227 2228 platform_set_drvdata(pdev, i2c_dev); 2229 2230 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 2231 STM32F7_AUTOSUSPEND_DELAY); 2232 pm_runtime_use_autosuspend(i2c_dev->dev); 2233 pm_runtime_set_active(i2c_dev->dev); 2234 pm_runtime_enable(i2c_dev->dev); 2235 2236 pm_runtime_get_noresume(&pdev->dev); 2237 2238 stm32f7_i2c_hw_config(i2c_dev); 2239 2240 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); 2241 2242 ret = i2c_add_adapter(adap); 2243 if (ret) 2244 goto pm_disable; 2245 2246 if (i2c_dev->smbus_mode) { 2247 ret = stm32f7_i2c_enable_smbus_host(i2c_dev); 2248 if (ret) { 2249 dev_err(i2c_dev->dev, 2250 "failed to enable SMBus Host-Notify protocol (%d)\n", 2251 ret); 2252 goto i2c_adapter_remove; 2253 } 2254 } 2255 2256 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { 2257 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev); 2258 if (ret) { 2259 dev_err(i2c_dev->dev, 2260 "failed to enable SMBus alert protocol (%d)\n", 2261 ret); 2262 goto i2c_disable_smbus_host; 2263 } 2264 } 2265 2266 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2267 2268 pm_runtime_mark_last_busy(i2c_dev->dev); 2269 pm_runtime_put_autosuspend(i2c_dev->dev); 2270 2271 return 0; 2272 2273 i2c_disable_smbus_host: 2274 stm32f7_i2c_disable_smbus_host(i2c_dev); 2275 2276 i2c_adapter_remove: 2277 i2c_del_adapter(adap); 2278 2279 pm_disable: 2280 pm_runtime_put_noidle(i2c_dev->dev); 2281 pm_runtime_disable(i2c_dev->dev); 2282 pm_runtime_set_suspended(i2c_dev->dev); 2283 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2284 2285 if (i2c_dev->wakeup_src) 2286 dev_pm_clear_wake_irq(i2c_dev->dev); 2287 2288 clr_wakeup_capable: 2289 if (i2c_dev->wakeup_src) 2290 device_set_wakeup_capable(i2c_dev->dev, false); 2291 2292 if (i2c_dev->dma) { 2293 stm32_i2c_dma_free(i2c_dev->dma); 2294 i2c_dev->dma = NULL; 2295 } 2296 2297 fmp_clear: 2298 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2299 2300 clk_free: 2301 clk_disable_unprepare(i2c_dev->clk); 2302 2303 return ret; 2304 } 2305 2306 static int stm32f7_i2c_remove(struct platform_device *pdev) 2307 { 2308 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2309 2310 stm32f7_i2c_disable_smbus_alert(i2c_dev); 2311 stm32f7_i2c_disable_smbus_host(i2c_dev); 2312 2313 i2c_del_adapter(&i2c_dev->adap); 2314 pm_runtime_get_sync(i2c_dev->dev); 2315 2316 if (i2c_dev->wakeup_src) { 2317 dev_pm_clear_wake_irq(i2c_dev->dev); 2318 /* 2319 * enforce that wakeup is disabled and that the device 2320 * is marked as non wakeup capable 2321 */ 2322 device_init_wakeup(i2c_dev->dev, false); 2323 } 2324 2325 pm_runtime_put_noidle(i2c_dev->dev); 2326 pm_runtime_disable(i2c_dev->dev); 2327 pm_runtime_set_suspended(i2c_dev->dev); 2328 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2329 2330 if (i2c_dev->dma) { 2331 stm32_i2c_dma_free(i2c_dev->dma); 2332 i2c_dev->dma = NULL; 2333 } 2334 2335 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2336 2337 clk_disable_unprepare(i2c_dev->clk); 2338 2339 return 0; 2340 } 2341 2342 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev) 2343 { 2344 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2345 2346 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2347 clk_disable_unprepare(i2c_dev->clk); 2348 2349 return 0; 2350 } 2351 2352 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev) 2353 { 2354 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2355 int ret; 2356 2357 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2358 ret = clk_prepare_enable(i2c_dev->clk); 2359 if (ret) { 2360 dev_err(dev, "failed to prepare_enable clock\n"); 2361 return ret; 2362 } 2363 } 2364 2365 return 0; 2366 } 2367 2368 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2369 { 2370 int ret; 2371 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2372 2373 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2374 if (ret < 0) 2375 return ret; 2376 2377 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2378 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 2379 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 2380 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 2381 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); 2382 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2383 2384 pm_runtime_put_sync(i2c_dev->dev); 2385 2386 return ret; 2387 } 2388 2389 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2390 { 2391 u32 cr1; 2392 int ret; 2393 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2394 2395 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2396 if (ret < 0) 2397 return ret; 2398 2399 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2400 if (cr1 & STM32F7_I2C_CR1_PE) 2401 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 2402 STM32F7_I2C_CR1_PE); 2403 2404 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); 2405 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, 2406 i2c_dev->base + STM32F7_I2C_CR1); 2407 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) 2408 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 2409 STM32F7_I2C_CR1_PE); 2410 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); 2411 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); 2412 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); 2413 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2414 2415 pm_runtime_put_sync(i2c_dev->dev); 2416 2417 return ret; 2418 } 2419 2420 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev) 2421 { 2422 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2423 int ret; 2424 2425 i2c_mark_adapter_suspended(&i2c_dev->adap); 2426 2427 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2428 ret = stm32f7_i2c_regs_backup(i2c_dev); 2429 if (ret < 0) { 2430 i2c_mark_adapter_resumed(&i2c_dev->adap); 2431 return ret; 2432 } 2433 2434 pinctrl_pm_select_sleep_state(dev); 2435 pm_runtime_force_suspend(dev); 2436 } 2437 2438 return 0; 2439 } 2440 2441 static int __maybe_unused stm32f7_i2c_resume(struct device *dev) 2442 { 2443 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2444 int ret; 2445 2446 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2447 ret = pm_runtime_force_resume(dev); 2448 if (ret < 0) 2449 return ret; 2450 pinctrl_pm_select_default_state(dev); 2451 2452 ret = stm32f7_i2c_regs_restore(i2c_dev); 2453 if (ret < 0) 2454 return ret; 2455 } 2456 2457 i2c_mark_adapter_resumed(&i2c_dev->adap); 2458 2459 return 0; 2460 } 2461 2462 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2463 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2464 stm32f7_i2c_runtime_resume, NULL) 2465 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume) 2466 }; 2467 2468 static const struct of_device_id stm32f7_i2c_match[] = { 2469 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2470 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup}, 2471 {}, 2472 }; 2473 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2474 2475 static struct platform_driver stm32f7_i2c_driver = { 2476 .driver = { 2477 .name = "stm32f7-i2c", 2478 .of_match_table = stm32f7_i2c_match, 2479 .pm = &stm32f7_i2c_pm_ops, 2480 }, 2481 .probe = stm32f7_i2c_probe, 2482 .remove = stm32f7_i2c_remove, 2483 }; 2484 2485 module_platform_driver(stm32f7_i2c_driver); 2486 2487 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2488 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2489 MODULE_LICENSE("GPL v2"); 2490