1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/i2c-smbus.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/pm_wakeirq.h> 34 #include <linux/regmap.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 38 #include "i2c-stm32.h" 39 40 /* STM32F7 I2C registers */ 41 #define STM32F7_I2C_CR1 0x00 42 #define STM32F7_I2C_CR2 0x04 43 #define STM32F7_I2C_OAR1 0x08 44 #define STM32F7_I2C_OAR2 0x0C 45 #define STM32F7_I2C_PECR 0x20 46 #define STM32F7_I2C_TIMINGR 0x10 47 #define STM32F7_I2C_ISR 0x18 48 #define STM32F7_I2C_ICR 0x1C 49 #define STM32F7_I2C_RXDR 0x24 50 #define STM32F7_I2C_TXDR 0x28 51 52 /* STM32F7 I2C control 1 */ 53 #define STM32F7_I2C_CR1_PECEN BIT(23) 54 #define STM32F7_I2C_CR1_ALERTEN BIT(22) 55 #define STM32F7_I2C_CR1_SMBHEN BIT(20) 56 #define STM32F7_I2C_CR1_WUPEN BIT(18) 57 #define STM32F7_I2C_CR1_SBC BIT(16) 58 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 59 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 60 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 61 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8) 62 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8) 63 #define STM32F7_I2C_CR1_ERRIE BIT(7) 64 #define STM32F7_I2C_CR1_TCIE BIT(6) 65 #define STM32F7_I2C_CR1_STOPIE BIT(5) 66 #define STM32F7_I2C_CR1_NACKIE BIT(4) 67 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 68 #define STM32F7_I2C_CR1_RXIE BIT(2) 69 #define STM32F7_I2C_CR1_TXIE BIT(1) 70 #define STM32F7_I2C_CR1_PE BIT(0) 71 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 72 | STM32F7_I2C_CR1_TCIE \ 73 | STM32F7_I2C_CR1_STOPIE \ 74 | STM32F7_I2C_CR1_NACKIE \ 75 | STM32F7_I2C_CR1_RXIE \ 76 | STM32F7_I2C_CR1_TXIE) 77 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 78 | STM32F7_I2C_CR1_STOPIE \ 79 | STM32F7_I2C_CR1_NACKIE \ 80 | STM32F7_I2C_CR1_RXIE \ 81 | STM32F7_I2C_CR1_TXIE) 82 83 /* STM32F7 I2C control 2 */ 84 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 85 #define STM32F7_I2C_CR2_RELOAD BIT(24) 86 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 87 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 88 #define STM32F7_I2C_CR2_NACK BIT(15) 89 #define STM32F7_I2C_CR2_STOP BIT(14) 90 #define STM32F7_I2C_CR2_START BIT(13) 91 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 92 #define STM32F7_I2C_CR2_ADD10 BIT(11) 93 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 94 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 95 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 96 STM32F7_I2C_CR2_SADD10_MASK)) 97 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 98 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 99 100 /* STM32F7 I2C Own Address 1 */ 101 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 102 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 103 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 104 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 105 STM32F7_I2C_OAR1_OA1_10_MASK)) 106 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 107 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 108 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 109 | STM32F7_I2C_OAR1_OA1_10_MASK \ 110 | STM32F7_I2C_OAR1_OA1EN \ 111 | STM32F7_I2C_OAR1_OA1MODE) 112 113 /* STM32F7 I2C Own Address 2 */ 114 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 115 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 116 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 117 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 118 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 119 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 120 | STM32F7_I2C_OAR2_OA2_7_MASK \ 121 | STM32F7_I2C_OAR2_OA2EN) 122 123 /* STM32F7 I2C Interrupt Status */ 124 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 127 #define STM32F7_I2C_ISR_DIR BIT(16) 128 #define STM32F7_I2C_ISR_BUSY BIT(15) 129 #define STM32F7_I2C_ISR_ALERT BIT(13) 130 #define STM32F7_I2C_ISR_PECERR BIT(11) 131 #define STM32F7_I2C_ISR_ARLO BIT(9) 132 #define STM32F7_I2C_ISR_BERR BIT(8) 133 #define STM32F7_I2C_ISR_TCR BIT(7) 134 #define STM32F7_I2C_ISR_TC BIT(6) 135 #define STM32F7_I2C_ISR_STOPF BIT(5) 136 #define STM32F7_I2C_ISR_NACKF BIT(4) 137 #define STM32F7_I2C_ISR_ADDR BIT(3) 138 #define STM32F7_I2C_ISR_RXNE BIT(2) 139 #define STM32F7_I2C_ISR_TXIS BIT(1) 140 #define STM32F7_I2C_ISR_TXE BIT(0) 141 142 /* STM32F7 I2C Interrupt Clear */ 143 #define STM32F7_I2C_ICR_ALERTCF BIT(13) 144 #define STM32F7_I2C_ICR_PECCF BIT(11) 145 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 146 #define STM32F7_I2C_ICR_BERRCF BIT(8) 147 #define STM32F7_I2C_ICR_STOPCF BIT(5) 148 #define STM32F7_I2C_ICR_NACKCF BIT(4) 149 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 150 151 /* STM32F7 I2C Timing */ 152 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 153 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 154 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 155 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 156 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 157 158 #define STM32F7_I2C_MAX_LEN 0xff 159 #define STM32F7_I2C_DMA_LEN_MIN 0x16 160 enum { 161 STM32F7_SLAVE_HOSTNOTIFY, 162 STM32F7_SLAVE_7_10_BITS_ADDR, 163 STM32F7_SLAVE_7_BITS_ADDR, 164 STM32F7_I2C_MAX_SLAVE 165 }; 166 167 #define STM32F7_I2C_DNF_DEFAULT 0 168 #define STM32F7_I2C_DNF_MAX 15 169 170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 172 173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 175 176 #define STM32F7_PRESC_MAX BIT(4) 177 #define STM32F7_SCLDEL_MAX BIT(4) 178 #define STM32F7_SDADEL_MAX BIT(4) 179 #define STM32F7_SCLH_MAX BIT(8) 180 #define STM32F7_SCLL_MAX BIT(8) 181 182 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 183 184 /** 185 * struct stm32f7_i2c_regs - i2c f7 registers backup 186 * @cr1: Control register 1 187 * @cr2: Control register 2 188 * @oar1: Own address 1 register 189 * @oar2: Own address 2 register 190 * @tmgr: Timing register 191 */ 192 struct stm32f7_i2c_regs { 193 u32 cr1; 194 u32 cr2; 195 u32 oar1; 196 u32 oar2; 197 u32 tmgr; 198 }; 199 200 /** 201 * struct stm32f7_i2c_spec - private i2c specification timing 202 * @rate: I2C bus speed (Hz) 203 * @fall_max: Max fall time of both SDA and SCL signals (ns) 204 * @rise_max: Max rise time of both SDA and SCL signals (ns) 205 * @hddat_min: Min data hold time (ns) 206 * @vddat_max: Max data valid time (ns) 207 * @sudat_min: Min data setup time (ns) 208 * @l_min: Min low period of the SCL clock (ns) 209 * @h_min: Min high period of the SCL clock (ns) 210 */ 211 struct stm32f7_i2c_spec { 212 u32 rate; 213 u32 fall_max; 214 u32 rise_max; 215 u32 hddat_min; 216 u32 vddat_max; 217 u32 sudat_min; 218 u32 l_min; 219 u32 h_min; 220 }; 221 222 /** 223 * struct stm32f7_i2c_setup - private I2C timing setup parameters 224 * @speed_freq: I2C speed frequency (Hz) 225 * @clock_src: I2C clock source frequency (Hz) 226 * @rise_time: Rise time (ns) 227 * @fall_time: Fall time (ns) 228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 229 */ 230 struct stm32f7_i2c_setup { 231 u32 speed_freq; 232 u32 clock_src; 233 u32 rise_time; 234 u32 fall_time; 235 u32 fmp_clr_offset; 236 }; 237 238 /** 239 * struct stm32f7_i2c_timings - private I2C output parameters 240 * @node: List entry 241 * @presc: Prescaler value 242 * @scldel: Data setup time 243 * @sdadel: Data hold time 244 * @sclh: SCL high period (master mode) 245 * @scll: SCL low period (master mode) 246 */ 247 struct stm32f7_i2c_timings { 248 struct list_head node; 249 u8 presc; 250 u8 scldel; 251 u8 sdadel; 252 u8 sclh; 253 u8 scll; 254 }; 255 256 /** 257 * struct stm32f7_i2c_msg - client specific data 258 * @addr: 8-bit or 10-bit slave addr, including r/w bit 259 * @count: number of bytes to be transferred 260 * @buf: data buffer 261 * @result: result of the transfer 262 * @stop: last I2C msg to be sent, i.e. STOP to be generated 263 * @smbus: boolean to know if the I2C IP is used in SMBus mode 264 * @size: type of SMBus protocol 265 * @read_write: direction of SMBus protocol 266 * SMBus block read and SMBus block write - block read process call protocols 267 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 268 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 269 * This buffer has to be 32-bit aligned to be compliant with memory address 270 * register in DMA mode. 271 */ 272 struct stm32f7_i2c_msg { 273 u16 addr; 274 u32 count; 275 u8 *buf; 276 int result; 277 bool stop; 278 bool smbus; 279 int size; 280 char read_write; 281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 282 }; 283 284 /** 285 * struct stm32f7_i2c_alert - SMBus alert specific data 286 * @setup: platform data for the smbus_alert i2c client 287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert 288 * Response Address 289 */ 290 struct stm32f7_i2c_alert { 291 struct i2c_smbus_alert_setup setup; 292 struct i2c_client *ara; 293 }; 294 295 /** 296 * struct stm32f7_i2c_dev - private data of the controller 297 * @adap: I2C adapter for this controller 298 * @dev: device for this controller 299 * @base: virtual memory area 300 * @complete: completion of I2C message 301 * @clk: hw i2c clock 302 * @bus_rate: I2C clock frequency of the controller 303 * @msg: Pointer to data to be written 304 * @msg_num: number of I2C messages to be executed 305 * @msg_id: message identifiant 306 * @f7_msg: customized i2c msg for driver usage 307 * @setup: I2C timing input setup 308 * @timing: I2C computed timings 309 * @slave: list of slave devices registered on the I2C bus 310 * @slave_running: slave device currently used 311 * @backup_regs: backup of i2c controller registers (for suspend/resume) 312 * @slave_dir: transfer direction for the current slave device 313 * @master_mode: boolean to know in which mode the I2C is running (master or 314 * slave) 315 * @dma: dma data 316 * @use_dma: boolean to know if dma is used in the current transfer 317 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 318 * @fmp_sreg: register address for setting Fast Mode Plus bits 319 * @fmp_creg: register address for clearing Fast Mode Plus bits 320 * @fmp_mask: mask for Fast Mode Plus bits in set register 321 * @wakeup_src: boolean to know if the device is a wakeup source 322 * @smbus_mode: states that the controller is configured in SMBus mode 323 * @host_notify_client: SMBus host-notify client 324 * @analog_filter: boolean to indicate enabling of the analog filter 325 * @dnf_dt: value of digital filter requested via dt 326 * @dnf: value of digital filter to apply 327 * @alert: SMBus alert specific data 328 */ 329 struct stm32f7_i2c_dev { 330 struct i2c_adapter adap; 331 struct device *dev; 332 void __iomem *base; 333 struct completion complete; 334 struct clk *clk; 335 unsigned int bus_rate; 336 struct i2c_msg *msg; 337 unsigned int msg_num; 338 unsigned int msg_id; 339 struct stm32f7_i2c_msg f7_msg; 340 struct stm32f7_i2c_setup setup; 341 struct stm32f7_i2c_timings timing; 342 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 343 struct i2c_client *slave_running; 344 struct stm32f7_i2c_regs backup_regs; 345 u32 slave_dir; 346 bool master_mode; 347 struct stm32_i2c_dma *dma; 348 bool use_dma; 349 struct regmap *regmap; 350 u32 fmp_sreg; 351 u32 fmp_creg; 352 u32 fmp_mask; 353 bool wakeup_src; 354 bool smbus_mode; 355 struct i2c_client *host_notify_client; 356 bool analog_filter; 357 u32 dnf_dt; 358 u32 dnf; 359 struct stm32f7_i2c_alert *alert; 360 }; 361 362 /* 363 * All these values are coming from I2C Specification, Version 6.0, 4th of 364 * April 2014. 365 * 366 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 367 * and Fast-mode Plus I2C-bus devices 368 */ 369 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = { 370 { 371 .rate = I2C_MAX_STANDARD_MODE_FREQ, 372 .fall_max = 300, 373 .rise_max = 1000, 374 .hddat_min = 0, 375 .vddat_max = 3450, 376 .sudat_min = 250, 377 .l_min = 4700, 378 .h_min = 4000, 379 }, 380 { 381 .rate = I2C_MAX_FAST_MODE_FREQ, 382 .fall_max = 300, 383 .rise_max = 300, 384 .hddat_min = 0, 385 .vddat_max = 900, 386 .sudat_min = 100, 387 .l_min = 1300, 388 .h_min = 600, 389 }, 390 { 391 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ, 392 .fall_max = 100, 393 .rise_max = 120, 394 .hddat_min = 0, 395 .vddat_max = 450, 396 .sudat_min = 50, 397 .l_min = 500, 398 .h_min = 260, 399 }, 400 }; 401 402 static const struct stm32f7_i2c_setup stm32f7_setup = { 403 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 404 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 405 }; 406 407 static const struct stm32f7_i2c_setup stm32mp15_setup = { 408 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 409 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 410 .fmp_clr_offset = 0x40, 411 }; 412 413 static const struct stm32f7_i2c_setup stm32mp13_setup = { 414 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 415 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 416 .fmp_clr_offset = 0x4, 417 }; 418 419 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 420 { 421 writel_relaxed(readl_relaxed(reg) | mask, reg); 422 } 423 424 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 425 { 426 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 427 } 428 429 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 430 { 431 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 432 } 433 434 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate) 435 { 436 int i; 437 438 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++) 439 if (rate <= stm32f7_i2c_specs[i].rate) 440 return &stm32f7_i2c_specs[i]; 441 442 return ERR_PTR(-EINVAL); 443 } 444 445 #define RATE_MIN(rate) ((rate) * 8 / 10) 446 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 447 struct stm32f7_i2c_setup *setup, 448 struct stm32f7_i2c_timings *output) 449 { 450 struct stm32f7_i2c_spec *specs; 451 u32 p_prev = STM32F7_PRESC_MAX; 452 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 453 setup->clock_src); 454 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 455 setup->speed_freq); 456 u32 clk_error_prev = i2cbus; 457 u32 tsync; 458 u32 af_delay_min, af_delay_max; 459 u32 dnf_delay; 460 u32 clk_min, clk_max; 461 int sdadel_min, sdadel_max; 462 int scldel_min; 463 struct stm32f7_i2c_timings *v, *_v, *s; 464 struct list_head solutions; 465 u16 p, l, a, h; 466 int ret = 0; 467 468 specs = stm32f7_get_specs(setup->speed_freq); 469 if (specs == ERR_PTR(-EINVAL)) { 470 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", 471 setup->speed_freq); 472 return -EINVAL; 473 } 474 475 if ((setup->rise_time > specs->rise_max) || 476 (setup->fall_time > specs->fall_max)) { 477 dev_err(i2c_dev->dev, 478 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 479 setup->rise_time, specs->rise_max, 480 setup->fall_time, specs->fall_max); 481 return -EINVAL; 482 } 483 484 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); 485 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { 486 dev_err(i2c_dev->dev, 487 "DNF out of bound %d/%d\n", 488 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); 489 return -EINVAL; 490 } 491 492 /* Analog and Digital Filters */ 493 af_delay_min = 494 (i2c_dev->analog_filter ? 495 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 496 af_delay_max = 497 (i2c_dev->analog_filter ? 498 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 499 dnf_delay = i2c_dev->dnf * i2cclk; 500 501 sdadel_min = specs->hddat_min + setup->fall_time - 502 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; 503 504 sdadel_max = specs->vddat_max - setup->rise_time - 505 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; 506 507 scldel_min = setup->rise_time + specs->sudat_min; 508 509 if (sdadel_min < 0) 510 sdadel_min = 0; 511 if (sdadel_max < 0) 512 sdadel_max = 0; 513 514 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 515 sdadel_min, sdadel_max, scldel_min); 516 517 INIT_LIST_HEAD(&solutions); 518 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 519 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 520 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 521 u32 scldel = (l + 1) * (p + 1) * i2cclk; 522 523 if (scldel < scldel_min) 524 continue; 525 526 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 527 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 528 529 if (((sdadel >= sdadel_min) && 530 (sdadel <= sdadel_max)) && 531 (p != p_prev)) { 532 v = kmalloc(sizeof(*v), GFP_KERNEL); 533 if (!v) { 534 ret = -ENOMEM; 535 goto exit; 536 } 537 538 v->presc = p; 539 v->scldel = l; 540 v->sdadel = a; 541 p_prev = p; 542 543 list_add_tail(&v->node, 544 &solutions); 545 break; 546 } 547 } 548 549 if (p_prev == p) 550 break; 551 } 552 } 553 554 if (list_empty(&solutions)) { 555 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 556 ret = -EPERM; 557 goto exit; 558 } 559 560 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 561 s = NULL; 562 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); 563 clk_min = NSEC_PER_SEC / setup->speed_freq; 564 565 /* 566 * Among Prescaler possibilities discovered above figures out SCL Low 567 * and High Period. Provided: 568 * - SCL Low Period has to be higher than SCL Clock Low Period 569 * defined by I2C Specification. I2C Clock has to be lower than 570 * (SCL Low Period - Analog/Digital filters) / 4. 571 * - SCL High Period has to be lower than SCL Clock High Period 572 * defined by I2C Specification 573 * - I2C Clock has to be lower than SCL High Period 574 */ 575 list_for_each_entry(v, &solutions, node) { 576 u32 prescaler = (v->presc + 1) * i2cclk; 577 578 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 579 u32 tscl_l = (l + 1) * prescaler + tsync; 580 581 if ((tscl_l < specs->l_min) || 582 (i2cclk >= 583 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 584 continue; 585 } 586 587 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 588 u32 tscl_h = (h + 1) * prescaler + tsync; 589 u32 tscl = tscl_l + tscl_h + 590 setup->rise_time + setup->fall_time; 591 592 if ((tscl >= clk_min) && (tscl <= clk_max) && 593 (tscl_h >= specs->h_min) && 594 (i2cclk < tscl_h)) { 595 int clk_error = tscl - i2cbus; 596 597 if (clk_error < 0) 598 clk_error = -clk_error; 599 600 if (clk_error < clk_error_prev) { 601 clk_error_prev = clk_error; 602 v->scll = l; 603 v->sclh = h; 604 s = v; 605 } 606 } 607 } 608 } 609 } 610 611 if (!s) { 612 dev_err(i2c_dev->dev, "no solution at all\n"); 613 ret = -EPERM; 614 goto exit; 615 } 616 617 output->presc = s->presc; 618 output->scldel = s->scldel; 619 output->sdadel = s->sdadel; 620 output->scll = s->scll; 621 output->sclh = s->sclh; 622 623 dev_dbg(i2c_dev->dev, 624 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 625 output->presc, 626 output->scldel, output->sdadel, 627 output->scll, output->sclh); 628 629 exit: 630 /* Release list and memory */ 631 list_for_each_entry_safe(v, _v, &solutions, node) { 632 list_del(&v->node); 633 kfree(v); 634 } 635 636 return ret; 637 } 638 639 static u32 stm32f7_get_lower_rate(u32 rate) 640 { 641 int i = ARRAY_SIZE(stm32f7_i2c_specs); 642 643 while (--i) 644 if (stm32f7_i2c_specs[i].rate < rate) 645 break; 646 647 return stm32f7_i2c_specs[i].rate; 648 } 649 650 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 651 struct stm32f7_i2c_setup *setup) 652 { 653 struct i2c_timings timings, *t = &timings; 654 int ret = 0; 655 656 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 657 t->scl_rise_ns = i2c_dev->setup.rise_time; 658 t->scl_fall_ns = i2c_dev->setup.fall_time; 659 660 i2c_parse_fw_timings(i2c_dev->dev, t, false); 661 662 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { 663 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", 664 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); 665 return -EINVAL; 666 } 667 668 setup->speed_freq = t->bus_freq_hz; 669 i2c_dev->setup.rise_time = t->scl_rise_ns; 670 i2c_dev->setup.fall_time = t->scl_fall_ns; 671 i2c_dev->dnf_dt = t->digital_filter_width_ns; 672 setup->clock_src = clk_get_rate(i2c_dev->clk); 673 674 if (!setup->clock_src) { 675 dev_err(i2c_dev->dev, "clock rate is 0\n"); 676 return -EINVAL; 677 } 678 679 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) 680 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; 681 682 do { 683 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 684 &i2c_dev->timing); 685 if (ret) { 686 dev_err(i2c_dev->dev, 687 "failed to compute I2C timings.\n"); 688 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) 689 break; 690 setup->speed_freq = 691 stm32f7_get_lower_rate(setup->speed_freq); 692 dev_warn(i2c_dev->dev, 693 "downgrade I2C Speed Freq to (%i)\n", 694 setup->speed_freq); 695 } 696 } while (ret); 697 698 if (ret) { 699 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 700 return ret; 701 } 702 703 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, 704 "i2c-analog-filter"); 705 706 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 707 setup->speed_freq, setup->clock_src); 708 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 709 setup->rise_time, setup->fall_time); 710 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 711 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); 712 713 i2c_dev->bus_rate = setup->speed_freq; 714 715 return 0; 716 } 717 718 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 719 { 720 void __iomem *base = i2c_dev->base; 721 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 722 723 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 724 } 725 726 static void stm32f7_i2c_dma_callback(void *arg) 727 { 728 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 729 struct stm32_i2c_dma *dma = i2c_dev->dma; 730 struct device *dev = dma->chan_using->device->dev; 731 732 stm32f7_i2c_disable_dma_req(i2c_dev); 733 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 734 complete(&dma->dma_complete); 735 } 736 737 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 738 { 739 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 740 u32 timing = 0; 741 742 /* Timing settings */ 743 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 744 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 745 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 746 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 747 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 748 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 749 750 /* Configure the Analog Filter */ 751 if (i2c_dev->analog_filter) 752 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 753 STM32F7_I2C_CR1_ANFOFF); 754 else 755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 756 STM32F7_I2C_CR1_ANFOFF); 757 758 /* Program the Digital Filter */ 759 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 760 STM32F7_I2C_CR1_DNF_MASK); 761 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 762 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); 763 764 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 765 STM32F7_I2C_CR1_PE); 766 } 767 768 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 769 { 770 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 771 void __iomem *base = i2c_dev->base; 772 773 if (f7_msg->count) { 774 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 775 f7_msg->count--; 776 } 777 } 778 779 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 780 { 781 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 782 void __iomem *base = i2c_dev->base; 783 784 if (f7_msg->count) { 785 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 786 f7_msg->count--; 787 } else { 788 /* Flush RX buffer has no data is expected */ 789 readb_relaxed(base + STM32F7_I2C_RXDR); 790 } 791 } 792 793 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 794 { 795 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 796 u32 cr2; 797 798 if (i2c_dev->use_dma) 799 f7_msg->count -= STM32F7_I2C_MAX_LEN; 800 801 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 802 803 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 804 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 805 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 806 } else { 807 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 808 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 809 } 810 811 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 812 } 813 814 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 815 { 816 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 817 u32 cr2; 818 u8 *val; 819 820 /* 821 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 822 * data received inform us how many data will follow. 823 */ 824 stm32f7_i2c_read_rx_data(i2c_dev); 825 826 /* 827 * Update NBYTES with the value read to continue the transfer 828 */ 829 val = f7_msg->buf - sizeof(u8); 830 f7_msg->count = *val; 831 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 832 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 833 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 834 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 835 } 836 837 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 838 { 839 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 840 841 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 842 STM32F7_I2C_CR1_PE); 843 844 stm32f7_i2c_hw_config(i2c_dev); 845 } 846 847 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 848 { 849 u32 status; 850 int ret; 851 852 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 853 status, 854 !(status & STM32F7_I2C_ISR_BUSY), 855 10, 1000); 856 if (!ret) 857 return 0; 858 859 stm32f7_i2c_release_bus(&i2c_dev->adap); 860 861 return -EBUSY; 862 } 863 864 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 865 struct i2c_msg *msg) 866 { 867 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 868 void __iomem *base = i2c_dev->base; 869 u32 cr1, cr2; 870 int ret; 871 872 f7_msg->addr = msg->addr; 873 f7_msg->buf = msg->buf; 874 f7_msg->count = msg->len; 875 f7_msg->result = 0; 876 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 877 878 reinit_completion(&i2c_dev->complete); 879 880 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 881 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 882 883 /* Set transfer direction */ 884 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 885 if (msg->flags & I2C_M_RD) 886 cr2 |= STM32F7_I2C_CR2_RD_WRN; 887 888 /* Set slave address */ 889 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 890 if (msg->flags & I2C_M_TEN) { 891 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 892 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 893 cr2 |= STM32F7_I2C_CR2_ADD10; 894 } else { 895 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 896 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 897 } 898 899 /* Set nb bytes to transfer and reload if needed */ 900 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 901 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 902 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 903 cr2 |= STM32F7_I2C_CR2_RELOAD; 904 } else { 905 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 906 } 907 908 /* Enable NACK, STOP, error and transfer complete interrupts */ 909 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 910 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 911 912 /* Clear DMA req and TX/RX interrupt */ 913 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 914 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 915 916 /* Configure DMA or enable RX/TX interrupt */ 917 i2c_dev->use_dma = false; 918 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 919 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 920 msg->flags & I2C_M_RD, 921 f7_msg->count, f7_msg->buf, 922 stm32f7_i2c_dma_callback, 923 i2c_dev); 924 if (!ret) 925 i2c_dev->use_dma = true; 926 else 927 dev_warn(i2c_dev->dev, "can't use DMA\n"); 928 } 929 930 if (!i2c_dev->use_dma) { 931 if (msg->flags & I2C_M_RD) 932 cr1 |= STM32F7_I2C_CR1_RXIE; 933 else 934 cr1 |= STM32F7_I2C_CR1_TXIE; 935 } else { 936 if (msg->flags & I2C_M_RD) 937 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 938 else 939 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 940 } 941 942 /* Configure Start/Repeated Start */ 943 cr2 |= STM32F7_I2C_CR2_START; 944 945 i2c_dev->master_mode = true; 946 947 /* Write configurations registers */ 948 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 949 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 950 } 951 952 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 953 unsigned short flags, u8 command, 954 union i2c_smbus_data *data) 955 { 956 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 957 struct device *dev = i2c_dev->dev; 958 void __iomem *base = i2c_dev->base; 959 u32 cr1, cr2; 960 int i, ret; 961 962 f7_msg->result = 0; 963 reinit_completion(&i2c_dev->complete); 964 965 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 966 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 967 968 /* Set transfer direction */ 969 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 970 if (f7_msg->read_write) 971 cr2 |= STM32F7_I2C_CR2_RD_WRN; 972 973 /* Set slave address */ 974 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 975 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 976 977 f7_msg->smbus_buf[0] = command; 978 switch (f7_msg->size) { 979 case I2C_SMBUS_QUICK: 980 f7_msg->stop = true; 981 f7_msg->count = 0; 982 break; 983 case I2C_SMBUS_BYTE: 984 f7_msg->stop = true; 985 f7_msg->count = 1; 986 break; 987 case I2C_SMBUS_BYTE_DATA: 988 if (f7_msg->read_write) { 989 f7_msg->stop = false; 990 f7_msg->count = 1; 991 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 992 } else { 993 f7_msg->stop = true; 994 f7_msg->count = 2; 995 f7_msg->smbus_buf[1] = data->byte; 996 } 997 break; 998 case I2C_SMBUS_WORD_DATA: 999 if (f7_msg->read_write) { 1000 f7_msg->stop = false; 1001 f7_msg->count = 1; 1002 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1003 } else { 1004 f7_msg->stop = true; 1005 f7_msg->count = 3; 1006 f7_msg->smbus_buf[1] = data->word & 0xff; 1007 f7_msg->smbus_buf[2] = data->word >> 8; 1008 } 1009 break; 1010 case I2C_SMBUS_BLOCK_DATA: 1011 if (f7_msg->read_write) { 1012 f7_msg->stop = false; 1013 f7_msg->count = 1; 1014 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1015 } else { 1016 f7_msg->stop = true; 1017 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 1018 !data->block[0]) { 1019 dev_err(dev, "Invalid block write size %d\n", 1020 data->block[0]); 1021 return -EINVAL; 1022 } 1023 f7_msg->count = data->block[0] + 2; 1024 for (i = 1; i < f7_msg->count; i++) 1025 f7_msg->smbus_buf[i] = data->block[i - 1]; 1026 } 1027 break; 1028 case I2C_SMBUS_PROC_CALL: 1029 f7_msg->stop = false; 1030 f7_msg->count = 3; 1031 f7_msg->smbus_buf[1] = data->word & 0xff; 1032 f7_msg->smbus_buf[2] = data->word >> 8; 1033 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1034 f7_msg->read_write = I2C_SMBUS_READ; 1035 break; 1036 case I2C_SMBUS_BLOCK_PROC_CALL: 1037 f7_msg->stop = false; 1038 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 1039 dev_err(dev, "Invalid block write size %d\n", 1040 data->block[0]); 1041 return -EINVAL; 1042 } 1043 f7_msg->count = data->block[0] + 2; 1044 for (i = 1; i < f7_msg->count; i++) 1045 f7_msg->smbus_buf[i] = data->block[i - 1]; 1046 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1047 f7_msg->read_write = I2C_SMBUS_READ; 1048 break; 1049 case I2C_SMBUS_I2C_BLOCK_DATA: 1050 /* Rely on emulated i2c transfer (through master_xfer) */ 1051 return -EOPNOTSUPP; 1052 default: 1053 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 1054 return -EOPNOTSUPP; 1055 } 1056 1057 f7_msg->buf = f7_msg->smbus_buf; 1058 1059 /* Configure PEC */ 1060 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 1061 cr1 |= STM32F7_I2C_CR1_PECEN; 1062 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1063 if (!f7_msg->read_write) 1064 f7_msg->count++; 1065 } else { 1066 cr1 &= ~STM32F7_I2C_CR1_PECEN; 1067 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 1068 } 1069 1070 /* Set number of bytes to be transferred */ 1071 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 1072 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1073 1074 /* Enable NACK, STOP, error and transfer complete interrupts */ 1075 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 1076 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 1077 1078 /* Clear DMA req and TX/RX interrupt */ 1079 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1080 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1081 1082 /* Configure DMA or enable RX/TX interrupt */ 1083 i2c_dev->use_dma = false; 1084 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 1085 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1086 cr2 & STM32F7_I2C_CR2_RD_WRN, 1087 f7_msg->count, f7_msg->buf, 1088 stm32f7_i2c_dma_callback, 1089 i2c_dev); 1090 if (!ret) 1091 i2c_dev->use_dma = true; 1092 else 1093 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1094 } 1095 1096 if (!i2c_dev->use_dma) { 1097 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1098 cr1 |= STM32F7_I2C_CR1_RXIE; 1099 else 1100 cr1 |= STM32F7_I2C_CR1_TXIE; 1101 } else { 1102 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1103 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1104 else 1105 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1106 } 1107 1108 /* Set Start bit */ 1109 cr2 |= STM32F7_I2C_CR2_START; 1110 1111 i2c_dev->master_mode = true; 1112 1113 /* Write configurations registers */ 1114 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1115 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1116 1117 return 0; 1118 } 1119 1120 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1121 { 1122 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1123 void __iomem *base = i2c_dev->base; 1124 u32 cr1, cr2; 1125 int ret; 1126 1127 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1128 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1129 1130 /* Set transfer direction */ 1131 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1132 1133 switch (f7_msg->size) { 1134 case I2C_SMBUS_BYTE_DATA: 1135 f7_msg->count = 1; 1136 break; 1137 case I2C_SMBUS_WORD_DATA: 1138 case I2C_SMBUS_PROC_CALL: 1139 f7_msg->count = 2; 1140 break; 1141 case I2C_SMBUS_BLOCK_DATA: 1142 case I2C_SMBUS_BLOCK_PROC_CALL: 1143 f7_msg->count = 1; 1144 cr2 |= STM32F7_I2C_CR2_RELOAD; 1145 break; 1146 } 1147 1148 f7_msg->buf = f7_msg->smbus_buf; 1149 f7_msg->stop = true; 1150 1151 /* Add one byte for PEC if needed */ 1152 if (cr1 & STM32F7_I2C_CR1_PECEN) 1153 f7_msg->count++; 1154 1155 /* Set number of bytes to be transferred */ 1156 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1157 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1158 1159 /* 1160 * Configure RX/TX interrupt: 1161 */ 1162 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1163 cr1 |= STM32F7_I2C_CR1_RXIE; 1164 1165 /* 1166 * Configure DMA or enable RX/TX interrupt: 1167 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1168 * dma as we don't know in advance how many data will be received 1169 */ 1170 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1171 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1172 1173 i2c_dev->use_dma = false; 1174 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1175 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1176 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1177 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1178 cr2 & STM32F7_I2C_CR2_RD_WRN, 1179 f7_msg->count, f7_msg->buf, 1180 stm32f7_i2c_dma_callback, 1181 i2c_dev); 1182 1183 if (!ret) 1184 i2c_dev->use_dma = true; 1185 else 1186 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1187 } 1188 1189 if (!i2c_dev->use_dma) 1190 cr1 |= STM32F7_I2C_CR1_RXIE; 1191 else 1192 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1193 1194 /* Configure Repeated Start */ 1195 cr2 |= STM32F7_I2C_CR2_START; 1196 1197 /* Write configurations registers */ 1198 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1199 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1200 } 1201 1202 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1203 { 1204 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1205 u8 count, internal_pec, received_pec; 1206 1207 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1208 1209 switch (f7_msg->size) { 1210 case I2C_SMBUS_BYTE: 1211 case I2C_SMBUS_BYTE_DATA: 1212 received_pec = f7_msg->smbus_buf[1]; 1213 break; 1214 case I2C_SMBUS_WORD_DATA: 1215 case I2C_SMBUS_PROC_CALL: 1216 received_pec = f7_msg->smbus_buf[2]; 1217 break; 1218 case I2C_SMBUS_BLOCK_DATA: 1219 case I2C_SMBUS_BLOCK_PROC_CALL: 1220 count = f7_msg->smbus_buf[0]; 1221 received_pec = f7_msg->smbus_buf[count]; 1222 break; 1223 default: 1224 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1225 return -EINVAL; 1226 } 1227 1228 if (internal_pec != received_pec) { 1229 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1230 internal_pec, received_pec); 1231 return -EBADMSG; 1232 } 1233 1234 return 0; 1235 } 1236 1237 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1238 { 1239 u32 addr; 1240 1241 if (!slave) 1242 return false; 1243 1244 if (slave->flags & I2C_CLIENT_TEN) { 1245 /* 1246 * For 10-bit addr, addcode = 11110XY with 1247 * X = Bit 9 of slave address 1248 * Y = Bit 8 of slave address 1249 */ 1250 addr = slave->addr >> 8; 1251 addr |= 0x78; 1252 if (addr == addcode) 1253 return true; 1254 } else { 1255 addr = slave->addr & 0x7f; 1256 if (addr == addcode) 1257 return true; 1258 } 1259 1260 return false; 1261 } 1262 1263 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1264 { 1265 struct i2c_client *slave = i2c_dev->slave_running; 1266 void __iomem *base = i2c_dev->base; 1267 u32 mask; 1268 u8 value = 0; 1269 1270 if (i2c_dev->slave_dir) { 1271 /* Notify i2c slave that new read transfer is starting */ 1272 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1273 1274 /* 1275 * Disable slave TX config in case of I2C combined message 1276 * (I2C Write followed by I2C Read) 1277 */ 1278 mask = STM32F7_I2C_CR2_RELOAD; 1279 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1280 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1281 STM32F7_I2C_CR1_TCIE; 1282 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1283 1284 /* Enable TX empty, STOP, NACK interrupts */ 1285 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1286 STM32F7_I2C_CR1_TXIE; 1287 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1288 1289 /* Write 1st data byte */ 1290 writel_relaxed(value, base + STM32F7_I2C_TXDR); 1291 } else { 1292 /* Notify i2c slave that new write transfer is starting */ 1293 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1294 1295 /* Set reload mode to be able to ACK/NACK each received byte */ 1296 mask = STM32F7_I2C_CR2_RELOAD; 1297 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1298 1299 /* 1300 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1301 * Set Slave Byte Control to be able to ACK/NACK each data 1302 * byte received 1303 */ 1304 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1305 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1306 STM32F7_I2C_CR1_TCIE; 1307 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1308 } 1309 } 1310 1311 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1312 { 1313 void __iomem *base = i2c_dev->base; 1314 u32 isr, addcode, dir, mask; 1315 int i; 1316 1317 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1318 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1319 dir = isr & STM32F7_I2C_ISR_DIR; 1320 1321 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1322 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1323 i2c_dev->slave_running = i2c_dev->slave[i]; 1324 i2c_dev->slave_dir = dir; 1325 1326 /* Start I2C slave processing */ 1327 stm32f7_i2c_slave_start(i2c_dev); 1328 1329 /* Clear ADDR flag */ 1330 mask = STM32F7_I2C_ICR_ADDRCF; 1331 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1332 break; 1333 } 1334 } 1335 } 1336 1337 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1338 struct i2c_client *slave, int *id) 1339 { 1340 int i; 1341 1342 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1343 if (i2c_dev->slave[i] == slave) { 1344 *id = i; 1345 return 0; 1346 } 1347 } 1348 1349 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1350 1351 return -ENODEV; 1352 } 1353 1354 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1355 struct i2c_client *slave, int *id) 1356 { 1357 struct device *dev = i2c_dev->dev; 1358 int i; 1359 1360 /* 1361 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8) 1362 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address 1363 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only 1364 */ 1365 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { 1366 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) 1367 goto fail; 1368 *id = STM32F7_SLAVE_HOSTNOTIFY; 1369 return 0; 1370 } 1371 1372 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { 1373 if ((i == STM32F7_SLAVE_7_BITS_ADDR) && 1374 (slave->flags & I2C_CLIENT_TEN)) 1375 continue; 1376 if (!i2c_dev->slave[i]) { 1377 *id = i; 1378 return 0; 1379 } 1380 } 1381 1382 fail: 1383 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1384 1385 return -EINVAL; 1386 } 1387 1388 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1389 { 1390 int i; 1391 1392 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1393 if (i2c_dev->slave[i]) 1394 return true; 1395 } 1396 1397 return false; 1398 } 1399 1400 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1401 { 1402 int i, busy; 1403 1404 busy = 0; 1405 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1406 if (i2c_dev->slave[i]) 1407 busy++; 1408 } 1409 1410 return i == busy; 1411 } 1412 1413 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev) 1414 { 1415 void __iomem *base = i2c_dev->base; 1416 u32 cr2, status, mask; 1417 u8 val; 1418 int ret; 1419 1420 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1421 1422 /* Slave transmitter mode */ 1423 if (status & STM32F7_I2C_ISR_TXIS) { 1424 i2c_slave_event(i2c_dev->slave_running, 1425 I2C_SLAVE_READ_PROCESSED, 1426 &val); 1427 1428 /* Write data byte */ 1429 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1430 } 1431 1432 /* Transfer Complete Reload for Slave receiver mode */ 1433 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1434 /* 1435 * Read data byte then set NBYTES to receive next byte or NACK 1436 * the current received byte 1437 */ 1438 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1439 ret = i2c_slave_event(i2c_dev->slave_running, 1440 I2C_SLAVE_WRITE_RECEIVED, 1441 &val); 1442 if (!ret) { 1443 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1444 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1445 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1446 } else { 1447 mask = STM32F7_I2C_CR2_NACK; 1448 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1449 } 1450 } 1451 1452 /* NACK received */ 1453 if (status & STM32F7_I2C_ISR_NACKF) { 1454 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1455 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1456 } 1457 1458 /* STOP received */ 1459 if (status & STM32F7_I2C_ISR_STOPF) { 1460 /* Disable interrupts */ 1461 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1462 1463 if (i2c_dev->slave_dir) { 1464 /* 1465 * Flush TX buffer in order to not used the byte in 1466 * TXDR for the next transfer 1467 */ 1468 mask = STM32F7_I2C_ISR_TXE; 1469 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1470 } 1471 1472 /* Clear STOP flag */ 1473 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1474 1475 /* Notify i2c slave that a STOP flag has been detected */ 1476 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1477 1478 i2c_dev->slave_running = NULL; 1479 } 1480 1481 /* Address match received */ 1482 if (status & STM32F7_I2C_ISR_ADDR) 1483 stm32f7_i2c_slave_addr(i2c_dev); 1484 1485 return IRQ_HANDLED; 1486 } 1487 1488 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1489 { 1490 struct stm32f7_i2c_dev *i2c_dev = data; 1491 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1492 struct stm32_i2c_dma *dma = i2c_dev->dma; 1493 void __iomem *base = i2c_dev->base; 1494 u32 status, mask; 1495 int ret = IRQ_HANDLED; 1496 1497 /* Check if the interrupt if for a slave device */ 1498 if (!i2c_dev->master_mode) { 1499 ret = stm32f7_i2c_slave_isr_event(i2c_dev); 1500 return ret; 1501 } 1502 1503 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1504 1505 /* Tx empty */ 1506 if (status & STM32F7_I2C_ISR_TXIS) 1507 stm32f7_i2c_write_tx_data(i2c_dev); 1508 1509 /* RX not empty */ 1510 if (status & STM32F7_I2C_ISR_RXNE) 1511 stm32f7_i2c_read_rx_data(i2c_dev); 1512 1513 /* NACK received */ 1514 if (status & STM32F7_I2C_ISR_NACKF) { 1515 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", 1516 __func__, f7_msg->addr); 1517 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1518 if (i2c_dev->use_dma) { 1519 stm32f7_i2c_disable_dma_req(i2c_dev); 1520 dmaengine_terminate_async(dma->chan_using); 1521 } 1522 f7_msg->result = -ENXIO; 1523 } 1524 1525 /* STOP detection flag */ 1526 if (status & STM32F7_I2C_ISR_STOPF) { 1527 /* Disable interrupts */ 1528 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1529 mask = STM32F7_I2C_XFER_IRQ_MASK; 1530 else 1531 mask = STM32F7_I2C_ALL_IRQ_MASK; 1532 stm32f7_i2c_disable_irq(i2c_dev, mask); 1533 1534 /* Clear STOP flag */ 1535 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1536 1537 if (i2c_dev->use_dma && !f7_msg->result) { 1538 ret = IRQ_WAKE_THREAD; 1539 } else { 1540 i2c_dev->master_mode = false; 1541 complete(&i2c_dev->complete); 1542 } 1543 } 1544 1545 /* Transfer complete */ 1546 if (status & STM32F7_I2C_ISR_TC) { 1547 if (f7_msg->stop) { 1548 mask = STM32F7_I2C_CR2_STOP; 1549 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1550 } else if (i2c_dev->use_dma && !f7_msg->result) { 1551 ret = IRQ_WAKE_THREAD; 1552 } else if (f7_msg->smbus) { 1553 stm32f7_i2c_smbus_rep_start(i2c_dev); 1554 } else { 1555 i2c_dev->msg_id++; 1556 i2c_dev->msg++; 1557 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1558 } 1559 } 1560 1561 if (status & STM32F7_I2C_ISR_TCR) { 1562 if (f7_msg->smbus) 1563 stm32f7_i2c_smbus_reload(i2c_dev); 1564 else 1565 stm32f7_i2c_reload(i2c_dev); 1566 } 1567 1568 return ret; 1569 } 1570 1571 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1572 { 1573 struct stm32f7_i2c_dev *i2c_dev = data; 1574 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1575 struct stm32_i2c_dma *dma = i2c_dev->dma; 1576 u32 status; 1577 int ret; 1578 1579 /* 1580 * Wait for dma transfer completion before sending next message or 1581 * notity the end of xfer to the client 1582 */ 1583 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1584 if (!ret) { 1585 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1586 stm32f7_i2c_disable_dma_req(i2c_dev); 1587 dmaengine_terminate_async(dma->chan_using); 1588 f7_msg->result = -ETIMEDOUT; 1589 } 1590 1591 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1592 1593 if (status & STM32F7_I2C_ISR_TC) { 1594 if (f7_msg->smbus) { 1595 stm32f7_i2c_smbus_rep_start(i2c_dev); 1596 } else { 1597 i2c_dev->msg_id++; 1598 i2c_dev->msg++; 1599 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1600 } 1601 } else { 1602 i2c_dev->master_mode = false; 1603 complete(&i2c_dev->complete); 1604 } 1605 1606 return IRQ_HANDLED; 1607 } 1608 1609 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data) 1610 { 1611 struct stm32f7_i2c_dev *i2c_dev = data; 1612 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1613 void __iomem *base = i2c_dev->base; 1614 struct device *dev = i2c_dev->dev; 1615 struct stm32_i2c_dma *dma = i2c_dev->dma; 1616 u32 status; 1617 1618 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1619 1620 /* Bus error */ 1621 if (status & STM32F7_I2C_ISR_BERR) { 1622 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n", 1623 __func__, f7_msg->addr); 1624 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1625 stm32f7_i2c_release_bus(&i2c_dev->adap); 1626 f7_msg->result = -EIO; 1627 } 1628 1629 /* Arbitration loss */ 1630 if (status & STM32F7_I2C_ISR_ARLO) { 1631 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n", 1632 __func__, f7_msg->addr); 1633 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1634 f7_msg->result = -EAGAIN; 1635 } 1636 1637 if (status & STM32F7_I2C_ISR_PECERR) { 1638 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n", 1639 __func__, f7_msg->addr); 1640 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1641 f7_msg->result = -EINVAL; 1642 } 1643 1644 if (status & STM32F7_I2C_ISR_ALERT) { 1645 dev_dbg(dev, "<%s>: SMBus alert received\n", __func__); 1646 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR); 1647 i2c_handle_smbus_alert(i2c_dev->alert->ara); 1648 return IRQ_HANDLED; 1649 } 1650 1651 if (!i2c_dev->slave_running) { 1652 u32 mask; 1653 /* Disable interrupts */ 1654 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1655 mask = STM32F7_I2C_XFER_IRQ_MASK; 1656 else 1657 mask = STM32F7_I2C_ALL_IRQ_MASK; 1658 stm32f7_i2c_disable_irq(i2c_dev, mask); 1659 } 1660 1661 /* Disable dma */ 1662 if (i2c_dev->use_dma) { 1663 stm32f7_i2c_disable_dma_req(i2c_dev); 1664 dmaengine_terminate_async(dma->chan_using); 1665 } 1666 1667 i2c_dev->master_mode = false; 1668 complete(&i2c_dev->complete); 1669 1670 return IRQ_HANDLED; 1671 } 1672 1673 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1674 struct i2c_msg msgs[], int num) 1675 { 1676 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1677 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1678 struct stm32_i2c_dma *dma = i2c_dev->dma; 1679 unsigned long time_left; 1680 int ret; 1681 1682 i2c_dev->msg = msgs; 1683 i2c_dev->msg_num = num; 1684 i2c_dev->msg_id = 0; 1685 f7_msg->smbus = false; 1686 1687 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1688 if (ret < 0) 1689 return ret; 1690 1691 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1692 if (ret) 1693 goto pm_free; 1694 1695 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1696 1697 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1698 i2c_dev->adap.timeout); 1699 ret = f7_msg->result; 1700 if (ret) { 1701 if (i2c_dev->use_dma) 1702 dmaengine_synchronize(dma->chan_using); 1703 1704 /* 1705 * It is possible that some unsent data have already been 1706 * written into TXDR. To avoid sending old data in a 1707 * further transfer, flush TXDR in case of any error 1708 */ 1709 writel_relaxed(STM32F7_I2C_ISR_TXE, 1710 i2c_dev->base + STM32F7_I2C_ISR); 1711 goto pm_free; 1712 } 1713 1714 if (!time_left) { 1715 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1716 i2c_dev->msg->addr); 1717 if (i2c_dev->use_dma) 1718 dmaengine_terminate_sync(dma->chan_using); 1719 stm32f7_i2c_wait_free_bus(i2c_dev); 1720 ret = -ETIMEDOUT; 1721 } 1722 1723 pm_free: 1724 pm_runtime_mark_last_busy(i2c_dev->dev); 1725 pm_runtime_put_autosuspend(i2c_dev->dev); 1726 1727 return (ret < 0) ? ret : num; 1728 } 1729 1730 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1731 unsigned short flags, char read_write, 1732 u8 command, int size, 1733 union i2c_smbus_data *data) 1734 { 1735 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1736 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1737 struct stm32_i2c_dma *dma = i2c_dev->dma; 1738 struct device *dev = i2c_dev->dev; 1739 unsigned long timeout; 1740 int i, ret; 1741 1742 f7_msg->addr = addr; 1743 f7_msg->size = size; 1744 f7_msg->read_write = read_write; 1745 f7_msg->smbus = true; 1746 1747 ret = pm_runtime_resume_and_get(dev); 1748 if (ret < 0) 1749 return ret; 1750 1751 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1752 if (ret) 1753 goto pm_free; 1754 1755 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1756 if (ret) 1757 goto pm_free; 1758 1759 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1760 i2c_dev->adap.timeout); 1761 ret = f7_msg->result; 1762 if (ret) { 1763 if (i2c_dev->use_dma) 1764 dmaengine_synchronize(dma->chan_using); 1765 1766 /* 1767 * It is possible that some unsent data have already been 1768 * written into TXDR. To avoid sending old data in a 1769 * further transfer, flush TXDR in case of any error 1770 */ 1771 writel_relaxed(STM32F7_I2C_ISR_TXE, 1772 i2c_dev->base + STM32F7_I2C_ISR); 1773 goto pm_free; 1774 } 1775 1776 if (!timeout) { 1777 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1778 if (i2c_dev->use_dma) 1779 dmaengine_terminate_sync(dma->chan_using); 1780 stm32f7_i2c_wait_free_bus(i2c_dev); 1781 ret = -ETIMEDOUT; 1782 goto pm_free; 1783 } 1784 1785 /* Check PEC */ 1786 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1787 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1788 if (ret) 1789 goto pm_free; 1790 } 1791 1792 if (read_write && size != I2C_SMBUS_QUICK) { 1793 switch (size) { 1794 case I2C_SMBUS_BYTE: 1795 case I2C_SMBUS_BYTE_DATA: 1796 data->byte = f7_msg->smbus_buf[0]; 1797 break; 1798 case I2C_SMBUS_WORD_DATA: 1799 case I2C_SMBUS_PROC_CALL: 1800 data->word = f7_msg->smbus_buf[0] | 1801 (f7_msg->smbus_buf[1] << 8); 1802 break; 1803 case I2C_SMBUS_BLOCK_DATA: 1804 case I2C_SMBUS_BLOCK_PROC_CALL: 1805 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1806 data->block[i] = f7_msg->smbus_buf[i]; 1807 break; 1808 default: 1809 dev_err(dev, "Unsupported smbus transaction\n"); 1810 ret = -EINVAL; 1811 } 1812 } 1813 1814 pm_free: 1815 pm_runtime_mark_last_busy(dev); 1816 pm_runtime_put_autosuspend(dev); 1817 return ret; 1818 } 1819 1820 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, 1821 bool enable) 1822 { 1823 void __iomem *base = i2c_dev->base; 1824 u32 mask = STM32F7_I2C_CR1_WUPEN; 1825 1826 if (!i2c_dev->wakeup_src) 1827 return; 1828 1829 if (enable) { 1830 device_set_wakeup_enable(i2c_dev->dev, true); 1831 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1832 } else { 1833 device_set_wakeup_enable(i2c_dev->dev, false); 1834 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1835 } 1836 } 1837 1838 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1839 { 1840 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1841 void __iomem *base = i2c_dev->base; 1842 struct device *dev = i2c_dev->dev; 1843 u32 oar1, oar2, mask; 1844 int id, ret; 1845 1846 if (slave->flags & I2C_CLIENT_PEC) { 1847 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1848 return -EINVAL; 1849 } 1850 1851 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1852 dev_err(dev, "Too much slave registered\n"); 1853 return -EBUSY; 1854 } 1855 1856 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1857 if (ret) 1858 return ret; 1859 1860 ret = pm_runtime_resume_and_get(dev); 1861 if (ret < 0) 1862 return ret; 1863 1864 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1865 stm32f7_i2c_enable_wakeup(i2c_dev, true); 1866 1867 switch (id) { 1868 case 0: 1869 /* Slave SMBus Host */ 1870 i2c_dev->slave[id] = slave; 1871 break; 1872 1873 case 1: 1874 /* Configure Own Address 1 */ 1875 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1876 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1877 if (slave->flags & I2C_CLIENT_TEN) { 1878 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1879 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1880 } else { 1881 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1882 } 1883 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1884 i2c_dev->slave[id] = slave; 1885 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1886 break; 1887 1888 case 2: 1889 /* Configure Own Address 2 */ 1890 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1891 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1892 if (slave->flags & I2C_CLIENT_TEN) { 1893 ret = -EOPNOTSUPP; 1894 goto pm_free; 1895 } 1896 1897 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1898 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1899 i2c_dev->slave[id] = slave; 1900 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1901 break; 1902 1903 default: 1904 dev_err(dev, "I2C slave id not supported\n"); 1905 ret = -ENODEV; 1906 goto pm_free; 1907 } 1908 1909 /* Enable ACK */ 1910 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1911 1912 /* Enable Address match interrupt, error interrupt and enable I2C */ 1913 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1914 STM32F7_I2C_CR1_PE; 1915 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1916 1917 ret = 0; 1918 pm_free: 1919 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1920 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1921 1922 pm_runtime_mark_last_busy(dev); 1923 pm_runtime_put_autosuspend(dev); 1924 1925 return ret; 1926 } 1927 1928 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1929 { 1930 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1931 void __iomem *base = i2c_dev->base; 1932 u32 mask; 1933 int id, ret; 1934 1935 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1936 if (ret) 1937 return ret; 1938 1939 WARN_ON(!i2c_dev->slave[id]); 1940 1941 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1942 if (ret < 0) 1943 return ret; 1944 1945 if (id == 1) { 1946 mask = STM32F7_I2C_OAR1_OA1EN; 1947 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1948 } else if (id == 2) { 1949 mask = STM32F7_I2C_OAR2_OA2EN; 1950 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1951 } 1952 1953 i2c_dev->slave[id] = NULL; 1954 1955 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 1956 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1957 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1958 } 1959 1960 pm_runtime_mark_last_busy(i2c_dev->dev); 1961 pm_runtime_put_autosuspend(i2c_dev->dev); 1962 1963 return 0; 1964 } 1965 1966 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, 1967 bool enable) 1968 { 1969 int ret; 1970 1971 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || 1972 IS_ERR_OR_NULL(i2c_dev->regmap)) 1973 /* Optional */ 1974 return 0; 1975 1976 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) 1977 ret = regmap_update_bits(i2c_dev->regmap, 1978 i2c_dev->fmp_sreg, 1979 i2c_dev->fmp_mask, 1980 enable ? i2c_dev->fmp_mask : 0); 1981 else 1982 ret = regmap_write(i2c_dev->regmap, 1983 enable ? i2c_dev->fmp_sreg : 1984 i2c_dev->fmp_creg, 1985 i2c_dev->fmp_mask); 1986 1987 return ret; 1988 } 1989 1990 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 1991 struct stm32f7_i2c_dev *i2c_dev) 1992 { 1993 struct device_node *np = pdev->dev.of_node; 1994 int ret; 1995 1996 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 1997 if (IS_ERR(i2c_dev->regmap)) 1998 /* Optional */ 1999 return 0; 2000 2001 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, 2002 &i2c_dev->fmp_sreg); 2003 if (ret) 2004 return ret; 2005 2006 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + 2007 i2c_dev->setup.fmp_clr_offset; 2008 2009 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, 2010 &i2c_dev->fmp_mask); 2011 } 2012 2013 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2014 { 2015 struct i2c_adapter *adap = &i2c_dev->adap; 2016 void __iomem *base = i2c_dev->base; 2017 struct i2c_client *client; 2018 2019 client = i2c_new_slave_host_notify_device(adap); 2020 if (IS_ERR(client)) 2021 return PTR_ERR(client); 2022 2023 i2c_dev->host_notify_client = client; 2024 2025 /* Enable SMBus Host address */ 2026 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN); 2027 2028 return 0; 2029 } 2030 2031 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2032 { 2033 void __iomem *base = i2c_dev->base; 2034 2035 if (i2c_dev->host_notify_client) { 2036 /* Disable SMBus Host address */ 2037 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2038 STM32F7_I2C_CR1_SMBHEN); 2039 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); 2040 } 2041 } 2042 2043 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2044 { 2045 struct stm32f7_i2c_alert *alert; 2046 struct i2c_adapter *adap = &i2c_dev->adap; 2047 struct device *dev = i2c_dev->dev; 2048 void __iomem *base = i2c_dev->base; 2049 2050 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL); 2051 if (!alert) 2052 return -ENOMEM; 2053 2054 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); 2055 if (IS_ERR(alert->ara)) 2056 return PTR_ERR(alert->ara); 2057 2058 i2c_dev->alert = alert; 2059 2060 /* Enable SMBus Alert */ 2061 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN); 2062 2063 return 0; 2064 } 2065 2066 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2067 { 2068 struct stm32f7_i2c_alert *alert = i2c_dev->alert; 2069 void __iomem *base = i2c_dev->base; 2070 2071 if (alert) { 2072 /* Disable SMBus Alert */ 2073 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2074 STM32F7_I2C_CR1_ALERTEN); 2075 i2c_unregister_device(alert->ara); 2076 } 2077 } 2078 2079 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 2080 { 2081 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 2082 2083 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 2084 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 2085 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 2086 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 2087 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 2088 I2C_FUNC_SMBUS_I2C_BLOCK; 2089 2090 if (i2c_dev->smbus_mode) 2091 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 2092 2093 return func; 2094 } 2095 2096 static const struct i2c_algorithm stm32f7_i2c_algo = { 2097 .master_xfer = stm32f7_i2c_xfer, 2098 .smbus_xfer = stm32f7_i2c_smbus_xfer, 2099 .functionality = stm32f7_i2c_func, 2100 .reg_slave = stm32f7_i2c_reg_slave, 2101 .unreg_slave = stm32f7_i2c_unreg_slave, 2102 }; 2103 2104 static int stm32f7_i2c_probe(struct platform_device *pdev) 2105 { 2106 struct stm32f7_i2c_dev *i2c_dev; 2107 const struct stm32f7_i2c_setup *setup; 2108 struct resource *res; 2109 struct i2c_adapter *adap; 2110 struct reset_control *rst; 2111 dma_addr_t phy_addr; 2112 int irq_error, irq_event, ret; 2113 2114 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 2115 if (!i2c_dev) 2116 return -ENOMEM; 2117 2118 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2119 if (IS_ERR(i2c_dev->base)) 2120 return PTR_ERR(i2c_dev->base); 2121 phy_addr = (dma_addr_t)res->start; 2122 2123 irq_event = platform_get_irq(pdev, 0); 2124 if (irq_event <= 0) 2125 return irq_event ? : -ENOENT; 2126 2127 irq_error = platform_get_irq(pdev, 1); 2128 if (irq_error <= 0) 2129 return irq_error ? : -ENOENT; 2130 2131 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, 2132 "wakeup-source"); 2133 2134 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 2135 if (IS_ERR(i2c_dev->clk)) 2136 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), 2137 "Failed to get controller clock\n"); 2138 2139 ret = clk_prepare_enable(i2c_dev->clk); 2140 if (ret) { 2141 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); 2142 return ret; 2143 } 2144 2145 rst = devm_reset_control_get(&pdev->dev, NULL); 2146 if (IS_ERR(rst)) { 2147 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), 2148 "Error: Missing reset ctrl\n"); 2149 goto clk_free; 2150 } 2151 reset_control_assert(rst); 2152 udelay(2); 2153 reset_control_deassert(rst); 2154 2155 i2c_dev->dev = &pdev->dev; 2156 2157 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 2158 stm32f7_i2c_isr_event, 2159 stm32f7_i2c_isr_event_thread, 2160 IRQF_ONESHOT, 2161 pdev->name, i2c_dev); 2162 if (ret) { 2163 dev_err(&pdev->dev, "Failed to request irq event %i\n", 2164 irq_event); 2165 goto clk_free; 2166 } 2167 2168 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, 2169 pdev->name, i2c_dev); 2170 if (ret) { 2171 dev_err(&pdev->dev, "Failed to request irq error %i\n", 2172 irq_error); 2173 goto clk_free; 2174 } 2175 2176 setup = of_device_get_match_data(&pdev->dev); 2177 if (!setup) { 2178 dev_err(&pdev->dev, "Can't get device data\n"); 2179 ret = -ENODEV; 2180 goto clk_free; 2181 } 2182 i2c_dev->setup = *setup; 2183 2184 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 2185 if (ret) 2186 goto clk_free; 2187 2188 /* Setup Fast mode plus if necessary */ 2189 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { 2190 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 2191 if (ret) 2192 goto clk_free; 2193 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2194 if (ret) 2195 goto clk_free; 2196 } 2197 2198 adap = &i2c_dev->adap; 2199 i2c_set_adapdata(adap, i2c_dev); 2200 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 2201 &res->start); 2202 adap->owner = THIS_MODULE; 2203 adap->timeout = 2 * HZ; 2204 adap->retries = 3; 2205 adap->algo = &stm32f7_i2c_algo; 2206 adap->dev.parent = &pdev->dev; 2207 adap->dev.of_node = pdev->dev.of_node; 2208 2209 init_completion(&i2c_dev->complete); 2210 2211 /* Init DMA config if supported */ 2212 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 2213 STM32F7_I2C_TXDR, 2214 STM32F7_I2C_RXDR); 2215 if (IS_ERR(i2c_dev->dma)) { 2216 ret = PTR_ERR(i2c_dev->dma); 2217 /* DMA support is optional, only report other errors */ 2218 if (ret != -ENODEV) 2219 goto fmp_clear; 2220 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); 2221 i2c_dev->dma = NULL; 2222 } 2223 2224 if (i2c_dev->wakeup_src) { 2225 device_set_wakeup_capable(i2c_dev->dev, true); 2226 2227 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); 2228 if (ret) { 2229 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); 2230 goto clr_wakeup_capable; 2231 } 2232 } 2233 2234 platform_set_drvdata(pdev, i2c_dev); 2235 2236 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 2237 STM32F7_AUTOSUSPEND_DELAY); 2238 pm_runtime_use_autosuspend(i2c_dev->dev); 2239 pm_runtime_set_active(i2c_dev->dev); 2240 pm_runtime_enable(i2c_dev->dev); 2241 2242 pm_runtime_get_noresume(&pdev->dev); 2243 2244 stm32f7_i2c_hw_config(i2c_dev); 2245 2246 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); 2247 2248 ret = i2c_add_adapter(adap); 2249 if (ret) 2250 goto pm_disable; 2251 2252 if (i2c_dev->smbus_mode) { 2253 ret = stm32f7_i2c_enable_smbus_host(i2c_dev); 2254 if (ret) { 2255 dev_err(i2c_dev->dev, 2256 "failed to enable SMBus Host-Notify protocol (%d)\n", 2257 ret); 2258 goto i2c_adapter_remove; 2259 } 2260 } 2261 2262 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { 2263 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev); 2264 if (ret) { 2265 dev_err(i2c_dev->dev, 2266 "failed to enable SMBus alert protocol (%d)\n", 2267 ret); 2268 goto i2c_disable_smbus_host; 2269 } 2270 } 2271 2272 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2273 2274 pm_runtime_mark_last_busy(i2c_dev->dev); 2275 pm_runtime_put_autosuspend(i2c_dev->dev); 2276 2277 return 0; 2278 2279 i2c_disable_smbus_host: 2280 stm32f7_i2c_disable_smbus_host(i2c_dev); 2281 2282 i2c_adapter_remove: 2283 i2c_del_adapter(adap); 2284 2285 pm_disable: 2286 pm_runtime_put_noidle(i2c_dev->dev); 2287 pm_runtime_disable(i2c_dev->dev); 2288 pm_runtime_set_suspended(i2c_dev->dev); 2289 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2290 2291 if (i2c_dev->wakeup_src) 2292 dev_pm_clear_wake_irq(i2c_dev->dev); 2293 2294 clr_wakeup_capable: 2295 if (i2c_dev->wakeup_src) 2296 device_set_wakeup_capable(i2c_dev->dev, false); 2297 2298 if (i2c_dev->dma) { 2299 stm32_i2c_dma_free(i2c_dev->dma); 2300 i2c_dev->dma = NULL; 2301 } 2302 2303 fmp_clear: 2304 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2305 2306 clk_free: 2307 clk_disable_unprepare(i2c_dev->clk); 2308 2309 return ret; 2310 } 2311 2312 static void stm32f7_i2c_remove(struct platform_device *pdev) 2313 { 2314 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2315 2316 stm32f7_i2c_disable_smbus_alert(i2c_dev); 2317 stm32f7_i2c_disable_smbus_host(i2c_dev); 2318 2319 i2c_del_adapter(&i2c_dev->adap); 2320 pm_runtime_get_sync(i2c_dev->dev); 2321 2322 if (i2c_dev->wakeup_src) { 2323 dev_pm_clear_wake_irq(i2c_dev->dev); 2324 /* 2325 * enforce that wakeup is disabled and that the device 2326 * is marked as non wakeup capable 2327 */ 2328 device_init_wakeup(i2c_dev->dev, false); 2329 } 2330 2331 pm_runtime_put_noidle(i2c_dev->dev); 2332 pm_runtime_disable(i2c_dev->dev); 2333 pm_runtime_set_suspended(i2c_dev->dev); 2334 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2335 2336 if (i2c_dev->dma) { 2337 stm32_i2c_dma_free(i2c_dev->dma); 2338 i2c_dev->dma = NULL; 2339 } 2340 2341 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2342 2343 clk_disable_unprepare(i2c_dev->clk); 2344 } 2345 2346 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev) 2347 { 2348 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2349 2350 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2351 clk_disable_unprepare(i2c_dev->clk); 2352 2353 return 0; 2354 } 2355 2356 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev) 2357 { 2358 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2359 int ret; 2360 2361 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2362 ret = clk_prepare_enable(i2c_dev->clk); 2363 if (ret) { 2364 dev_err(dev, "failed to prepare_enable clock\n"); 2365 return ret; 2366 } 2367 } 2368 2369 return 0; 2370 } 2371 2372 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2373 { 2374 int ret; 2375 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2376 2377 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2378 if (ret < 0) 2379 return ret; 2380 2381 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2382 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 2383 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 2384 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 2385 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); 2386 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2387 2388 pm_runtime_put_sync(i2c_dev->dev); 2389 2390 return ret; 2391 } 2392 2393 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2394 { 2395 u32 cr1; 2396 int ret; 2397 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2398 2399 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2400 if (ret < 0) 2401 return ret; 2402 2403 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2404 if (cr1 & STM32F7_I2C_CR1_PE) 2405 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 2406 STM32F7_I2C_CR1_PE); 2407 2408 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); 2409 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, 2410 i2c_dev->base + STM32F7_I2C_CR1); 2411 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) 2412 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 2413 STM32F7_I2C_CR1_PE); 2414 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); 2415 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); 2416 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); 2417 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2418 2419 pm_runtime_put_sync(i2c_dev->dev); 2420 2421 return ret; 2422 } 2423 2424 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev) 2425 { 2426 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2427 int ret; 2428 2429 i2c_mark_adapter_suspended(&i2c_dev->adap); 2430 2431 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2432 ret = stm32f7_i2c_regs_backup(i2c_dev); 2433 if (ret < 0) { 2434 i2c_mark_adapter_resumed(&i2c_dev->adap); 2435 return ret; 2436 } 2437 2438 pinctrl_pm_select_sleep_state(dev); 2439 pm_runtime_force_suspend(dev); 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int __maybe_unused stm32f7_i2c_resume(struct device *dev) 2446 { 2447 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2448 int ret; 2449 2450 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2451 ret = pm_runtime_force_resume(dev); 2452 if (ret < 0) 2453 return ret; 2454 pinctrl_pm_select_default_state(dev); 2455 2456 ret = stm32f7_i2c_regs_restore(i2c_dev); 2457 if (ret < 0) 2458 return ret; 2459 } 2460 2461 i2c_mark_adapter_resumed(&i2c_dev->adap); 2462 2463 return 0; 2464 } 2465 2466 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2467 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2468 stm32f7_i2c_runtime_resume, NULL) 2469 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume) 2470 }; 2471 2472 static const struct of_device_id stm32f7_i2c_match[] = { 2473 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2474 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup}, 2475 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup}, 2476 {}, 2477 }; 2478 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2479 2480 static struct platform_driver stm32f7_i2c_driver = { 2481 .driver = { 2482 .name = "stm32f7-i2c", 2483 .of_match_table = stm32f7_i2c_match, 2484 .pm = &stm32f7_i2c_pm_ops, 2485 }, 2486 .probe = stm32f7_i2c_probe, 2487 .remove_new = stm32f7_i2c_remove, 2488 }; 2489 2490 module_platform_driver(stm32f7_i2c_driver); 2491 2492 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2493 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2494 MODULE_LICENSE("GPL v2"); 2495