1 /* 2 * Driver for STMicroelectronics STM32F7 I2C controller 3 * 4 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 5 * reference manual. 6 * Please see below a link to the documentation: 7 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 8 * 9 * Copyright (C) M'boumba Cedric Madianga 2017 10 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 11 * 12 * This driver is based on i2c-stm32f4.c 13 * 14 * License terms: GNU General Public License (GPL), version 2 15 */ 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/i2c.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/reset.h> 30 #include <linux/slab.h> 31 32 #include "i2c-stm32.h" 33 34 /* STM32F7 I2C registers */ 35 #define STM32F7_I2C_CR1 0x00 36 #define STM32F7_I2C_CR2 0x04 37 #define STM32F7_I2C_TIMINGR 0x10 38 #define STM32F7_I2C_ISR 0x18 39 #define STM32F7_I2C_ICR 0x1C 40 #define STM32F7_I2C_RXDR 0x24 41 #define STM32F7_I2C_TXDR 0x28 42 43 /* STM32F7 I2C control 1 */ 44 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 45 #define STM32F7_I2C_CR1_ERRIE BIT(7) 46 #define STM32F7_I2C_CR1_TCIE BIT(6) 47 #define STM32F7_I2C_CR1_STOPIE BIT(5) 48 #define STM32F7_I2C_CR1_NACKIE BIT(4) 49 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 50 #define STM32F7_I2C_CR1_RXIE BIT(2) 51 #define STM32F7_I2C_CR1_TXIE BIT(1) 52 #define STM32F7_I2C_CR1_PE BIT(0) 53 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 54 | STM32F7_I2C_CR1_TCIE \ 55 | STM32F7_I2C_CR1_STOPIE \ 56 | STM32F7_I2C_CR1_NACKIE \ 57 | STM32F7_I2C_CR1_RXIE \ 58 | STM32F7_I2C_CR1_TXIE) 59 60 /* STM32F7 I2C control 2 */ 61 #define STM32F7_I2C_CR2_RELOAD BIT(24) 62 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 63 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 64 #define STM32F7_I2C_CR2_NACK BIT(15) 65 #define STM32F7_I2C_CR2_STOP BIT(14) 66 #define STM32F7_I2C_CR2_START BIT(13) 67 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 68 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 69 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 70 71 /* STM32F7 I2C Interrupt Status */ 72 #define STM32F7_I2C_ISR_BUSY BIT(15) 73 #define STM32F7_I2C_ISR_ARLO BIT(9) 74 #define STM32F7_I2C_ISR_BERR BIT(8) 75 #define STM32F7_I2C_ISR_TCR BIT(7) 76 #define STM32F7_I2C_ISR_TC BIT(6) 77 #define STM32F7_I2C_ISR_STOPF BIT(5) 78 #define STM32F7_I2C_ISR_NACKF BIT(4) 79 #define STM32F7_I2C_ISR_RXNE BIT(2) 80 #define STM32F7_I2C_ISR_TXIS BIT(1) 81 82 /* STM32F7 I2C Interrupt Clear */ 83 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 84 #define STM32F7_I2C_ICR_BERRCF BIT(8) 85 #define STM32F7_I2C_ICR_STOPCF BIT(5) 86 #define STM32F7_I2C_ICR_NACKCF BIT(4) 87 88 /* STM32F7 I2C Timing */ 89 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 90 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 91 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 92 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 93 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 94 95 #define STM32F7_I2C_MAX_LEN 0xff 96 97 #define STM32F7_I2C_DNF_DEFAULT 0 98 #define STM32F7_I2C_DNF_MAX 16 99 100 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1 101 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 102 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 103 104 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 105 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 106 107 #define STM32F7_PRESC_MAX BIT(4) 108 #define STM32F7_SCLDEL_MAX BIT(4) 109 #define STM32F7_SDADEL_MAX BIT(4) 110 #define STM32F7_SCLH_MAX BIT(8) 111 #define STM32F7_SCLL_MAX BIT(8) 112 113 /** 114 * struct stm32f7_i2c_spec - private i2c specification timing 115 * @rate: I2C bus speed (Hz) 116 * @rate_min: 80% of I2C bus speed (Hz) 117 * @rate_max: 100% of I2C bus speed (Hz) 118 * @fall_max: Max fall time of both SDA and SCL signals (ns) 119 * @rise_max: Max rise time of both SDA and SCL signals (ns) 120 * @hddat_min: Min data hold time (ns) 121 * @vddat_max: Max data valid time (ns) 122 * @sudat_min: Min data setup time (ns) 123 * @l_min: Min low period of the SCL clock (ns) 124 * @h_min: Min high period of the SCL clock (ns) 125 */ 126 struct stm32f7_i2c_spec { 127 u32 rate; 128 u32 rate_min; 129 u32 rate_max; 130 u32 fall_max; 131 u32 rise_max; 132 u32 hddat_min; 133 u32 vddat_max; 134 u32 sudat_min; 135 u32 l_min; 136 u32 h_min; 137 }; 138 139 /** 140 * struct stm32f7_i2c_setup - private I2C timing setup parameters 141 * @speed: I2C speed mode (standard, Fast Plus) 142 * @speed_freq: I2C speed frequency (Hz) 143 * @clock_src: I2C clock source frequency (Hz) 144 * @rise_time: Rise time (ns) 145 * @fall_time: Fall time (ns) 146 * @dnf: Digital filter coefficient (0-16) 147 * @analog_filter: Analog filter delay (On/Off) 148 */ 149 struct stm32f7_i2c_setup { 150 enum stm32_i2c_speed speed; 151 u32 speed_freq; 152 u32 clock_src; 153 u32 rise_time; 154 u32 fall_time; 155 u8 dnf; 156 bool analog_filter; 157 }; 158 159 /** 160 * struct stm32f7_i2c_timings - private I2C output parameters 161 * @prec: Prescaler value 162 * @scldel: Data setup time 163 * @sdadel: Data hold time 164 * @sclh: SCL high period (master mode) 165 * @sclh: SCL low period (master mode) 166 */ 167 struct stm32f7_i2c_timings { 168 struct list_head node; 169 u8 presc; 170 u8 scldel; 171 u8 sdadel; 172 u8 sclh; 173 u8 scll; 174 }; 175 176 /** 177 * struct stm32f7_i2c_msg - client specific data 178 * @addr: 8-bit slave addr, including r/w bit 179 * @count: number of bytes to be transferred 180 * @buf: data buffer 181 * @result: result of the transfer 182 * @stop: last I2C msg to be sent, i.e. STOP to be generated 183 */ 184 struct stm32f7_i2c_msg { 185 u8 addr; 186 u32 count; 187 u8 *buf; 188 int result; 189 bool stop; 190 }; 191 192 /** 193 * struct stm32f7_i2c_dev - private data of the controller 194 * @adap: I2C adapter for this controller 195 * @dev: device for this controller 196 * @base: virtual memory area 197 * @complete: completion of I2C message 198 * @clk: hw i2c clock 199 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+ 200 * @msg: Pointer to data to be written 201 * @msg_num: number of I2C messages to be executed 202 * @msg_id: message identifiant 203 * @f7_msg: customized i2c msg for driver usage 204 * @setup: I2C timing input setup 205 * @timing: I2C computed timings 206 */ 207 struct stm32f7_i2c_dev { 208 struct i2c_adapter adap; 209 struct device *dev; 210 void __iomem *base; 211 struct completion complete; 212 struct clk *clk; 213 int speed; 214 struct i2c_msg *msg; 215 unsigned int msg_num; 216 unsigned int msg_id; 217 struct stm32f7_i2c_msg f7_msg; 218 struct stm32f7_i2c_setup *setup; 219 struct stm32f7_i2c_timings timing; 220 }; 221 222 /** 223 * All these values are coming from I2C Specification, Version 6.0, 4th of 224 * April 2014. 225 * 226 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 227 * and Fast-mode Plus I2C-bus devices 228 */ 229 static struct stm32f7_i2c_spec i2c_specs[] = { 230 [STM32_I2C_SPEED_STANDARD] = { 231 .rate = 100000, 232 .rate_min = 80000, 233 .rate_max = 100000, 234 .fall_max = 300, 235 .rise_max = 1000, 236 .hddat_min = 0, 237 .vddat_max = 3450, 238 .sudat_min = 250, 239 .l_min = 4700, 240 .h_min = 4000, 241 }, 242 [STM32_I2C_SPEED_FAST] = { 243 .rate = 400000, 244 .rate_min = 320000, 245 .rate_max = 400000, 246 .fall_max = 300, 247 .rise_max = 300, 248 .hddat_min = 0, 249 .vddat_max = 900, 250 .sudat_min = 100, 251 .l_min = 1300, 252 .h_min = 600, 253 }, 254 [STM32_I2C_SPEED_FAST_PLUS] = { 255 .rate = 1000000, 256 .rate_min = 800000, 257 .rate_max = 1000000, 258 .fall_max = 100, 259 .rise_max = 120, 260 .hddat_min = 0, 261 .vddat_max = 450, 262 .sudat_min = 50, 263 .l_min = 500, 264 .h_min = 260, 265 }, 266 }; 267 268 struct stm32f7_i2c_setup stm32f7_setup = { 269 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 270 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 271 .dnf = STM32F7_I2C_DNF_DEFAULT, 272 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE, 273 }; 274 275 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 276 { 277 writel_relaxed(readl_relaxed(reg) | mask, reg); 278 } 279 280 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 281 { 282 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 283 } 284 285 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 286 struct stm32f7_i2c_setup *setup, 287 struct stm32f7_i2c_timings *output) 288 { 289 u32 p_prev = STM32F7_PRESC_MAX; 290 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 291 setup->clock_src); 292 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 293 setup->speed_freq); 294 u32 clk_error_prev = i2cbus; 295 u32 tsync; 296 u32 af_delay_min, af_delay_max; 297 u32 dnf_delay; 298 u32 clk_min, clk_max; 299 int sdadel_min, sdadel_max; 300 int scldel_min; 301 struct stm32f7_i2c_timings *v, *_v, *s; 302 struct list_head solutions; 303 u16 p, l, a, h; 304 int ret = 0; 305 306 if (setup->speed >= STM32_I2C_SPEED_END) { 307 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n", 308 setup->speed, STM32_I2C_SPEED_END - 1); 309 return -EINVAL; 310 } 311 312 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || 313 (setup->fall_time > i2c_specs[setup->speed].fall_max)) { 314 dev_err(i2c_dev->dev, 315 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 316 setup->rise_time, i2c_specs[setup->speed].rise_max, 317 setup->fall_time, i2c_specs[setup->speed].fall_max); 318 return -EINVAL; 319 } 320 321 if (setup->dnf > STM32F7_I2C_DNF_MAX) { 322 dev_err(i2c_dev->dev, 323 "DNF out of bound %d/%d\n", 324 setup->dnf, STM32F7_I2C_DNF_MAX); 325 return -EINVAL; 326 } 327 328 if (setup->speed_freq > i2c_specs[setup->speed].rate) { 329 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n", 330 setup->speed_freq, i2c_specs[setup->speed].rate); 331 return -EINVAL; 332 } 333 334 /* Analog and Digital Filters */ 335 af_delay_min = 336 (setup->analog_filter ? 337 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 338 af_delay_max = 339 (setup->analog_filter ? 340 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 341 dnf_delay = setup->dnf * i2cclk; 342 343 sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min - 344 af_delay_min - (setup->dnf + 3) * i2cclk; 345 346 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - 347 af_delay_max - (setup->dnf + 4) * i2cclk; 348 349 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; 350 351 if (sdadel_min < 0) 352 sdadel_min = 0; 353 if (sdadel_max < 0) 354 sdadel_max = 0; 355 356 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 357 sdadel_min, sdadel_max, scldel_min); 358 359 INIT_LIST_HEAD(&solutions); 360 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 361 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 362 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 363 u32 scldel = (l + 1) * (p + 1) * i2cclk; 364 365 if (scldel < scldel_min) 366 continue; 367 368 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 369 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 370 371 if (((sdadel >= sdadel_min) && 372 (sdadel <= sdadel_max)) && 373 (p != p_prev)) { 374 v = kmalloc(sizeof(*v), GFP_KERNEL); 375 if (!v) { 376 ret = -ENOMEM; 377 goto exit; 378 } 379 380 v->presc = p; 381 v->scldel = l; 382 v->sdadel = a; 383 p_prev = p; 384 385 list_add_tail(&v->node, 386 &solutions); 387 } 388 } 389 } 390 } 391 392 if (list_empty(&solutions)) { 393 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 394 ret = -EPERM; 395 goto exit; 396 } 397 398 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 399 s = NULL; 400 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; 401 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; 402 403 /* 404 * Among Prescaler possibilities discovered above figures out SCL Low 405 * and High Period. Provided: 406 * - SCL Low Period has to be higher than SCL Clock Low Period 407 * defined by I2C Specification. I2C Clock has to be lower than 408 * (SCL Low Period - Analog/Digital filters) / 4. 409 * - SCL High Period has to be lower than SCL Clock High Period 410 * defined by I2C Specification 411 * - I2C Clock has to be lower than SCL High Period 412 */ 413 list_for_each_entry(v, &solutions, node) { 414 u32 prescaler = (v->presc + 1) * i2cclk; 415 416 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 417 u32 tscl_l = (l + 1) * prescaler + tsync; 418 419 if ((tscl_l < i2c_specs[setup->speed].l_min) || 420 (i2cclk >= 421 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 422 continue; 423 } 424 425 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 426 u32 tscl_h = (h + 1) * prescaler + tsync; 427 u32 tscl = tscl_l + tscl_h + 428 setup->rise_time + setup->fall_time; 429 430 if ((tscl >= clk_min) && (tscl <= clk_max) && 431 (tscl_h >= i2c_specs[setup->speed].h_min) && 432 (i2cclk < tscl_h)) { 433 int clk_error = tscl - i2cbus; 434 435 if (clk_error < 0) 436 clk_error = -clk_error; 437 438 if (clk_error < clk_error_prev) { 439 clk_error_prev = clk_error; 440 v->scll = l; 441 v->sclh = h; 442 s = v; 443 } 444 } 445 } 446 } 447 } 448 449 if (!s) { 450 dev_err(i2c_dev->dev, "no solution at all\n"); 451 ret = -EPERM; 452 goto exit; 453 } 454 455 output->presc = s->presc; 456 output->scldel = s->scldel; 457 output->sdadel = s->sdadel; 458 output->scll = s->scll; 459 output->sclh = s->sclh; 460 461 dev_dbg(i2c_dev->dev, 462 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 463 output->presc, 464 output->scldel, output->sdadel, 465 output->scll, output->sclh); 466 467 exit: 468 /* Release list and memory */ 469 list_for_each_entry_safe(v, _v, &solutions, node) { 470 list_del(&v->node); 471 kfree(v); 472 } 473 474 return ret; 475 } 476 477 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 478 struct stm32f7_i2c_setup *setup) 479 { 480 int ret = 0; 481 482 setup->speed = i2c_dev->speed; 483 setup->speed_freq = i2c_specs[setup->speed].rate; 484 setup->clock_src = clk_get_rate(i2c_dev->clk); 485 486 if (!setup->clock_src) { 487 dev_err(i2c_dev->dev, "clock rate is 0\n"); 488 return -EINVAL; 489 } 490 491 do { 492 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 493 &i2c_dev->timing); 494 if (ret) { 495 dev_err(i2c_dev->dev, 496 "failed to compute I2C timings.\n"); 497 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) { 498 i2c_dev->speed--; 499 setup->speed = i2c_dev->speed; 500 setup->speed_freq = 501 i2c_specs[setup->speed].rate; 502 dev_warn(i2c_dev->dev, 503 "downgrade I2C Speed Freq to (%i)\n", 504 i2c_specs[setup->speed].rate); 505 } else { 506 break; 507 } 508 } 509 } while (ret); 510 511 if (ret) { 512 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 513 return ret; 514 } 515 516 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n", 517 setup->speed, setup->speed_freq, setup->clock_src); 518 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 519 setup->rise_time, setup->fall_time); 520 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 521 (setup->analog_filter ? "On" : "Off"), setup->dnf); 522 523 return 0; 524 } 525 526 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 527 { 528 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 529 u32 timing = 0; 530 531 /* Timing settings */ 532 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 533 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 534 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 535 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 536 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 537 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 538 539 /* Enable I2C */ 540 if (i2c_dev->setup->analog_filter) 541 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 542 STM32F7_I2C_CR1_ANFOFF); 543 else 544 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 545 STM32F7_I2C_CR1_ANFOFF); 546 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 547 STM32F7_I2C_CR1_PE); 548 } 549 550 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 551 { 552 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 553 void __iomem *base = i2c_dev->base; 554 555 if (f7_msg->count) { 556 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 557 f7_msg->count--; 558 } 559 } 560 561 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 562 { 563 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 564 void __iomem *base = i2c_dev->base; 565 566 if (f7_msg->count) { 567 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 568 f7_msg->count--; 569 } 570 } 571 572 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 573 { 574 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 575 u32 cr2; 576 577 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 578 579 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 580 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 581 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 582 } else { 583 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 584 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 585 } 586 587 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 588 } 589 590 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 591 { 592 u32 status; 593 int ret; 594 595 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 596 status, 597 !(status & STM32F7_I2C_ISR_BUSY), 598 10, 1000); 599 if (ret) { 600 dev_dbg(i2c_dev->dev, "bus busy\n"); 601 ret = -EBUSY; 602 } 603 604 return ret; 605 } 606 607 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 608 struct i2c_msg *msg) 609 { 610 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 611 void __iomem *base = i2c_dev->base; 612 u32 cr1, cr2; 613 614 f7_msg->addr = msg->addr; 615 f7_msg->buf = msg->buf; 616 f7_msg->count = msg->len; 617 f7_msg->result = 0; 618 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 619 620 reinit_completion(&i2c_dev->complete); 621 622 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 623 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 624 625 /* Set transfer direction */ 626 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 627 if (msg->flags & I2C_M_RD) 628 cr2 |= STM32F7_I2C_CR2_RD_WRN; 629 630 /* Set slave address */ 631 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 632 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 633 634 /* Set nb bytes to transfer and reload if needed */ 635 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 636 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 637 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 638 cr2 |= STM32F7_I2C_CR2_RELOAD; 639 } else { 640 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 641 } 642 643 /* Enable NACK, STOP, error and transfer complete interrupts */ 644 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 645 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 646 647 /* Clear TX/RX interrupt */ 648 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 649 650 /* Enable RX/TX interrupt according to msg direction */ 651 if (msg->flags & I2C_M_RD) 652 cr1 |= STM32F7_I2C_CR1_RXIE; 653 else 654 cr1 |= STM32F7_I2C_CR1_TXIE; 655 656 /* Configure Start/Repeated Start */ 657 cr2 |= STM32F7_I2C_CR2_START; 658 659 /* Write configurations registers */ 660 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 661 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 662 } 663 664 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 665 { 666 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 667 } 668 669 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 670 { 671 struct stm32f7_i2c_dev *i2c_dev = data; 672 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 673 void __iomem *base = i2c_dev->base; 674 u32 status, mask; 675 676 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 677 678 /* Tx empty */ 679 if (status & STM32F7_I2C_ISR_TXIS) 680 stm32f7_i2c_write_tx_data(i2c_dev); 681 682 /* RX not empty */ 683 if (status & STM32F7_I2C_ISR_RXNE) 684 stm32f7_i2c_read_rx_data(i2c_dev); 685 686 /* NACK received */ 687 if (status & STM32F7_I2C_ISR_NACKF) { 688 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 689 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 690 f7_msg->result = -ENXIO; 691 } 692 693 /* STOP detection flag */ 694 if (status & STM32F7_I2C_ISR_STOPF) { 695 /* Disable interrupts */ 696 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 697 698 /* Clear STOP flag */ 699 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 700 701 complete(&i2c_dev->complete); 702 } 703 704 /* Transfer complete */ 705 if (status & STM32F7_I2C_ISR_TC) { 706 if (f7_msg->stop) { 707 mask = STM32F7_I2C_CR2_STOP; 708 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 709 } else { 710 i2c_dev->msg_id++; 711 i2c_dev->msg++; 712 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 713 } 714 } 715 716 /* 717 * Transfer Complete Reload: 255 data bytes have been transferred 718 * We have to prepare the I2C controller to transfer the remaining 719 * data. 720 */ 721 if (status & STM32F7_I2C_ISR_TCR) 722 stm32f7_i2c_reload(i2c_dev); 723 724 return IRQ_HANDLED; 725 } 726 727 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data) 728 { 729 struct stm32f7_i2c_dev *i2c_dev = data; 730 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 731 void __iomem *base = i2c_dev->base; 732 struct device *dev = i2c_dev->dev; 733 u32 status; 734 735 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 736 737 /* Bus error */ 738 if (status & STM32F7_I2C_ISR_BERR) { 739 dev_err(dev, "<%s>: Bus error\n", __func__); 740 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 741 f7_msg->result = -EIO; 742 } 743 744 /* Arbitration loss */ 745 if (status & STM32F7_I2C_ISR_ARLO) { 746 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__); 747 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 748 f7_msg->result = -EAGAIN; 749 } 750 751 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 752 753 complete(&i2c_dev->complete); 754 755 return IRQ_HANDLED; 756 } 757 758 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 759 struct i2c_msg msgs[], int num) 760 { 761 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 762 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 763 unsigned long time_left; 764 int ret; 765 766 i2c_dev->msg = msgs; 767 i2c_dev->msg_num = num; 768 i2c_dev->msg_id = 0; 769 770 ret = clk_enable(i2c_dev->clk); 771 if (ret) { 772 dev_err(i2c_dev->dev, "Failed to enable clock\n"); 773 return ret; 774 } 775 776 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 777 if (ret) 778 goto clk_free; 779 780 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 781 782 time_left = wait_for_completion_timeout(&i2c_dev->complete, 783 i2c_dev->adap.timeout); 784 ret = f7_msg->result; 785 786 if (!time_left) { 787 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 788 i2c_dev->msg->addr); 789 ret = -ETIMEDOUT; 790 } 791 792 clk_free: 793 clk_disable(i2c_dev->clk); 794 795 return (ret < 0) ? ret : num; 796 } 797 798 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 799 { 800 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 801 } 802 803 static struct i2c_algorithm stm32f7_i2c_algo = { 804 .master_xfer = stm32f7_i2c_xfer, 805 .functionality = stm32f7_i2c_func, 806 }; 807 808 static int stm32f7_i2c_probe(struct platform_device *pdev) 809 { 810 struct device_node *np = pdev->dev.of_node; 811 struct stm32f7_i2c_dev *i2c_dev; 812 const struct stm32f7_i2c_setup *setup; 813 struct resource *res; 814 u32 irq_error, irq_event, clk_rate, rise_time, fall_time; 815 struct i2c_adapter *adap; 816 struct reset_control *rst; 817 int ret; 818 819 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 820 if (!i2c_dev) 821 return -ENOMEM; 822 823 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 824 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 825 if (IS_ERR(i2c_dev->base)) 826 return PTR_ERR(i2c_dev->base); 827 828 irq_event = irq_of_parse_and_map(np, 0); 829 if (!irq_event) { 830 dev_err(&pdev->dev, "IRQ event missing or invalid\n"); 831 return -EINVAL; 832 } 833 834 irq_error = irq_of_parse_and_map(np, 1); 835 if (!irq_error) { 836 dev_err(&pdev->dev, "IRQ error missing or invalid\n"); 837 return -EINVAL; 838 } 839 840 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 841 if (IS_ERR(i2c_dev->clk)) { 842 dev_err(&pdev->dev, "Error: Missing controller clock\n"); 843 return PTR_ERR(i2c_dev->clk); 844 } 845 ret = clk_prepare_enable(i2c_dev->clk); 846 if (ret) { 847 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); 848 return ret; 849 } 850 851 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; 852 ret = device_property_read_u32(&pdev->dev, "clock-frequency", 853 &clk_rate); 854 if (!ret && clk_rate >= 1000000) 855 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS; 856 else if (!ret && clk_rate >= 400000) 857 i2c_dev->speed = STM32_I2C_SPEED_FAST; 858 else if (!ret && clk_rate >= 100000) 859 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; 860 861 rst = devm_reset_control_get(&pdev->dev, NULL); 862 if (IS_ERR(rst)) { 863 dev_err(&pdev->dev, "Error: Missing controller reset\n"); 864 ret = PTR_ERR(rst); 865 goto clk_free; 866 } 867 reset_control_assert(rst); 868 udelay(2); 869 reset_control_deassert(rst); 870 871 i2c_dev->dev = &pdev->dev; 872 873 ret = devm_request_irq(&pdev->dev, irq_event, stm32f7_i2c_isr_event, 0, 874 pdev->name, i2c_dev); 875 if (ret) { 876 dev_err(&pdev->dev, "Failed to request irq event %i\n", 877 irq_event); 878 goto clk_free; 879 } 880 881 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, 882 pdev->name, i2c_dev); 883 if (ret) { 884 dev_err(&pdev->dev, "Failed to request irq error %i\n", 885 irq_error); 886 goto clk_free; 887 } 888 889 setup = of_device_get_match_data(&pdev->dev); 890 i2c_dev->setup->rise_time = setup->rise_time; 891 i2c_dev->setup->fall_time = setup->fall_time; 892 i2c_dev->setup->dnf = setup->dnf; 893 i2c_dev->setup->analog_filter = setup->analog_filter; 894 895 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns", 896 &rise_time); 897 if (!ret) 898 i2c_dev->setup->rise_time = rise_time; 899 900 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns", 901 &fall_time); 902 if (!ret) 903 i2c_dev->setup->fall_time = fall_time; 904 905 ret = stm32f7_i2c_setup_timing(i2c_dev, i2c_dev->setup); 906 if (ret) 907 goto clk_free; 908 909 stm32f7_i2c_hw_config(i2c_dev); 910 911 adap = &i2c_dev->adap; 912 i2c_set_adapdata(adap, i2c_dev); 913 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 914 &res->start); 915 adap->owner = THIS_MODULE; 916 adap->timeout = 2 * HZ; 917 adap->retries = 3; 918 adap->algo = &stm32f7_i2c_algo; 919 adap->dev.parent = &pdev->dev; 920 adap->dev.of_node = pdev->dev.of_node; 921 922 init_completion(&i2c_dev->complete); 923 924 ret = i2c_add_adapter(adap); 925 if (ret) 926 goto clk_free; 927 928 platform_set_drvdata(pdev, i2c_dev); 929 930 clk_disable(i2c_dev->clk); 931 932 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 933 934 return 0; 935 936 clk_free: 937 clk_disable_unprepare(i2c_dev->clk); 938 939 return ret; 940 } 941 942 static int stm32f7_i2c_remove(struct platform_device *pdev) 943 { 944 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 945 946 i2c_del_adapter(&i2c_dev->adap); 947 948 clk_unprepare(i2c_dev->clk); 949 950 return 0; 951 } 952 953 static const struct of_device_id stm32f7_i2c_match[] = { 954 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 955 {}, 956 }; 957 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 958 959 static struct platform_driver stm32f7_i2c_driver = { 960 .driver = { 961 .name = "stm32f7-i2c", 962 .of_match_table = stm32f7_i2c_match, 963 }, 964 .probe = stm32f7_i2c_probe, 965 .remove = stm32f7_i2c_remove, 966 }; 967 968 module_platform_driver(stm32f7_i2c_driver); 969 970 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 971 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 972 MODULE_LICENSE("GPL v2"); 973