1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/iopoll.h> 24 #include <linux/mfd/syscon.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regmap.h> 34 #include <linux/reset.h> 35 #include <linux/slab.h> 36 37 #include "i2c-stm32.h" 38 39 /* STM32F7 I2C registers */ 40 #define STM32F7_I2C_CR1 0x00 41 #define STM32F7_I2C_CR2 0x04 42 #define STM32F7_I2C_OAR1 0x08 43 #define STM32F7_I2C_OAR2 0x0C 44 #define STM32F7_I2C_PECR 0x20 45 #define STM32F7_I2C_TIMINGR 0x10 46 #define STM32F7_I2C_ISR 0x18 47 #define STM32F7_I2C_ICR 0x1C 48 #define STM32F7_I2C_RXDR 0x24 49 #define STM32F7_I2C_TXDR 0x28 50 51 /* STM32F7 I2C control 1 */ 52 #define STM32F7_I2C_CR1_PECEN BIT(23) 53 #define STM32F7_I2C_CR1_SBC BIT(16) 54 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 55 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 56 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 57 #define STM32F7_I2C_CR1_ERRIE BIT(7) 58 #define STM32F7_I2C_CR1_TCIE BIT(6) 59 #define STM32F7_I2C_CR1_STOPIE BIT(5) 60 #define STM32F7_I2C_CR1_NACKIE BIT(4) 61 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 62 #define STM32F7_I2C_CR1_RXIE BIT(2) 63 #define STM32F7_I2C_CR1_TXIE BIT(1) 64 #define STM32F7_I2C_CR1_PE BIT(0) 65 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 66 | STM32F7_I2C_CR1_TCIE \ 67 | STM32F7_I2C_CR1_STOPIE \ 68 | STM32F7_I2C_CR1_NACKIE \ 69 | STM32F7_I2C_CR1_RXIE \ 70 | STM32F7_I2C_CR1_TXIE) 71 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 72 | STM32F7_I2C_CR1_STOPIE \ 73 | STM32F7_I2C_CR1_NACKIE \ 74 | STM32F7_I2C_CR1_RXIE \ 75 | STM32F7_I2C_CR1_TXIE) 76 77 /* STM32F7 I2C control 2 */ 78 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 79 #define STM32F7_I2C_CR2_RELOAD BIT(24) 80 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 81 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 82 #define STM32F7_I2C_CR2_NACK BIT(15) 83 #define STM32F7_I2C_CR2_STOP BIT(14) 84 #define STM32F7_I2C_CR2_START BIT(13) 85 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 86 #define STM32F7_I2C_CR2_ADD10 BIT(11) 87 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 88 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 89 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 90 STM32F7_I2C_CR2_SADD10_MASK)) 91 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 92 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 93 94 /* STM32F7 I2C Own Address 1 */ 95 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 96 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 97 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 98 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 99 STM32F7_I2C_OAR1_OA1_10_MASK)) 100 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 101 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 102 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 103 | STM32F7_I2C_OAR1_OA1_10_MASK \ 104 | STM32F7_I2C_OAR1_OA1EN \ 105 | STM32F7_I2C_OAR1_OA1MODE) 106 107 /* STM32F7 I2C Own Address 2 */ 108 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 109 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 110 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 111 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 112 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 113 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 114 | STM32F7_I2C_OAR2_OA2_7_MASK \ 115 | STM32F7_I2C_OAR2_OA2EN) 116 117 /* STM32F7 I2C Interrupt Status */ 118 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 119 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 120 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 121 #define STM32F7_I2C_ISR_DIR BIT(16) 122 #define STM32F7_I2C_ISR_BUSY BIT(15) 123 #define STM32F7_I2C_ISR_PECERR BIT(11) 124 #define STM32F7_I2C_ISR_ARLO BIT(9) 125 #define STM32F7_I2C_ISR_BERR BIT(8) 126 #define STM32F7_I2C_ISR_TCR BIT(7) 127 #define STM32F7_I2C_ISR_TC BIT(6) 128 #define STM32F7_I2C_ISR_STOPF BIT(5) 129 #define STM32F7_I2C_ISR_NACKF BIT(4) 130 #define STM32F7_I2C_ISR_ADDR BIT(3) 131 #define STM32F7_I2C_ISR_RXNE BIT(2) 132 #define STM32F7_I2C_ISR_TXIS BIT(1) 133 #define STM32F7_I2C_ISR_TXE BIT(0) 134 135 /* STM32F7 I2C Interrupt Clear */ 136 #define STM32F7_I2C_ICR_PECCF BIT(11) 137 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 138 #define STM32F7_I2C_ICR_BERRCF BIT(8) 139 #define STM32F7_I2C_ICR_STOPCF BIT(5) 140 #define STM32F7_I2C_ICR_NACKCF BIT(4) 141 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 142 143 /* STM32F7 I2C Timing */ 144 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 145 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 146 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 147 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 148 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 149 150 #define STM32F7_I2C_MAX_LEN 0xff 151 #define STM32F7_I2C_DMA_LEN_MIN 0x16 152 #define STM32F7_I2C_MAX_SLAVE 0x2 153 154 #define STM32F7_I2C_DNF_DEFAULT 0 155 #define STM32F7_I2C_DNF_MAX 16 156 157 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1 158 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 159 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 160 161 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 162 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 163 164 #define STM32F7_PRESC_MAX BIT(4) 165 #define STM32F7_SCLDEL_MAX BIT(4) 166 #define STM32F7_SDADEL_MAX BIT(4) 167 #define STM32F7_SCLH_MAX BIT(8) 168 #define STM32F7_SCLL_MAX BIT(8) 169 170 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 171 172 /** 173 * struct stm32f7_i2c_spec - private i2c specification timing 174 * @rate: I2C bus speed (Hz) 175 * @rate_min: 80% of I2C bus speed (Hz) 176 * @rate_max: 100% of I2C bus speed (Hz) 177 * @fall_max: Max fall time of both SDA and SCL signals (ns) 178 * @rise_max: Max rise time of both SDA and SCL signals (ns) 179 * @hddat_min: Min data hold time (ns) 180 * @vddat_max: Max data valid time (ns) 181 * @sudat_min: Min data setup time (ns) 182 * @l_min: Min low period of the SCL clock (ns) 183 * @h_min: Min high period of the SCL clock (ns) 184 */ 185 struct stm32f7_i2c_spec { 186 u32 rate; 187 u32 rate_min; 188 u32 rate_max; 189 u32 fall_max; 190 u32 rise_max; 191 u32 hddat_min; 192 u32 vddat_max; 193 u32 sudat_min; 194 u32 l_min; 195 u32 h_min; 196 }; 197 198 /** 199 * struct stm32f7_i2c_setup - private I2C timing setup parameters 200 * @speed: I2C speed mode (standard, Fast Plus) 201 * @speed_freq: I2C speed frequency (Hz) 202 * @clock_src: I2C clock source frequency (Hz) 203 * @rise_time: Rise time (ns) 204 * @fall_time: Fall time (ns) 205 * @dnf: Digital filter coefficient (0-16) 206 * @analog_filter: Analog filter delay (On/Off) 207 */ 208 struct stm32f7_i2c_setup { 209 enum stm32_i2c_speed speed; 210 u32 speed_freq; 211 u32 clock_src; 212 u32 rise_time; 213 u32 fall_time; 214 u8 dnf; 215 bool analog_filter; 216 }; 217 218 /** 219 * struct stm32f7_i2c_timings - private I2C output parameters 220 * @node: List entry 221 * @presc: Prescaler value 222 * @scldel: Data setup time 223 * @sdadel: Data hold time 224 * @sclh: SCL high period (master mode) 225 * @scll: SCL low period (master mode) 226 */ 227 struct stm32f7_i2c_timings { 228 struct list_head node; 229 u8 presc; 230 u8 scldel; 231 u8 sdadel; 232 u8 sclh; 233 u8 scll; 234 }; 235 236 /** 237 * struct stm32f7_i2c_msg - client specific data 238 * @addr: 8-bit or 10-bit slave addr, including r/w bit 239 * @count: number of bytes to be transferred 240 * @buf: data buffer 241 * @result: result of the transfer 242 * @stop: last I2C msg to be sent, i.e. STOP to be generated 243 * @smbus: boolean to know if the I2C IP is used in SMBus mode 244 * @size: type of SMBus protocol 245 * @read_write: direction of SMBus protocol 246 * SMBus block read and SMBus block write - block read process call protocols 247 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 248 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 249 * This buffer has to be 32-bit aligned to be compliant with memory address 250 * register in DMA mode. 251 */ 252 struct stm32f7_i2c_msg { 253 u16 addr; 254 u32 count; 255 u8 *buf; 256 int result; 257 bool stop; 258 bool smbus; 259 int size; 260 char read_write; 261 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 262 }; 263 264 /** 265 * struct stm32f7_i2c_dev - private data of the controller 266 * @adap: I2C adapter for this controller 267 * @dev: device for this controller 268 * @base: virtual memory area 269 * @complete: completion of I2C message 270 * @clk: hw i2c clock 271 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+ 272 * @msg: Pointer to data to be written 273 * @msg_num: number of I2C messages to be executed 274 * @msg_id: message identifiant 275 * @f7_msg: customized i2c msg for driver usage 276 * @setup: I2C timing input setup 277 * @timing: I2C computed timings 278 * @slave: list of slave devices registered on the I2C bus 279 * @slave_running: slave device currently used 280 * @slave_dir: transfer direction for the current slave device 281 * @master_mode: boolean to know in which mode the I2C is running (master or 282 * slave) 283 * @dma: dma data 284 * @use_dma: boolean to know if dma is used in the current transfer 285 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 286 */ 287 struct stm32f7_i2c_dev { 288 struct i2c_adapter adap; 289 struct device *dev; 290 void __iomem *base; 291 struct completion complete; 292 struct clk *clk; 293 int speed; 294 struct i2c_msg *msg; 295 unsigned int msg_num; 296 unsigned int msg_id; 297 struct stm32f7_i2c_msg f7_msg; 298 struct stm32f7_i2c_setup setup; 299 struct stm32f7_i2c_timings timing; 300 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 301 struct i2c_client *slave_running; 302 u32 slave_dir; 303 bool master_mode; 304 struct stm32_i2c_dma *dma; 305 bool use_dma; 306 struct regmap *regmap; 307 }; 308 309 /** 310 * All these values are coming from I2C Specification, Version 6.0, 4th of 311 * April 2014. 312 * 313 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 314 * and Fast-mode Plus I2C-bus devices 315 */ 316 static struct stm32f7_i2c_spec i2c_specs[] = { 317 [STM32_I2C_SPEED_STANDARD] = { 318 .rate = 100000, 319 .rate_min = 80000, 320 .rate_max = 100000, 321 .fall_max = 300, 322 .rise_max = 1000, 323 .hddat_min = 0, 324 .vddat_max = 3450, 325 .sudat_min = 250, 326 .l_min = 4700, 327 .h_min = 4000, 328 }, 329 [STM32_I2C_SPEED_FAST] = { 330 .rate = 400000, 331 .rate_min = 320000, 332 .rate_max = 400000, 333 .fall_max = 300, 334 .rise_max = 300, 335 .hddat_min = 0, 336 .vddat_max = 900, 337 .sudat_min = 100, 338 .l_min = 1300, 339 .h_min = 600, 340 }, 341 [STM32_I2C_SPEED_FAST_PLUS] = { 342 .rate = 1000000, 343 .rate_min = 800000, 344 .rate_max = 1000000, 345 .fall_max = 100, 346 .rise_max = 120, 347 .hddat_min = 0, 348 .vddat_max = 450, 349 .sudat_min = 50, 350 .l_min = 500, 351 .h_min = 260, 352 }, 353 }; 354 355 static const struct stm32f7_i2c_setup stm32f7_setup = { 356 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 357 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 358 .dnf = STM32F7_I2C_DNF_DEFAULT, 359 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE, 360 }; 361 362 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 363 { 364 writel_relaxed(readl_relaxed(reg) | mask, reg); 365 } 366 367 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 368 { 369 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 370 } 371 372 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 373 { 374 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 375 } 376 377 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 378 struct stm32f7_i2c_setup *setup, 379 struct stm32f7_i2c_timings *output) 380 { 381 u32 p_prev = STM32F7_PRESC_MAX; 382 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 383 setup->clock_src); 384 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 385 setup->speed_freq); 386 u32 clk_error_prev = i2cbus; 387 u32 tsync; 388 u32 af_delay_min, af_delay_max; 389 u32 dnf_delay; 390 u32 clk_min, clk_max; 391 int sdadel_min, sdadel_max; 392 int scldel_min; 393 struct stm32f7_i2c_timings *v, *_v, *s; 394 struct list_head solutions; 395 u16 p, l, a, h; 396 int ret = 0; 397 398 if (setup->speed >= STM32_I2C_SPEED_END) { 399 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n", 400 setup->speed, STM32_I2C_SPEED_END - 1); 401 return -EINVAL; 402 } 403 404 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || 405 (setup->fall_time > i2c_specs[setup->speed].fall_max)) { 406 dev_err(i2c_dev->dev, 407 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 408 setup->rise_time, i2c_specs[setup->speed].rise_max, 409 setup->fall_time, i2c_specs[setup->speed].fall_max); 410 return -EINVAL; 411 } 412 413 if (setup->dnf > STM32F7_I2C_DNF_MAX) { 414 dev_err(i2c_dev->dev, 415 "DNF out of bound %d/%d\n", 416 setup->dnf, STM32F7_I2C_DNF_MAX); 417 return -EINVAL; 418 } 419 420 if (setup->speed_freq > i2c_specs[setup->speed].rate) { 421 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n", 422 setup->speed_freq, i2c_specs[setup->speed].rate); 423 return -EINVAL; 424 } 425 426 /* Analog and Digital Filters */ 427 af_delay_min = 428 (setup->analog_filter ? 429 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 430 af_delay_max = 431 (setup->analog_filter ? 432 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 433 dnf_delay = setup->dnf * i2cclk; 434 435 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time - 436 af_delay_min - (setup->dnf + 3) * i2cclk; 437 438 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - 439 af_delay_max - (setup->dnf + 4) * i2cclk; 440 441 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; 442 443 if (sdadel_min < 0) 444 sdadel_min = 0; 445 if (sdadel_max < 0) 446 sdadel_max = 0; 447 448 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 449 sdadel_min, sdadel_max, scldel_min); 450 451 INIT_LIST_HEAD(&solutions); 452 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 453 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 454 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 455 u32 scldel = (l + 1) * (p + 1) * i2cclk; 456 457 if (scldel < scldel_min) 458 continue; 459 460 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 461 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 462 463 if (((sdadel >= sdadel_min) && 464 (sdadel <= sdadel_max)) && 465 (p != p_prev)) { 466 v = kmalloc(sizeof(*v), GFP_KERNEL); 467 if (!v) { 468 ret = -ENOMEM; 469 goto exit; 470 } 471 472 v->presc = p; 473 v->scldel = l; 474 v->sdadel = a; 475 p_prev = p; 476 477 list_add_tail(&v->node, 478 &solutions); 479 break; 480 } 481 } 482 483 if (p_prev == p) 484 break; 485 } 486 } 487 488 if (list_empty(&solutions)) { 489 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 490 ret = -EPERM; 491 goto exit; 492 } 493 494 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 495 s = NULL; 496 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; 497 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; 498 499 /* 500 * Among Prescaler possibilities discovered above figures out SCL Low 501 * and High Period. Provided: 502 * - SCL Low Period has to be higher than SCL Clock Low Period 503 * defined by I2C Specification. I2C Clock has to be lower than 504 * (SCL Low Period - Analog/Digital filters) / 4. 505 * - SCL High Period has to be lower than SCL Clock High Period 506 * defined by I2C Specification 507 * - I2C Clock has to be lower than SCL High Period 508 */ 509 list_for_each_entry(v, &solutions, node) { 510 u32 prescaler = (v->presc + 1) * i2cclk; 511 512 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 513 u32 tscl_l = (l + 1) * prescaler + tsync; 514 515 if ((tscl_l < i2c_specs[setup->speed].l_min) || 516 (i2cclk >= 517 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 518 continue; 519 } 520 521 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 522 u32 tscl_h = (h + 1) * prescaler + tsync; 523 u32 tscl = tscl_l + tscl_h + 524 setup->rise_time + setup->fall_time; 525 526 if ((tscl >= clk_min) && (tscl <= clk_max) && 527 (tscl_h >= i2c_specs[setup->speed].h_min) && 528 (i2cclk < tscl_h)) { 529 int clk_error = tscl - i2cbus; 530 531 if (clk_error < 0) 532 clk_error = -clk_error; 533 534 if (clk_error < clk_error_prev) { 535 clk_error_prev = clk_error; 536 v->scll = l; 537 v->sclh = h; 538 s = v; 539 } 540 } 541 } 542 } 543 } 544 545 if (!s) { 546 dev_err(i2c_dev->dev, "no solution at all\n"); 547 ret = -EPERM; 548 goto exit; 549 } 550 551 output->presc = s->presc; 552 output->scldel = s->scldel; 553 output->sdadel = s->sdadel; 554 output->scll = s->scll; 555 output->sclh = s->sclh; 556 557 dev_dbg(i2c_dev->dev, 558 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 559 output->presc, 560 output->scldel, output->sdadel, 561 output->scll, output->sclh); 562 563 exit: 564 /* Release list and memory */ 565 list_for_each_entry_safe(v, _v, &solutions, node) { 566 list_del(&v->node); 567 kfree(v); 568 } 569 570 return ret; 571 } 572 573 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 574 struct stm32f7_i2c_setup *setup) 575 { 576 int ret = 0; 577 578 setup->speed = i2c_dev->speed; 579 setup->speed_freq = i2c_specs[setup->speed].rate; 580 setup->clock_src = clk_get_rate(i2c_dev->clk); 581 582 if (!setup->clock_src) { 583 dev_err(i2c_dev->dev, "clock rate is 0\n"); 584 return -EINVAL; 585 } 586 587 do { 588 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 589 &i2c_dev->timing); 590 if (ret) { 591 dev_err(i2c_dev->dev, 592 "failed to compute I2C timings.\n"); 593 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) { 594 i2c_dev->speed--; 595 setup->speed = i2c_dev->speed; 596 setup->speed_freq = 597 i2c_specs[setup->speed].rate; 598 dev_warn(i2c_dev->dev, 599 "downgrade I2C Speed Freq to (%i)\n", 600 i2c_specs[setup->speed].rate); 601 } else { 602 break; 603 } 604 } 605 } while (ret); 606 607 if (ret) { 608 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 609 return ret; 610 } 611 612 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n", 613 setup->speed, setup->speed_freq, setup->clock_src); 614 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 615 setup->rise_time, setup->fall_time); 616 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 617 (setup->analog_filter ? "On" : "Off"), setup->dnf); 618 619 return 0; 620 } 621 622 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 623 { 624 void __iomem *base = i2c_dev->base; 625 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 626 627 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 628 } 629 630 static void stm32f7_i2c_dma_callback(void *arg) 631 { 632 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 633 struct stm32_i2c_dma *dma = i2c_dev->dma; 634 struct device *dev = dma->chan_using->device->dev; 635 636 stm32f7_i2c_disable_dma_req(i2c_dev); 637 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 638 complete(&dma->dma_complete); 639 } 640 641 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 642 { 643 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 644 u32 timing = 0; 645 646 /* Timing settings */ 647 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 648 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 649 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 650 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 651 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 652 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 653 654 /* Enable I2C */ 655 if (i2c_dev->setup.analog_filter) 656 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 657 STM32F7_I2C_CR1_ANFOFF); 658 else 659 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 660 STM32F7_I2C_CR1_ANFOFF); 661 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 662 STM32F7_I2C_CR1_PE); 663 } 664 665 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 666 { 667 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 668 void __iomem *base = i2c_dev->base; 669 670 if (f7_msg->count) { 671 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 672 f7_msg->count--; 673 } 674 } 675 676 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 677 { 678 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 679 void __iomem *base = i2c_dev->base; 680 681 if (f7_msg->count) { 682 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 683 f7_msg->count--; 684 } else { 685 /* Flush RX buffer has no data is expected */ 686 readb_relaxed(base + STM32F7_I2C_RXDR); 687 } 688 } 689 690 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 691 { 692 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 693 u32 cr2; 694 695 if (i2c_dev->use_dma) 696 f7_msg->count -= STM32F7_I2C_MAX_LEN; 697 698 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 699 700 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 701 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 702 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 703 } else { 704 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 705 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 706 } 707 708 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 709 } 710 711 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 712 { 713 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 714 u32 cr2; 715 u8 *val; 716 717 /* 718 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 719 * data received inform us how many data will follow. 720 */ 721 stm32f7_i2c_read_rx_data(i2c_dev); 722 723 /* 724 * Update NBYTES with the value read to continue the transfer 725 */ 726 val = f7_msg->buf - sizeof(u8); 727 f7_msg->count = *val; 728 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 729 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 730 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 731 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 732 } 733 734 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 735 { 736 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 737 738 dev_info(i2c_dev->dev, "Trying to recover bus\n"); 739 740 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 741 STM32F7_I2C_CR1_PE); 742 743 stm32f7_i2c_hw_config(i2c_dev); 744 745 return 0; 746 } 747 748 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 749 { 750 u32 status; 751 int ret; 752 753 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 754 status, 755 !(status & STM32F7_I2C_ISR_BUSY), 756 10, 1000); 757 if (!ret) 758 return 0; 759 760 dev_info(i2c_dev->dev, "bus busy\n"); 761 762 ret = stm32f7_i2c_release_bus(&i2c_dev->adap); 763 if (ret) { 764 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); 765 return ret; 766 } 767 768 return -EBUSY; 769 } 770 771 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 772 struct i2c_msg *msg) 773 { 774 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 775 void __iomem *base = i2c_dev->base; 776 u32 cr1, cr2; 777 int ret; 778 779 f7_msg->addr = msg->addr; 780 f7_msg->buf = msg->buf; 781 f7_msg->count = msg->len; 782 f7_msg->result = 0; 783 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 784 785 reinit_completion(&i2c_dev->complete); 786 787 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 788 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 789 790 /* Set transfer direction */ 791 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 792 if (msg->flags & I2C_M_RD) 793 cr2 |= STM32F7_I2C_CR2_RD_WRN; 794 795 /* Set slave address */ 796 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 797 if (msg->flags & I2C_M_TEN) { 798 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 799 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 800 cr2 |= STM32F7_I2C_CR2_ADD10; 801 } else { 802 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 803 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 804 } 805 806 /* Set nb bytes to transfer and reload if needed */ 807 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 808 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 809 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 810 cr2 |= STM32F7_I2C_CR2_RELOAD; 811 } else { 812 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 813 } 814 815 /* Enable NACK, STOP, error and transfer complete interrupts */ 816 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 817 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 818 819 /* Clear DMA req and TX/RX interrupt */ 820 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 821 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 822 823 /* Configure DMA or enable RX/TX interrupt */ 824 i2c_dev->use_dma = false; 825 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 826 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 827 msg->flags & I2C_M_RD, 828 f7_msg->count, f7_msg->buf, 829 stm32f7_i2c_dma_callback, 830 i2c_dev); 831 if (!ret) 832 i2c_dev->use_dma = true; 833 else 834 dev_warn(i2c_dev->dev, "can't use DMA\n"); 835 } 836 837 if (!i2c_dev->use_dma) { 838 if (msg->flags & I2C_M_RD) 839 cr1 |= STM32F7_I2C_CR1_RXIE; 840 else 841 cr1 |= STM32F7_I2C_CR1_TXIE; 842 } else { 843 if (msg->flags & I2C_M_RD) 844 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 845 else 846 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 847 } 848 849 /* Configure Start/Repeated Start */ 850 cr2 |= STM32F7_I2C_CR2_START; 851 852 i2c_dev->master_mode = true; 853 854 /* Write configurations registers */ 855 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 856 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 857 } 858 859 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 860 unsigned short flags, u8 command, 861 union i2c_smbus_data *data) 862 { 863 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 864 struct device *dev = i2c_dev->dev; 865 void __iomem *base = i2c_dev->base; 866 u32 cr1, cr2; 867 int i, ret; 868 869 f7_msg->result = 0; 870 reinit_completion(&i2c_dev->complete); 871 872 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 873 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 874 875 /* Set transfer direction */ 876 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 877 if (f7_msg->read_write) 878 cr2 |= STM32F7_I2C_CR2_RD_WRN; 879 880 /* Set slave address */ 881 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 882 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 883 884 f7_msg->smbus_buf[0] = command; 885 switch (f7_msg->size) { 886 case I2C_SMBUS_QUICK: 887 f7_msg->stop = true; 888 f7_msg->count = 0; 889 break; 890 case I2C_SMBUS_BYTE: 891 f7_msg->stop = true; 892 f7_msg->count = 1; 893 break; 894 case I2C_SMBUS_BYTE_DATA: 895 if (f7_msg->read_write) { 896 f7_msg->stop = false; 897 f7_msg->count = 1; 898 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 899 } else { 900 f7_msg->stop = true; 901 f7_msg->count = 2; 902 f7_msg->smbus_buf[1] = data->byte; 903 } 904 break; 905 case I2C_SMBUS_WORD_DATA: 906 if (f7_msg->read_write) { 907 f7_msg->stop = false; 908 f7_msg->count = 1; 909 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 910 } else { 911 f7_msg->stop = true; 912 f7_msg->count = 3; 913 f7_msg->smbus_buf[1] = data->word & 0xff; 914 f7_msg->smbus_buf[2] = data->word >> 8; 915 } 916 break; 917 case I2C_SMBUS_BLOCK_DATA: 918 if (f7_msg->read_write) { 919 f7_msg->stop = false; 920 f7_msg->count = 1; 921 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 922 } else { 923 f7_msg->stop = true; 924 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 925 !data->block[0]) { 926 dev_err(dev, "Invalid block write size %d\n", 927 data->block[0]); 928 return -EINVAL; 929 } 930 f7_msg->count = data->block[0] + 2; 931 for (i = 1; i < f7_msg->count; i++) 932 f7_msg->smbus_buf[i] = data->block[i - 1]; 933 } 934 break; 935 case I2C_SMBUS_PROC_CALL: 936 f7_msg->stop = false; 937 f7_msg->count = 3; 938 f7_msg->smbus_buf[1] = data->word & 0xff; 939 f7_msg->smbus_buf[2] = data->word >> 8; 940 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 941 f7_msg->read_write = I2C_SMBUS_READ; 942 break; 943 case I2C_SMBUS_BLOCK_PROC_CALL: 944 f7_msg->stop = false; 945 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 946 dev_err(dev, "Invalid block write size %d\n", 947 data->block[0]); 948 return -EINVAL; 949 } 950 f7_msg->count = data->block[0] + 2; 951 for (i = 1; i < f7_msg->count; i++) 952 f7_msg->smbus_buf[i] = data->block[i - 1]; 953 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 954 f7_msg->read_write = I2C_SMBUS_READ; 955 break; 956 default: 957 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 958 return -EOPNOTSUPP; 959 } 960 961 f7_msg->buf = f7_msg->smbus_buf; 962 963 /* Configure PEC */ 964 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 965 cr1 |= STM32F7_I2C_CR1_PECEN; 966 cr2 |= STM32F7_I2C_CR2_PECBYTE; 967 if (!f7_msg->read_write) 968 f7_msg->count++; 969 } else { 970 cr1 &= ~STM32F7_I2C_CR1_PECEN; 971 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 972 } 973 974 /* Set number of bytes to be transferred */ 975 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 976 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 977 978 /* Enable NACK, STOP, error and transfer complete interrupts */ 979 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 980 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 981 982 /* Clear DMA req and TX/RX interrupt */ 983 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 984 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 985 986 /* Configure DMA or enable RX/TX interrupt */ 987 i2c_dev->use_dma = false; 988 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 989 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 990 cr2 & STM32F7_I2C_CR2_RD_WRN, 991 f7_msg->count, f7_msg->buf, 992 stm32f7_i2c_dma_callback, 993 i2c_dev); 994 if (!ret) 995 i2c_dev->use_dma = true; 996 else 997 dev_warn(i2c_dev->dev, "can't use DMA\n"); 998 } 999 1000 if (!i2c_dev->use_dma) { 1001 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1002 cr1 |= STM32F7_I2C_CR1_RXIE; 1003 else 1004 cr1 |= STM32F7_I2C_CR1_TXIE; 1005 } else { 1006 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1007 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1008 else 1009 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1010 } 1011 1012 /* Set Start bit */ 1013 cr2 |= STM32F7_I2C_CR2_START; 1014 1015 i2c_dev->master_mode = true; 1016 1017 /* Write configurations registers */ 1018 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1019 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1020 1021 return 0; 1022 } 1023 1024 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1025 { 1026 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1027 void __iomem *base = i2c_dev->base; 1028 u32 cr1, cr2; 1029 int ret; 1030 1031 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1032 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1033 1034 /* Set transfer direction */ 1035 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1036 1037 switch (f7_msg->size) { 1038 case I2C_SMBUS_BYTE_DATA: 1039 f7_msg->count = 1; 1040 break; 1041 case I2C_SMBUS_WORD_DATA: 1042 case I2C_SMBUS_PROC_CALL: 1043 f7_msg->count = 2; 1044 break; 1045 case I2C_SMBUS_BLOCK_DATA: 1046 case I2C_SMBUS_BLOCK_PROC_CALL: 1047 f7_msg->count = 1; 1048 cr2 |= STM32F7_I2C_CR2_RELOAD; 1049 break; 1050 } 1051 1052 f7_msg->buf = f7_msg->smbus_buf; 1053 f7_msg->stop = true; 1054 1055 /* Add one byte for PEC if needed */ 1056 if (cr1 & STM32F7_I2C_CR1_PECEN) 1057 f7_msg->count++; 1058 1059 /* Set number of bytes to be transferred */ 1060 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1061 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1062 1063 /* 1064 * Configure RX/TX interrupt: 1065 */ 1066 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1067 cr1 |= STM32F7_I2C_CR1_RXIE; 1068 1069 /* 1070 * Configure DMA or enable RX/TX interrupt: 1071 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1072 * dma as we don't know in advance how many data will be received 1073 */ 1074 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1075 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1076 1077 i2c_dev->use_dma = false; 1078 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1079 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1080 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1081 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1082 cr2 & STM32F7_I2C_CR2_RD_WRN, 1083 f7_msg->count, f7_msg->buf, 1084 stm32f7_i2c_dma_callback, 1085 i2c_dev); 1086 1087 if (!ret) 1088 i2c_dev->use_dma = true; 1089 else 1090 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1091 } 1092 1093 if (!i2c_dev->use_dma) 1094 cr1 |= STM32F7_I2C_CR1_RXIE; 1095 else 1096 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1097 1098 /* Configure Repeated Start */ 1099 cr2 |= STM32F7_I2C_CR2_START; 1100 1101 /* Write configurations registers */ 1102 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1103 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1104 } 1105 1106 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1107 { 1108 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1109 u8 count, internal_pec, received_pec; 1110 1111 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1112 1113 switch (f7_msg->size) { 1114 case I2C_SMBUS_BYTE: 1115 case I2C_SMBUS_BYTE_DATA: 1116 received_pec = f7_msg->smbus_buf[1]; 1117 break; 1118 case I2C_SMBUS_WORD_DATA: 1119 case I2C_SMBUS_PROC_CALL: 1120 received_pec = f7_msg->smbus_buf[2]; 1121 break; 1122 case I2C_SMBUS_BLOCK_DATA: 1123 case I2C_SMBUS_BLOCK_PROC_CALL: 1124 count = f7_msg->smbus_buf[0]; 1125 received_pec = f7_msg->smbus_buf[count]; 1126 break; 1127 default: 1128 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1129 return -EINVAL; 1130 } 1131 1132 if (internal_pec != received_pec) { 1133 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1134 internal_pec, received_pec); 1135 return -EBADMSG; 1136 } 1137 1138 return 0; 1139 } 1140 1141 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1142 { 1143 u32 addr; 1144 1145 if (!slave) 1146 return false; 1147 1148 if (slave->flags & I2C_CLIENT_TEN) { 1149 /* 1150 * For 10-bit addr, addcode = 11110XY with 1151 * X = Bit 9 of slave address 1152 * Y = Bit 8 of slave address 1153 */ 1154 addr = slave->addr >> 8; 1155 addr |= 0x78; 1156 if (addr == addcode) 1157 return true; 1158 } else { 1159 addr = slave->addr & 0x7f; 1160 if (addr == addcode) 1161 return true; 1162 } 1163 1164 return false; 1165 } 1166 1167 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1168 { 1169 struct i2c_client *slave = i2c_dev->slave_running; 1170 void __iomem *base = i2c_dev->base; 1171 u32 mask; 1172 u8 value = 0; 1173 1174 if (i2c_dev->slave_dir) { 1175 /* Notify i2c slave that new read transfer is starting */ 1176 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1177 1178 /* 1179 * Disable slave TX config in case of I2C combined message 1180 * (I2C Write followed by I2C Read) 1181 */ 1182 mask = STM32F7_I2C_CR2_RELOAD; 1183 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1184 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1185 STM32F7_I2C_CR1_TCIE; 1186 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1187 1188 /* Enable TX empty, STOP, NACK interrupts */ 1189 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1190 STM32F7_I2C_CR1_TXIE; 1191 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1192 1193 } else { 1194 /* Notify i2c slave that new write transfer is starting */ 1195 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1196 1197 /* Set reload mode to be able to ACK/NACK each received byte */ 1198 mask = STM32F7_I2C_CR2_RELOAD; 1199 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1200 1201 /* 1202 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1203 * Set Slave Byte Control to be able to ACK/NACK each data 1204 * byte received 1205 */ 1206 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1207 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1208 STM32F7_I2C_CR1_TCIE; 1209 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1210 } 1211 } 1212 1213 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1214 { 1215 void __iomem *base = i2c_dev->base; 1216 u32 isr, addcode, dir, mask; 1217 int i; 1218 1219 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1220 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1221 dir = isr & STM32F7_I2C_ISR_DIR; 1222 1223 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1224 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1225 i2c_dev->slave_running = i2c_dev->slave[i]; 1226 i2c_dev->slave_dir = dir; 1227 1228 /* Start I2C slave processing */ 1229 stm32f7_i2c_slave_start(i2c_dev); 1230 1231 /* Clear ADDR flag */ 1232 mask = STM32F7_I2C_ICR_ADDRCF; 1233 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1234 break; 1235 } 1236 } 1237 } 1238 1239 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1240 struct i2c_client *slave, int *id) 1241 { 1242 int i; 1243 1244 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1245 if (i2c_dev->slave[i] == slave) { 1246 *id = i; 1247 return 0; 1248 } 1249 } 1250 1251 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1252 1253 return -ENODEV; 1254 } 1255 1256 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1257 struct i2c_client *slave, int *id) 1258 { 1259 struct device *dev = i2c_dev->dev; 1260 int i; 1261 1262 /* 1263 * slave[0] supports 7-bit and 10-bit slave address 1264 * slave[1] supports 7-bit slave address only 1265 */ 1266 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1267 if (i == 1 && (slave->flags & I2C_CLIENT_PEC)) 1268 continue; 1269 if (!i2c_dev->slave[i]) { 1270 *id = i; 1271 return 0; 1272 } 1273 } 1274 1275 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1276 1277 return -EINVAL; 1278 } 1279 1280 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1281 { 1282 int i; 1283 1284 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1285 if (i2c_dev->slave[i]) 1286 return true; 1287 } 1288 1289 return false; 1290 } 1291 1292 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1293 { 1294 int i, busy; 1295 1296 busy = 0; 1297 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1298 if (i2c_dev->slave[i]) 1299 busy++; 1300 } 1301 1302 return i == busy; 1303 } 1304 1305 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev) 1306 { 1307 void __iomem *base = i2c_dev->base; 1308 u32 cr2, status, mask; 1309 u8 val; 1310 int ret; 1311 1312 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1313 1314 /* Slave transmitter mode */ 1315 if (status & STM32F7_I2C_ISR_TXIS) { 1316 i2c_slave_event(i2c_dev->slave_running, 1317 I2C_SLAVE_READ_PROCESSED, 1318 &val); 1319 1320 /* Write data byte */ 1321 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1322 } 1323 1324 /* Transfer Complete Reload for Slave receiver mode */ 1325 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1326 /* 1327 * Read data byte then set NBYTES to receive next byte or NACK 1328 * the current received byte 1329 */ 1330 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1331 ret = i2c_slave_event(i2c_dev->slave_running, 1332 I2C_SLAVE_WRITE_RECEIVED, 1333 &val); 1334 if (!ret) { 1335 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1336 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1337 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1338 } else { 1339 mask = STM32F7_I2C_CR2_NACK; 1340 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1341 } 1342 } 1343 1344 /* NACK received */ 1345 if (status & STM32F7_I2C_ISR_NACKF) { 1346 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1347 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1348 } 1349 1350 /* STOP received */ 1351 if (status & STM32F7_I2C_ISR_STOPF) { 1352 /* Disable interrupts */ 1353 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1354 1355 if (i2c_dev->slave_dir) { 1356 /* 1357 * Flush TX buffer in order to not used the byte in 1358 * TXDR for the next transfer 1359 */ 1360 mask = STM32F7_I2C_ISR_TXE; 1361 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1362 } 1363 1364 /* Clear STOP flag */ 1365 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1366 1367 /* Notify i2c slave that a STOP flag has been detected */ 1368 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1369 1370 i2c_dev->slave_running = NULL; 1371 } 1372 1373 /* Address match received */ 1374 if (status & STM32F7_I2C_ISR_ADDR) 1375 stm32f7_i2c_slave_addr(i2c_dev); 1376 1377 return IRQ_HANDLED; 1378 } 1379 1380 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1381 { 1382 struct stm32f7_i2c_dev *i2c_dev = data; 1383 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1384 void __iomem *base = i2c_dev->base; 1385 u32 status, mask; 1386 int ret = IRQ_HANDLED; 1387 1388 /* Check if the interrupt if for a slave device */ 1389 if (!i2c_dev->master_mode) { 1390 ret = stm32f7_i2c_slave_isr_event(i2c_dev); 1391 return ret; 1392 } 1393 1394 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1395 1396 /* Tx empty */ 1397 if (status & STM32F7_I2C_ISR_TXIS) 1398 stm32f7_i2c_write_tx_data(i2c_dev); 1399 1400 /* RX not empty */ 1401 if (status & STM32F7_I2C_ISR_RXNE) 1402 stm32f7_i2c_read_rx_data(i2c_dev); 1403 1404 /* NACK received */ 1405 if (status & STM32F7_I2C_ISR_NACKF) { 1406 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1407 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1408 f7_msg->result = -ENXIO; 1409 } 1410 1411 /* STOP detection flag */ 1412 if (status & STM32F7_I2C_ISR_STOPF) { 1413 /* Disable interrupts */ 1414 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1415 mask = STM32F7_I2C_XFER_IRQ_MASK; 1416 else 1417 mask = STM32F7_I2C_ALL_IRQ_MASK; 1418 stm32f7_i2c_disable_irq(i2c_dev, mask); 1419 1420 /* Clear STOP flag */ 1421 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1422 1423 if (i2c_dev->use_dma) { 1424 ret = IRQ_WAKE_THREAD; 1425 } else { 1426 i2c_dev->master_mode = false; 1427 complete(&i2c_dev->complete); 1428 } 1429 } 1430 1431 /* Transfer complete */ 1432 if (status & STM32F7_I2C_ISR_TC) { 1433 if (f7_msg->stop) { 1434 mask = STM32F7_I2C_CR2_STOP; 1435 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1436 } else if (i2c_dev->use_dma) { 1437 ret = IRQ_WAKE_THREAD; 1438 } else if (f7_msg->smbus) { 1439 stm32f7_i2c_smbus_rep_start(i2c_dev); 1440 } else { 1441 i2c_dev->msg_id++; 1442 i2c_dev->msg++; 1443 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1444 } 1445 } 1446 1447 if (status & STM32F7_I2C_ISR_TCR) { 1448 if (f7_msg->smbus) 1449 stm32f7_i2c_smbus_reload(i2c_dev); 1450 else 1451 stm32f7_i2c_reload(i2c_dev); 1452 } 1453 1454 return ret; 1455 } 1456 1457 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1458 { 1459 struct stm32f7_i2c_dev *i2c_dev = data; 1460 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1461 struct stm32_i2c_dma *dma = i2c_dev->dma; 1462 u32 status; 1463 int ret; 1464 1465 /* 1466 * Wait for dma transfer completion before sending next message or 1467 * notity the end of xfer to the client 1468 */ 1469 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1470 if (!ret) { 1471 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1472 stm32f7_i2c_disable_dma_req(i2c_dev); 1473 dmaengine_terminate_all(dma->chan_using); 1474 f7_msg->result = -ETIMEDOUT; 1475 } 1476 1477 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1478 1479 if (status & STM32F7_I2C_ISR_TC) { 1480 if (f7_msg->smbus) { 1481 stm32f7_i2c_smbus_rep_start(i2c_dev); 1482 } else { 1483 i2c_dev->msg_id++; 1484 i2c_dev->msg++; 1485 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1486 } 1487 } else { 1488 i2c_dev->master_mode = false; 1489 complete(&i2c_dev->complete); 1490 } 1491 1492 return IRQ_HANDLED; 1493 } 1494 1495 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data) 1496 { 1497 struct stm32f7_i2c_dev *i2c_dev = data; 1498 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1499 void __iomem *base = i2c_dev->base; 1500 struct device *dev = i2c_dev->dev; 1501 struct stm32_i2c_dma *dma = i2c_dev->dma; 1502 u32 mask, status; 1503 1504 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1505 1506 /* Bus error */ 1507 if (status & STM32F7_I2C_ISR_BERR) { 1508 dev_err(dev, "<%s>: Bus error\n", __func__); 1509 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1510 stm32f7_i2c_release_bus(&i2c_dev->adap); 1511 f7_msg->result = -EIO; 1512 } 1513 1514 /* Arbitration loss */ 1515 if (status & STM32F7_I2C_ISR_ARLO) { 1516 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__); 1517 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1518 f7_msg->result = -EAGAIN; 1519 } 1520 1521 if (status & STM32F7_I2C_ISR_PECERR) { 1522 dev_err(dev, "<%s>: PEC error in reception\n", __func__); 1523 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1524 f7_msg->result = -EINVAL; 1525 } 1526 1527 /* Disable interrupts */ 1528 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1529 mask = STM32F7_I2C_XFER_IRQ_MASK; 1530 else 1531 mask = STM32F7_I2C_ALL_IRQ_MASK; 1532 stm32f7_i2c_disable_irq(i2c_dev, mask); 1533 1534 /* Disable dma */ 1535 if (i2c_dev->use_dma) { 1536 stm32f7_i2c_disable_dma_req(i2c_dev); 1537 dmaengine_terminate_all(dma->chan_using); 1538 } 1539 1540 i2c_dev->master_mode = false; 1541 complete(&i2c_dev->complete); 1542 1543 return IRQ_HANDLED; 1544 } 1545 1546 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1547 struct i2c_msg msgs[], int num) 1548 { 1549 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1550 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1551 struct stm32_i2c_dma *dma = i2c_dev->dma; 1552 unsigned long time_left; 1553 int ret; 1554 1555 i2c_dev->msg = msgs; 1556 i2c_dev->msg_num = num; 1557 i2c_dev->msg_id = 0; 1558 f7_msg->smbus = false; 1559 1560 ret = pm_runtime_get_sync(i2c_dev->dev); 1561 if (ret < 0) 1562 return ret; 1563 1564 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1565 if (ret) 1566 goto pm_free; 1567 1568 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1569 1570 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1571 i2c_dev->adap.timeout); 1572 ret = f7_msg->result; 1573 1574 if (!time_left) { 1575 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1576 i2c_dev->msg->addr); 1577 if (i2c_dev->use_dma) 1578 dmaengine_terminate_all(dma->chan_using); 1579 ret = -ETIMEDOUT; 1580 } 1581 1582 pm_free: 1583 pm_runtime_mark_last_busy(i2c_dev->dev); 1584 pm_runtime_put_autosuspend(i2c_dev->dev); 1585 1586 return (ret < 0) ? ret : num; 1587 } 1588 1589 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1590 unsigned short flags, char read_write, 1591 u8 command, int size, 1592 union i2c_smbus_data *data) 1593 { 1594 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1595 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1596 struct stm32_i2c_dma *dma = i2c_dev->dma; 1597 struct device *dev = i2c_dev->dev; 1598 unsigned long timeout; 1599 int i, ret; 1600 1601 f7_msg->addr = addr; 1602 f7_msg->size = size; 1603 f7_msg->read_write = read_write; 1604 f7_msg->smbus = true; 1605 1606 ret = pm_runtime_get_sync(dev); 1607 if (ret < 0) 1608 return ret; 1609 1610 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1611 if (ret) 1612 goto pm_free; 1613 1614 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1615 if (ret) 1616 goto pm_free; 1617 1618 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1619 i2c_dev->adap.timeout); 1620 ret = f7_msg->result; 1621 if (ret) 1622 goto pm_free; 1623 1624 if (!timeout) { 1625 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1626 if (i2c_dev->use_dma) 1627 dmaengine_terminate_all(dma->chan_using); 1628 ret = -ETIMEDOUT; 1629 goto pm_free; 1630 } 1631 1632 /* Check PEC */ 1633 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1634 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1635 if (ret) 1636 goto pm_free; 1637 } 1638 1639 if (read_write && size != I2C_SMBUS_QUICK) { 1640 switch (size) { 1641 case I2C_SMBUS_BYTE: 1642 case I2C_SMBUS_BYTE_DATA: 1643 data->byte = f7_msg->smbus_buf[0]; 1644 break; 1645 case I2C_SMBUS_WORD_DATA: 1646 case I2C_SMBUS_PROC_CALL: 1647 data->word = f7_msg->smbus_buf[0] | 1648 (f7_msg->smbus_buf[1] << 8); 1649 break; 1650 case I2C_SMBUS_BLOCK_DATA: 1651 case I2C_SMBUS_BLOCK_PROC_CALL: 1652 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1653 data->block[i] = f7_msg->smbus_buf[i]; 1654 break; 1655 default: 1656 dev_err(dev, "Unsupported smbus transaction\n"); 1657 ret = -EINVAL; 1658 } 1659 } 1660 1661 pm_free: 1662 pm_runtime_mark_last_busy(dev); 1663 pm_runtime_put_autosuspend(dev); 1664 return ret; 1665 } 1666 1667 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1668 { 1669 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1670 void __iomem *base = i2c_dev->base; 1671 struct device *dev = i2c_dev->dev; 1672 u32 oar1, oar2, mask; 1673 int id, ret; 1674 1675 if (slave->flags & I2C_CLIENT_PEC) { 1676 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1677 return -EINVAL; 1678 } 1679 1680 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1681 dev_err(dev, "Too much slave registered\n"); 1682 return -EBUSY; 1683 } 1684 1685 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1686 if (ret) 1687 return ret; 1688 1689 ret = pm_runtime_get_sync(dev); 1690 if (ret < 0) 1691 return ret; 1692 1693 if (id == 0) { 1694 /* Configure Own Address 1 */ 1695 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1696 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1697 if (slave->flags & I2C_CLIENT_TEN) { 1698 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1699 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1700 } else { 1701 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1702 } 1703 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1704 i2c_dev->slave[id] = slave; 1705 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1706 } else if (id == 1) { 1707 /* Configure Own Address 2 */ 1708 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1709 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1710 if (slave->flags & I2C_CLIENT_TEN) { 1711 ret = -EOPNOTSUPP; 1712 goto pm_free; 1713 } 1714 1715 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1716 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1717 i2c_dev->slave[id] = slave; 1718 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1719 } else { 1720 ret = -ENODEV; 1721 goto pm_free; 1722 } 1723 1724 /* Enable ACK */ 1725 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1726 1727 /* Enable Address match interrupt, error interrupt and enable I2C */ 1728 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1729 STM32F7_I2C_CR1_PE; 1730 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1731 1732 ret = 0; 1733 pm_free: 1734 pm_runtime_mark_last_busy(dev); 1735 pm_runtime_put_autosuspend(dev); 1736 1737 return ret; 1738 } 1739 1740 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1741 { 1742 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1743 void __iomem *base = i2c_dev->base; 1744 u32 mask; 1745 int id, ret; 1746 1747 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1748 if (ret) 1749 return ret; 1750 1751 WARN_ON(!i2c_dev->slave[id]); 1752 1753 ret = pm_runtime_get_sync(i2c_dev->dev); 1754 if (ret < 0) 1755 return ret; 1756 1757 if (id == 0) { 1758 mask = STM32F7_I2C_OAR1_OA1EN; 1759 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1760 } else { 1761 mask = STM32F7_I2C_OAR2_OA2EN; 1762 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1763 } 1764 1765 i2c_dev->slave[id] = NULL; 1766 1767 if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) 1768 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1769 1770 pm_runtime_mark_last_busy(i2c_dev->dev); 1771 pm_runtime_put_autosuspend(i2c_dev->dev); 1772 1773 return 0; 1774 } 1775 1776 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 1777 struct stm32f7_i2c_dev *i2c_dev) 1778 { 1779 struct device_node *np = pdev->dev.of_node; 1780 int ret; 1781 u32 reg, mask; 1782 1783 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 1784 if (IS_ERR(i2c_dev->regmap)) { 1785 /* Optional */ 1786 return 0; 1787 } 1788 1789 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, ®); 1790 if (ret) 1791 return ret; 1792 1793 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 2, &mask); 1794 if (ret) 1795 return ret; 1796 1797 return regmap_update_bits(i2c_dev->regmap, reg, mask, mask); 1798 } 1799 1800 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 1801 { 1802 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 1803 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 1804 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 1805 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1806 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC; 1807 } 1808 1809 static struct i2c_algorithm stm32f7_i2c_algo = { 1810 .master_xfer = stm32f7_i2c_xfer, 1811 .smbus_xfer = stm32f7_i2c_smbus_xfer, 1812 .functionality = stm32f7_i2c_func, 1813 .reg_slave = stm32f7_i2c_reg_slave, 1814 .unreg_slave = stm32f7_i2c_unreg_slave, 1815 }; 1816 1817 static int stm32f7_i2c_probe(struct platform_device *pdev) 1818 { 1819 struct device_node *np = pdev->dev.of_node; 1820 struct stm32f7_i2c_dev *i2c_dev; 1821 const struct stm32f7_i2c_setup *setup; 1822 struct resource *res; 1823 u32 irq_error, irq_event, clk_rate, rise_time, fall_time; 1824 struct i2c_adapter *adap; 1825 struct reset_control *rst; 1826 dma_addr_t phy_addr; 1827 int ret; 1828 1829 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1830 if (!i2c_dev) 1831 return -ENOMEM; 1832 1833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1834 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 1835 if (IS_ERR(i2c_dev->base)) 1836 return PTR_ERR(i2c_dev->base); 1837 phy_addr = (dma_addr_t)res->start; 1838 1839 irq_event = irq_of_parse_and_map(np, 0); 1840 if (!irq_event) { 1841 dev_err(&pdev->dev, "IRQ event missing or invalid\n"); 1842 return -EINVAL; 1843 } 1844 1845 irq_error = irq_of_parse_and_map(np, 1); 1846 if (!irq_error) { 1847 dev_err(&pdev->dev, "IRQ error missing or invalid\n"); 1848 return -EINVAL; 1849 } 1850 1851 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 1852 if (IS_ERR(i2c_dev->clk)) { 1853 dev_err(&pdev->dev, "Error: Missing controller clock\n"); 1854 return PTR_ERR(i2c_dev->clk); 1855 } 1856 1857 ret = clk_prepare_enable(i2c_dev->clk); 1858 if (ret) { 1859 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); 1860 return ret; 1861 } 1862 1863 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; 1864 ret = device_property_read_u32(&pdev->dev, "clock-frequency", 1865 &clk_rate); 1866 if (!ret && clk_rate >= 1000000) { 1867 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS; 1868 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 1869 if (ret) 1870 goto clk_free; 1871 } else if (!ret && clk_rate >= 400000) { 1872 i2c_dev->speed = STM32_I2C_SPEED_FAST; 1873 } else if (!ret && clk_rate >= 100000) { 1874 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; 1875 } 1876 1877 rst = devm_reset_control_get(&pdev->dev, NULL); 1878 if (IS_ERR(rst)) { 1879 dev_err(&pdev->dev, "Error: Missing controller reset\n"); 1880 ret = PTR_ERR(rst); 1881 goto clk_free; 1882 } 1883 reset_control_assert(rst); 1884 udelay(2); 1885 reset_control_deassert(rst); 1886 1887 i2c_dev->dev = &pdev->dev; 1888 1889 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 1890 stm32f7_i2c_isr_event, 1891 stm32f7_i2c_isr_event_thread, 1892 IRQF_ONESHOT, 1893 pdev->name, i2c_dev); 1894 if (ret) { 1895 dev_err(&pdev->dev, "Failed to request irq event %i\n", 1896 irq_event); 1897 goto clk_free; 1898 } 1899 1900 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, 1901 pdev->name, i2c_dev); 1902 if (ret) { 1903 dev_err(&pdev->dev, "Failed to request irq error %i\n", 1904 irq_error); 1905 goto clk_free; 1906 } 1907 1908 setup = of_device_get_match_data(&pdev->dev); 1909 if (!setup) { 1910 dev_err(&pdev->dev, "Can't get device data\n"); 1911 ret = -ENODEV; 1912 goto clk_free; 1913 } 1914 i2c_dev->setup = *setup; 1915 1916 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns", 1917 &rise_time); 1918 if (!ret) 1919 i2c_dev->setup.rise_time = rise_time; 1920 1921 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns", 1922 &fall_time); 1923 if (!ret) 1924 i2c_dev->setup.fall_time = fall_time; 1925 1926 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 1927 if (ret) 1928 goto clk_free; 1929 1930 adap = &i2c_dev->adap; 1931 i2c_set_adapdata(adap, i2c_dev); 1932 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 1933 &res->start); 1934 adap->owner = THIS_MODULE; 1935 adap->timeout = 2 * HZ; 1936 adap->retries = 3; 1937 adap->algo = &stm32f7_i2c_algo; 1938 adap->dev.parent = &pdev->dev; 1939 adap->dev.of_node = pdev->dev.of_node; 1940 1941 init_completion(&i2c_dev->complete); 1942 1943 /* Init DMA config if supported */ 1944 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 1945 STM32F7_I2C_TXDR, 1946 STM32F7_I2C_RXDR); 1947 1948 platform_set_drvdata(pdev, i2c_dev); 1949 1950 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 1951 STM32F7_AUTOSUSPEND_DELAY); 1952 pm_runtime_use_autosuspend(i2c_dev->dev); 1953 pm_runtime_set_active(i2c_dev->dev); 1954 pm_runtime_enable(i2c_dev->dev); 1955 1956 pm_runtime_get_noresume(&pdev->dev); 1957 1958 stm32f7_i2c_hw_config(i2c_dev); 1959 1960 ret = i2c_add_adapter(adap); 1961 if (ret) 1962 goto pm_disable; 1963 1964 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 1965 1966 pm_runtime_mark_last_busy(i2c_dev->dev); 1967 pm_runtime_put_autosuspend(i2c_dev->dev); 1968 1969 return 0; 1970 1971 pm_disable: 1972 pm_runtime_put_noidle(i2c_dev->dev); 1973 pm_runtime_disable(i2c_dev->dev); 1974 pm_runtime_set_suspended(i2c_dev->dev); 1975 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 1976 1977 clk_free: 1978 clk_disable_unprepare(i2c_dev->clk); 1979 1980 return ret; 1981 } 1982 1983 static int stm32f7_i2c_remove(struct platform_device *pdev) 1984 { 1985 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1986 1987 if (i2c_dev->dma) { 1988 stm32_i2c_dma_free(i2c_dev->dma); 1989 i2c_dev->dma = NULL; 1990 } 1991 1992 i2c_del_adapter(&i2c_dev->adap); 1993 pm_runtime_get_sync(i2c_dev->dev); 1994 1995 clk_disable_unprepare(i2c_dev->clk); 1996 1997 pm_runtime_put_noidle(i2c_dev->dev); 1998 pm_runtime_disable(i2c_dev->dev); 1999 pm_runtime_set_suspended(i2c_dev->dev); 2000 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2001 2002 return 0; 2003 } 2004 2005 #ifdef CONFIG_PM 2006 static int stm32f7_i2c_runtime_suspend(struct device *dev) 2007 { 2008 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2009 2010 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2011 clk_disable_unprepare(i2c_dev->clk); 2012 2013 return 0; 2014 } 2015 2016 static int stm32f7_i2c_runtime_resume(struct device *dev) 2017 { 2018 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2019 int ret; 2020 2021 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2022 ret = clk_prepare_enable(i2c_dev->clk); 2023 if (ret) { 2024 dev_err(dev, "failed to prepare_enable clock\n"); 2025 return ret; 2026 } 2027 } 2028 2029 return 0; 2030 } 2031 #endif 2032 2033 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2034 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2035 stm32f7_i2c_runtime_resume, NULL) 2036 }; 2037 2038 static const struct of_device_id stm32f7_i2c_match[] = { 2039 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2040 {}, 2041 }; 2042 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2043 2044 static struct platform_driver stm32f7_i2c_driver = { 2045 .driver = { 2046 .name = "stm32f7-i2c", 2047 .of_match_table = stm32f7_i2c_match, 2048 .pm = &stm32f7_i2c_pm_ops, 2049 }, 2050 .probe = stm32f7_i2c_probe, 2051 .remove = stm32f7_i2c_remove, 2052 }; 2053 2054 module_platform_driver(stm32f7_i2c_driver); 2055 2056 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2057 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2058 MODULE_LICENSE("GPL v2"); 2059