1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/i2c-smbus.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/pm_wakeirq.h> 34 #include <linux/regmap.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 38 #include "i2c-stm32.h" 39 40 /* STM32F7 I2C registers */ 41 #define STM32F7_I2C_CR1 0x00 42 #define STM32F7_I2C_CR2 0x04 43 #define STM32F7_I2C_OAR1 0x08 44 #define STM32F7_I2C_OAR2 0x0C 45 #define STM32F7_I2C_PECR 0x20 46 #define STM32F7_I2C_TIMINGR 0x10 47 #define STM32F7_I2C_ISR 0x18 48 #define STM32F7_I2C_ICR 0x1C 49 #define STM32F7_I2C_RXDR 0x24 50 #define STM32F7_I2C_TXDR 0x28 51 52 /* STM32F7 I2C control 1 */ 53 #define STM32F7_I2C_CR1_PECEN BIT(23) 54 #define STM32F7_I2C_CR1_ALERTEN BIT(22) 55 #define STM32F7_I2C_CR1_SMBHEN BIT(20) 56 #define STM32F7_I2C_CR1_WUPEN BIT(18) 57 #define STM32F7_I2C_CR1_SBC BIT(16) 58 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 59 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 60 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 61 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8) 62 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8) 63 #define STM32F7_I2C_CR1_ERRIE BIT(7) 64 #define STM32F7_I2C_CR1_TCIE BIT(6) 65 #define STM32F7_I2C_CR1_STOPIE BIT(5) 66 #define STM32F7_I2C_CR1_NACKIE BIT(4) 67 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 68 #define STM32F7_I2C_CR1_RXIE BIT(2) 69 #define STM32F7_I2C_CR1_TXIE BIT(1) 70 #define STM32F7_I2C_CR1_PE BIT(0) 71 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 72 | STM32F7_I2C_CR1_TCIE \ 73 | STM32F7_I2C_CR1_STOPIE \ 74 | STM32F7_I2C_CR1_NACKIE \ 75 | STM32F7_I2C_CR1_RXIE \ 76 | STM32F7_I2C_CR1_TXIE) 77 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 78 | STM32F7_I2C_CR1_STOPIE \ 79 | STM32F7_I2C_CR1_NACKIE \ 80 | STM32F7_I2C_CR1_RXIE \ 81 | STM32F7_I2C_CR1_TXIE) 82 83 /* STM32F7 I2C control 2 */ 84 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 85 #define STM32F7_I2C_CR2_RELOAD BIT(24) 86 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 87 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 88 #define STM32F7_I2C_CR2_NACK BIT(15) 89 #define STM32F7_I2C_CR2_STOP BIT(14) 90 #define STM32F7_I2C_CR2_START BIT(13) 91 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 92 #define STM32F7_I2C_CR2_ADD10 BIT(11) 93 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 94 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 95 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 96 STM32F7_I2C_CR2_SADD10_MASK)) 97 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 98 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 99 100 /* STM32F7 I2C Own Address 1 */ 101 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 102 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 103 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 104 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 105 STM32F7_I2C_OAR1_OA1_10_MASK)) 106 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 107 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 108 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 109 | STM32F7_I2C_OAR1_OA1_10_MASK \ 110 | STM32F7_I2C_OAR1_OA1EN \ 111 | STM32F7_I2C_OAR1_OA1MODE) 112 113 /* STM32F7 I2C Own Address 2 */ 114 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 115 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 116 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 117 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 118 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 119 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 120 | STM32F7_I2C_OAR2_OA2_7_MASK \ 121 | STM32F7_I2C_OAR2_OA2EN) 122 123 /* STM32F7 I2C Interrupt Status */ 124 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 127 #define STM32F7_I2C_ISR_DIR BIT(16) 128 #define STM32F7_I2C_ISR_BUSY BIT(15) 129 #define STM32F7_I2C_ISR_ALERT BIT(13) 130 #define STM32F7_I2C_ISR_PECERR BIT(11) 131 #define STM32F7_I2C_ISR_ARLO BIT(9) 132 #define STM32F7_I2C_ISR_BERR BIT(8) 133 #define STM32F7_I2C_ISR_TCR BIT(7) 134 #define STM32F7_I2C_ISR_TC BIT(6) 135 #define STM32F7_I2C_ISR_STOPF BIT(5) 136 #define STM32F7_I2C_ISR_NACKF BIT(4) 137 #define STM32F7_I2C_ISR_ADDR BIT(3) 138 #define STM32F7_I2C_ISR_RXNE BIT(2) 139 #define STM32F7_I2C_ISR_TXIS BIT(1) 140 #define STM32F7_I2C_ISR_TXE BIT(0) 141 142 /* STM32F7 I2C Interrupt Clear */ 143 #define STM32F7_I2C_ICR_ALERTCF BIT(13) 144 #define STM32F7_I2C_ICR_PECCF BIT(11) 145 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 146 #define STM32F7_I2C_ICR_BERRCF BIT(8) 147 #define STM32F7_I2C_ICR_STOPCF BIT(5) 148 #define STM32F7_I2C_ICR_NACKCF BIT(4) 149 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 150 151 /* STM32F7 I2C Timing */ 152 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 153 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 154 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 155 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 156 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 157 158 #define STM32F7_I2C_MAX_LEN 0xff 159 #define STM32F7_I2C_DMA_LEN_MIN 0x16 160 enum { 161 STM32F7_SLAVE_HOSTNOTIFY, 162 STM32F7_SLAVE_7_10_BITS_ADDR, 163 STM32F7_SLAVE_7_BITS_ADDR, 164 STM32F7_I2C_MAX_SLAVE 165 }; 166 167 #define STM32F7_I2C_DNF_DEFAULT 0 168 #define STM32F7_I2C_DNF_MAX 15 169 170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 172 173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 175 176 #define STM32F7_PRESC_MAX BIT(4) 177 #define STM32F7_SCLDEL_MAX BIT(4) 178 #define STM32F7_SDADEL_MAX BIT(4) 179 #define STM32F7_SCLH_MAX BIT(8) 180 #define STM32F7_SCLL_MAX BIT(8) 181 182 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 183 184 /** 185 * struct stm32f7_i2c_regs - i2c f7 registers backup 186 * @cr1: Control register 1 187 * @cr2: Control register 2 188 * @oar1: Own address 1 register 189 * @oar2: Own address 2 register 190 * @tmgr: Timing register 191 */ 192 struct stm32f7_i2c_regs { 193 u32 cr1; 194 u32 cr2; 195 u32 oar1; 196 u32 oar2; 197 u32 tmgr; 198 }; 199 200 /** 201 * struct stm32f7_i2c_spec - private i2c specification timing 202 * @rate: I2C bus speed (Hz) 203 * @fall_max: Max fall time of both SDA and SCL signals (ns) 204 * @rise_max: Max rise time of both SDA and SCL signals (ns) 205 * @hddat_min: Min data hold time (ns) 206 * @vddat_max: Max data valid time (ns) 207 * @sudat_min: Min data setup time (ns) 208 * @l_min: Min low period of the SCL clock (ns) 209 * @h_min: Min high period of the SCL clock (ns) 210 */ 211 struct stm32f7_i2c_spec { 212 u32 rate; 213 u32 fall_max; 214 u32 rise_max; 215 u32 hddat_min; 216 u32 vddat_max; 217 u32 sudat_min; 218 u32 l_min; 219 u32 h_min; 220 }; 221 222 /** 223 * struct stm32f7_i2c_setup - private I2C timing setup parameters 224 * @speed_freq: I2C speed frequency (Hz) 225 * @clock_src: I2C clock source frequency (Hz) 226 * @rise_time: Rise time (ns) 227 * @fall_time: Fall time (ns) 228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 229 */ 230 struct stm32f7_i2c_setup { 231 u32 speed_freq; 232 u32 clock_src; 233 u32 rise_time; 234 u32 fall_time; 235 u32 fmp_clr_offset; 236 }; 237 238 /** 239 * struct stm32f7_i2c_timings - private I2C output parameters 240 * @node: List entry 241 * @presc: Prescaler value 242 * @scldel: Data setup time 243 * @sdadel: Data hold time 244 * @sclh: SCL high period (master mode) 245 * @scll: SCL low period (master mode) 246 */ 247 struct stm32f7_i2c_timings { 248 struct list_head node; 249 u8 presc; 250 u8 scldel; 251 u8 sdadel; 252 u8 sclh; 253 u8 scll; 254 }; 255 256 /** 257 * struct stm32f7_i2c_msg - client specific data 258 * @addr: 8-bit or 10-bit slave addr, including r/w bit 259 * @count: number of bytes to be transferred 260 * @buf: data buffer 261 * @result: result of the transfer 262 * @stop: last I2C msg to be sent, i.e. STOP to be generated 263 * @smbus: boolean to know if the I2C IP is used in SMBus mode 264 * @size: type of SMBus protocol 265 * @read_write: direction of SMBus protocol 266 * SMBus block read and SMBus block write - block read process call protocols 267 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 268 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 269 * This buffer has to be 32-bit aligned to be compliant with memory address 270 * register in DMA mode. 271 */ 272 struct stm32f7_i2c_msg { 273 u16 addr; 274 u32 count; 275 u8 *buf; 276 int result; 277 bool stop; 278 bool smbus; 279 int size; 280 char read_write; 281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 282 }; 283 284 /** 285 * struct stm32f7_i2c_alert - SMBus alert specific data 286 * @setup: platform data for the smbus_alert i2c client 287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert 288 * Response Address 289 */ 290 struct stm32f7_i2c_alert { 291 struct i2c_smbus_alert_setup setup; 292 struct i2c_client *ara; 293 }; 294 295 /** 296 * struct stm32f7_i2c_dev - private data of the controller 297 * @adap: I2C adapter for this controller 298 * @dev: device for this controller 299 * @base: virtual memory area 300 * @complete: completion of I2C message 301 * @clk: hw i2c clock 302 * @bus_rate: I2C clock frequency of the controller 303 * @msg: Pointer to data to be written 304 * @msg_num: number of I2C messages to be executed 305 * @msg_id: message identifiant 306 * @f7_msg: customized i2c msg for driver usage 307 * @setup: I2C timing input setup 308 * @timing: I2C computed timings 309 * @slave: list of slave devices registered on the I2C bus 310 * @slave_running: slave device currently used 311 * @backup_regs: backup of i2c controller registers (for suspend/resume) 312 * @slave_dir: transfer direction for the current slave device 313 * @master_mode: boolean to know in which mode the I2C is running (master or 314 * slave) 315 * @dma: dma data 316 * @use_dma: boolean to know if dma is used in the current transfer 317 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 318 * @fmp_sreg: register address for setting Fast Mode Plus bits 319 * @fmp_creg: register address for clearing Fast Mode Plus bits 320 * @fmp_mask: mask for Fast Mode Plus bits in set register 321 * @wakeup_src: boolean to know if the device is a wakeup source 322 * @smbus_mode: states that the controller is configured in SMBus mode 323 * @host_notify_client: SMBus host-notify client 324 * @analog_filter: boolean to indicate enabling of the analog filter 325 * @dnf_dt: value of digital filter requested via dt 326 * @dnf: value of digital filter to apply 327 * @alert: SMBus alert specific data 328 */ 329 struct stm32f7_i2c_dev { 330 struct i2c_adapter adap; 331 struct device *dev; 332 void __iomem *base; 333 struct completion complete; 334 struct clk *clk; 335 unsigned int bus_rate; 336 struct i2c_msg *msg; 337 unsigned int msg_num; 338 unsigned int msg_id; 339 struct stm32f7_i2c_msg f7_msg; 340 struct stm32f7_i2c_setup setup; 341 struct stm32f7_i2c_timings timing; 342 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 343 struct i2c_client *slave_running; 344 struct stm32f7_i2c_regs backup_regs; 345 u32 slave_dir; 346 bool master_mode; 347 struct stm32_i2c_dma *dma; 348 bool use_dma; 349 struct regmap *regmap; 350 u32 fmp_sreg; 351 u32 fmp_creg; 352 u32 fmp_mask; 353 bool wakeup_src; 354 bool smbus_mode; 355 struct i2c_client *host_notify_client; 356 bool analog_filter; 357 u32 dnf_dt; 358 u32 dnf; 359 struct stm32f7_i2c_alert *alert; 360 }; 361 362 /* 363 * All these values are coming from I2C Specification, Version 6.0, 4th of 364 * April 2014. 365 * 366 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 367 * and Fast-mode Plus I2C-bus devices 368 */ 369 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = { 370 { 371 .rate = I2C_MAX_STANDARD_MODE_FREQ, 372 .fall_max = 300, 373 .rise_max = 1000, 374 .hddat_min = 0, 375 .vddat_max = 3450, 376 .sudat_min = 250, 377 .l_min = 4700, 378 .h_min = 4000, 379 }, 380 { 381 .rate = I2C_MAX_FAST_MODE_FREQ, 382 .fall_max = 300, 383 .rise_max = 300, 384 .hddat_min = 0, 385 .vddat_max = 900, 386 .sudat_min = 100, 387 .l_min = 1300, 388 .h_min = 600, 389 }, 390 { 391 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ, 392 .fall_max = 100, 393 .rise_max = 120, 394 .hddat_min = 0, 395 .vddat_max = 450, 396 .sudat_min = 50, 397 .l_min = 500, 398 .h_min = 260, 399 }, 400 }; 401 402 static const struct stm32f7_i2c_setup stm32f7_setup = { 403 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 404 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 405 }; 406 407 static const struct stm32f7_i2c_setup stm32mp15_setup = { 408 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 409 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 410 .fmp_clr_offset = 0x40, 411 }; 412 413 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 414 { 415 writel_relaxed(readl_relaxed(reg) | mask, reg); 416 } 417 418 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 419 { 420 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 421 } 422 423 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 424 { 425 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 426 } 427 428 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate) 429 { 430 int i; 431 432 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++) 433 if (rate <= stm32f7_i2c_specs[i].rate) 434 return &stm32f7_i2c_specs[i]; 435 436 return ERR_PTR(-EINVAL); 437 } 438 439 #define RATE_MIN(rate) ((rate) * 8 / 10) 440 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 441 struct stm32f7_i2c_setup *setup, 442 struct stm32f7_i2c_timings *output) 443 { 444 struct stm32f7_i2c_spec *specs; 445 u32 p_prev = STM32F7_PRESC_MAX; 446 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 447 setup->clock_src); 448 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 449 setup->speed_freq); 450 u32 clk_error_prev = i2cbus; 451 u32 tsync; 452 u32 af_delay_min, af_delay_max; 453 u32 dnf_delay; 454 u32 clk_min, clk_max; 455 int sdadel_min, sdadel_max; 456 int scldel_min; 457 struct stm32f7_i2c_timings *v, *_v, *s; 458 struct list_head solutions; 459 u16 p, l, a, h; 460 int ret = 0; 461 462 specs = stm32f7_get_specs(setup->speed_freq); 463 if (specs == ERR_PTR(-EINVAL)) { 464 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", 465 setup->speed_freq); 466 return -EINVAL; 467 } 468 469 if ((setup->rise_time > specs->rise_max) || 470 (setup->fall_time > specs->fall_max)) { 471 dev_err(i2c_dev->dev, 472 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 473 setup->rise_time, specs->rise_max, 474 setup->fall_time, specs->fall_max); 475 return -EINVAL; 476 } 477 478 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); 479 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { 480 dev_err(i2c_dev->dev, 481 "DNF out of bound %d/%d\n", 482 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); 483 return -EINVAL; 484 } 485 486 /* Analog and Digital Filters */ 487 af_delay_min = 488 (i2c_dev->analog_filter ? 489 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 490 af_delay_max = 491 (i2c_dev->analog_filter ? 492 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 493 dnf_delay = i2c_dev->dnf * i2cclk; 494 495 sdadel_min = specs->hddat_min + setup->fall_time - 496 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; 497 498 sdadel_max = specs->vddat_max - setup->rise_time - 499 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; 500 501 scldel_min = setup->rise_time + specs->sudat_min; 502 503 if (sdadel_min < 0) 504 sdadel_min = 0; 505 if (sdadel_max < 0) 506 sdadel_max = 0; 507 508 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 509 sdadel_min, sdadel_max, scldel_min); 510 511 INIT_LIST_HEAD(&solutions); 512 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 513 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 514 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 515 u32 scldel = (l + 1) * (p + 1) * i2cclk; 516 517 if (scldel < scldel_min) 518 continue; 519 520 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 521 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 522 523 if (((sdadel >= sdadel_min) && 524 (sdadel <= sdadel_max)) && 525 (p != p_prev)) { 526 v = kmalloc(sizeof(*v), GFP_KERNEL); 527 if (!v) { 528 ret = -ENOMEM; 529 goto exit; 530 } 531 532 v->presc = p; 533 v->scldel = l; 534 v->sdadel = a; 535 p_prev = p; 536 537 list_add_tail(&v->node, 538 &solutions); 539 break; 540 } 541 } 542 543 if (p_prev == p) 544 break; 545 } 546 } 547 548 if (list_empty(&solutions)) { 549 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 550 ret = -EPERM; 551 goto exit; 552 } 553 554 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 555 s = NULL; 556 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); 557 clk_min = NSEC_PER_SEC / setup->speed_freq; 558 559 /* 560 * Among Prescaler possibilities discovered above figures out SCL Low 561 * and High Period. Provided: 562 * - SCL Low Period has to be higher than SCL Clock Low Period 563 * defined by I2C Specification. I2C Clock has to be lower than 564 * (SCL Low Period - Analog/Digital filters) / 4. 565 * - SCL High Period has to be lower than SCL Clock High Period 566 * defined by I2C Specification 567 * - I2C Clock has to be lower than SCL High Period 568 */ 569 list_for_each_entry(v, &solutions, node) { 570 u32 prescaler = (v->presc + 1) * i2cclk; 571 572 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 573 u32 tscl_l = (l + 1) * prescaler + tsync; 574 575 if ((tscl_l < specs->l_min) || 576 (i2cclk >= 577 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 578 continue; 579 } 580 581 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 582 u32 tscl_h = (h + 1) * prescaler + tsync; 583 u32 tscl = tscl_l + tscl_h + 584 setup->rise_time + setup->fall_time; 585 586 if ((tscl >= clk_min) && (tscl <= clk_max) && 587 (tscl_h >= specs->h_min) && 588 (i2cclk < tscl_h)) { 589 int clk_error = tscl - i2cbus; 590 591 if (clk_error < 0) 592 clk_error = -clk_error; 593 594 if (clk_error < clk_error_prev) { 595 clk_error_prev = clk_error; 596 v->scll = l; 597 v->sclh = h; 598 s = v; 599 } 600 } 601 } 602 } 603 } 604 605 if (!s) { 606 dev_err(i2c_dev->dev, "no solution at all\n"); 607 ret = -EPERM; 608 goto exit; 609 } 610 611 output->presc = s->presc; 612 output->scldel = s->scldel; 613 output->sdadel = s->sdadel; 614 output->scll = s->scll; 615 output->sclh = s->sclh; 616 617 dev_dbg(i2c_dev->dev, 618 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 619 output->presc, 620 output->scldel, output->sdadel, 621 output->scll, output->sclh); 622 623 exit: 624 /* Release list and memory */ 625 list_for_each_entry_safe(v, _v, &solutions, node) { 626 list_del(&v->node); 627 kfree(v); 628 } 629 630 return ret; 631 } 632 633 static u32 stm32f7_get_lower_rate(u32 rate) 634 { 635 int i = ARRAY_SIZE(stm32f7_i2c_specs); 636 637 while (--i) 638 if (stm32f7_i2c_specs[i].rate < rate) 639 break; 640 641 return stm32f7_i2c_specs[i].rate; 642 } 643 644 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 645 struct stm32f7_i2c_setup *setup) 646 { 647 struct i2c_timings timings, *t = &timings; 648 int ret = 0; 649 650 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 651 t->scl_rise_ns = i2c_dev->setup.rise_time; 652 t->scl_fall_ns = i2c_dev->setup.fall_time; 653 654 i2c_parse_fw_timings(i2c_dev->dev, t, false); 655 656 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { 657 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", 658 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); 659 return -EINVAL; 660 } 661 662 setup->speed_freq = t->bus_freq_hz; 663 i2c_dev->setup.rise_time = t->scl_rise_ns; 664 i2c_dev->setup.fall_time = t->scl_fall_ns; 665 i2c_dev->dnf_dt = t->digital_filter_width_ns; 666 setup->clock_src = clk_get_rate(i2c_dev->clk); 667 668 if (!setup->clock_src) { 669 dev_err(i2c_dev->dev, "clock rate is 0\n"); 670 return -EINVAL; 671 } 672 673 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) 674 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; 675 676 do { 677 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 678 &i2c_dev->timing); 679 if (ret) { 680 dev_err(i2c_dev->dev, 681 "failed to compute I2C timings.\n"); 682 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) 683 break; 684 setup->speed_freq = 685 stm32f7_get_lower_rate(setup->speed_freq); 686 dev_warn(i2c_dev->dev, 687 "downgrade I2C Speed Freq to (%i)\n", 688 setup->speed_freq); 689 } 690 } while (ret); 691 692 if (ret) { 693 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 694 return ret; 695 } 696 697 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, 698 "i2c-analog-filter"); 699 700 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 701 setup->speed_freq, setup->clock_src); 702 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 703 setup->rise_time, setup->fall_time); 704 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 705 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); 706 707 i2c_dev->bus_rate = setup->speed_freq; 708 709 return 0; 710 } 711 712 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 713 { 714 void __iomem *base = i2c_dev->base; 715 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 716 717 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 718 } 719 720 static void stm32f7_i2c_dma_callback(void *arg) 721 { 722 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 723 struct stm32_i2c_dma *dma = i2c_dev->dma; 724 struct device *dev = dma->chan_using->device->dev; 725 726 stm32f7_i2c_disable_dma_req(i2c_dev); 727 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 728 complete(&dma->dma_complete); 729 } 730 731 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 732 { 733 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 734 u32 timing = 0; 735 736 /* Timing settings */ 737 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 738 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 739 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 740 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 741 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 742 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 743 744 /* Configure the Analog Filter */ 745 if (i2c_dev->analog_filter) 746 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 747 STM32F7_I2C_CR1_ANFOFF); 748 else 749 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 750 STM32F7_I2C_CR1_ANFOFF); 751 752 /* Program the Digital Filter */ 753 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 754 STM32F7_I2C_CR1_DNF_MASK); 755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 756 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); 757 758 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 759 STM32F7_I2C_CR1_PE); 760 } 761 762 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 763 { 764 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 765 void __iomem *base = i2c_dev->base; 766 767 if (f7_msg->count) { 768 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 769 f7_msg->count--; 770 } 771 } 772 773 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 774 { 775 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 776 void __iomem *base = i2c_dev->base; 777 778 if (f7_msg->count) { 779 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 780 f7_msg->count--; 781 } else { 782 /* Flush RX buffer has no data is expected */ 783 readb_relaxed(base + STM32F7_I2C_RXDR); 784 } 785 } 786 787 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 788 { 789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 790 u32 cr2; 791 792 if (i2c_dev->use_dma) 793 f7_msg->count -= STM32F7_I2C_MAX_LEN; 794 795 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 796 797 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 798 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 799 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 800 } else { 801 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 802 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 803 } 804 805 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 806 } 807 808 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 809 { 810 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 811 u32 cr2; 812 u8 *val; 813 814 /* 815 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 816 * data received inform us how many data will follow. 817 */ 818 stm32f7_i2c_read_rx_data(i2c_dev); 819 820 /* 821 * Update NBYTES with the value read to continue the transfer 822 */ 823 val = f7_msg->buf - sizeof(u8); 824 f7_msg->count = *val; 825 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 826 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 827 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 828 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 829 } 830 831 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 832 { 833 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 834 835 dev_info(i2c_dev->dev, "Trying to recover bus\n"); 836 837 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 838 STM32F7_I2C_CR1_PE); 839 840 stm32f7_i2c_hw_config(i2c_dev); 841 842 return 0; 843 } 844 845 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 846 { 847 u32 status; 848 int ret; 849 850 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 851 status, 852 !(status & STM32F7_I2C_ISR_BUSY), 853 10, 1000); 854 if (!ret) 855 return 0; 856 857 dev_info(i2c_dev->dev, "bus busy\n"); 858 859 ret = stm32f7_i2c_release_bus(&i2c_dev->adap); 860 if (ret) { 861 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); 862 return ret; 863 } 864 865 return -EBUSY; 866 } 867 868 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 869 struct i2c_msg *msg) 870 { 871 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 872 void __iomem *base = i2c_dev->base; 873 u32 cr1, cr2; 874 int ret; 875 876 f7_msg->addr = msg->addr; 877 f7_msg->buf = msg->buf; 878 f7_msg->count = msg->len; 879 f7_msg->result = 0; 880 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 881 882 reinit_completion(&i2c_dev->complete); 883 884 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 885 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 886 887 /* Set transfer direction */ 888 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 889 if (msg->flags & I2C_M_RD) 890 cr2 |= STM32F7_I2C_CR2_RD_WRN; 891 892 /* Set slave address */ 893 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 894 if (msg->flags & I2C_M_TEN) { 895 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 896 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 897 cr2 |= STM32F7_I2C_CR2_ADD10; 898 } else { 899 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 900 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 901 } 902 903 /* Set nb bytes to transfer and reload if needed */ 904 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 905 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 906 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 907 cr2 |= STM32F7_I2C_CR2_RELOAD; 908 } else { 909 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 910 } 911 912 /* Enable NACK, STOP, error and transfer complete interrupts */ 913 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 914 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 915 916 /* Clear DMA req and TX/RX interrupt */ 917 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 918 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 919 920 /* Configure DMA or enable RX/TX interrupt */ 921 i2c_dev->use_dma = false; 922 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 923 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 924 msg->flags & I2C_M_RD, 925 f7_msg->count, f7_msg->buf, 926 stm32f7_i2c_dma_callback, 927 i2c_dev); 928 if (!ret) 929 i2c_dev->use_dma = true; 930 else 931 dev_warn(i2c_dev->dev, "can't use DMA\n"); 932 } 933 934 if (!i2c_dev->use_dma) { 935 if (msg->flags & I2C_M_RD) 936 cr1 |= STM32F7_I2C_CR1_RXIE; 937 else 938 cr1 |= STM32F7_I2C_CR1_TXIE; 939 } else { 940 if (msg->flags & I2C_M_RD) 941 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 942 else 943 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 944 } 945 946 /* Configure Start/Repeated Start */ 947 cr2 |= STM32F7_I2C_CR2_START; 948 949 i2c_dev->master_mode = true; 950 951 /* Write configurations registers */ 952 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 953 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 954 } 955 956 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 957 unsigned short flags, u8 command, 958 union i2c_smbus_data *data) 959 { 960 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 961 struct device *dev = i2c_dev->dev; 962 void __iomem *base = i2c_dev->base; 963 u32 cr1, cr2; 964 int i, ret; 965 966 f7_msg->result = 0; 967 reinit_completion(&i2c_dev->complete); 968 969 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 970 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 971 972 /* Set transfer direction */ 973 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 974 if (f7_msg->read_write) 975 cr2 |= STM32F7_I2C_CR2_RD_WRN; 976 977 /* Set slave address */ 978 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 979 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 980 981 f7_msg->smbus_buf[0] = command; 982 switch (f7_msg->size) { 983 case I2C_SMBUS_QUICK: 984 f7_msg->stop = true; 985 f7_msg->count = 0; 986 break; 987 case I2C_SMBUS_BYTE: 988 f7_msg->stop = true; 989 f7_msg->count = 1; 990 break; 991 case I2C_SMBUS_BYTE_DATA: 992 if (f7_msg->read_write) { 993 f7_msg->stop = false; 994 f7_msg->count = 1; 995 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 996 } else { 997 f7_msg->stop = true; 998 f7_msg->count = 2; 999 f7_msg->smbus_buf[1] = data->byte; 1000 } 1001 break; 1002 case I2C_SMBUS_WORD_DATA: 1003 if (f7_msg->read_write) { 1004 f7_msg->stop = false; 1005 f7_msg->count = 1; 1006 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1007 } else { 1008 f7_msg->stop = true; 1009 f7_msg->count = 3; 1010 f7_msg->smbus_buf[1] = data->word & 0xff; 1011 f7_msg->smbus_buf[2] = data->word >> 8; 1012 } 1013 break; 1014 case I2C_SMBUS_BLOCK_DATA: 1015 if (f7_msg->read_write) { 1016 f7_msg->stop = false; 1017 f7_msg->count = 1; 1018 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1019 } else { 1020 f7_msg->stop = true; 1021 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 1022 !data->block[0]) { 1023 dev_err(dev, "Invalid block write size %d\n", 1024 data->block[0]); 1025 return -EINVAL; 1026 } 1027 f7_msg->count = data->block[0] + 2; 1028 for (i = 1; i < f7_msg->count; i++) 1029 f7_msg->smbus_buf[i] = data->block[i - 1]; 1030 } 1031 break; 1032 case I2C_SMBUS_PROC_CALL: 1033 f7_msg->stop = false; 1034 f7_msg->count = 3; 1035 f7_msg->smbus_buf[1] = data->word & 0xff; 1036 f7_msg->smbus_buf[2] = data->word >> 8; 1037 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1038 f7_msg->read_write = I2C_SMBUS_READ; 1039 break; 1040 case I2C_SMBUS_BLOCK_PROC_CALL: 1041 f7_msg->stop = false; 1042 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 1043 dev_err(dev, "Invalid block write size %d\n", 1044 data->block[0]); 1045 return -EINVAL; 1046 } 1047 f7_msg->count = data->block[0] + 2; 1048 for (i = 1; i < f7_msg->count; i++) 1049 f7_msg->smbus_buf[i] = data->block[i - 1]; 1050 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1051 f7_msg->read_write = I2C_SMBUS_READ; 1052 break; 1053 case I2C_SMBUS_I2C_BLOCK_DATA: 1054 /* Rely on emulated i2c transfer (through master_xfer) */ 1055 return -EOPNOTSUPP; 1056 default: 1057 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 1058 return -EOPNOTSUPP; 1059 } 1060 1061 f7_msg->buf = f7_msg->smbus_buf; 1062 1063 /* Configure PEC */ 1064 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 1065 cr1 |= STM32F7_I2C_CR1_PECEN; 1066 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1067 if (!f7_msg->read_write) 1068 f7_msg->count++; 1069 } else { 1070 cr1 &= ~STM32F7_I2C_CR1_PECEN; 1071 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 1072 } 1073 1074 /* Set number of bytes to be transferred */ 1075 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 1076 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1077 1078 /* Enable NACK, STOP, error and transfer complete interrupts */ 1079 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 1080 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 1081 1082 /* Clear DMA req and TX/RX interrupt */ 1083 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1084 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1085 1086 /* Configure DMA or enable RX/TX interrupt */ 1087 i2c_dev->use_dma = false; 1088 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 1089 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1090 cr2 & STM32F7_I2C_CR2_RD_WRN, 1091 f7_msg->count, f7_msg->buf, 1092 stm32f7_i2c_dma_callback, 1093 i2c_dev); 1094 if (!ret) 1095 i2c_dev->use_dma = true; 1096 else 1097 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1098 } 1099 1100 if (!i2c_dev->use_dma) { 1101 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1102 cr1 |= STM32F7_I2C_CR1_RXIE; 1103 else 1104 cr1 |= STM32F7_I2C_CR1_TXIE; 1105 } else { 1106 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1107 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1108 else 1109 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1110 } 1111 1112 /* Set Start bit */ 1113 cr2 |= STM32F7_I2C_CR2_START; 1114 1115 i2c_dev->master_mode = true; 1116 1117 /* Write configurations registers */ 1118 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1119 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1120 1121 return 0; 1122 } 1123 1124 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1125 { 1126 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1127 void __iomem *base = i2c_dev->base; 1128 u32 cr1, cr2; 1129 int ret; 1130 1131 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1132 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1133 1134 /* Set transfer direction */ 1135 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1136 1137 switch (f7_msg->size) { 1138 case I2C_SMBUS_BYTE_DATA: 1139 f7_msg->count = 1; 1140 break; 1141 case I2C_SMBUS_WORD_DATA: 1142 case I2C_SMBUS_PROC_CALL: 1143 f7_msg->count = 2; 1144 break; 1145 case I2C_SMBUS_BLOCK_DATA: 1146 case I2C_SMBUS_BLOCK_PROC_CALL: 1147 f7_msg->count = 1; 1148 cr2 |= STM32F7_I2C_CR2_RELOAD; 1149 break; 1150 } 1151 1152 f7_msg->buf = f7_msg->smbus_buf; 1153 f7_msg->stop = true; 1154 1155 /* Add one byte for PEC if needed */ 1156 if (cr1 & STM32F7_I2C_CR1_PECEN) 1157 f7_msg->count++; 1158 1159 /* Set number of bytes to be transferred */ 1160 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1161 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1162 1163 /* 1164 * Configure RX/TX interrupt: 1165 */ 1166 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1167 cr1 |= STM32F7_I2C_CR1_RXIE; 1168 1169 /* 1170 * Configure DMA or enable RX/TX interrupt: 1171 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1172 * dma as we don't know in advance how many data will be received 1173 */ 1174 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1175 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1176 1177 i2c_dev->use_dma = false; 1178 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1179 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1180 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1181 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1182 cr2 & STM32F7_I2C_CR2_RD_WRN, 1183 f7_msg->count, f7_msg->buf, 1184 stm32f7_i2c_dma_callback, 1185 i2c_dev); 1186 1187 if (!ret) 1188 i2c_dev->use_dma = true; 1189 else 1190 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1191 } 1192 1193 if (!i2c_dev->use_dma) 1194 cr1 |= STM32F7_I2C_CR1_RXIE; 1195 else 1196 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1197 1198 /* Configure Repeated Start */ 1199 cr2 |= STM32F7_I2C_CR2_START; 1200 1201 /* Write configurations registers */ 1202 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1203 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1204 } 1205 1206 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1207 { 1208 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1209 u8 count, internal_pec, received_pec; 1210 1211 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1212 1213 switch (f7_msg->size) { 1214 case I2C_SMBUS_BYTE: 1215 case I2C_SMBUS_BYTE_DATA: 1216 received_pec = f7_msg->smbus_buf[1]; 1217 break; 1218 case I2C_SMBUS_WORD_DATA: 1219 case I2C_SMBUS_PROC_CALL: 1220 received_pec = f7_msg->smbus_buf[2]; 1221 break; 1222 case I2C_SMBUS_BLOCK_DATA: 1223 case I2C_SMBUS_BLOCK_PROC_CALL: 1224 count = f7_msg->smbus_buf[0]; 1225 received_pec = f7_msg->smbus_buf[count]; 1226 break; 1227 default: 1228 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1229 return -EINVAL; 1230 } 1231 1232 if (internal_pec != received_pec) { 1233 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1234 internal_pec, received_pec); 1235 return -EBADMSG; 1236 } 1237 1238 return 0; 1239 } 1240 1241 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1242 { 1243 u32 addr; 1244 1245 if (!slave) 1246 return false; 1247 1248 if (slave->flags & I2C_CLIENT_TEN) { 1249 /* 1250 * For 10-bit addr, addcode = 11110XY with 1251 * X = Bit 9 of slave address 1252 * Y = Bit 8 of slave address 1253 */ 1254 addr = slave->addr >> 8; 1255 addr |= 0x78; 1256 if (addr == addcode) 1257 return true; 1258 } else { 1259 addr = slave->addr & 0x7f; 1260 if (addr == addcode) 1261 return true; 1262 } 1263 1264 return false; 1265 } 1266 1267 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1268 { 1269 struct i2c_client *slave = i2c_dev->slave_running; 1270 void __iomem *base = i2c_dev->base; 1271 u32 mask; 1272 u8 value = 0; 1273 1274 if (i2c_dev->slave_dir) { 1275 /* Notify i2c slave that new read transfer is starting */ 1276 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1277 1278 /* 1279 * Disable slave TX config in case of I2C combined message 1280 * (I2C Write followed by I2C Read) 1281 */ 1282 mask = STM32F7_I2C_CR2_RELOAD; 1283 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1284 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1285 STM32F7_I2C_CR1_TCIE; 1286 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1287 1288 /* Enable TX empty, STOP, NACK interrupts */ 1289 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1290 STM32F7_I2C_CR1_TXIE; 1291 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1292 1293 /* Write 1st data byte */ 1294 writel_relaxed(value, base + STM32F7_I2C_TXDR); 1295 } else { 1296 /* Notify i2c slave that new write transfer is starting */ 1297 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1298 1299 /* Set reload mode to be able to ACK/NACK each received byte */ 1300 mask = STM32F7_I2C_CR2_RELOAD; 1301 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1302 1303 /* 1304 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1305 * Set Slave Byte Control to be able to ACK/NACK each data 1306 * byte received 1307 */ 1308 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1309 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1310 STM32F7_I2C_CR1_TCIE; 1311 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1312 } 1313 } 1314 1315 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1316 { 1317 void __iomem *base = i2c_dev->base; 1318 u32 isr, addcode, dir, mask; 1319 int i; 1320 1321 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1322 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1323 dir = isr & STM32F7_I2C_ISR_DIR; 1324 1325 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1326 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1327 i2c_dev->slave_running = i2c_dev->slave[i]; 1328 i2c_dev->slave_dir = dir; 1329 1330 /* Start I2C slave processing */ 1331 stm32f7_i2c_slave_start(i2c_dev); 1332 1333 /* Clear ADDR flag */ 1334 mask = STM32F7_I2C_ICR_ADDRCF; 1335 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1336 break; 1337 } 1338 } 1339 } 1340 1341 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1342 struct i2c_client *slave, int *id) 1343 { 1344 int i; 1345 1346 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1347 if (i2c_dev->slave[i] == slave) { 1348 *id = i; 1349 return 0; 1350 } 1351 } 1352 1353 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1354 1355 return -ENODEV; 1356 } 1357 1358 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1359 struct i2c_client *slave, int *id) 1360 { 1361 struct device *dev = i2c_dev->dev; 1362 int i; 1363 1364 /* 1365 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8) 1366 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address 1367 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only 1368 */ 1369 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { 1370 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) 1371 goto fail; 1372 *id = STM32F7_SLAVE_HOSTNOTIFY; 1373 return 0; 1374 } 1375 1376 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { 1377 if ((i == STM32F7_SLAVE_7_BITS_ADDR) && 1378 (slave->flags & I2C_CLIENT_TEN)) 1379 continue; 1380 if (!i2c_dev->slave[i]) { 1381 *id = i; 1382 return 0; 1383 } 1384 } 1385 1386 fail: 1387 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1388 1389 return -EINVAL; 1390 } 1391 1392 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1393 { 1394 int i; 1395 1396 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1397 if (i2c_dev->slave[i]) 1398 return true; 1399 } 1400 1401 return false; 1402 } 1403 1404 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1405 { 1406 int i, busy; 1407 1408 busy = 0; 1409 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1410 if (i2c_dev->slave[i]) 1411 busy++; 1412 } 1413 1414 return i == busy; 1415 } 1416 1417 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev) 1418 { 1419 void __iomem *base = i2c_dev->base; 1420 u32 cr2, status, mask; 1421 u8 val; 1422 int ret; 1423 1424 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1425 1426 /* Slave transmitter mode */ 1427 if (status & STM32F7_I2C_ISR_TXIS) { 1428 i2c_slave_event(i2c_dev->slave_running, 1429 I2C_SLAVE_READ_PROCESSED, 1430 &val); 1431 1432 /* Write data byte */ 1433 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1434 } 1435 1436 /* Transfer Complete Reload for Slave receiver mode */ 1437 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1438 /* 1439 * Read data byte then set NBYTES to receive next byte or NACK 1440 * the current received byte 1441 */ 1442 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1443 ret = i2c_slave_event(i2c_dev->slave_running, 1444 I2C_SLAVE_WRITE_RECEIVED, 1445 &val); 1446 if (!ret) { 1447 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1448 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1449 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1450 } else { 1451 mask = STM32F7_I2C_CR2_NACK; 1452 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1453 } 1454 } 1455 1456 /* NACK received */ 1457 if (status & STM32F7_I2C_ISR_NACKF) { 1458 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1459 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1460 } 1461 1462 /* STOP received */ 1463 if (status & STM32F7_I2C_ISR_STOPF) { 1464 /* Disable interrupts */ 1465 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1466 1467 if (i2c_dev->slave_dir) { 1468 /* 1469 * Flush TX buffer in order to not used the byte in 1470 * TXDR for the next transfer 1471 */ 1472 mask = STM32F7_I2C_ISR_TXE; 1473 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1474 } 1475 1476 /* Clear STOP flag */ 1477 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1478 1479 /* Notify i2c slave that a STOP flag has been detected */ 1480 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1481 1482 i2c_dev->slave_running = NULL; 1483 } 1484 1485 /* Address match received */ 1486 if (status & STM32F7_I2C_ISR_ADDR) 1487 stm32f7_i2c_slave_addr(i2c_dev); 1488 1489 return IRQ_HANDLED; 1490 } 1491 1492 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1493 { 1494 struct stm32f7_i2c_dev *i2c_dev = data; 1495 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1496 struct stm32_i2c_dma *dma = i2c_dev->dma; 1497 void __iomem *base = i2c_dev->base; 1498 u32 status, mask; 1499 int ret = IRQ_HANDLED; 1500 1501 /* Check if the interrupt if for a slave device */ 1502 if (!i2c_dev->master_mode) { 1503 ret = stm32f7_i2c_slave_isr_event(i2c_dev); 1504 return ret; 1505 } 1506 1507 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1508 1509 /* Tx empty */ 1510 if (status & STM32F7_I2C_ISR_TXIS) 1511 stm32f7_i2c_write_tx_data(i2c_dev); 1512 1513 /* RX not empty */ 1514 if (status & STM32F7_I2C_ISR_RXNE) 1515 stm32f7_i2c_read_rx_data(i2c_dev); 1516 1517 /* NACK received */ 1518 if (status & STM32F7_I2C_ISR_NACKF) { 1519 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", 1520 __func__, f7_msg->addr); 1521 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1522 if (i2c_dev->use_dma) { 1523 stm32f7_i2c_disable_dma_req(i2c_dev); 1524 dmaengine_terminate_async(dma->chan_using); 1525 } 1526 f7_msg->result = -ENXIO; 1527 } 1528 1529 /* STOP detection flag */ 1530 if (status & STM32F7_I2C_ISR_STOPF) { 1531 /* Disable interrupts */ 1532 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1533 mask = STM32F7_I2C_XFER_IRQ_MASK; 1534 else 1535 mask = STM32F7_I2C_ALL_IRQ_MASK; 1536 stm32f7_i2c_disable_irq(i2c_dev, mask); 1537 1538 /* Clear STOP flag */ 1539 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1540 1541 if (i2c_dev->use_dma && !f7_msg->result) { 1542 ret = IRQ_WAKE_THREAD; 1543 } else { 1544 i2c_dev->master_mode = false; 1545 complete(&i2c_dev->complete); 1546 } 1547 } 1548 1549 /* Transfer complete */ 1550 if (status & STM32F7_I2C_ISR_TC) { 1551 if (f7_msg->stop) { 1552 mask = STM32F7_I2C_CR2_STOP; 1553 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1554 } else if (i2c_dev->use_dma && !f7_msg->result) { 1555 ret = IRQ_WAKE_THREAD; 1556 } else if (f7_msg->smbus) { 1557 stm32f7_i2c_smbus_rep_start(i2c_dev); 1558 } else { 1559 i2c_dev->msg_id++; 1560 i2c_dev->msg++; 1561 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1562 } 1563 } 1564 1565 if (status & STM32F7_I2C_ISR_TCR) { 1566 if (f7_msg->smbus) 1567 stm32f7_i2c_smbus_reload(i2c_dev); 1568 else 1569 stm32f7_i2c_reload(i2c_dev); 1570 } 1571 1572 return ret; 1573 } 1574 1575 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1576 { 1577 struct stm32f7_i2c_dev *i2c_dev = data; 1578 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1579 struct stm32_i2c_dma *dma = i2c_dev->dma; 1580 u32 status; 1581 int ret; 1582 1583 /* 1584 * Wait for dma transfer completion before sending next message or 1585 * notity the end of xfer to the client 1586 */ 1587 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1588 if (!ret) { 1589 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1590 stm32f7_i2c_disable_dma_req(i2c_dev); 1591 dmaengine_terminate_async(dma->chan_using); 1592 f7_msg->result = -ETIMEDOUT; 1593 } 1594 1595 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1596 1597 if (status & STM32F7_I2C_ISR_TC) { 1598 if (f7_msg->smbus) { 1599 stm32f7_i2c_smbus_rep_start(i2c_dev); 1600 } else { 1601 i2c_dev->msg_id++; 1602 i2c_dev->msg++; 1603 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1604 } 1605 } else { 1606 i2c_dev->master_mode = false; 1607 complete(&i2c_dev->complete); 1608 } 1609 1610 return IRQ_HANDLED; 1611 } 1612 1613 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data) 1614 { 1615 struct stm32f7_i2c_dev *i2c_dev = data; 1616 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1617 void __iomem *base = i2c_dev->base; 1618 struct device *dev = i2c_dev->dev; 1619 struct stm32_i2c_dma *dma = i2c_dev->dma; 1620 u32 status; 1621 1622 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1623 1624 /* Bus error */ 1625 if (status & STM32F7_I2C_ISR_BERR) { 1626 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n", 1627 __func__, f7_msg->addr); 1628 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1629 stm32f7_i2c_release_bus(&i2c_dev->adap); 1630 f7_msg->result = -EIO; 1631 } 1632 1633 /* Arbitration loss */ 1634 if (status & STM32F7_I2C_ISR_ARLO) { 1635 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n", 1636 __func__, f7_msg->addr); 1637 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1638 f7_msg->result = -EAGAIN; 1639 } 1640 1641 if (status & STM32F7_I2C_ISR_PECERR) { 1642 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n", 1643 __func__, f7_msg->addr); 1644 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1645 f7_msg->result = -EINVAL; 1646 } 1647 1648 if (status & STM32F7_I2C_ISR_ALERT) { 1649 dev_dbg(dev, "<%s>: SMBus alert received\n", __func__); 1650 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR); 1651 i2c_handle_smbus_alert(i2c_dev->alert->ara); 1652 return IRQ_HANDLED; 1653 } 1654 1655 if (!i2c_dev->slave_running) { 1656 u32 mask; 1657 /* Disable interrupts */ 1658 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1659 mask = STM32F7_I2C_XFER_IRQ_MASK; 1660 else 1661 mask = STM32F7_I2C_ALL_IRQ_MASK; 1662 stm32f7_i2c_disable_irq(i2c_dev, mask); 1663 } 1664 1665 /* Disable dma */ 1666 if (i2c_dev->use_dma) { 1667 stm32f7_i2c_disable_dma_req(i2c_dev); 1668 dmaengine_terminate_async(dma->chan_using); 1669 } 1670 1671 i2c_dev->master_mode = false; 1672 complete(&i2c_dev->complete); 1673 1674 return IRQ_HANDLED; 1675 } 1676 1677 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1678 struct i2c_msg msgs[], int num) 1679 { 1680 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1681 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1682 struct stm32_i2c_dma *dma = i2c_dev->dma; 1683 unsigned long time_left; 1684 int ret; 1685 1686 i2c_dev->msg = msgs; 1687 i2c_dev->msg_num = num; 1688 i2c_dev->msg_id = 0; 1689 f7_msg->smbus = false; 1690 1691 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1692 if (ret < 0) 1693 return ret; 1694 1695 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1696 if (ret) 1697 goto pm_free; 1698 1699 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1700 1701 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1702 i2c_dev->adap.timeout); 1703 ret = f7_msg->result; 1704 if (ret) { 1705 if (i2c_dev->use_dma) 1706 dmaengine_synchronize(dma->chan_using); 1707 1708 /* 1709 * It is possible that some unsent data have already been 1710 * written into TXDR. To avoid sending old data in a 1711 * further transfer, flush TXDR in case of any error 1712 */ 1713 writel_relaxed(STM32F7_I2C_ISR_TXE, 1714 i2c_dev->base + STM32F7_I2C_ISR); 1715 goto pm_free; 1716 } 1717 1718 if (!time_left) { 1719 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1720 i2c_dev->msg->addr); 1721 if (i2c_dev->use_dma) 1722 dmaengine_terminate_sync(dma->chan_using); 1723 stm32f7_i2c_wait_free_bus(i2c_dev); 1724 ret = -ETIMEDOUT; 1725 } 1726 1727 pm_free: 1728 pm_runtime_mark_last_busy(i2c_dev->dev); 1729 pm_runtime_put_autosuspend(i2c_dev->dev); 1730 1731 return (ret < 0) ? ret : num; 1732 } 1733 1734 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1735 unsigned short flags, char read_write, 1736 u8 command, int size, 1737 union i2c_smbus_data *data) 1738 { 1739 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1740 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1741 struct stm32_i2c_dma *dma = i2c_dev->dma; 1742 struct device *dev = i2c_dev->dev; 1743 unsigned long timeout; 1744 int i, ret; 1745 1746 f7_msg->addr = addr; 1747 f7_msg->size = size; 1748 f7_msg->read_write = read_write; 1749 f7_msg->smbus = true; 1750 1751 ret = pm_runtime_resume_and_get(dev); 1752 if (ret < 0) 1753 return ret; 1754 1755 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1756 if (ret) 1757 goto pm_free; 1758 1759 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1760 if (ret) 1761 goto pm_free; 1762 1763 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1764 i2c_dev->adap.timeout); 1765 ret = f7_msg->result; 1766 if (ret) { 1767 if (i2c_dev->use_dma) 1768 dmaengine_synchronize(dma->chan_using); 1769 1770 /* 1771 * It is possible that some unsent data have already been 1772 * written into TXDR. To avoid sending old data in a 1773 * further transfer, flush TXDR in case of any error 1774 */ 1775 writel_relaxed(STM32F7_I2C_ISR_TXE, 1776 i2c_dev->base + STM32F7_I2C_ISR); 1777 goto pm_free; 1778 } 1779 1780 if (!timeout) { 1781 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1782 if (i2c_dev->use_dma) 1783 dmaengine_terminate_sync(dma->chan_using); 1784 stm32f7_i2c_wait_free_bus(i2c_dev); 1785 ret = -ETIMEDOUT; 1786 goto pm_free; 1787 } 1788 1789 /* Check PEC */ 1790 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1791 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1792 if (ret) 1793 goto pm_free; 1794 } 1795 1796 if (read_write && size != I2C_SMBUS_QUICK) { 1797 switch (size) { 1798 case I2C_SMBUS_BYTE: 1799 case I2C_SMBUS_BYTE_DATA: 1800 data->byte = f7_msg->smbus_buf[0]; 1801 break; 1802 case I2C_SMBUS_WORD_DATA: 1803 case I2C_SMBUS_PROC_CALL: 1804 data->word = f7_msg->smbus_buf[0] | 1805 (f7_msg->smbus_buf[1] << 8); 1806 break; 1807 case I2C_SMBUS_BLOCK_DATA: 1808 case I2C_SMBUS_BLOCK_PROC_CALL: 1809 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1810 data->block[i] = f7_msg->smbus_buf[i]; 1811 break; 1812 default: 1813 dev_err(dev, "Unsupported smbus transaction\n"); 1814 ret = -EINVAL; 1815 } 1816 } 1817 1818 pm_free: 1819 pm_runtime_mark_last_busy(dev); 1820 pm_runtime_put_autosuspend(dev); 1821 return ret; 1822 } 1823 1824 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, 1825 bool enable) 1826 { 1827 void __iomem *base = i2c_dev->base; 1828 u32 mask = STM32F7_I2C_CR1_WUPEN; 1829 1830 if (!i2c_dev->wakeup_src) 1831 return; 1832 1833 if (enable) { 1834 device_set_wakeup_enable(i2c_dev->dev, true); 1835 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1836 } else { 1837 device_set_wakeup_enable(i2c_dev->dev, false); 1838 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1839 } 1840 } 1841 1842 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1843 { 1844 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1845 void __iomem *base = i2c_dev->base; 1846 struct device *dev = i2c_dev->dev; 1847 u32 oar1, oar2, mask; 1848 int id, ret; 1849 1850 if (slave->flags & I2C_CLIENT_PEC) { 1851 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1852 return -EINVAL; 1853 } 1854 1855 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1856 dev_err(dev, "Too much slave registered\n"); 1857 return -EBUSY; 1858 } 1859 1860 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1861 if (ret) 1862 return ret; 1863 1864 ret = pm_runtime_resume_and_get(dev); 1865 if (ret < 0) 1866 return ret; 1867 1868 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1869 stm32f7_i2c_enable_wakeup(i2c_dev, true); 1870 1871 switch (id) { 1872 case 0: 1873 /* Slave SMBus Host */ 1874 i2c_dev->slave[id] = slave; 1875 break; 1876 1877 case 1: 1878 /* Configure Own Address 1 */ 1879 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1880 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1881 if (slave->flags & I2C_CLIENT_TEN) { 1882 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1883 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1884 } else { 1885 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1886 } 1887 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1888 i2c_dev->slave[id] = slave; 1889 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1890 break; 1891 1892 case 2: 1893 /* Configure Own Address 2 */ 1894 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1895 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1896 if (slave->flags & I2C_CLIENT_TEN) { 1897 ret = -EOPNOTSUPP; 1898 goto pm_free; 1899 } 1900 1901 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1902 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1903 i2c_dev->slave[id] = slave; 1904 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1905 break; 1906 1907 default: 1908 dev_err(dev, "I2C slave id not supported\n"); 1909 ret = -ENODEV; 1910 goto pm_free; 1911 } 1912 1913 /* Enable ACK */ 1914 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1915 1916 /* Enable Address match interrupt, error interrupt and enable I2C */ 1917 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1918 STM32F7_I2C_CR1_PE; 1919 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1920 1921 ret = 0; 1922 pm_free: 1923 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1924 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1925 1926 pm_runtime_mark_last_busy(dev); 1927 pm_runtime_put_autosuspend(dev); 1928 1929 return ret; 1930 } 1931 1932 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1933 { 1934 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1935 void __iomem *base = i2c_dev->base; 1936 u32 mask; 1937 int id, ret; 1938 1939 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1940 if (ret) 1941 return ret; 1942 1943 WARN_ON(!i2c_dev->slave[id]); 1944 1945 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1946 if (ret < 0) 1947 return ret; 1948 1949 if (id == 1) { 1950 mask = STM32F7_I2C_OAR1_OA1EN; 1951 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1952 } else if (id == 2) { 1953 mask = STM32F7_I2C_OAR2_OA2EN; 1954 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1955 } 1956 1957 i2c_dev->slave[id] = NULL; 1958 1959 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 1960 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1961 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1962 } 1963 1964 pm_runtime_mark_last_busy(i2c_dev->dev); 1965 pm_runtime_put_autosuspend(i2c_dev->dev); 1966 1967 return 0; 1968 } 1969 1970 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, 1971 bool enable) 1972 { 1973 int ret; 1974 1975 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || 1976 IS_ERR_OR_NULL(i2c_dev->regmap)) 1977 /* Optional */ 1978 return 0; 1979 1980 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) 1981 ret = regmap_update_bits(i2c_dev->regmap, 1982 i2c_dev->fmp_sreg, 1983 i2c_dev->fmp_mask, 1984 enable ? i2c_dev->fmp_mask : 0); 1985 else 1986 ret = regmap_write(i2c_dev->regmap, 1987 enable ? i2c_dev->fmp_sreg : 1988 i2c_dev->fmp_creg, 1989 i2c_dev->fmp_mask); 1990 1991 return ret; 1992 } 1993 1994 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 1995 struct stm32f7_i2c_dev *i2c_dev) 1996 { 1997 struct device_node *np = pdev->dev.of_node; 1998 int ret; 1999 2000 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 2001 if (IS_ERR(i2c_dev->regmap)) 2002 /* Optional */ 2003 return 0; 2004 2005 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, 2006 &i2c_dev->fmp_sreg); 2007 if (ret) 2008 return ret; 2009 2010 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + 2011 i2c_dev->setup.fmp_clr_offset; 2012 2013 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, 2014 &i2c_dev->fmp_mask); 2015 } 2016 2017 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2018 { 2019 struct i2c_adapter *adap = &i2c_dev->adap; 2020 void __iomem *base = i2c_dev->base; 2021 struct i2c_client *client; 2022 2023 client = i2c_new_slave_host_notify_device(adap); 2024 if (IS_ERR(client)) 2025 return PTR_ERR(client); 2026 2027 i2c_dev->host_notify_client = client; 2028 2029 /* Enable SMBus Host address */ 2030 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN); 2031 2032 return 0; 2033 } 2034 2035 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2036 { 2037 void __iomem *base = i2c_dev->base; 2038 2039 if (i2c_dev->host_notify_client) { 2040 /* Disable SMBus Host address */ 2041 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2042 STM32F7_I2C_CR1_SMBHEN); 2043 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); 2044 } 2045 } 2046 2047 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2048 { 2049 struct stm32f7_i2c_alert *alert; 2050 struct i2c_adapter *adap = &i2c_dev->adap; 2051 struct device *dev = i2c_dev->dev; 2052 void __iomem *base = i2c_dev->base; 2053 2054 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL); 2055 if (!alert) 2056 return -ENOMEM; 2057 2058 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); 2059 if (IS_ERR(alert->ara)) 2060 return PTR_ERR(alert->ara); 2061 2062 i2c_dev->alert = alert; 2063 2064 /* Enable SMBus Alert */ 2065 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN); 2066 2067 return 0; 2068 } 2069 2070 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2071 { 2072 struct stm32f7_i2c_alert *alert = i2c_dev->alert; 2073 void __iomem *base = i2c_dev->base; 2074 2075 if (alert) { 2076 /* Disable SMBus Alert */ 2077 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2078 STM32F7_I2C_CR1_ALERTEN); 2079 i2c_unregister_device(alert->ara); 2080 } 2081 } 2082 2083 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 2084 { 2085 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 2086 2087 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 2088 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 2089 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 2090 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 2091 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 2092 I2C_FUNC_SMBUS_I2C_BLOCK; 2093 2094 if (i2c_dev->smbus_mode) 2095 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 2096 2097 return func; 2098 } 2099 2100 static const struct i2c_algorithm stm32f7_i2c_algo = { 2101 .master_xfer = stm32f7_i2c_xfer, 2102 .smbus_xfer = stm32f7_i2c_smbus_xfer, 2103 .functionality = stm32f7_i2c_func, 2104 .reg_slave = stm32f7_i2c_reg_slave, 2105 .unreg_slave = stm32f7_i2c_unreg_slave, 2106 }; 2107 2108 static int stm32f7_i2c_probe(struct platform_device *pdev) 2109 { 2110 struct stm32f7_i2c_dev *i2c_dev; 2111 const struct stm32f7_i2c_setup *setup; 2112 struct resource *res; 2113 struct i2c_adapter *adap; 2114 struct reset_control *rst; 2115 dma_addr_t phy_addr; 2116 int irq_error, irq_event, ret; 2117 2118 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 2119 if (!i2c_dev) 2120 return -ENOMEM; 2121 2122 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2123 if (IS_ERR(i2c_dev->base)) 2124 return PTR_ERR(i2c_dev->base); 2125 phy_addr = (dma_addr_t)res->start; 2126 2127 irq_event = platform_get_irq(pdev, 0); 2128 if (irq_event <= 0) 2129 return irq_event ? : -ENOENT; 2130 2131 irq_error = platform_get_irq(pdev, 1); 2132 if (irq_error <= 0) 2133 return irq_error ? : -ENOENT; 2134 2135 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, 2136 "wakeup-source"); 2137 2138 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 2139 if (IS_ERR(i2c_dev->clk)) 2140 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), 2141 "Failed to get controller clock\n"); 2142 2143 ret = clk_prepare_enable(i2c_dev->clk); 2144 if (ret) { 2145 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); 2146 return ret; 2147 } 2148 2149 rst = devm_reset_control_get(&pdev->dev, NULL); 2150 if (IS_ERR(rst)) { 2151 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), 2152 "Error: Missing reset ctrl\n"); 2153 goto clk_free; 2154 } 2155 reset_control_assert(rst); 2156 udelay(2); 2157 reset_control_deassert(rst); 2158 2159 i2c_dev->dev = &pdev->dev; 2160 2161 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 2162 stm32f7_i2c_isr_event, 2163 stm32f7_i2c_isr_event_thread, 2164 IRQF_ONESHOT, 2165 pdev->name, i2c_dev); 2166 if (ret) { 2167 dev_err(&pdev->dev, "Failed to request irq event %i\n", 2168 irq_event); 2169 goto clk_free; 2170 } 2171 2172 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, 2173 pdev->name, i2c_dev); 2174 if (ret) { 2175 dev_err(&pdev->dev, "Failed to request irq error %i\n", 2176 irq_error); 2177 goto clk_free; 2178 } 2179 2180 setup = of_device_get_match_data(&pdev->dev); 2181 if (!setup) { 2182 dev_err(&pdev->dev, "Can't get device data\n"); 2183 ret = -ENODEV; 2184 goto clk_free; 2185 } 2186 i2c_dev->setup = *setup; 2187 2188 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 2189 if (ret) 2190 goto clk_free; 2191 2192 /* Setup Fast mode plus if necessary */ 2193 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { 2194 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 2195 if (ret) 2196 goto clk_free; 2197 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2198 if (ret) 2199 goto clk_free; 2200 } 2201 2202 adap = &i2c_dev->adap; 2203 i2c_set_adapdata(adap, i2c_dev); 2204 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 2205 &res->start); 2206 adap->owner = THIS_MODULE; 2207 adap->timeout = 2 * HZ; 2208 adap->retries = 3; 2209 adap->algo = &stm32f7_i2c_algo; 2210 adap->dev.parent = &pdev->dev; 2211 adap->dev.of_node = pdev->dev.of_node; 2212 2213 init_completion(&i2c_dev->complete); 2214 2215 /* Init DMA config if supported */ 2216 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 2217 STM32F7_I2C_TXDR, 2218 STM32F7_I2C_RXDR); 2219 if (IS_ERR(i2c_dev->dma)) { 2220 ret = PTR_ERR(i2c_dev->dma); 2221 /* DMA support is optional, only report other errors */ 2222 if (ret != -ENODEV) 2223 goto fmp_clear; 2224 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); 2225 i2c_dev->dma = NULL; 2226 } 2227 2228 if (i2c_dev->wakeup_src) { 2229 device_set_wakeup_capable(i2c_dev->dev, true); 2230 2231 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); 2232 if (ret) { 2233 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); 2234 goto clr_wakeup_capable; 2235 } 2236 } 2237 2238 platform_set_drvdata(pdev, i2c_dev); 2239 2240 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 2241 STM32F7_AUTOSUSPEND_DELAY); 2242 pm_runtime_use_autosuspend(i2c_dev->dev); 2243 pm_runtime_set_active(i2c_dev->dev); 2244 pm_runtime_enable(i2c_dev->dev); 2245 2246 pm_runtime_get_noresume(&pdev->dev); 2247 2248 stm32f7_i2c_hw_config(i2c_dev); 2249 2250 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); 2251 2252 ret = i2c_add_adapter(adap); 2253 if (ret) 2254 goto pm_disable; 2255 2256 if (i2c_dev->smbus_mode) { 2257 ret = stm32f7_i2c_enable_smbus_host(i2c_dev); 2258 if (ret) { 2259 dev_err(i2c_dev->dev, 2260 "failed to enable SMBus Host-Notify protocol (%d)\n", 2261 ret); 2262 goto i2c_adapter_remove; 2263 } 2264 } 2265 2266 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { 2267 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev); 2268 if (ret) { 2269 dev_err(i2c_dev->dev, 2270 "failed to enable SMBus alert protocol (%d)\n", 2271 ret); 2272 goto i2c_disable_smbus_host; 2273 } 2274 } 2275 2276 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2277 2278 pm_runtime_mark_last_busy(i2c_dev->dev); 2279 pm_runtime_put_autosuspend(i2c_dev->dev); 2280 2281 return 0; 2282 2283 i2c_disable_smbus_host: 2284 stm32f7_i2c_disable_smbus_host(i2c_dev); 2285 2286 i2c_adapter_remove: 2287 i2c_del_adapter(adap); 2288 2289 pm_disable: 2290 pm_runtime_put_noidle(i2c_dev->dev); 2291 pm_runtime_disable(i2c_dev->dev); 2292 pm_runtime_set_suspended(i2c_dev->dev); 2293 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2294 2295 if (i2c_dev->wakeup_src) 2296 dev_pm_clear_wake_irq(i2c_dev->dev); 2297 2298 clr_wakeup_capable: 2299 if (i2c_dev->wakeup_src) 2300 device_set_wakeup_capable(i2c_dev->dev, false); 2301 2302 if (i2c_dev->dma) { 2303 stm32_i2c_dma_free(i2c_dev->dma); 2304 i2c_dev->dma = NULL; 2305 } 2306 2307 fmp_clear: 2308 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2309 2310 clk_free: 2311 clk_disable_unprepare(i2c_dev->clk); 2312 2313 return ret; 2314 } 2315 2316 static int stm32f7_i2c_remove(struct platform_device *pdev) 2317 { 2318 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2319 2320 stm32f7_i2c_disable_smbus_alert(i2c_dev); 2321 stm32f7_i2c_disable_smbus_host(i2c_dev); 2322 2323 i2c_del_adapter(&i2c_dev->adap); 2324 pm_runtime_get_sync(i2c_dev->dev); 2325 2326 if (i2c_dev->wakeup_src) { 2327 dev_pm_clear_wake_irq(i2c_dev->dev); 2328 /* 2329 * enforce that wakeup is disabled and that the device 2330 * is marked as non wakeup capable 2331 */ 2332 device_init_wakeup(i2c_dev->dev, false); 2333 } 2334 2335 pm_runtime_put_noidle(i2c_dev->dev); 2336 pm_runtime_disable(i2c_dev->dev); 2337 pm_runtime_set_suspended(i2c_dev->dev); 2338 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2339 2340 if (i2c_dev->dma) { 2341 stm32_i2c_dma_free(i2c_dev->dma); 2342 i2c_dev->dma = NULL; 2343 } 2344 2345 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2346 2347 clk_disable_unprepare(i2c_dev->clk); 2348 2349 return 0; 2350 } 2351 2352 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev) 2353 { 2354 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2355 2356 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2357 clk_disable_unprepare(i2c_dev->clk); 2358 2359 return 0; 2360 } 2361 2362 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev) 2363 { 2364 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2365 int ret; 2366 2367 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2368 ret = clk_prepare_enable(i2c_dev->clk); 2369 if (ret) { 2370 dev_err(dev, "failed to prepare_enable clock\n"); 2371 return ret; 2372 } 2373 } 2374 2375 return 0; 2376 } 2377 2378 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2379 { 2380 int ret; 2381 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2382 2383 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2384 if (ret < 0) 2385 return ret; 2386 2387 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2388 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 2389 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 2390 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 2391 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); 2392 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2393 2394 pm_runtime_put_sync(i2c_dev->dev); 2395 2396 return ret; 2397 } 2398 2399 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2400 { 2401 u32 cr1; 2402 int ret; 2403 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2404 2405 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2406 if (ret < 0) 2407 return ret; 2408 2409 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2410 if (cr1 & STM32F7_I2C_CR1_PE) 2411 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 2412 STM32F7_I2C_CR1_PE); 2413 2414 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); 2415 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, 2416 i2c_dev->base + STM32F7_I2C_CR1); 2417 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) 2418 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 2419 STM32F7_I2C_CR1_PE); 2420 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); 2421 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); 2422 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); 2423 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2424 2425 pm_runtime_put_sync(i2c_dev->dev); 2426 2427 return ret; 2428 } 2429 2430 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev) 2431 { 2432 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2433 int ret; 2434 2435 i2c_mark_adapter_suspended(&i2c_dev->adap); 2436 2437 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2438 ret = stm32f7_i2c_regs_backup(i2c_dev); 2439 if (ret < 0) { 2440 i2c_mark_adapter_resumed(&i2c_dev->adap); 2441 return ret; 2442 } 2443 2444 pinctrl_pm_select_sleep_state(dev); 2445 pm_runtime_force_suspend(dev); 2446 } 2447 2448 return 0; 2449 } 2450 2451 static int __maybe_unused stm32f7_i2c_resume(struct device *dev) 2452 { 2453 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2454 int ret; 2455 2456 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2457 ret = pm_runtime_force_resume(dev); 2458 if (ret < 0) 2459 return ret; 2460 pinctrl_pm_select_default_state(dev); 2461 2462 ret = stm32f7_i2c_regs_restore(i2c_dev); 2463 if (ret < 0) 2464 return ret; 2465 } 2466 2467 i2c_mark_adapter_resumed(&i2c_dev->adap); 2468 2469 return 0; 2470 } 2471 2472 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2473 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2474 stm32f7_i2c_runtime_resume, NULL) 2475 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume) 2476 }; 2477 2478 static const struct of_device_id stm32f7_i2c_match[] = { 2479 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2480 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup}, 2481 {}, 2482 }; 2483 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2484 2485 static struct platform_driver stm32f7_i2c_driver = { 2486 .driver = { 2487 .name = "stm32f7-i2c", 2488 .of_match_table = stm32f7_i2c_match, 2489 .pm = &stm32f7_i2c_pm_ops, 2490 }, 2491 .probe = stm32f7_i2c_probe, 2492 .remove = stm32f7_i2c_remove, 2493 }; 2494 2495 module_platform_driver(stm32f7_i2c_driver); 2496 2497 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2498 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2499 MODULE_LICENSE("GPL v2"); 2500