1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/i2c-smbus.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/pm_wakeirq.h> 34 #include <linux/regmap.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 38 #include "i2c-stm32.h" 39 40 /* STM32F7 I2C registers */ 41 #define STM32F7_I2C_CR1 0x00 42 #define STM32F7_I2C_CR2 0x04 43 #define STM32F7_I2C_OAR1 0x08 44 #define STM32F7_I2C_OAR2 0x0C 45 #define STM32F7_I2C_PECR 0x20 46 #define STM32F7_I2C_TIMINGR 0x10 47 #define STM32F7_I2C_ISR 0x18 48 #define STM32F7_I2C_ICR 0x1C 49 #define STM32F7_I2C_RXDR 0x24 50 #define STM32F7_I2C_TXDR 0x28 51 52 /* STM32F7 I2C control 1 */ 53 #define STM32F7_I2C_CR1_PECEN BIT(23) 54 #define STM32F7_I2C_CR1_ALERTEN BIT(22) 55 #define STM32F7_I2C_CR1_SMBHEN BIT(20) 56 #define STM32F7_I2C_CR1_WUPEN BIT(18) 57 #define STM32F7_I2C_CR1_SBC BIT(16) 58 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 59 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 60 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 61 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8) 62 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8) 63 #define STM32F7_I2C_CR1_ERRIE BIT(7) 64 #define STM32F7_I2C_CR1_TCIE BIT(6) 65 #define STM32F7_I2C_CR1_STOPIE BIT(5) 66 #define STM32F7_I2C_CR1_NACKIE BIT(4) 67 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 68 #define STM32F7_I2C_CR1_RXIE BIT(2) 69 #define STM32F7_I2C_CR1_TXIE BIT(1) 70 #define STM32F7_I2C_CR1_PE BIT(0) 71 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 72 | STM32F7_I2C_CR1_TCIE \ 73 | STM32F7_I2C_CR1_STOPIE \ 74 | STM32F7_I2C_CR1_NACKIE \ 75 | STM32F7_I2C_CR1_RXIE \ 76 | STM32F7_I2C_CR1_TXIE) 77 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 78 | STM32F7_I2C_CR1_STOPIE \ 79 | STM32F7_I2C_CR1_NACKIE \ 80 | STM32F7_I2C_CR1_RXIE \ 81 | STM32F7_I2C_CR1_TXIE) 82 83 /* STM32F7 I2C control 2 */ 84 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 85 #define STM32F7_I2C_CR2_RELOAD BIT(24) 86 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 87 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 88 #define STM32F7_I2C_CR2_NACK BIT(15) 89 #define STM32F7_I2C_CR2_STOP BIT(14) 90 #define STM32F7_I2C_CR2_START BIT(13) 91 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 92 #define STM32F7_I2C_CR2_ADD10 BIT(11) 93 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 94 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 95 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 96 STM32F7_I2C_CR2_SADD10_MASK)) 97 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 98 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 99 100 /* STM32F7 I2C Own Address 1 */ 101 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 102 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 103 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 104 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 105 STM32F7_I2C_OAR1_OA1_10_MASK)) 106 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 107 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 108 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 109 | STM32F7_I2C_OAR1_OA1_10_MASK \ 110 | STM32F7_I2C_OAR1_OA1EN \ 111 | STM32F7_I2C_OAR1_OA1MODE) 112 113 /* STM32F7 I2C Own Address 2 */ 114 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 115 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 116 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 117 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 118 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 119 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 120 | STM32F7_I2C_OAR2_OA2_7_MASK \ 121 | STM32F7_I2C_OAR2_OA2EN) 122 123 /* STM32F7 I2C Interrupt Status */ 124 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 127 #define STM32F7_I2C_ISR_DIR BIT(16) 128 #define STM32F7_I2C_ISR_BUSY BIT(15) 129 #define STM32F7_I2C_ISR_ALERT BIT(13) 130 #define STM32F7_I2C_ISR_PECERR BIT(11) 131 #define STM32F7_I2C_ISR_ARLO BIT(9) 132 #define STM32F7_I2C_ISR_BERR BIT(8) 133 #define STM32F7_I2C_ISR_TCR BIT(7) 134 #define STM32F7_I2C_ISR_TC BIT(6) 135 #define STM32F7_I2C_ISR_STOPF BIT(5) 136 #define STM32F7_I2C_ISR_NACKF BIT(4) 137 #define STM32F7_I2C_ISR_ADDR BIT(3) 138 #define STM32F7_I2C_ISR_RXNE BIT(2) 139 #define STM32F7_I2C_ISR_TXIS BIT(1) 140 #define STM32F7_I2C_ISR_TXE BIT(0) 141 142 /* STM32F7 I2C Interrupt Clear */ 143 #define STM32F7_I2C_ICR_ALERTCF BIT(13) 144 #define STM32F7_I2C_ICR_PECCF BIT(11) 145 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 146 #define STM32F7_I2C_ICR_BERRCF BIT(8) 147 #define STM32F7_I2C_ICR_STOPCF BIT(5) 148 #define STM32F7_I2C_ICR_NACKCF BIT(4) 149 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 150 151 /* STM32F7 I2C Timing */ 152 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 153 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 154 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 155 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 156 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 157 158 #define STM32F7_I2C_MAX_LEN 0xff 159 #define STM32F7_I2C_DMA_LEN_MIN 0x16 160 enum { 161 STM32F7_SLAVE_HOSTNOTIFY, 162 STM32F7_SLAVE_7_10_BITS_ADDR, 163 STM32F7_SLAVE_7_BITS_ADDR, 164 STM32F7_I2C_MAX_SLAVE 165 }; 166 167 #define STM32F7_I2C_DNF_DEFAULT 0 168 #define STM32F7_I2C_DNF_MAX 15 169 170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 172 173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 175 176 #define STM32F7_PRESC_MAX BIT(4) 177 #define STM32F7_SCLDEL_MAX BIT(4) 178 #define STM32F7_SDADEL_MAX BIT(4) 179 #define STM32F7_SCLH_MAX BIT(8) 180 #define STM32F7_SCLL_MAX BIT(8) 181 182 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 183 184 /** 185 * struct stm32f7_i2c_regs - i2c f7 registers backup 186 * @cr1: Control register 1 187 * @cr2: Control register 2 188 * @oar1: Own address 1 register 189 * @oar2: Own address 2 register 190 * @tmgr: Timing register 191 */ 192 struct stm32f7_i2c_regs { 193 u32 cr1; 194 u32 cr2; 195 u32 oar1; 196 u32 oar2; 197 u32 tmgr; 198 }; 199 200 /** 201 * struct stm32f7_i2c_spec - private i2c specification timing 202 * @rate: I2C bus speed (Hz) 203 * @fall_max: Max fall time of both SDA and SCL signals (ns) 204 * @rise_max: Max rise time of both SDA and SCL signals (ns) 205 * @hddat_min: Min data hold time (ns) 206 * @vddat_max: Max data valid time (ns) 207 * @sudat_min: Min data setup time (ns) 208 * @l_min: Min low period of the SCL clock (ns) 209 * @h_min: Min high period of the SCL clock (ns) 210 */ 211 struct stm32f7_i2c_spec { 212 u32 rate; 213 u32 fall_max; 214 u32 rise_max; 215 u32 hddat_min; 216 u32 vddat_max; 217 u32 sudat_min; 218 u32 l_min; 219 u32 h_min; 220 }; 221 222 /** 223 * struct stm32f7_i2c_setup - private I2C timing setup parameters 224 * @speed_freq: I2C speed frequency (Hz) 225 * @clock_src: I2C clock source frequency (Hz) 226 * @rise_time: Rise time (ns) 227 * @fall_time: Fall time (ns) 228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 229 */ 230 struct stm32f7_i2c_setup { 231 u32 speed_freq; 232 u32 clock_src; 233 u32 rise_time; 234 u32 fall_time; 235 u32 fmp_clr_offset; 236 }; 237 238 /** 239 * struct stm32f7_i2c_timings - private I2C output parameters 240 * @node: List entry 241 * @presc: Prescaler value 242 * @scldel: Data setup time 243 * @sdadel: Data hold time 244 * @sclh: SCL high period (master mode) 245 * @scll: SCL low period (master mode) 246 */ 247 struct stm32f7_i2c_timings { 248 struct list_head node; 249 u8 presc; 250 u8 scldel; 251 u8 sdadel; 252 u8 sclh; 253 u8 scll; 254 }; 255 256 /** 257 * struct stm32f7_i2c_msg - client specific data 258 * @addr: 8-bit or 10-bit slave addr, including r/w bit 259 * @count: number of bytes to be transferred 260 * @buf: data buffer 261 * @result: result of the transfer 262 * @stop: last I2C msg to be sent, i.e. STOP to be generated 263 * @smbus: boolean to know if the I2C IP is used in SMBus mode 264 * @size: type of SMBus protocol 265 * @read_write: direction of SMBus protocol 266 * SMBus block read and SMBus block write - block read process call protocols 267 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 268 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 269 * This buffer has to be 32-bit aligned to be compliant with memory address 270 * register in DMA mode. 271 */ 272 struct stm32f7_i2c_msg { 273 u16 addr; 274 u32 count; 275 u8 *buf; 276 int result; 277 bool stop; 278 bool smbus; 279 int size; 280 char read_write; 281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 282 }; 283 284 /** 285 * struct stm32f7_i2c_alert - SMBus alert specific data 286 * @setup: platform data for the smbus_alert i2c client 287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert 288 * Response Address 289 */ 290 struct stm32f7_i2c_alert { 291 struct i2c_smbus_alert_setup setup; 292 struct i2c_client *ara; 293 }; 294 295 /** 296 * struct stm32f7_i2c_dev - private data of the controller 297 * @adap: I2C adapter for this controller 298 * @dev: device for this controller 299 * @base: virtual memory area 300 * @complete: completion of I2C message 301 * @clk: hw i2c clock 302 * @bus_rate: I2C clock frequency of the controller 303 * @msg: Pointer to data to be written 304 * @msg_num: number of I2C messages to be executed 305 * @msg_id: message identifiant 306 * @f7_msg: customized i2c msg for driver usage 307 * @setup: I2C timing input setup 308 * @timing: I2C computed timings 309 * @slave: list of slave devices registered on the I2C bus 310 * @slave_running: slave device currently used 311 * @backup_regs: backup of i2c controller registers (for suspend/resume) 312 * @slave_dir: transfer direction for the current slave device 313 * @master_mode: boolean to know in which mode the I2C is running (master or 314 * slave) 315 * @dma: dma data 316 * @use_dma: boolean to know if dma is used in the current transfer 317 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 318 * @fmp_sreg: register address for setting Fast Mode Plus bits 319 * @fmp_creg: register address for clearing Fast Mode Plus bits 320 * @fmp_mask: mask for Fast Mode Plus bits in set register 321 * @wakeup_src: boolean to know if the device is a wakeup source 322 * @smbus_mode: states that the controller is configured in SMBus mode 323 * @host_notify_client: SMBus host-notify client 324 * @analog_filter: boolean to indicate enabling of the analog filter 325 * @dnf_dt: value of digital filter requested via dt 326 * @dnf: value of digital filter to apply 327 * @alert: SMBus alert specific data 328 */ 329 struct stm32f7_i2c_dev { 330 struct i2c_adapter adap; 331 struct device *dev; 332 void __iomem *base; 333 struct completion complete; 334 struct clk *clk; 335 unsigned int bus_rate; 336 struct i2c_msg *msg; 337 unsigned int msg_num; 338 unsigned int msg_id; 339 struct stm32f7_i2c_msg f7_msg; 340 struct stm32f7_i2c_setup setup; 341 struct stm32f7_i2c_timings timing; 342 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 343 struct i2c_client *slave_running; 344 struct stm32f7_i2c_regs backup_regs; 345 u32 slave_dir; 346 bool master_mode; 347 struct stm32_i2c_dma *dma; 348 bool use_dma; 349 struct regmap *regmap; 350 u32 fmp_sreg; 351 u32 fmp_creg; 352 u32 fmp_mask; 353 bool wakeup_src; 354 bool smbus_mode; 355 struct i2c_client *host_notify_client; 356 bool analog_filter; 357 u32 dnf_dt; 358 u32 dnf; 359 struct stm32f7_i2c_alert *alert; 360 bool atomic; 361 }; 362 363 /* 364 * All these values are coming from I2C Specification, Version 6.0, 4th of 365 * April 2014. 366 * 367 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 368 * and Fast-mode Plus I2C-bus devices 369 */ 370 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = { 371 { 372 .rate = I2C_MAX_STANDARD_MODE_FREQ, 373 .fall_max = 300, 374 .rise_max = 1000, 375 .hddat_min = 0, 376 .vddat_max = 3450, 377 .sudat_min = 250, 378 .l_min = 4700, 379 .h_min = 4000, 380 }, 381 { 382 .rate = I2C_MAX_FAST_MODE_FREQ, 383 .fall_max = 300, 384 .rise_max = 300, 385 .hddat_min = 0, 386 .vddat_max = 900, 387 .sudat_min = 100, 388 .l_min = 1300, 389 .h_min = 600, 390 }, 391 { 392 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ, 393 .fall_max = 100, 394 .rise_max = 120, 395 .hddat_min = 0, 396 .vddat_max = 450, 397 .sudat_min = 50, 398 .l_min = 500, 399 .h_min = 260, 400 }, 401 }; 402 403 static const struct stm32f7_i2c_setup stm32f7_setup = { 404 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 405 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 406 }; 407 408 static const struct stm32f7_i2c_setup stm32mp15_setup = { 409 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 410 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 411 .fmp_clr_offset = 0x40, 412 }; 413 414 static const struct stm32f7_i2c_setup stm32mp13_setup = { 415 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 416 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 417 .fmp_clr_offset = 0x4, 418 }; 419 420 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 421 { 422 writel_relaxed(readl_relaxed(reg) | mask, reg); 423 } 424 425 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 426 { 427 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 428 } 429 430 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 431 { 432 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 433 } 434 435 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate) 436 { 437 int i; 438 439 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++) 440 if (rate <= stm32f7_i2c_specs[i].rate) 441 return &stm32f7_i2c_specs[i]; 442 443 return ERR_PTR(-EINVAL); 444 } 445 446 #define RATE_MIN(rate) ((rate) * 8 / 10) 447 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 448 struct stm32f7_i2c_setup *setup, 449 struct stm32f7_i2c_timings *output) 450 { 451 struct stm32f7_i2c_spec *specs; 452 u32 p_prev = STM32F7_PRESC_MAX; 453 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 454 setup->clock_src); 455 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 456 setup->speed_freq); 457 u32 clk_error_prev = i2cbus; 458 u32 tsync; 459 u32 af_delay_min, af_delay_max; 460 u32 dnf_delay; 461 u32 clk_min, clk_max; 462 int sdadel_min, sdadel_max; 463 int scldel_min; 464 struct stm32f7_i2c_timings *v, *_v, *s; 465 struct list_head solutions; 466 u16 p, l, a, h; 467 int ret = 0; 468 469 specs = stm32f7_get_specs(setup->speed_freq); 470 if (specs == ERR_PTR(-EINVAL)) { 471 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", 472 setup->speed_freq); 473 return -EINVAL; 474 } 475 476 if ((setup->rise_time > specs->rise_max) || 477 (setup->fall_time > specs->fall_max)) { 478 dev_err(i2c_dev->dev, 479 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 480 setup->rise_time, specs->rise_max, 481 setup->fall_time, specs->fall_max); 482 return -EINVAL; 483 } 484 485 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); 486 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { 487 dev_err(i2c_dev->dev, 488 "DNF out of bound %d/%d\n", 489 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); 490 return -EINVAL; 491 } 492 493 /* Analog and Digital Filters */ 494 af_delay_min = 495 (i2c_dev->analog_filter ? 496 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 497 af_delay_max = 498 (i2c_dev->analog_filter ? 499 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 500 dnf_delay = i2c_dev->dnf * i2cclk; 501 502 sdadel_min = specs->hddat_min + setup->fall_time - 503 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; 504 505 sdadel_max = specs->vddat_max - setup->rise_time - 506 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; 507 508 scldel_min = setup->rise_time + specs->sudat_min; 509 510 if (sdadel_min < 0) 511 sdadel_min = 0; 512 if (sdadel_max < 0) 513 sdadel_max = 0; 514 515 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 516 sdadel_min, sdadel_max, scldel_min); 517 518 INIT_LIST_HEAD(&solutions); 519 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 520 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 521 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 522 u32 scldel = (l + 1) * (p + 1) * i2cclk; 523 524 if (scldel < scldel_min) 525 continue; 526 527 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 528 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 529 530 if (((sdadel >= sdadel_min) && 531 (sdadel <= sdadel_max)) && 532 (p != p_prev)) { 533 v = kmalloc(sizeof(*v), GFP_KERNEL); 534 if (!v) { 535 ret = -ENOMEM; 536 goto exit; 537 } 538 539 v->presc = p; 540 v->scldel = l; 541 v->sdadel = a; 542 p_prev = p; 543 544 list_add_tail(&v->node, 545 &solutions); 546 break; 547 } 548 } 549 550 if (p_prev == p) 551 break; 552 } 553 } 554 555 if (list_empty(&solutions)) { 556 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 557 ret = -EPERM; 558 goto exit; 559 } 560 561 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 562 s = NULL; 563 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); 564 clk_min = NSEC_PER_SEC / setup->speed_freq; 565 566 /* 567 * Among Prescaler possibilities discovered above figures out SCL Low 568 * and High Period. Provided: 569 * - SCL Low Period has to be higher than SCL Clock Low Period 570 * defined by I2C Specification. I2C Clock has to be lower than 571 * (SCL Low Period - Analog/Digital filters) / 4. 572 * - SCL High Period has to be lower than SCL Clock High Period 573 * defined by I2C Specification 574 * - I2C Clock has to be lower than SCL High Period 575 */ 576 list_for_each_entry(v, &solutions, node) { 577 u32 prescaler = (v->presc + 1) * i2cclk; 578 579 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 580 u32 tscl_l = (l + 1) * prescaler + tsync; 581 582 if ((tscl_l < specs->l_min) || 583 (i2cclk >= 584 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 585 continue; 586 } 587 588 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 589 u32 tscl_h = (h + 1) * prescaler + tsync; 590 u32 tscl = tscl_l + tscl_h + 591 setup->rise_time + setup->fall_time; 592 593 if ((tscl >= clk_min) && (tscl <= clk_max) && 594 (tscl_h >= specs->h_min) && 595 (i2cclk < tscl_h)) { 596 int clk_error = tscl - i2cbus; 597 598 if (clk_error < 0) 599 clk_error = -clk_error; 600 601 if (clk_error < clk_error_prev) { 602 clk_error_prev = clk_error; 603 v->scll = l; 604 v->sclh = h; 605 s = v; 606 } 607 } 608 } 609 } 610 } 611 612 if (!s) { 613 dev_err(i2c_dev->dev, "no solution at all\n"); 614 ret = -EPERM; 615 goto exit; 616 } 617 618 output->presc = s->presc; 619 output->scldel = s->scldel; 620 output->sdadel = s->sdadel; 621 output->scll = s->scll; 622 output->sclh = s->sclh; 623 624 dev_dbg(i2c_dev->dev, 625 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 626 output->presc, 627 output->scldel, output->sdadel, 628 output->scll, output->sclh); 629 630 exit: 631 /* Release list and memory */ 632 list_for_each_entry_safe(v, _v, &solutions, node) { 633 list_del(&v->node); 634 kfree(v); 635 } 636 637 return ret; 638 } 639 640 static u32 stm32f7_get_lower_rate(u32 rate) 641 { 642 int i = ARRAY_SIZE(stm32f7_i2c_specs); 643 644 while (--i) 645 if (stm32f7_i2c_specs[i].rate < rate) 646 break; 647 648 return stm32f7_i2c_specs[i].rate; 649 } 650 651 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 652 struct stm32f7_i2c_setup *setup) 653 { 654 struct i2c_timings timings, *t = &timings; 655 int ret = 0; 656 657 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 658 t->scl_rise_ns = i2c_dev->setup.rise_time; 659 t->scl_fall_ns = i2c_dev->setup.fall_time; 660 661 i2c_parse_fw_timings(i2c_dev->dev, t, false); 662 663 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { 664 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", 665 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); 666 return -EINVAL; 667 } 668 669 setup->speed_freq = t->bus_freq_hz; 670 i2c_dev->setup.rise_time = t->scl_rise_ns; 671 i2c_dev->setup.fall_time = t->scl_fall_ns; 672 i2c_dev->dnf_dt = t->digital_filter_width_ns; 673 setup->clock_src = clk_get_rate(i2c_dev->clk); 674 675 if (!setup->clock_src) { 676 dev_err(i2c_dev->dev, "clock rate is 0\n"); 677 return -EINVAL; 678 } 679 680 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) 681 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; 682 683 do { 684 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 685 &i2c_dev->timing); 686 if (ret) { 687 dev_err(i2c_dev->dev, 688 "failed to compute I2C timings.\n"); 689 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) 690 break; 691 setup->speed_freq = 692 stm32f7_get_lower_rate(setup->speed_freq); 693 dev_warn(i2c_dev->dev, 694 "downgrade I2C Speed Freq to (%i)\n", 695 setup->speed_freq); 696 } 697 } while (ret); 698 699 if (ret) { 700 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 701 return ret; 702 } 703 704 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, 705 "i2c-analog-filter"); 706 707 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 708 setup->speed_freq, setup->clock_src); 709 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 710 setup->rise_time, setup->fall_time); 711 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 712 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); 713 714 i2c_dev->bus_rate = setup->speed_freq; 715 716 return 0; 717 } 718 719 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 720 { 721 void __iomem *base = i2c_dev->base; 722 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 723 724 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 725 } 726 727 static void stm32f7_i2c_dma_callback(void *arg) 728 { 729 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 730 struct stm32_i2c_dma *dma = i2c_dev->dma; 731 struct device *dev = dma->chan_using->device->dev; 732 733 stm32f7_i2c_disable_dma_req(i2c_dev); 734 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 735 complete(&dma->dma_complete); 736 } 737 738 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 739 { 740 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 741 u32 timing = 0; 742 743 /* Timing settings */ 744 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 745 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 746 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 747 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 748 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 749 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 750 751 /* Configure the Analog Filter */ 752 if (i2c_dev->analog_filter) 753 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 754 STM32F7_I2C_CR1_ANFOFF); 755 else 756 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 757 STM32F7_I2C_CR1_ANFOFF); 758 759 /* Program the Digital Filter */ 760 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 761 STM32F7_I2C_CR1_DNF_MASK); 762 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 763 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); 764 765 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 766 STM32F7_I2C_CR1_PE); 767 } 768 769 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 770 { 771 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 772 void __iomem *base = i2c_dev->base; 773 774 if (f7_msg->count) { 775 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 776 f7_msg->count--; 777 } 778 } 779 780 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 781 { 782 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 783 void __iomem *base = i2c_dev->base; 784 785 if (f7_msg->count) { 786 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 787 f7_msg->count--; 788 } else { 789 /* Flush RX buffer has no data is expected */ 790 readb_relaxed(base + STM32F7_I2C_RXDR); 791 } 792 } 793 794 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 795 { 796 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 797 u32 cr2; 798 799 if (i2c_dev->use_dma) 800 f7_msg->count -= STM32F7_I2C_MAX_LEN; 801 802 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 803 804 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 805 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 806 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 807 } else { 808 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 809 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 810 } 811 812 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 813 } 814 815 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 816 { 817 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 818 u32 cr2; 819 u8 *val; 820 821 /* 822 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 823 * data received inform us how many data will follow. 824 */ 825 stm32f7_i2c_read_rx_data(i2c_dev); 826 827 /* 828 * Update NBYTES with the value read to continue the transfer 829 */ 830 val = f7_msg->buf - sizeof(u8); 831 f7_msg->count = *val; 832 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 833 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 834 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 835 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 836 } 837 838 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 839 { 840 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 841 842 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 843 STM32F7_I2C_CR1_PE); 844 845 stm32f7_i2c_hw_config(i2c_dev); 846 } 847 848 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 849 { 850 u32 status; 851 int ret; 852 853 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 854 status, 855 !(status & STM32F7_I2C_ISR_BUSY), 856 10, 1000); 857 if (!ret) 858 return 0; 859 860 stm32f7_i2c_release_bus(&i2c_dev->adap); 861 862 return -EBUSY; 863 } 864 865 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 866 struct i2c_msg *msg) 867 { 868 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 869 void __iomem *base = i2c_dev->base; 870 u32 cr1, cr2; 871 int ret; 872 873 f7_msg->addr = msg->addr; 874 f7_msg->buf = msg->buf; 875 f7_msg->count = msg->len; 876 f7_msg->result = 0; 877 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 878 879 reinit_completion(&i2c_dev->complete); 880 881 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 882 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 883 884 /* Set transfer direction */ 885 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 886 if (msg->flags & I2C_M_RD) 887 cr2 |= STM32F7_I2C_CR2_RD_WRN; 888 889 /* Set slave address */ 890 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 891 if (msg->flags & I2C_M_TEN) { 892 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 893 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 894 cr2 |= STM32F7_I2C_CR2_ADD10; 895 } else { 896 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 897 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 898 } 899 900 /* Set nb bytes to transfer and reload if needed */ 901 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 902 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 903 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 904 cr2 |= STM32F7_I2C_CR2_RELOAD; 905 } else { 906 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 907 } 908 909 /* Enable NACK, STOP, error and transfer complete interrupts */ 910 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 911 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 912 913 /* Clear DMA req and TX/RX interrupt */ 914 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 915 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 916 917 /* Configure DMA or enable RX/TX interrupt */ 918 i2c_dev->use_dma = false; 919 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN 920 && !i2c_dev->atomic) { 921 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 922 msg->flags & I2C_M_RD, 923 f7_msg->count, f7_msg->buf, 924 stm32f7_i2c_dma_callback, 925 i2c_dev); 926 if (!ret) 927 i2c_dev->use_dma = true; 928 else 929 dev_warn(i2c_dev->dev, "can't use DMA\n"); 930 } 931 932 if (!i2c_dev->use_dma) { 933 if (msg->flags & I2C_M_RD) 934 cr1 |= STM32F7_I2C_CR1_RXIE; 935 else 936 cr1 |= STM32F7_I2C_CR1_TXIE; 937 } else { 938 if (msg->flags & I2C_M_RD) 939 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 940 else 941 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 942 } 943 944 if (i2c_dev->atomic) 945 cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */ 946 947 /* Configure Start/Repeated Start */ 948 cr2 |= STM32F7_I2C_CR2_START; 949 950 i2c_dev->master_mode = true; 951 952 /* Write configurations registers */ 953 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 954 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 955 } 956 957 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 958 unsigned short flags, u8 command, 959 union i2c_smbus_data *data) 960 { 961 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 962 struct device *dev = i2c_dev->dev; 963 void __iomem *base = i2c_dev->base; 964 u32 cr1, cr2; 965 int i, ret; 966 967 f7_msg->result = 0; 968 reinit_completion(&i2c_dev->complete); 969 970 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 971 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 972 973 /* Set transfer direction */ 974 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 975 if (f7_msg->read_write) 976 cr2 |= STM32F7_I2C_CR2_RD_WRN; 977 978 /* Set slave address */ 979 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 980 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 981 982 f7_msg->smbus_buf[0] = command; 983 switch (f7_msg->size) { 984 case I2C_SMBUS_QUICK: 985 f7_msg->stop = true; 986 f7_msg->count = 0; 987 break; 988 case I2C_SMBUS_BYTE: 989 f7_msg->stop = true; 990 f7_msg->count = 1; 991 break; 992 case I2C_SMBUS_BYTE_DATA: 993 if (f7_msg->read_write) { 994 f7_msg->stop = false; 995 f7_msg->count = 1; 996 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 997 } else { 998 f7_msg->stop = true; 999 f7_msg->count = 2; 1000 f7_msg->smbus_buf[1] = data->byte; 1001 } 1002 break; 1003 case I2C_SMBUS_WORD_DATA: 1004 if (f7_msg->read_write) { 1005 f7_msg->stop = false; 1006 f7_msg->count = 1; 1007 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1008 } else { 1009 f7_msg->stop = true; 1010 f7_msg->count = 3; 1011 f7_msg->smbus_buf[1] = data->word & 0xff; 1012 f7_msg->smbus_buf[2] = data->word >> 8; 1013 } 1014 break; 1015 case I2C_SMBUS_BLOCK_DATA: 1016 if (f7_msg->read_write) { 1017 f7_msg->stop = false; 1018 f7_msg->count = 1; 1019 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1020 } else { 1021 f7_msg->stop = true; 1022 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 1023 !data->block[0]) { 1024 dev_err(dev, "Invalid block write size %d\n", 1025 data->block[0]); 1026 return -EINVAL; 1027 } 1028 f7_msg->count = data->block[0] + 2; 1029 for (i = 1; i < f7_msg->count; i++) 1030 f7_msg->smbus_buf[i] = data->block[i - 1]; 1031 } 1032 break; 1033 case I2C_SMBUS_PROC_CALL: 1034 f7_msg->stop = false; 1035 f7_msg->count = 3; 1036 f7_msg->smbus_buf[1] = data->word & 0xff; 1037 f7_msg->smbus_buf[2] = data->word >> 8; 1038 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1039 f7_msg->read_write = I2C_SMBUS_READ; 1040 break; 1041 case I2C_SMBUS_BLOCK_PROC_CALL: 1042 f7_msg->stop = false; 1043 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 1044 dev_err(dev, "Invalid block write size %d\n", 1045 data->block[0]); 1046 return -EINVAL; 1047 } 1048 f7_msg->count = data->block[0] + 2; 1049 for (i = 1; i < f7_msg->count; i++) 1050 f7_msg->smbus_buf[i] = data->block[i - 1]; 1051 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1052 f7_msg->read_write = I2C_SMBUS_READ; 1053 break; 1054 case I2C_SMBUS_I2C_BLOCK_DATA: 1055 /* Rely on emulated i2c transfer (through master_xfer) */ 1056 return -EOPNOTSUPP; 1057 default: 1058 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 1059 return -EOPNOTSUPP; 1060 } 1061 1062 f7_msg->buf = f7_msg->smbus_buf; 1063 1064 /* Configure PEC */ 1065 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 1066 cr1 |= STM32F7_I2C_CR1_PECEN; 1067 if (!f7_msg->read_write) { 1068 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1069 f7_msg->count++; 1070 } 1071 } else { 1072 cr1 &= ~STM32F7_I2C_CR1_PECEN; 1073 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 1074 } 1075 1076 /* Set number of bytes to be transferred */ 1077 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 1078 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1079 1080 /* Enable NACK, STOP, error and transfer complete interrupts */ 1081 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 1082 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 1083 1084 /* Clear DMA req and TX/RX interrupt */ 1085 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1086 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1087 1088 /* Configure DMA or enable RX/TX interrupt */ 1089 i2c_dev->use_dma = false; 1090 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 1091 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1092 cr2 & STM32F7_I2C_CR2_RD_WRN, 1093 f7_msg->count, f7_msg->buf, 1094 stm32f7_i2c_dma_callback, 1095 i2c_dev); 1096 if (!ret) 1097 i2c_dev->use_dma = true; 1098 else 1099 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1100 } 1101 1102 if (!i2c_dev->use_dma) { 1103 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1104 cr1 |= STM32F7_I2C_CR1_RXIE; 1105 else 1106 cr1 |= STM32F7_I2C_CR1_TXIE; 1107 } else { 1108 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1109 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1110 else 1111 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1112 } 1113 1114 /* Set Start bit */ 1115 cr2 |= STM32F7_I2C_CR2_START; 1116 1117 i2c_dev->master_mode = true; 1118 1119 /* Write configurations registers */ 1120 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1121 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1122 1123 return 0; 1124 } 1125 1126 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1127 { 1128 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1129 void __iomem *base = i2c_dev->base; 1130 u32 cr1, cr2; 1131 int ret; 1132 1133 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1134 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1135 1136 /* Set transfer direction */ 1137 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1138 1139 switch (f7_msg->size) { 1140 case I2C_SMBUS_BYTE_DATA: 1141 f7_msg->count = 1; 1142 break; 1143 case I2C_SMBUS_WORD_DATA: 1144 case I2C_SMBUS_PROC_CALL: 1145 f7_msg->count = 2; 1146 break; 1147 case I2C_SMBUS_BLOCK_DATA: 1148 case I2C_SMBUS_BLOCK_PROC_CALL: 1149 f7_msg->count = 1; 1150 cr2 |= STM32F7_I2C_CR2_RELOAD; 1151 break; 1152 } 1153 1154 f7_msg->buf = f7_msg->smbus_buf; 1155 f7_msg->stop = true; 1156 1157 /* Add one byte for PEC if needed */ 1158 if (cr1 & STM32F7_I2C_CR1_PECEN) { 1159 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1160 f7_msg->count++; 1161 } 1162 1163 /* Set number of bytes to be transferred */ 1164 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1165 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1166 1167 /* 1168 * Configure RX/TX interrupt: 1169 */ 1170 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1171 cr1 |= STM32F7_I2C_CR1_RXIE; 1172 1173 /* 1174 * Configure DMA or enable RX/TX interrupt: 1175 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1176 * dma as we don't know in advance how many data will be received 1177 */ 1178 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1179 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1180 1181 i2c_dev->use_dma = false; 1182 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1183 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1184 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1185 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1186 cr2 & STM32F7_I2C_CR2_RD_WRN, 1187 f7_msg->count, f7_msg->buf, 1188 stm32f7_i2c_dma_callback, 1189 i2c_dev); 1190 1191 if (!ret) 1192 i2c_dev->use_dma = true; 1193 else 1194 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1195 } 1196 1197 if (!i2c_dev->use_dma) 1198 cr1 |= STM32F7_I2C_CR1_RXIE; 1199 else 1200 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1201 1202 /* Configure Repeated Start */ 1203 cr2 |= STM32F7_I2C_CR2_START; 1204 1205 /* Write configurations registers */ 1206 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1207 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1208 } 1209 1210 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1211 { 1212 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1213 u8 count, internal_pec, received_pec; 1214 1215 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1216 1217 switch (f7_msg->size) { 1218 case I2C_SMBUS_BYTE: 1219 case I2C_SMBUS_BYTE_DATA: 1220 received_pec = f7_msg->smbus_buf[1]; 1221 break; 1222 case I2C_SMBUS_WORD_DATA: 1223 case I2C_SMBUS_PROC_CALL: 1224 received_pec = f7_msg->smbus_buf[2]; 1225 break; 1226 case I2C_SMBUS_BLOCK_DATA: 1227 case I2C_SMBUS_BLOCK_PROC_CALL: 1228 count = f7_msg->smbus_buf[0]; 1229 received_pec = f7_msg->smbus_buf[count]; 1230 break; 1231 default: 1232 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1233 return -EINVAL; 1234 } 1235 1236 if (internal_pec != received_pec) { 1237 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1238 internal_pec, received_pec); 1239 return -EBADMSG; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1246 { 1247 u32 addr; 1248 1249 if (!slave) 1250 return false; 1251 1252 if (slave->flags & I2C_CLIENT_TEN) { 1253 /* 1254 * For 10-bit addr, addcode = 11110XY with 1255 * X = Bit 9 of slave address 1256 * Y = Bit 8 of slave address 1257 */ 1258 addr = slave->addr >> 8; 1259 addr |= 0x78; 1260 if (addr == addcode) 1261 return true; 1262 } else { 1263 addr = slave->addr & 0x7f; 1264 if (addr == addcode) 1265 return true; 1266 } 1267 1268 return false; 1269 } 1270 1271 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1272 { 1273 struct i2c_client *slave = i2c_dev->slave_running; 1274 void __iomem *base = i2c_dev->base; 1275 u32 mask; 1276 u8 value = 0; 1277 1278 if (i2c_dev->slave_dir) { 1279 /* Notify i2c slave that new read transfer is starting */ 1280 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1281 1282 /* 1283 * Disable slave TX config in case of I2C combined message 1284 * (I2C Write followed by I2C Read) 1285 */ 1286 mask = STM32F7_I2C_CR2_RELOAD; 1287 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1288 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1289 STM32F7_I2C_CR1_TCIE; 1290 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1291 1292 /* Enable TX empty, STOP, NACK interrupts */ 1293 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1294 STM32F7_I2C_CR1_TXIE; 1295 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1296 1297 /* Write 1st data byte */ 1298 writel_relaxed(value, base + STM32F7_I2C_TXDR); 1299 } else { 1300 /* Notify i2c slave that new write transfer is starting */ 1301 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1302 1303 /* Set reload mode to be able to ACK/NACK each received byte */ 1304 mask = STM32F7_I2C_CR2_RELOAD; 1305 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1306 1307 /* 1308 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1309 * Set Slave Byte Control to be able to ACK/NACK each data 1310 * byte received 1311 */ 1312 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1313 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1314 STM32F7_I2C_CR1_TCIE; 1315 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1316 } 1317 } 1318 1319 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1320 { 1321 void __iomem *base = i2c_dev->base; 1322 u32 isr, addcode, dir, mask; 1323 int i; 1324 1325 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1326 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1327 dir = isr & STM32F7_I2C_ISR_DIR; 1328 1329 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1330 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1331 i2c_dev->slave_running = i2c_dev->slave[i]; 1332 i2c_dev->slave_dir = dir; 1333 1334 /* Start I2C slave processing */ 1335 stm32f7_i2c_slave_start(i2c_dev); 1336 1337 /* Clear ADDR flag */ 1338 mask = STM32F7_I2C_ICR_ADDRCF; 1339 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1340 break; 1341 } 1342 } 1343 } 1344 1345 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1346 struct i2c_client *slave, int *id) 1347 { 1348 int i; 1349 1350 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1351 if (i2c_dev->slave[i] == slave) { 1352 *id = i; 1353 return 0; 1354 } 1355 } 1356 1357 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1358 1359 return -ENODEV; 1360 } 1361 1362 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1363 struct i2c_client *slave, int *id) 1364 { 1365 struct device *dev = i2c_dev->dev; 1366 int i; 1367 1368 /* 1369 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8) 1370 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address 1371 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only 1372 */ 1373 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { 1374 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) 1375 goto fail; 1376 *id = STM32F7_SLAVE_HOSTNOTIFY; 1377 return 0; 1378 } 1379 1380 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { 1381 if ((i == STM32F7_SLAVE_7_BITS_ADDR) && 1382 (slave->flags & I2C_CLIENT_TEN)) 1383 continue; 1384 if (!i2c_dev->slave[i]) { 1385 *id = i; 1386 return 0; 1387 } 1388 } 1389 1390 fail: 1391 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1392 1393 return -EINVAL; 1394 } 1395 1396 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1397 { 1398 int i; 1399 1400 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1401 if (i2c_dev->slave[i]) 1402 return true; 1403 } 1404 1405 return false; 1406 } 1407 1408 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1409 { 1410 int i, busy; 1411 1412 busy = 0; 1413 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1414 if (i2c_dev->slave[i]) 1415 busy++; 1416 } 1417 1418 return i == busy; 1419 } 1420 1421 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev) 1422 { 1423 void __iomem *base = i2c_dev->base; 1424 u32 cr2, status, mask; 1425 u8 val; 1426 int ret; 1427 1428 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1429 1430 /* Slave transmitter mode */ 1431 if (status & STM32F7_I2C_ISR_TXIS) { 1432 i2c_slave_event(i2c_dev->slave_running, 1433 I2C_SLAVE_READ_PROCESSED, 1434 &val); 1435 1436 /* Write data byte */ 1437 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1438 } 1439 1440 /* Transfer Complete Reload for Slave receiver mode */ 1441 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1442 /* 1443 * Read data byte then set NBYTES to receive next byte or NACK 1444 * the current received byte 1445 */ 1446 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1447 ret = i2c_slave_event(i2c_dev->slave_running, 1448 I2C_SLAVE_WRITE_RECEIVED, 1449 &val); 1450 if (!ret) { 1451 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1452 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1453 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1454 } else { 1455 mask = STM32F7_I2C_CR2_NACK; 1456 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1457 } 1458 } 1459 1460 /* NACK received */ 1461 if (status & STM32F7_I2C_ISR_NACKF) { 1462 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1463 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1464 } 1465 1466 /* STOP received */ 1467 if (status & STM32F7_I2C_ISR_STOPF) { 1468 /* Disable interrupts */ 1469 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1470 1471 if (i2c_dev->slave_dir) { 1472 /* 1473 * Flush TX buffer in order to not used the byte in 1474 * TXDR for the next transfer 1475 */ 1476 mask = STM32F7_I2C_ISR_TXE; 1477 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1478 } 1479 1480 /* Clear STOP flag */ 1481 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1482 1483 /* Notify i2c slave that a STOP flag has been detected */ 1484 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1485 1486 i2c_dev->slave_running = NULL; 1487 } 1488 1489 /* Address match received */ 1490 if (status & STM32F7_I2C_ISR_ADDR) 1491 stm32f7_i2c_slave_addr(i2c_dev); 1492 1493 return IRQ_HANDLED; 1494 } 1495 1496 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1497 { 1498 struct stm32f7_i2c_dev *i2c_dev = data; 1499 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1500 struct stm32_i2c_dma *dma = i2c_dev->dma; 1501 void __iomem *base = i2c_dev->base; 1502 u32 status, mask; 1503 int ret = IRQ_HANDLED; 1504 1505 /* Check if the interrupt if for a slave device */ 1506 if (!i2c_dev->master_mode) { 1507 ret = stm32f7_i2c_slave_isr_event(i2c_dev); 1508 return ret; 1509 } 1510 1511 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1512 1513 /* Tx empty */ 1514 if (status & STM32F7_I2C_ISR_TXIS) 1515 stm32f7_i2c_write_tx_data(i2c_dev); 1516 1517 /* RX not empty */ 1518 if (status & STM32F7_I2C_ISR_RXNE) 1519 stm32f7_i2c_read_rx_data(i2c_dev); 1520 1521 /* NACK received */ 1522 if (status & STM32F7_I2C_ISR_NACKF) { 1523 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", 1524 __func__, f7_msg->addr); 1525 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1526 if (i2c_dev->use_dma) { 1527 stm32f7_i2c_disable_dma_req(i2c_dev); 1528 dmaengine_terminate_async(dma->chan_using); 1529 } 1530 f7_msg->result = -ENXIO; 1531 } 1532 1533 /* STOP detection flag */ 1534 if (status & STM32F7_I2C_ISR_STOPF) { 1535 /* Disable interrupts */ 1536 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1537 mask = STM32F7_I2C_XFER_IRQ_MASK; 1538 else 1539 mask = STM32F7_I2C_ALL_IRQ_MASK; 1540 stm32f7_i2c_disable_irq(i2c_dev, mask); 1541 1542 /* Clear STOP flag */ 1543 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1544 1545 if (i2c_dev->use_dma && !f7_msg->result) { 1546 ret = IRQ_WAKE_THREAD; 1547 } else { 1548 i2c_dev->master_mode = false; 1549 complete(&i2c_dev->complete); 1550 } 1551 } 1552 1553 /* Transfer complete */ 1554 if (status & STM32F7_I2C_ISR_TC) { 1555 if (f7_msg->stop) { 1556 mask = STM32F7_I2C_CR2_STOP; 1557 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1558 } else if (i2c_dev->use_dma && !f7_msg->result) { 1559 ret = IRQ_WAKE_THREAD; 1560 } else if (f7_msg->smbus) { 1561 stm32f7_i2c_smbus_rep_start(i2c_dev); 1562 } else { 1563 i2c_dev->msg_id++; 1564 i2c_dev->msg++; 1565 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1566 } 1567 } 1568 1569 if (status & STM32F7_I2C_ISR_TCR) { 1570 if (f7_msg->smbus) 1571 stm32f7_i2c_smbus_reload(i2c_dev); 1572 else 1573 stm32f7_i2c_reload(i2c_dev); 1574 } 1575 1576 return ret; 1577 } 1578 1579 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1580 { 1581 struct stm32f7_i2c_dev *i2c_dev = data; 1582 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1583 struct stm32_i2c_dma *dma = i2c_dev->dma; 1584 u32 status; 1585 int ret; 1586 1587 /* 1588 * Wait for dma transfer completion before sending next message or 1589 * notity the end of xfer to the client 1590 */ 1591 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1592 if (!ret) { 1593 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1594 stm32f7_i2c_disable_dma_req(i2c_dev); 1595 dmaengine_terminate_async(dma->chan_using); 1596 f7_msg->result = -ETIMEDOUT; 1597 } 1598 1599 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1600 1601 if (status & STM32F7_I2C_ISR_TC) { 1602 if (f7_msg->smbus) { 1603 stm32f7_i2c_smbus_rep_start(i2c_dev); 1604 } else { 1605 i2c_dev->msg_id++; 1606 i2c_dev->msg++; 1607 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1608 } 1609 } else { 1610 i2c_dev->master_mode = false; 1611 complete(&i2c_dev->complete); 1612 } 1613 1614 return IRQ_HANDLED; 1615 } 1616 1617 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data) 1618 { 1619 struct stm32f7_i2c_dev *i2c_dev = data; 1620 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1621 void __iomem *base = i2c_dev->base; 1622 struct device *dev = i2c_dev->dev; 1623 struct stm32_i2c_dma *dma = i2c_dev->dma; 1624 u32 status; 1625 1626 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1627 1628 /* Bus error */ 1629 if (status & STM32F7_I2C_ISR_BERR) { 1630 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n", 1631 __func__, f7_msg->addr); 1632 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1633 stm32f7_i2c_release_bus(&i2c_dev->adap); 1634 f7_msg->result = -EIO; 1635 } 1636 1637 /* Arbitration loss */ 1638 if (status & STM32F7_I2C_ISR_ARLO) { 1639 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n", 1640 __func__, f7_msg->addr); 1641 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1642 f7_msg->result = -EAGAIN; 1643 } 1644 1645 if (status & STM32F7_I2C_ISR_PECERR) { 1646 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n", 1647 __func__, f7_msg->addr); 1648 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1649 f7_msg->result = -EINVAL; 1650 } 1651 1652 if (status & STM32F7_I2C_ISR_ALERT) { 1653 dev_dbg(dev, "<%s>: SMBus alert received\n", __func__); 1654 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR); 1655 i2c_handle_smbus_alert(i2c_dev->alert->ara); 1656 return IRQ_HANDLED; 1657 } 1658 1659 if (!i2c_dev->slave_running) { 1660 u32 mask; 1661 /* Disable interrupts */ 1662 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1663 mask = STM32F7_I2C_XFER_IRQ_MASK; 1664 else 1665 mask = STM32F7_I2C_ALL_IRQ_MASK; 1666 stm32f7_i2c_disable_irq(i2c_dev, mask); 1667 } 1668 1669 /* Disable dma */ 1670 if (i2c_dev->use_dma) { 1671 stm32f7_i2c_disable_dma_req(i2c_dev); 1672 dmaengine_terminate_async(dma->chan_using); 1673 } 1674 1675 i2c_dev->master_mode = false; 1676 complete(&i2c_dev->complete); 1677 1678 return IRQ_HANDLED; 1679 } 1680 1681 static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev) 1682 { 1683 ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout); 1684 1685 while (ktime_compare(ktime_get(), timeout) < 0) { 1686 udelay(5); 1687 stm32f7_i2c_isr_event(0, i2c_dev); 1688 1689 if (completion_done(&i2c_dev->complete)) 1690 return 1; 1691 } 1692 1693 return 0; 1694 } 1695 1696 static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap, 1697 struct i2c_msg msgs[], int num) 1698 { 1699 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1700 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1701 struct stm32_i2c_dma *dma = i2c_dev->dma; 1702 unsigned long time_left; 1703 int ret; 1704 1705 i2c_dev->msg = msgs; 1706 i2c_dev->msg_num = num; 1707 i2c_dev->msg_id = 0; 1708 f7_msg->smbus = false; 1709 1710 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1711 if (ret < 0) 1712 return ret; 1713 1714 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1715 if (ret) 1716 goto pm_free; 1717 1718 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1719 1720 if (!i2c_dev->atomic) 1721 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1722 i2c_dev->adap.timeout); 1723 else 1724 time_left = stm32f7_i2c_wait_polling(i2c_dev); 1725 1726 ret = f7_msg->result; 1727 if (ret) { 1728 if (i2c_dev->use_dma) 1729 dmaengine_synchronize(dma->chan_using); 1730 1731 /* 1732 * It is possible that some unsent data have already been 1733 * written into TXDR. To avoid sending old data in a 1734 * further transfer, flush TXDR in case of any error 1735 */ 1736 writel_relaxed(STM32F7_I2C_ISR_TXE, 1737 i2c_dev->base + STM32F7_I2C_ISR); 1738 goto pm_free; 1739 } 1740 1741 if (!time_left) { 1742 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1743 i2c_dev->msg->addr); 1744 if (i2c_dev->use_dma) 1745 dmaengine_terminate_sync(dma->chan_using); 1746 stm32f7_i2c_wait_free_bus(i2c_dev); 1747 ret = -ETIMEDOUT; 1748 } 1749 1750 pm_free: 1751 pm_runtime_mark_last_busy(i2c_dev->dev); 1752 pm_runtime_put_autosuspend(i2c_dev->dev); 1753 1754 return (ret < 0) ? ret : num; 1755 } 1756 1757 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1758 struct i2c_msg msgs[], int num) 1759 { 1760 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1761 1762 i2c_dev->atomic = false; 1763 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num); 1764 } 1765 1766 static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap, 1767 struct i2c_msg msgs[], int num) 1768 { 1769 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1770 1771 i2c_dev->atomic = true; 1772 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num); 1773 } 1774 1775 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1776 unsigned short flags, char read_write, 1777 u8 command, int size, 1778 union i2c_smbus_data *data) 1779 { 1780 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1781 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1782 struct stm32_i2c_dma *dma = i2c_dev->dma; 1783 struct device *dev = i2c_dev->dev; 1784 unsigned long timeout; 1785 int i, ret; 1786 1787 f7_msg->addr = addr; 1788 f7_msg->size = size; 1789 f7_msg->read_write = read_write; 1790 f7_msg->smbus = true; 1791 1792 ret = pm_runtime_resume_and_get(dev); 1793 if (ret < 0) 1794 return ret; 1795 1796 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1797 if (ret) 1798 goto pm_free; 1799 1800 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1801 if (ret) 1802 goto pm_free; 1803 1804 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1805 i2c_dev->adap.timeout); 1806 ret = f7_msg->result; 1807 if (ret) { 1808 if (i2c_dev->use_dma) 1809 dmaengine_synchronize(dma->chan_using); 1810 1811 /* 1812 * It is possible that some unsent data have already been 1813 * written into TXDR. To avoid sending old data in a 1814 * further transfer, flush TXDR in case of any error 1815 */ 1816 writel_relaxed(STM32F7_I2C_ISR_TXE, 1817 i2c_dev->base + STM32F7_I2C_ISR); 1818 goto pm_free; 1819 } 1820 1821 if (!timeout) { 1822 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1823 if (i2c_dev->use_dma) 1824 dmaengine_terminate_sync(dma->chan_using); 1825 stm32f7_i2c_wait_free_bus(i2c_dev); 1826 ret = -ETIMEDOUT; 1827 goto pm_free; 1828 } 1829 1830 /* Check PEC */ 1831 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1832 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1833 if (ret) 1834 goto pm_free; 1835 } 1836 1837 if (read_write && size != I2C_SMBUS_QUICK) { 1838 switch (size) { 1839 case I2C_SMBUS_BYTE: 1840 case I2C_SMBUS_BYTE_DATA: 1841 data->byte = f7_msg->smbus_buf[0]; 1842 break; 1843 case I2C_SMBUS_WORD_DATA: 1844 case I2C_SMBUS_PROC_CALL: 1845 data->word = f7_msg->smbus_buf[0] | 1846 (f7_msg->smbus_buf[1] << 8); 1847 break; 1848 case I2C_SMBUS_BLOCK_DATA: 1849 case I2C_SMBUS_BLOCK_PROC_CALL: 1850 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1851 data->block[i] = f7_msg->smbus_buf[i]; 1852 break; 1853 default: 1854 dev_err(dev, "Unsupported smbus transaction\n"); 1855 ret = -EINVAL; 1856 } 1857 } 1858 1859 pm_free: 1860 pm_runtime_mark_last_busy(dev); 1861 pm_runtime_put_autosuspend(dev); 1862 return ret; 1863 } 1864 1865 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, 1866 bool enable) 1867 { 1868 void __iomem *base = i2c_dev->base; 1869 u32 mask = STM32F7_I2C_CR1_WUPEN; 1870 1871 if (!i2c_dev->wakeup_src) 1872 return; 1873 1874 if (enable) { 1875 device_set_wakeup_enable(i2c_dev->dev, true); 1876 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1877 } else { 1878 device_set_wakeup_enable(i2c_dev->dev, false); 1879 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1880 } 1881 } 1882 1883 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1884 { 1885 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1886 void __iomem *base = i2c_dev->base; 1887 struct device *dev = i2c_dev->dev; 1888 u32 oar1, oar2, mask; 1889 int id, ret; 1890 1891 if (slave->flags & I2C_CLIENT_PEC) { 1892 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1893 return -EINVAL; 1894 } 1895 1896 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1897 dev_err(dev, "Too much slave registered\n"); 1898 return -EBUSY; 1899 } 1900 1901 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1902 if (ret) 1903 return ret; 1904 1905 ret = pm_runtime_resume_and_get(dev); 1906 if (ret < 0) 1907 return ret; 1908 1909 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1910 stm32f7_i2c_enable_wakeup(i2c_dev, true); 1911 1912 switch (id) { 1913 case 0: 1914 /* Slave SMBus Host */ 1915 i2c_dev->slave[id] = slave; 1916 break; 1917 1918 case 1: 1919 /* Configure Own Address 1 */ 1920 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1921 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1922 if (slave->flags & I2C_CLIENT_TEN) { 1923 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1924 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1925 } else { 1926 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1927 } 1928 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1929 i2c_dev->slave[id] = slave; 1930 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1931 break; 1932 1933 case 2: 1934 /* Configure Own Address 2 */ 1935 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1936 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1937 if (slave->flags & I2C_CLIENT_TEN) { 1938 ret = -EOPNOTSUPP; 1939 goto pm_free; 1940 } 1941 1942 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1943 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1944 i2c_dev->slave[id] = slave; 1945 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1946 break; 1947 1948 default: 1949 dev_err(dev, "I2C slave id not supported\n"); 1950 ret = -ENODEV; 1951 goto pm_free; 1952 } 1953 1954 /* Enable ACK */ 1955 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1956 1957 /* Enable Address match interrupt, error interrupt and enable I2C */ 1958 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1959 STM32F7_I2C_CR1_PE; 1960 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1961 1962 ret = 0; 1963 pm_free: 1964 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1965 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1966 1967 pm_runtime_mark_last_busy(dev); 1968 pm_runtime_put_autosuspend(dev); 1969 1970 return ret; 1971 } 1972 1973 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1974 { 1975 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1976 void __iomem *base = i2c_dev->base; 1977 u32 mask; 1978 int id, ret; 1979 1980 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1981 if (ret) 1982 return ret; 1983 1984 WARN_ON(!i2c_dev->slave[id]); 1985 1986 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1987 if (ret < 0) 1988 return ret; 1989 1990 if (id == 1) { 1991 mask = STM32F7_I2C_OAR1_OA1EN; 1992 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1993 } else if (id == 2) { 1994 mask = STM32F7_I2C_OAR2_OA2EN; 1995 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1996 } 1997 1998 i2c_dev->slave[id] = NULL; 1999 2000 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2001 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 2002 stm32f7_i2c_enable_wakeup(i2c_dev, false); 2003 } 2004 2005 pm_runtime_mark_last_busy(i2c_dev->dev); 2006 pm_runtime_put_autosuspend(i2c_dev->dev); 2007 2008 return 0; 2009 } 2010 2011 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, 2012 bool enable) 2013 { 2014 int ret; 2015 2016 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || 2017 IS_ERR_OR_NULL(i2c_dev->regmap)) 2018 /* Optional */ 2019 return 0; 2020 2021 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) 2022 ret = regmap_update_bits(i2c_dev->regmap, 2023 i2c_dev->fmp_sreg, 2024 i2c_dev->fmp_mask, 2025 enable ? i2c_dev->fmp_mask : 0); 2026 else 2027 ret = regmap_write(i2c_dev->regmap, 2028 enable ? i2c_dev->fmp_sreg : 2029 i2c_dev->fmp_creg, 2030 i2c_dev->fmp_mask); 2031 2032 return ret; 2033 } 2034 2035 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 2036 struct stm32f7_i2c_dev *i2c_dev) 2037 { 2038 struct device_node *np = pdev->dev.of_node; 2039 int ret; 2040 2041 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 2042 if (IS_ERR(i2c_dev->regmap)) 2043 /* Optional */ 2044 return 0; 2045 2046 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, 2047 &i2c_dev->fmp_sreg); 2048 if (ret) 2049 return ret; 2050 2051 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + 2052 i2c_dev->setup.fmp_clr_offset; 2053 2054 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, 2055 &i2c_dev->fmp_mask); 2056 } 2057 2058 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2059 { 2060 struct i2c_adapter *adap = &i2c_dev->adap; 2061 void __iomem *base = i2c_dev->base; 2062 struct i2c_client *client; 2063 2064 client = i2c_new_slave_host_notify_device(adap); 2065 if (IS_ERR(client)) 2066 return PTR_ERR(client); 2067 2068 i2c_dev->host_notify_client = client; 2069 2070 /* Enable SMBus Host address */ 2071 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN); 2072 2073 return 0; 2074 } 2075 2076 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2077 { 2078 void __iomem *base = i2c_dev->base; 2079 2080 if (i2c_dev->host_notify_client) { 2081 /* Disable SMBus Host address */ 2082 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2083 STM32F7_I2C_CR1_SMBHEN); 2084 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); 2085 } 2086 } 2087 2088 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2089 { 2090 struct stm32f7_i2c_alert *alert; 2091 struct i2c_adapter *adap = &i2c_dev->adap; 2092 struct device *dev = i2c_dev->dev; 2093 void __iomem *base = i2c_dev->base; 2094 2095 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL); 2096 if (!alert) 2097 return -ENOMEM; 2098 2099 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); 2100 if (IS_ERR(alert->ara)) 2101 return PTR_ERR(alert->ara); 2102 2103 i2c_dev->alert = alert; 2104 2105 /* Enable SMBus Alert */ 2106 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN); 2107 2108 return 0; 2109 } 2110 2111 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2112 { 2113 struct stm32f7_i2c_alert *alert = i2c_dev->alert; 2114 void __iomem *base = i2c_dev->base; 2115 2116 if (alert) { 2117 /* Disable SMBus Alert */ 2118 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2119 STM32F7_I2C_CR1_ALERTEN); 2120 i2c_unregister_device(alert->ara); 2121 } 2122 } 2123 2124 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 2125 { 2126 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 2127 2128 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 2129 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 2130 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 2131 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 2132 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 2133 I2C_FUNC_SMBUS_I2C_BLOCK; 2134 2135 if (i2c_dev->smbus_mode) 2136 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 2137 2138 return func; 2139 } 2140 2141 static const struct i2c_algorithm stm32f7_i2c_algo = { 2142 .master_xfer = stm32f7_i2c_xfer, 2143 .master_xfer_atomic = stm32f7_i2c_xfer_atomic, 2144 .smbus_xfer = stm32f7_i2c_smbus_xfer, 2145 .functionality = stm32f7_i2c_func, 2146 .reg_slave = stm32f7_i2c_reg_slave, 2147 .unreg_slave = stm32f7_i2c_unreg_slave, 2148 }; 2149 2150 static int stm32f7_i2c_probe(struct platform_device *pdev) 2151 { 2152 struct stm32f7_i2c_dev *i2c_dev; 2153 const struct stm32f7_i2c_setup *setup; 2154 struct resource *res; 2155 struct i2c_adapter *adap; 2156 struct reset_control *rst; 2157 dma_addr_t phy_addr; 2158 int irq_error, irq_event, ret; 2159 2160 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 2161 if (!i2c_dev) 2162 return -ENOMEM; 2163 2164 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2165 if (IS_ERR(i2c_dev->base)) 2166 return PTR_ERR(i2c_dev->base); 2167 phy_addr = (dma_addr_t)res->start; 2168 2169 irq_event = platform_get_irq(pdev, 0); 2170 if (irq_event < 0) 2171 return irq_event; 2172 2173 irq_error = platform_get_irq(pdev, 1); 2174 if (irq_error < 0) 2175 return irq_error; 2176 2177 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, 2178 "wakeup-source"); 2179 2180 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 2181 if (IS_ERR(i2c_dev->clk)) 2182 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), 2183 "Failed to get controller clock\n"); 2184 2185 ret = clk_prepare_enable(i2c_dev->clk); 2186 if (ret) { 2187 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); 2188 return ret; 2189 } 2190 2191 rst = devm_reset_control_get(&pdev->dev, NULL); 2192 if (IS_ERR(rst)) { 2193 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), 2194 "Error: Missing reset ctrl\n"); 2195 goto clk_free; 2196 } 2197 reset_control_assert(rst); 2198 udelay(2); 2199 reset_control_deassert(rst); 2200 2201 i2c_dev->dev = &pdev->dev; 2202 2203 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 2204 stm32f7_i2c_isr_event, 2205 stm32f7_i2c_isr_event_thread, 2206 IRQF_ONESHOT, 2207 pdev->name, i2c_dev); 2208 if (ret) { 2209 dev_err(&pdev->dev, "Failed to request irq event %i\n", 2210 irq_event); 2211 goto clk_free; 2212 } 2213 2214 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, 2215 pdev->name, i2c_dev); 2216 if (ret) { 2217 dev_err(&pdev->dev, "Failed to request irq error %i\n", 2218 irq_error); 2219 goto clk_free; 2220 } 2221 2222 setup = of_device_get_match_data(&pdev->dev); 2223 if (!setup) { 2224 dev_err(&pdev->dev, "Can't get device data\n"); 2225 ret = -ENODEV; 2226 goto clk_free; 2227 } 2228 i2c_dev->setup = *setup; 2229 2230 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 2231 if (ret) 2232 goto clk_free; 2233 2234 /* Setup Fast mode plus if necessary */ 2235 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { 2236 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 2237 if (ret) 2238 goto clk_free; 2239 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2240 if (ret) 2241 goto clk_free; 2242 } 2243 2244 adap = &i2c_dev->adap; 2245 i2c_set_adapdata(adap, i2c_dev); 2246 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 2247 &res->start); 2248 adap->owner = THIS_MODULE; 2249 adap->timeout = 2 * HZ; 2250 adap->retries = 3; 2251 adap->algo = &stm32f7_i2c_algo; 2252 adap->dev.parent = &pdev->dev; 2253 adap->dev.of_node = pdev->dev.of_node; 2254 2255 init_completion(&i2c_dev->complete); 2256 2257 /* Init DMA config if supported */ 2258 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 2259 STM32F7_I2C_TXDR, 2260 STM32F7_I2C_RXDR); 2261 if (IS_ERR(i2c_dev->dma)) { 2262 ret = PTR_ERR(i2c_dev->dma); 2263 /* DMA support is optional, only report other errors */ 2264 if (ret != -ENODEV) 2265 goto fmp_clear; 2266 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); 2267 i2c_dev->dma = NULL; 2268 } 2269 2270 if (i2c_dev->wakeup_src) { 2271 device_set_wakeup_capable(i2c_dev->dev, true); 2272 2273 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); 2274 if (ret) { 2275 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); 2276 goto clr_wakeup_capable; 2277 } 2278 } 2279 2280 platform_set_drvdata(pdev, i2c_dev); 2281 2282 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 2283 STM32F7_AUTOSUSPEND_DELAY); 2284 pm_runtime_use_autosuspend(i2c_dev->dev); 2285 pm_runtime_set_active(i2c_dev->dev); 2286 pm_runtime_enable(i2c_dev->dev); 2287 2288 pm_runtime_get_noresume(&pdev->dev); 2289 2290 stm32f7_i2c_hw_config(i2c_dev); 2291 2292 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); 2293 2294 ret = i2c_add_adapter(adap); 2295 if (ret) 2296 goto pm_disable; 2297 2298 if (i2c_dev->smbus_mode) { 2299 ret = stm32f7_i2c_enable_smbus_host(i2c_dev); 2300 if (ret) { 2301 dev_err(i2c_dev->dev, 2302 "failed to enable SMBus Host-Notify protocol (%d)\n", 2303 ret); 2304 goto i2c_adapter_remove; 2305 } 2306 } 2307 2308 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { 2309 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev); 2310 if (ret) { 2311 dev_err(i2c_dev->dev, 2312 "failed to enable SMBus alert protocol (%d)\n", 2313 ret); 2314 goto i2c_disable_smbus_host; 2315 } 2316 } 2317 2318 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2319 2320 pm_runtime_mark_last_busy(i2c_dev->dev); 2321 pm_runtime_put_autosuspend(i2c_dev->dev); 2322 2323 return 0; 2324 2325 i2c_disable_smbus_host: 2326 stm32f7_i2c_disable_smbus_host(i2c_dev); 2327 2328 i2c_adapter_remove: 2329 i2c_del_adapter(adap); 2330 2331 pm_disable: 2332 pm_runtime_put_noidle(i2c_dev->dev); 2333 pm_runtime_disable(i2c_dev->dev); 2334 pm_runtime_set_suspended(i2c_dev->dev); 2335 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2336 2337 if (i2c_dev->wakeup_src) 2338 dev_pm_clear_wake_irq(i2c_dev->dev); 2339 2340 clr_wakeup_capable: 2341 if (i2c_dev->wakeup_src) 2342 device_set_wakeup_capable(i2c_dev->dev, false); 2343 2344 if (i2c_dev->dma) { 2345 stm32_i2c_dma_free(i2c_dev->dma); 2346 i2c_dev->dma = NULL; 2347 } 2348 2349 fmp_clear: 2350 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2351 2352 clk_free: 2353 clk_disable_unprepare(i2c_dev->clk); 2354 2355 return ret; 2356 } 2357 2358 static void stm32f7_i2c_remove(struct platform_device *pdev) 2359 { 2360 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2361 2362 stm32f7_i2c_disable_smbus_alert(i2c_dev); 2363 stm32f7_i2c_disable_smbus_host(i2c_dev); 2364 2365 i2c_del_adapter(&i2c_dev->adap); 2366 pm_runtime_get_sync(i2c_dev->dev); 2367 2368 if (i2c_dev->wakeup_src) { 2369 dev_pm_clear_wake_irq(i2c_dev->dev); 2370 /* 2371 * enforce that wakeup is disabled and that the device 2372 * is marked as non wakeup capable 2373 */ 2374 device_init_wakeup(i2c_dev->dev, false); 2375 } 2376 2377 pm_runtime_put_noidle(i2c_dev->dev); 2378 pm_runtime_disable(i2c_dev->dev); 2379 pm_runtime_set_suspended(i2c_dev->dev); 2380 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2381 2382 if (i2c_dev->dma) { 2383 stm32_i2c_dma_free(i2c_dev->dma); 2384 i2c_dev->dma = NULL; 2385 } 2386 2387 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2388 2389 clk_disable_unprepare(i2c_dev->clk); 2390 } 2391 2392 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev) 2393 { 2394 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2395 2396 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2397 clk_disable_unprepare(i2c_dev->clk); 2398 2399 return 0; 2400 } 2401 2402 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev) 2403 { 2404 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2405 int ret; 2406 2407 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2408 ret = clk_prepare_enable(i2c_dev->clk); 2409 if (ret) { 2410 dev_err(dev, "failed to prepare_enable clock\n"); 2411 return ret; 2412 } 2413 } 2414 2415 return 0; 2416 } 2417 2418 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2419 { 2420 int ret; 2421 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2422 2423 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2424 if (ret < 0) 2425 return ret; 2426 2427 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2428 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 2429 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 2430 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 2431 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); 2432 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2433 2434 pm_runtime_put_sync(i2c_dev->dev); 2435 2436 return ret; 2437 } 2438 2439 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2440 { 2441 u32 cr1; 2442 int ret; 2443 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2444 2445 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2446 if (ret < 0) 2447 return ret; 2448 2449 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2450 if (cr1 & STM32F7_I2C_CR1_PE) 2451 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 2452 STM32F7_I2C_CR1_PE); 2453 2454 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); 2455 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, 2456 i2c_dev->base + STM32F7_I2C_CR1); 2457 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) 2458 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 2459 STM32F7_I2C_CR1_PE); 2460 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); 2461 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); 2462 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); 2463 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2464 2465 pm_runtime_put_sync(i2c_dev->dev); 2466 2467 return ret; 2468 } 2469 2470 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev) 2471 { 2472 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2473 int ret; 2474 2475 i2c_mark_adapter_suspended(&i2c_dev->adap); 2476 2477 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2478 ret = stm32f7_i2c_regs_backup(i2c_dev); 2479 if (ret < 0) { 2480 i2c_mark_adapter_resumed(&i2c_dev->adap); 2481 return ret; 2482 } 2483 2484 pinctrl_pm_select_sleep_state(dev); 2485 pm_runtime_force_suspend(dev); 2486 } 2487 2488 return 0; 2489 } 2490 2491 static int __maybe_unused stm32f7_i2c_resume(struct device *dev) 2492 { 2493 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2494 int ret; 2495 2496 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2497 ret = pm_runtime_force_resume(dev); 2498 if (ret < 0) 2499 return ret; 2500 pinctrl_pm_select_default_state(dev); 2501 2502 ret = stm32f7_i2c_regs_restore(i2c_dev); 2503 if (ret < 0) 2504 return ret; 2505 } 2506 2507 i2c_mark_adapter_resumed(&i2c_dev->adap); 2508 2509 return 0; 2510 } 2511 2512 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2513 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2514 stm32f7_i2c_runtime_resume, NULL) 2515 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume) 2516 }; 2517 2518 static const struct of_device_id stm32f7_i2c_match[] = { 2519 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2520 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup}, 2521 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup}, 2522 {}, 2523 }; 2524 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2525 2526 static struct platform_driver stm32f7_i2c_driver = { 2527 .driver = { 2528 .name = "stm32f7-i2c", 2529 .of_match_table = stm32f7_i2c_match, 2530 .pm = &stm32f7_i2c_pm_ops, 2531 }, 2532 .probe = stm32f7_i2c_probe, 2533 .remove_new = stm32f7_i2c_remove, 2534 }; 2535 2536 module_platform_driver(stm32f7_i2c_driver); 2537 2538 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2539 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2540 MODULE_LICENSE("GPL v2"); 2541