xref: /openbmc/linux/drivers/i2c/busses/i2c-st.c (revision c819e2cf)
1 /*
2  * Copyright (C) 2013 STMicroelectronics
3  *
4  * I2C master mode controller driver, used in STMicroelectronics devices.
5  *
6  * Author: Maxime Coquelin <maxime.coquelin@st.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2, as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c.h>
16 #include <linux/clk.h>
17 #include <linux/io.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 
25 /* SSC registers */
26 #define SSC_BRG				0x000
27 #define SSC_TBUF			0x004
28 #define SSC_RBUF			0x008
29 #define SSC_CTL				0x00C
30 #define SSC_IEN				0x010
31 #define SSC_STA				0x014
32 #define SSC_I2C				0x018
33 #define SSC_SLAD			0x01C
34 #define SSC_REP_START_HOLD		0x020
35 #define SSC_START_HOLD			0x024
36 #define SSC_REP_START_SETUP		0x028
37 #define SSC_DATA_SETUP			0x02C
38 #define SSC_STOP_SETUP			0x030
39 #define SSC_BUS_FREE			0x034
40 #define SSC_TX_FSTAT			0x038
41 #define SSC_RX_FSTAT			0x03C
42 #define SSC_PRE_SCALER_BRG		0x040
43 #define SSC_CLR				0x080
44 #define SSC_NOISE_SUPP_WIDTH		0x100
45 #define SSC_PRSCALER			0x104
46 #define SSC_NOISE_SUPP_WIDTH_DATAOUT	0x108
47 #define SSC_PRSCALER_DATAOUT		0x10c
48 
49 /* SSC Control */
50 #define SSC_CTL_DATA_WIDTH_9		0x8
51 #define SSC_CTL_DATA_WIDTH_MSK		0xf
52 #define SSC_CTL_BM			0xf
53 #define SSC_CTL_HB			BIT(4)
54 #define SSC_CTL_PH			BIT(5)
55 #define SSC_CTL_PO			BIT(6)
56 #define SSC_CTL_SR			BIT(7)
57 #define SSC_CTL_MS			BIT(8)
58 #define SSC_CTL_EN			BIT(9)
59 #define SSC_CTL_LPB			BIT(10)
60 #define SSC_CTL_EN_TX_FIFO		BIT(11)
61 #define SSC_CTL_EN_RX_FIFO		BIT(12)
62 #define SSC_CTL_EN_CLST_RX		BIT(13)
63 
64 /* SSC Interrupt Enable */
65 #define SSC_IEN_RIEN			BIT(0)
66 #define SSC_IEN_TIEN			BIT(1)
67 #define SSC_IEN_TEEN			BIT(2)
68 #define SSC_IEN_REEN			BIT(3)
69 #define SSC_IEN_PEEN			BIT(4)
70 #define SSC_IEN_AASEN			BIT(6)
71 #define SSC_IEN_STOPEN			BIT(7)
72 #define SSC_IEN_ARBLEN			BIT(8)
73 #define SSC_IEN_NACKEN			BIT(10)
74 #define SSC_IEN_REPSTRTEN		BIT(11)
75 #define SSC_IEN_TX_FIFO_HALF		BIT(12)
76 #define SSC_IEN_RX_FIFO_HALF_FULL	BIT(14)
77 
78 /* SSC Status */
79 #define SSC_STA_RIR			BIT(0)
80 #define SSC_STA_TIR			BIT(1)
81 #define SSC_STA_TE			BIT(2)
82 #define SSC_STA_RE			BIT(3)
83 #define SSC_STA_PE			BIT(4)
84 #define SSC_STA_CLST			BIT(5)
85 #define SSC_STA_AAS			BIT(6)
86 #define SSC_STA_STOP			BIT(7)
87 #define SSC_STA_ARBL			BIT(8)
88 #define SSC_STA_BUSY			BIT(9)
89 #define SSC_STA_NACK			BIT(10)
90 #define SSC_STA_REPSTRT			BIT(11)
91 #define SSC_STA_TX_FIFO_HALF		BIT(12)
92 #define SSC_STA_TX_FIFO_FULL		BIT(13)
93 #define SSC_STA_RX_FIFO_HALF		BIT(14)
94 
95 /* SSC I2C Control */
96 #define SSC_I2C_I2CM			BIT(0)
97 #define SSC_I2C_STRTG			BIT(1)
98 #define SSC_I2C_STOPG			BIT(2)
99 #define SSC_I2C_ACKG			BIT(3)
100 #define SSC_I2C_AD10			BIT(4)
101 #define SSC_I2C_TXENB			BIT(5)
102 #define SSC_I2C_REPSTRTG		BIT(11)
103 #define SSC_I2C_SLAVE_DISABLE		BIT(12)
104 
105 /* SSC Tx FIFO Status */
106 #define SSC_TX_FSTAT_STATUS		0x07
107 
108 /* SSC Rx FIFO Status */
109 #define SSC_RX_FSTAT_STATUS		0x07
110 
111 /* SSC Clear bit operation */
112 #define SSC_CLR_SSCAAS			BIT(6)
113 #define SSC_CLR_SSCSTOP			BIT(7)
114 #define SSC_CLR_SSCARBL			BIT(8)
115 #define SSC_CLR_NACK			BIT(10)
116 #define SSC_CLR_REPSTRT			BIT(11)
117 
118 /* SSC Clock Prescaler */
119 #define SSC_PRSC_VALUE			0x0f
120 
121 
122 #define SSC_TXFIFO_SIZE			0x8
123 #define SSC_RXFIFO_SIZE			0x8
124 
125 enum st_i2c_mode {
126 	I2C_MODE_STANDARD,
127 	I2C_MODE_FAST,
128 	I2C_MODE_END,
129 };
130 
131 /**
132  * struct st_i2c_timings - per-Mode tuning parameters
133  * @rate: I2C bus rate
134  * @rep_start_hold: I2C repeated start hold time requirement
135  * @rep_start_setup: I2C repeated start set up time requirement
136  * @start_hold: I2C start hold time requirement
137  * @data_setup_time: I2C data set up time requirement
138  * @stop_setup_time: I2C stop set up time requirement
139  * @bus_free_time: I2C bus free time requirement
140  * @sda_pulse_min_limit: I2C SDA pulse mini width limit
141  */
142 struct st_i2c_timings {
143 	u32 rate;
144 	u32 rep_start_hold;
145 	u32 rep_start_setup;
146 	u32 start_hold;
147 	u32 data_setup_time;
148 	u32 stop_setup_time;
149 	u32 bus_free_time;
150 	u32 sda_pulse_min_limit;
151 };
152 
153 /**
154  * struct st_i2c_client - client specific data
155  * @addr: 8-bit slave addr, including r/w bit
156  * @count: number of bytes to be transfered
157  * @xfered: number of bytes already transferred
158  * @buf: data buffer
159  * @result: result of the transfer
160  * @stop: last I2C msg to be sent, i.e. STOP to be generated
161  */
162 struct st_i2c_client {
163 	u8	addr;
164 	u32	count;
165 	u32	xfered;
166 	u8	*buf;
167 	int	result;
168 	bool	stop;
169 };
170 
171 /**
172  * struct st_i2c_dev - private data of the controller
173  * @adap: I2C adapter for this controller
174  * @dev: device for this controller
175  * @base: virtual memory area
176  * @complete: completion of I2C message
177  * @irq: interrupt line for th controller
178  * @clk: hw ssc block clock
179  * @mode: I2C mode of the controller. Standard or Fast only supported
180  * @scl_min_width_us: SCL line minimum pulse width in us
181  * @sda_min_width_us: SDA line minimum pulse width in us
182  * @client: I2C transfert information
183  * @busy: I2C transfer on-going
184  */
185 struct st_i2c_dev {
186 	struct i2c_adapter	adap;
187 	struct device		*dev;
188 	void __iomem		*base;
189 	struct completion	complete;
190 	int			irq;
191 	struct clk		*clk;
192 	int			mode;
193 	u32			scl_min_width_us;
194 	u32			sda_min_width_us;
195 	struct st_i2c_client	client;
196 	bool			busy;
197 };
198 
199 static inline void st_i2c_set_bits(void __iomem *reg, u32 mask)
200 {
201 	writel_relaxed(readl_relaxed(reg) | mask, reg);
202 }
203 
204 static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask)
205 {
206 	writel_relaxed(readl_relaxed(reg) & ~mask, reg);
207 }
208 
209 /*
210  * From I2C Specifications v0.5.
211  *
212  * All the values below have +10% margin added to be
213  * compatible with some out-of-spec devices,
214  * like HDMI link of the Toshiba 19AV600 TV.
215  */
216 static struct st_i2c_timings i2c_timings[] = {
217 	[I2C_MODE_STANDARD] = {
218 		.rate			= 100000,
219 		.rep_start_hold		= 4400,
220 		.rep_start_setup	= 5170,
221 		.start_hold		= 4400,
222 		.data_setup_time	= 275,
223 		.stop_setup_time	= 4400,
224 		.bus_free_time		= 5170,
225 	},
226 	[I2C_MODE_FAST] = {
227 		.rate			= 400000,
228 		.rep_start_hold		= 660,
229 		.rep_start_setup	= 660,
230 		.start_hold		= 660,
231 		.data_setup_time	= 110,
232 		.stop_setup_time	= 660,
233 		.bus_free_time		= 1430,
234 	},
235 };
236 
237 static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev)
238 {
239 	int count, i;
240 
241 	/*
242 	 * Counter only counts up to 7 but fifo size is 8...
243 	 * When fifo is full, counter is 0 and RIR bit of status register is
244 	 * set
245 	 */
246 	if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
247 		count = SSC_RXFIFO_SIZE;
248 	else
249 		count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
250 			SSC_RX_FSTAT_STATUS;
251 
252 	for (i = 0; i < count; i++)
253 		readl_relaxed(i2c_dev->base + SSC_RBUF);
254 }
255 
256 static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev)
257 {
258 	/*
259 	 * FIFO needs to be emptied before reseting the IP,
260 	 * else the controller raises a BUSY error.
261 	 */
262 	st_i2c_flush_rx_fifo(i2c_dev);
263 
264 	st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
265 	st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
266 }
267 
268 /**
269  * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings
270  * @i2c_dev: Controller's private data
271  */
272 static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev)
273 {
274 	unsigned long rate;
275 	u32 val, ns_per_clk;
276 	struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode];
277 
278 	st_i2c_soft_reset(i2c_dev);
279 
280 	val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL |
281 		SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP;
282 	writel_relaxed(val, i2c_dev->base + SSC_CLR);
283 
284 	/* SSC Control register setup */
285 	val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9;
286 	writel_relaxed(val, i2c_dev->base + SSC_CTL);
287 
288 	rate = clk_get_rate(i2c_dev->clk);
289 	ns_per_clk = 1000000000 / rate;
290 
291 	/* Baudrate */
292 	val = rate / (2 * t->rate);
293 	writel_relaxed(val, i2c_dev->base + SSC_BRG);
294 
295 	/* Pre-scaler baudrate */
296 	writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG);
297 
298 	/* Enable I2C mode */
299 	writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C);
300 
301 	/* Repeated start hold time */
302 	val = t->rep_start_hold / ns_per_clk;
303 	writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD);
304 
305 	/* Repeated start set up time */
306 	val = t->rep_start_setup / ns_per_clk;
307 	writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP);
308 
309 	/* Start hold time */
310 	val = t->start_hold / ns_per_clk;
311 	writel_relaxed(val, i2c_dev->base + SSC_START_HOLD);
312 
313 	/* Data set up time */
314 	val = t->data_setup_time / ns_per_clk;
315 	writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP);
316 
317 	/* Stop set up time */
318 	val = t->stop_setup_time / ns_per_clk;
319 	writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP);
320 
321 	/* Bus free time */
322 	val = t->bus_free_time / ns_per_clk;
323 	writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE);
324 
325 	/* Prescalers set up */
326 	val = rate / 10000000;
327 	writel_relaxed(val, i2c_dev->base + SSC_PRSCALER);
328 	writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT);
329 
330 	/* Noise suppression witdh */
331 	val = i2c_dev->scl_min_width_us * rate / 100000000;
332 	writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH);
333 
334 	/* Noise suppression max output data delay width */
335 	val = i2c_dev->sda_min_width_us * rate / 100000000;
336 	writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT);
337 }
338 
339 static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev)
340 {
341 	u32 sta;
342 	int i;
343 
344 	for (i = 0; i < 10; i++) {
345 		sta = readl_relaxed(i2c_dev->base + SSC_STA);
346 		if (!(sta & SSC_STA_BUSY))
347 			return 0;
348 
349 		usleep_range(2000, 4000);
350 	}
351 
352 	dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta);
353 
354 	return -EBUSY;
355 }
356 
357 /**
358  * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO
359  * @i2c_dev: Controller's private data
360  * @byte: Data to write in the Tx FIFO
361  */
362 static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte)
363 {
364 	u16 tbuf = byte << 1;
365 
366 	writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF);
367 }
368 
369 /**
370  * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode
371  * @i2c_dev: Controller's private data
372  *
373  * This functions fills the Tx FIFO with I2C transfert buffer when
374  * in write mode.
375  */
376 static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev)
377 {
378 	struct st_i2c_client *c = &i2c_dev->client;
379 	u32 tx_fstat, sta;
380 	int i;
381 
382 	sta = readl_relaxed(i2c_dev->base + SSC_STA);
383 	if (sta & SSC_STA_TX_FIFO_FULL)
384 		return;
385 
386 	tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
387 	tx_fstat &= SSC_TX_FSTAT_STATUS;
388 
389 	if (c->count < (SSC_TXFIFO_SIZE - tx_fstat))
390 		i = c->count;
391 	else
392 		i = SSC_TXFIFO_SIZE - tx_fstat;
393 
394 	for (; i > 0; i--, c->count--, c->buf++)
395 		st_i2c_write_tx_fifo(i2c_dev, *c->buf);
396 }
397 
398 /**
399  * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode
400  * @i2c_dev: Controller's private data
401  *
402  * This functions fills the Tx FIFO with fixed pattern when
403  * in read mode to trigger clock.
404  */
405 static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max)
406 {
407 	struct st_i2c_client *c = &i2c_dev->client;
408 	u32 tx_fstat, sta;
409 	int i;
410 
411 	sta = readl_relaxed(i2c_dev->base + SSC_STA);
412 	if (sta & SSC_STA_TX_FIFO_FULL)
413 		return;
414 
415 	tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
416 	tx_fstat &= SSC_TX_FSTAT_STATUS;
417 
418 	if (max < (SSC_TXFIFO_SIZE - tx_fstat))
419 		i = max;
420 	else
421 		i = SSC_TXFIFO_SIZE - tx_fstat;
422 
423 	for (; i > 0; i--, c->xfered++)
424 		st_i2c_write_tx_fifo(i2c_dev, 0xff);
425 }
426 
427 static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev)
428 {
429 	struct st_i2c_client *c = &i2c_dev->client;
430 	u32 i, sta;
431 	u16 rbuf;
432 
433 	sta = readl_relaxed(i2c_dev->base + SSC_STA);
434 	if (sta & SSC_STA_RIR) {
435 		i = SSC_RXFIFO_SIZE;
436 	} else {
437 		i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT);
438 		i &= SSC_RX_FSTAT_STATUS;
439 	}
440 
441 	for (; (i > 0) && (c->count > 0); i--, c->count--) {
442 		rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1;
443 		*c->buf++ = (u8)rbuf & 0xff;
444 	}
445 
446 	if (i) {
447 		dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i);
448 		st_i2c_flush_rx_fifo(i2c_dev);
449 	}
450 }
451 
452 /**
453  * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition
454  * @i2c_dev: Controller's private data
455  */
456 static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev)
457 {
458 	struct st_i2c_client *c = &i2c_dev->client;
459 
460 	st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN);
461 	st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
462 
463 	if (c->stop) {
464 		st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN);
465 		st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
466 	} else {
467 		st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN);
468 		st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG);
469 	}
470 }
471 
472 /**
473  * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write
474  * @i2c_dev: Controller's private data
475  */
476 static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev)
477 {
478 	struct st_i2c_client *c = &i2c_dev->client;
479 
480 	st_i2c_flush_rx_fifo(i2c_dev);
481 
482 	if (!c->count)
483 		/* End of xfer, send stop or repstart */
484 		st_i2c_terminate_xfer(i2c_dev);
485 	else
486 		st_i2c_wr_fill_tx_fifo(i2c_dev);
487 }
488 
489 /**
490  * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read
491  * @i2c_dev: Controller's private data
492  */
493 static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev)
494 {
495 	struct st_i2c_client *c = &i2c_dev->client;
496 	u32 ien;
497 
498 	/* Trash the address read back */
499 	if (!c->xfered) {
500 		readl_relaxed(i2c_dev->base + SSC_RBUF);
501 		st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB);
502 	} else {
503 		st_i2c_read_rx_fifo(i2c_dev);
504 	}
505 
506 	if (!c->count) {
507 		/* End of xfer, send stop or repstart */
508 		st_i2c_terminate_xfer(i2c_dev);
509 	} else if (c->count == 1) {
510 		/* Penultimate byte to xfer, disable ACK gen. */
511 		st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG);
512 
513 		/* Last received byte is to be handled by NACK interrupt */
514 		ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN;
515 		writel_relaxed(ien, i2c_dev->base + SSC_IEN);
516 
517 		st_i2c_rd_fill_tx_fifo(i2c_dev, c->count);
518 	} else {
519 		st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1);
520 	}
521 }
522 
523 /**
524  * st_i2c_isr() - Interrupt routine
525  * @irq: interrupt number
526  * @data: Controller's private data
527  */
528 static irqreturn_t st_i2c_isr_thread(int irq, void *data)
529 {
530 	struct st_i2c_dev *i2c_dev = data;
531 	struct st_i2c_client *c = &i2c_dev->client;
532 	u32 sta, ien;
533 	int it;
534 
535 	ien = readl_relaxed(i2c_dev->base + SSC_IEN);
536 	sta = readl_relaxed(i2c_dev->base + SSC_STA);
537 
538 	/* Use __fls() to check error bits first */
539 	it = __fls(sta & ien);
540 	if (it < 0) {
541 		dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n",
542 				sta, ien);
543 		return IRQ_NONE;
544 	}
545 
546 	switch (1 << it) {
547 	case SSC_STA_TE:
548 		if (c->addr & I2C_M_RD)
549 			st_i2c_handle_read(i2c_dev);
550 		else
551 			st_i2c_handle_write(i2c_dev);
552 		break;
553 
554 	case SSC_STA_STOP:
555 	case SSC_STA_REPSTRT:
556 		writel_relaxed(0, i2c_dev->base + SSC_IEN);
557 		complete(&i2c_dev->complete);
558 		break;
559 
560 	case SSC_STA_NACK:
561 		writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR);
562 
563 		/* Last received byte handled by NACK interrupt */
564 		if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) {
565 			st_i2c_handle_read(i2c_dev);
566 			break;
567 		}
568 
569 		it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
570 		writel_relaxed(it, i2c_dev->base + SSC_IEN);
571 
572 		st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
573 		c->result = -EIO;
574 		break;
575 
576 	case SSC_STA_ARBL:
577 		writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR);
578 
579 		it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
580 		writel_relaxed(it, i2c_dev->base + SSC_IEN);
581 
582 		st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
583 		c->result = -EAGAIN;
584 		break;
585 
586 	default:
587 		dev_err(i2c_dev->dev,
588 				"it %d unhandled (sta=0x%04x)\n", it, sta);
589 	}
590 
591 	/*
592 	 * Read IEN register to ensure interrupt mask write is effective
593 	 * before re-enabling interrupt at GIC level, and thus avoid spurious
594 	 * interrupts.
595 	 */
596 	readl(i2c_dev->base + SSC_IEN);
597 
598 	return IRQ_HANDLED;
599 }
600 
601 /**
602  * st_i2c_xfer_msg() - Transfer a single I2C message
603  * @i2c_dev: Controller's private data
604  * @msg: I2C message to transfer
605  * @is_first: first message of the sequence
606  * @is_last: last message of the sequence
607  */
608 static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg,
609 			    bool is_first, bool is_last)
610 {
611 	struct st_i2c_client *c = &i2c_dev->client;
612 	u32 ctl, i2c, it;
613 	unsigned long timeout;
614 	int ret;
615 
616 	c->addr		= (u8)(msg->addr << 1);
617 	c->addr		|= (msg->flags & I2C_M_RD);
618 	c->buf		= msg->buf;
619 	c->count	= msg->len;
620 	c->xfered	= 0;
621 	c->result	= 0;
622 	c->stop		= is_last;
623 
624 	reinit_completion(&i2c_dev->complete);
625 
626 	ctl = SSC_CTL_EN | SSC_CTL_MS |	SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
627 	st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
628 
629 	i2c = SSC_I2C_TXENB;
630 	if (c->addr & I2C_M_RD)
631 		i2c |= SSC_I2C_ACKG;
632 	st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c);
633 
634 	/* Write slave address */
635 	st_i2c_write_tx_fifo(i2c_dev, c->addr);
636 
637 	/* Pre-fill Tx fifo with data in case of write */
638 	if (!(c->addr & I2C_M_RD))
639 		st_i2c_wr_fill_tx_fifo(i2c_dev);
640 
641 	it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN;
642 	writel_relaxed(it, i2c_dev->base + SSC_IEN);
643 
644 	if (is_first) {
645 		ret = st_i2c_wait_free_bus(i2c_dev);
646 		if (ret)
647 			return ret;
648 
649 		st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
650 	}
651 
652 	timeout = wait_for_completion_timeout(&i2c_dev->complete,
653 			i2c_dev->adap.timeout);
654 	ret = c->result;
655 
656 	if (!timeout) {
657 		dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n",
658 				c->addr);
659 		ret = -ETIMEDOUT;
660 	}
661 
662 	i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG;
663 	st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c);
664 
665 	writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT,
666 			i2c_dev->base + SSC_CLR);
667 
668 	return ret;
669 }
670 
671 /**
672  * st_i2c_xfer() - Transfer a single I2C message
673  * @i2c_adap: Adapter pointer to the controller
674  * @msgs: Pointer to data to be written.
675  * @num: Number of messages to be executed
676  */
677 static int st_i2c_xfer(struct i2c_adapter *i2c_adap,
678 			struct i2c_msg msgs[], int num)
679 {
680 	struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
681 	int ret, i;
682 
683 	i2c_dev->busy = true;
684 
685 	ret = clk_prepare_enable(i2c_dev->clk);
686 	if (ret) {
687 		dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
688 		return ret;
689 	}
690 
691 	pinctrl_pm_select_default_state(i2c_dev->dev);
692 
693 	st_i2c_hw_config(i2c_dev);
694 
695 	for (i = 0; (i < num) && !ret; i++)
696 		ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1);
697 
698 	pinctrl_pm_select_idle_state(i2c_dev->dev);
699 
700 	clk_disable_unprepare(i2c_dev->clk);
701 
702 	i2c_dev->busy = false;
703 
704 	return (ret < 0) ? ret : i;
705 }
706 
707 #ifdef CONFIG_PM_SLEEP
708 static int st_i2c_suspend(struct device *dev)
709 {
710 	struct platform_device *pdev =
711 		container_of(dev, struct platform_device, dev);
712 	struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
713 
714 	if (i2c_dev->busy)
715 		return -EBUSY;
716 
717 	pinctrl_pm_select_sleep_state(dev);
718 
719 	return 0;
720 }
721 
722 static int st_i2c_resume(struct device *dev)
723 {
724 	pinctrl_pm_select_default_state(dev);
725 	/* Go in idle state if available */
726 	pinctrl_pm_select_idle_state(dev);
727 
728 	return 0;
729 }
730 
731 static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume);
732 #define ST_I2C_PM	(&st_i2c_pm)
733 #else
734 #define ST_I2C_PM	NULL
735 #endif
736 
737 static u32 st_i2c_func(struct i2c_adapter *adap)
738 {
739 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
740 }
741 
742 static struct i2c_algorithm st_i2c_algo = {
743 	.master_xfer = st_i2c_xfer,
744 	.functionality = st_i2c_func,
745 };
746 
747 static int st_i2c_of_get_deglitch(struct device_node *np,
748 		struct st_i2c_dev *i2c_dev)
749 {
750 	int ret;
751 
752 	ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us",
753 			&i2c_dev->scl_min_width_us);
754 	if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
755 		dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n");
756 		return ret;
757 	}
758 
759 	ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us",
760 			&i2c_dev->sda_min_width_us);
761 	if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
762 		dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n");
763 		return ret;
764 	}
765 
766 	return 0;
767 }
768 
769 static int st_i2c_probe(struct platform_device *pdev)
770 {
771 	struct device_node *np = pdev->dev.of_node;
772 	struct st_i2c_dev *i2c_dev;
773 	struct resource *res;
774 	u32 clk_rate;
775 	struct i2c_adapter *adap;
776 	int ret;
777 
778 	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
779 	if (!i2c_dev)
780 		return -ENOMEM;
781 
782 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
783 	i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
784 	if (IS_ERR(i2c_dev->base))
785 		return PTR_ERR(i2c_dev->base);
786 
787 	i2c_dev->irq = irq_of_parse_and_map(np, 0);
788 	if (!i2c_dev->irq) {
789 		dev_err(&pdev->dev, "IRQ missing or invalid\n");
790 		return -EINVAL;
791 	}
792 
793 	i2c_dev->clk = of_clk_get_by_name(np, "ssc");
794 	if (IS_ERR(i2c_dev->clk)) {
795 		dev_err(&pdev->dev, "Unable to request clock\n");
796 		return PTR_ERR(i2c_dev->clk);
797 	}
798 
799 	i2c_dev->mode = I2C_MODE_STANDARD;
800 	ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
801 	if ((!ret) && (clk_rate == 400000))
802 		i2c_dev->mode = I2C_MODE_FAST;
803 
804 	i2c_dev->dev = &pdev->dev;
805 
806 	ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq,
807 			NULL, st_i2c_isr_thread,
808 			IRQF_ONESHOT, pdev->name, i2c_dev);
809 	if (ret) {
810 		dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
811 		return ret;
812 	}
813 
814 	pinctrl_pm_select_default_state(i2c_dev->dev);
815 	/* In case idle state available, select it */
816 	pinctrl_pm_select_idle_state(i2c_dev->dev);
817 
818 	ret = st_i2c_of_get_deglitch(np, i2c_dev);
819 	if (ret)
820 		return ret;
821 
822 	adap = &i2c_dev->adap;
823 	i2c_set_adapdata(adap, i2c_dev);
824 	snprintf(adap->name, sizeof(adap->name), "ST I2C(0x%pa)", &res->start);
825 	adap->owner = THIS_MODULE;
826 	adap->timeout = 2 * HZ;
827 	adap->retries = 0;
828 	adap->algo = &st_i2c_algo;
829 	adap->dev.parent = &pdev->dev;
830 	adap->dev.of_node = pdev->dev.of_node;
831 
832 	init_completion(&i2c_dev->complete);
833 
834 	ret = i2c_add_adapter(adap);
835 	if (ret) {
836 		dev_err(&pdev->dev, "Failed to add adapter\n");
837 		return ret;
838 	}
839 
840 	platform_set_drvdata(pdev, i2c_dev);
841 
842 	dev_info(i2c_dev->dev, "%s initialized\n", adap->name);
843 
844 	return 0;
845 }
846 
847 static int st_i2c_remove(struct platform_device *pdev)
848 {
849 	struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
850 
851 	i2c_del_adapter(&i2c_dev->adap);
852 
853 	return 0;
854 }
855 
856 static const struct of_device_id st_i2c_match[] = {
857 	{ .compatible = "st,comms-ssc-i2c", },
858 	{ .compatible = "st,comms-ssc4-i2c", },
859 	{},
860 };
861 MODULE_DEVICE_TABLE(of, st_i2c_match);
862 
863 static struct platform_driver st_i2c_driver = {
864 	.driver = {
865 		.name = "st-i2c",
866 		.of_match_table = st_i2c_match,
867 		.pm = ST_I2C_PM,
868 	},
869 	.probe = st_i2c_probe,
870 	.remove = st_i2c_remove,
871 };
872 
873 module_platform_driver(st_i2c_driver);
874 
875 MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>");
876 MODULE_DESCRIPTION("STMicroelectronics I2C driver");
877 MODULE_LICENSE("GPL v2");
878