185b4fab2SMaxime COQUELIN /* 285b4fab2SMaxime COQUELIN * Copyright (C) 2013 STMicroelectronics 385b4fab2SMaxime COQUELIN * 485b4fab2SMaxime COQUELIN * I2C master mode controller driver, used in STMicroelectronics devices. 585b4fab2SMaxime COQUELIN * 685b4fab2SMaxime COQUELIN * Author: Maxime Coquelin <maxime.coquelin@st.com> 785b4fab2SMaxime COQUELIN * 885b4fab2SMaxime COQUELIN * This program is free software; you can redistribute it and/or modify 985b4fab2SMaxime COQUELIN * it under the terms of the GNU General Public License version 2, as 1085b4fab2SMaxime COQUELIN * published by the Free Software Foundation. 1185b4fab2SMaxime COQUELIN */ 1285b4fab2SMaxime COQUELIN 1385b4fab2SMaxime COQUELIN #include <linux/clk.h> 1485b4fab2SMaxime COQUELIN #include <linux/delay.h> 1585b4fab2SMaxime COQUELIN #include <linux/err.h> 16fcdd5f09SWolfram Sang #include <linux/i2c.h> 17fcdd5f09SWolfram Sang #include <linux/interrupt.h> 18fcdd5f09SWolfram Sang #include <linux/io.h> 19fcdd5f09SWolfram Sang #include <linux/module.h> 2085b4fab2SMaxime COQUELIN #include <linux/of_address.h> 2185b4fab2SMaxime COQUELIN #include <linux/of_irq.h> 22fcdd5f09SWolfram Sang #include <linux/of.h> 23fcdd5f09SWolfram Sang #include <linux/pinctrl/consumer.h> 24fcdd5f09SWolfram Sang #include <linux/platform_device.h> 2585b4fab2SMaxime COQUELIN 2685b4fab2SMaxime COQUELIN /* SSC registers */ 2785b4fab2SMaxime COQUELIN #define SSC_BRG 0x000 2885b4fab2SMaxime COQUELIN #define SSC_TBUF 0x004 2985b4fab2SMaxime COQUELIN #define SSC_RBUF 0x008 3085b4fab2SMaxime COQUELIN #define SSC_CTL 0x00C 3185b4fab2SMaxime COQUELIN #define SSC_IEN 0x010 3285b4fab2SMaxime COQUELIN #define SSC_STA 0x014 3385b4fab2SMaxime COQUELIN #define SSC_I2C 0x018 3485b4fab2SMaxime COQUELIN #define SSC_SLAD 0x01C 3585b4fab2SMaxime COQUELIN #define SSC_REP_START_HOLD 0x020 3685b4fab2SMaxime COQUELIN #define SSC_START_HOLD 0x024 3785b4fab2SMaxime COQUELIN #define SSC_REP_START_SETUP 0x028 3885b4fab2SMaxime COQUELIN #define SSC_DATA_SETUP 0x02C 3985b4fab2SMaxime COQUELIN #define SSC_STOP_SETUP 0x030 4085b4fab2SMaxime COQUELIN #define SSC_BUS_FREE 0x034 4185b4fab2SMaxime COQUELIN #define SSC_TX_FSTAT 0x038 4285b4fab2SMaxime COQUELIN #define SSC_RX_FSTAT 0x03C 4385b4fab2SMaxime COQUELIN #define SSC_PRE_SCALER_BRG 0x040 4485b4fab2SMaxime COQUELIN #define SSC_CLR 0x080 4585b4fab2SMaxime COQUELIN #define SSC_NOISE_SUPP_WIDTH 0x100 4685b4fab2SMaxime COQUELIN #define SSC_PRSCALER 0x104 4785b4fab2SMaxime COQUELIN #define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108 4885b4fab2SMaxime COQUELIN #define SSC_PRSCALER_DATAOUT 0x10c 4985b4fab2SMaxime COQUELIN 5085b4fab2SMaxime COQUELIN /* SSC Control */ 5185b4fab2SMaxime COQUELIN #define SSC_CTL_DATA_WIDTH_9 0x8 5285b4fab2SMaxime COQUELIN #define SSC_CTL_DATA_WIDTH_MSK 0xf 5385b4fab2SMaxime COQUELIN #define SSC_CTL_BM 0xf 5485b4fab2SMaxime COQUELIN #define SSC_CTL_HB BIT(4) 5585b4fab2SMaxime COQUELIN #define SSC_CTL_PH BIT(5) 5685b4fab2SMaxime COQUELIN #define SSC_CTL_PO BIT(6) 5785b4fab2SMaxime COQUELIN #define SSC_CTL_SR BIT(7) 5885b4fab2SMaxime COQUELIN #define SSC_CTL_MS BIT(8) 5985b4fab2SMaxime COQUELIN #define SSC_CTL_EN BIT(9) 6085b4fab2SMaxime COQUELIN #define SSC_CTL_LPB BIT(10) 6185b4fab2SMaxime COQUELIN #define SSC_CTL_EN_TX_FIFO BIT(11) 6285b4fab2SMaxime COQUELIN #define SSC_CTL_EN_RX_FIFO BIT(12) 6385b4fab2SMaxime COQUELIN #define SSC_CTL_EN_CLST_RX BIT(13) 6485b4fab2SMaxime COQUELIN 6585b4fab2SMaxime COQUELIN /* SSC Interrupt Enable */ 6685b4fab2SMaxime COQUELIN #define SSC_IEN_RIEN BIT(0) 6785b4fab2SMaxime COQUELIN #define SSC_IEN_TIEN BIT(1) 6885b4fab2SMaxime COQUELIN #define SSC_IEN_TEEN BIT(2) 6985b4fab2SMaxime COQUELIN #define SSC_IEN_REEN BIT(3) 7085b4fab2SMaxime COQUELIN #define SSC_IEN_PEEN BIT(4) 7185b4fab2SMaxime COQUELIN #define SSC_IEN_AASEN BIT(6) 7285b4fab2SMaxime COQUELIN #define SSC_IEN_STOPEN BIT(7) 7385b4fab2SMaxime COQUELIN #define SSC_IEN_ARBLEN BIT(8) 7485b4fab2SMaxime COQUELIN #define SSC_IEN_NACKEN BIT(10) 7585b4fab2SMaxime COQUELIN #define SSC_IEN_REPSTRTEN BIT(11) 7685b4fab2SMaxime COQUELIN #define SSC_IEN_TX_FIFO_HALF BIT(12) 7785b4fab2SMaxime COQUELIN #define SSC_IEN_RX_FIFO_HALF_FULL BIT(14) 7885b4fab2SMaxime COQUELIN 7985b4fab2SMaxime COQUELIN /* SSC Status */ 8085b4fab2SMaxime COQUELIN #define SSC_STA_RIR BIT(0) 8185b4fab2SMaxime COQUELIN #define SSC_STA_TIR BIT(1) 8285b4fab2SMaxime COQUELIN #define SSC_STA_TE BIT(2) 8385b4fab2SMaxime COQUELIN #define SSC_STA_RE BIT(3) 8485b4fab2SMaxime COQUELIN #define SSC_STA_PE BIT(4) 8585b4fab2SMaxime COQUELIN #define SSC_STA_CLST BIT(5) 8685b4fab2SMaxime COQUELIN #define SSC_STA_AAS BIT(6) 8785b4fab2SMaxime COQUELIN #define SSC_STA_STOP BIT(7) 8885b4fab2SMaxime COQUELIN #define SSC_STA_ARBL BIT(8) 8985b4fab2SMaxime COQUELIN #define SSC_STA_BUSY BIT(9) 9085b4fab2SMaxime COQUELIN #define SSC_STA_NACK BIT(10) 9185b4fab2SMaxime COQUELIN #define SSC_STA_REPSTRT BIT(11) 9285b4fab2SMaxime COQUELIN #define SSC_STA_TX_FIFO_HALF BIT(12) 9385b4fab2SMaxime COQUELIN #define SSC_STA_TX_FIFO_FULL BIT(13) 9485b4fab2SMaxime COQUELIN #define SSC_STA_RX_FIFO_HALF BIT(14) 9585b4fab2SMaxime COQUELIN 9685b4fab2SMaxime COQUELIN /* SSC I2C Control */ 9785b4fab2SMaxime COQUELIN #define SSC_I2C_I2CM BIT(0) 9885b4fab2SMaxime COQUELIN #define SSC_I2C_STRTG BIT(1) 9985b4fab2SMaxime COQUELIN #define SSC_I2C_STOPG BIT(2) 10085b4fab2SMaxime COQUELIN #define SSC_I2C_ACKG BIT(3) 10185b4fab2SMaxime COQUELIN #define SSC_I2C_AD10 BIT(4) 10285b4fab2SMaxime COQUELIN #define SSC_I2C_TXENB BIT(5) 10385b4fab2SMaxime COQUELIN #define SSC_I2C_REPSTRTG BIT(11) 10485b4fab2SMaxime COQUELIN #define SSC_I2C_SLAVE_DISABLE BIT(12) 10585b4fab2SMaxime COQUELIN 10685b4fab2SMaxime COQUELIN /* SSC Tx FIFO Status */ 10785b4fab2SMaxime COQUELIN #define SSC_TX_FSTAT_STATUS 0x07 10885b4fab2SMaxime COQUELIN 10985b4fab2SMaxime COQUELIN /* SSC Rx FIFO Status */ 11085b4fab2SMaxime COQUELIN #define SSC_RX_FSTAT_STATUS 0x07 11185b4fab2SMaxime COQUELIN 11285b4fab2SMaxime COQUELIN /* SSC Clear bit operation */ 11385b4fab2SMaxime COQUELIN #define SSC_CLR_SSCAAS BIT(6) 11485b4fab2SMaxime COQUELIN #define SSC_CLR_SSCSTOP BIT(7) 11585b4fab2SMaxime COQUELIN #define SSC_CLR_SSCARBL BIT(8) 11685b4fab2SMaxime COQUELIN #define SSC_CLR_NACK BIT(10) 11785b4fab2SMaxime COQUELIN #define SSC_CLR_REPSTRT BIT(11) 11885b4fab2SMaxime COQUELIN 11985b4fab2SMaxime COQUELIN /* SSC Clock Prescaler */ 12085b4fab2SMaxime COQUELIN #define SSC_PRSC_VALUE 0x0f 12185b4fab2SMaxime COQUELIN 12285b4fab2SMaxime COQUELIN 12385b4fab2SMaxime COQUELIN #define SSC_TXFIFO_SIZE 0x8 12485b4fab2SMaxime COQUELIN #define SSC_RXFIFO_SIZE 0x8 12585b4fab2SMaxime COQUELIN 12685b4fab2SMaxime COQUELIN enum st_i2c_mode { 12785b4fab2SMaxime COQUELIN I2C_MODE_STANDARD, 12885b4fab2SMaxime COQUELIN I2C_MODE_FAST, 12985b4fab2SMaxime COQUELIN I2C_MODE_END, 13085b4fab2SMaxime COQUELIN }; 13185b4fab2SMaxime COQUELIN 13285b4fab2SMaxime COQUELIN /** 13385b4fab2SMaxime COQUELIN * struct st_i2c_timings - per-Mode tuning parameters 13485b4fab2SMaxime COQUELIN * @rate: I2C bus rate 13585b4fab2SMaxime COQUELIN * @rep_start_hold: I2C repeated start hold time requirement 13685b4fab2SMaxime COQUELIN * @rep_start_setup: I2C repeated start set up time requirement 13785b4fab2SMaxime COQUELIN * @start_hold: I2C start hold time requirement 13885b4fab2SMaxime COQUELIN * @data_setup_time: I2C data set up time requirement 13985b4fab2SMaxime COQUELIN * @stop_setup_time: I2C stop set up time requirement 14085b4fab2SMaxime COQUELIN * @bus_free_time: I2C bus free time requirement 14185b4fab2SMaxime COQUELIN * @sda_pulse_min_limit: I2C SDA pulse mini width limit 14285b4fab2SMaxime COQUELIN */ 14385b4fab2SMaxime COQUELIN struct st_i2c_timings { 14485b4fab2SMaxime COQUELIN u32 rate; 14585b4fab2SMaxime COQUELIN u32 rep_start_hold; 14685b4fab2SMaxime COQUELIN u32 rep_start_setup; 14785b4fab2SMaxime COQUELIN u32 start_hold; 14885b4fab2SMaxime COQUELIN u32 data_setup_time; 14985b4fab2SMaxime COQUELIN u32 stop_setup_time; 15085b4fab2SMaxime COQUELIN u32 bus_free_time; 15185b4fab2SMaxime COQUELIN u32 sda_pulse_min_limit; 15285b4fab2SMaxime COQUELIN }; 15385b4fab2SMaxime COQUELIN 15485b4fab2SMaxime COQUELIN /** 15585b4fab2SMaxime COQUELIN * struct st_i2c_client - client specific data 15685b4fab2SMaxime COQUELIN * @addr: 8-bit slave addr, including r/w bit 15785b4fab2SMaxime COQUELIN * @count: number of bytes to be transfered 15885b4fab2SMaxime COQUELIN * @xfered: number of bytes already transferred 15985b4fab2SMaxime COQUELIN * @buf: data buffer 16085b4fab2SMaxime COQUELIN * @result: result of the transfer 16185b4fab2SMaxime COQUELIN * @stop: last I2C msg to be sent, i.e. STOP to be generated 16285b4fab2SMaxime COQUELIN */ 16385b4fab2SMaxime COQUELIN struct st_i2c_client { 16485b4fab2SMaxime COQUELIN u8 addr; 16585b4fab2SMaxime COQUELIN u32 count; 16685b4fab2SMaxime COQUELIN u32 xfered; 16785b4fab2SMaxime COQUELIN u8 *buf; 16885b4fab2SMaxime COQUELIN int result; 16985b4fab2SMaxime COQUELIN bool stop; 17085b4fab2SMaxime COQUELIN }; 17185b4fab2SMaxime COQUELIN 17285b4fab2SMaxime COQUELIN /** 17385b4fab2SMaxime COQUELIN * struct st_i2c_dev - private data of the controller 17485b4fab2SMaxime COQUELIN * @adap: I2C adapter for this controller 17585b4fab2SMaxime COQUELIN * @dev: device for this controller 17685b4fab2SMaxime COQUELIN * @base: virtual memory area 17785b4fab2SMaxime COQUELIN * @complete: completion of I2C message 17885b4fab2SMaxime COQUELIN * @irq: interrupt line for th controller 17985b4fab2SMaxime COQUELIN * @clk: hw ssc block clock 18085b4fab2SMaxime COQUELIN * @mode: I2C mode of the controller. Standard or Fast only supported 18185b4fab2SMaxime COQUELIN * @scl_min_width_us: SCL line minimum pulse width in us 18285b4fab2SMaxime COQUELIN * @sda_min_width_us: SDA line minimum pulse width in us 18385b4fab2SMaxime COQUELIN * @client: I2C transfert information 18485b4fab2SMaxime COQUELIN * @busy: I2C transfer on-going 18585b4fab2SMaxime COQUELIN */ 18685b4fab2SMaxime COQUELIN struct st_i2c_dev { 18785b4fab2SMaxime COQUELIN struct i2c_adapter adap; 18885b4fab2SMaxime COQUELIN struct device *dev; 18985b4fab2SMaxime COQUELIN void __iomem *base; 19085b4fab2SMaxime COQUELIN struct completion complete; 19185b4fab2SMaxime COQUELIN int irq; 19285b4fab2SMaxime COQUELIN struct clk *clk; 19385b4fab2SMaxime COQUELIN int mode; 19485b4fab2SMaxime COQUELIN u32 scl_min_width_us; 19585b4fab2SMaxime COQUELIN u32 sda_min_width_us; 19685b4fab2SMaxime COQUELIN struct st_i2c_client client; 19785b4fab2SMaxime COQUELIN bool busy; 19885b4fab2SMaxime COQUELIN }; 19985b4fab2SMaxime COQUELIN 20085b4fab2SMaxime COQUELIN static inline void st_i2c_set_bits(void __iomem *reg, u32 mask) 20185b4fab2SMaxime COQUELIN { 20285b4fab2SMaxime COQUELIN writel_relaxed(readl_relaxed(reg) | mask, reg); 20385b4fab2SMaxime COQUELIN } 20485b4fab2SMaxime COQUELIN 20585b4fab2SMaxime COQUELIN static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask) 20685b4fab2SMaxime COQUELIN { 20785b4fab2SMaxime COQUELIN writel_relaxed(readl_relaxed(reg) & ~mask, reg); 20885b4fab2SMaxime COQUELIN } 20985b4fab2SMaxime COQUELIN 21052976fa7SMaxime COQUELIN /* 21152976fa7SMaxime COQUELIN * From I2C Specifications v0.5. 21252976fa7SMaxime COQUELIN * 21352976fa7SMaxime COQUELIN * All the values below have +10% margin added to be 21452976fa7SMaxime COQUELIN * compatible with some out-of-spec devices, 21552976fa7SMaxime COQUELIN * like HDMI link of the Toshiba 19AV600 TV. 21652976fa7SMaxime COQUELIN */ 21785b4fab2SMaxime COQUELIN static struct st_i2c_timings i2c_timings[] = { 21885b4fab2SMaxime COQUELIN [I2C_MODE_STANDARD] = { 21985b4fab2SMaxime COQUELIN .rate = 100000, 22052976fa7SMaxime COQUELIN .rep_start_hold = 4400, 22152976fa7SMaxime COQUELIN .rep_start_setup = 5170, 22252976fa7SMaxime COQUELIN .start_hold = 4400, 22352976fa7SMaxime COQUELIN .data_setup_time = 275, 22452976fa7SMaxime COQUELIN .stop_setup_time = 4400, 22552976fa7SMaxime COQUELIN .bus_free_time = 5170, 22685b4fab2SMaxime COQUELIN }, 22785b4fab2SMaxime COQUELIN [I2C_MODE_FAST] = { 22885b4fab2SMaxime COQUELIN .rate = 400000, 22952976fa7SMaxime COQUELIN .rep_start_hold = 660, 23052976fa7SMaxime COQUELIN .rep_start_setup = 660, 23152976fa7SMaxime COQUELIN .start_hold = 660, 23252976fa7SMaxime COQUELIN .data_setup_time = 110, 23352976fa7SMaxime COQUELIN .stop_setup_time = 660, 23452976fa7SMaxime COQUELIN .bus_free_time = 1430, 23585b4fab2SMaxime COQUELIN }, 23685b4fab2SMaxime COQUELIN }; 23785b4fab2SMaxime COQUELIN 23885b4fab2SMaxime COQUELIN static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev) 23985b4fab2SMaxime COQUELIN { 24085b4fab2SMaxime COQUELIN int count, i; 24185b4fab2SMaxime COQUELIN 24285b4fab2SMaxime COQUELIN /* 24385b4fab2SMaxime COQUELIN * Counter only counts up to 7 but fifo size is 8... 24485b4fab2SMaxime COQUELIN * When fifo is full, counter is 0 and RIR bit of status register is 24585b4fab2SMaxime COQUELIN * set 24685b4fab2SMaxime COQUELIN */ 24785b4fab2SMaxime COQUELIN if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) 24885b4fab2SMaxime COQUELIN count = SSC_RXFIFO_SIZE; 24985b4fab2SMaxime COQUELIN else 25085b4fab2SMaxime COQUELIN count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & 25185b4fab2SMaxime COQUELIN SSC_RX_FSTAT_STATUS; 25285b4fab2SMaxime COQUELIN 25385b4fab2SMaxime COQUELIN for (i = 0; i < count; i++) 25485b4fab2SMaxime COQUELIN readl_relaxed(i2c_dev->base + SSC_RBUF); 25585b4fab2SMaxime COQUELIN } 25685b4fab2SMaxime COQUELIN 25785b4fab2SMaxime COQUELIN static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev) 25885b4fab2SMaxime COQUELIN { 25985b4fab2SMaxime COQUELIN /* 26085b4fab2SMaxime COQUELIN * FIFO needs to be emptied before reseting the IP, 26185b4fab2SMaxime COQUELIN * else the controller raises a BUSY error. 26285b4fab2SMaxime COQUELIN */ 26385b4fab2SMaxime COQUELIN st_i2c_flush_rx_fifo(i2c_dev); 26485b4fab2SMaxime COQUELIN 26585b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 26685b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 26785b4fab2SMaxime COQUELIN } 26885b4fab2SMaxime COQUELIN 26985b4fab2SMaxime COQUELIN /** 27085b4fab2SMaxime COQUELIN * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings 27185b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 27285b4fab2SMaxime COQUELIN */ 27385b4fab2SMaxime COQUELIN static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev) 27485b4fab2SMaxime COQUELIN { 27585b4fab2SMaxime COQUELIN unsigned long rate; 27685b4fab2SMaxime COQUELIN u32 val, ns_per_clk; 27785b4fab2SMaxime COQUELIN struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode]; 27885b4fab2SMaxime COQUELIN 27985b4fab2SMaxime COQUELIN st_i2c_soft_reset(i2c_dev); 28085b4fab2SMaxime COQUELIN 28185b4fab2SMaxime COQUELIN val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL | 28285b4fab2SMaxime COQUELIN SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP; 28385b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_CLR); 28485b4fab2SMaxime COQUELIN 28585b4fab2SMaxime COQUELIN /* SSC Control register setup */ 28685b4fab2SMaxime COQUELIN val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9; 28785b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_CTL); 28885b4fab2SMaxime COQUELIN 28985b4fab2SMaxime COQUELIN rate = clk_get_rate(i2c_dev->clk); 29085b4fab2SMaxime COQUELIN ns_per_clk = 1000000000 / rate; 29185b4fab2SMaxime COQUELIN 29285b4fab2SMaxime COQUELIN /* Baudrate */ 29385b4fab2SMaxime COQUELIN val = rate / (2 * t->rate); 29485b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_BRG); 29585b4fab2SMaxime COQUELIN 29685b4fab2SMaxime COQUELIN /* Pre-scaler baudrate */ 29785b4fab2SMaxime COQUELIN writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); 29885b4fab2SMaxime COQUELIN 29985b4fab2SMaxime COQUELIN /* Enable I2C mode */ 30085b4fab2SMaxime COQUELIN writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); 30185b4fab2SMaxime COQUELIN 30285b4fab2SMaxime COQUELIN /* Repeated start hold time */ 30385b4fab2SMaxime COQUELIN val = t->rep_start_hold / ns_per_clk; 30485b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); 30585b4fab2SMaxime COQUELIN 30685b4fab2SMaxime COQUELIN /* Repeated start set up time */ 30785b4fab2SMaxime COQUELIN val = t->rep_start_setup / ns_per_clk; 30885b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); 30985b4fab2SMaxime COQUELIN 31085b4fab2SMaxime COQUELIN /* Start hold time */ 31185b4fab2SMaxime COQUELIN val = t->start_hold / ns_per_clk; 31285b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); 31385b4fab2SMaxime COQUELIN 31485b4fab2SMaxime COQUELIN /* Data set up time */ 31585b4fab2SMaxime COQUELIN val = t->data_setup_time / ns_per_clk; 31685b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP); 31785b4fab2SMaxime COQUELIN 31885b4fab2SMaxime COQUELIN /* Stop set up time */ 31985b4fab2SMaxime COQUELIN val = t->stop_setup_time / ns_per_clk; 32085b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP); 32185b4fab2SMaxime COQUELIN 32285b4fab2SMaxime COQUELIN /* Bus free time */ 32385b4fab2SMaxime COQUELIN val = t->bus_free_time / ns_per_clk; 32485b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE); 32585b4fab2SMaxime COQUELIN 32685b4fab2SMaxime COQUELIN /* Prescalers set up */ 32785b4fab2SMaxime COQUELIN val = rate / 10000000; 32885b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_PRSCALER); 32985b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT); 33085b4fab2SMaxime COQUELIN 33185b4fab2SMaxime COQUELIN /* Noise suppression witdh */ 33285b4fab2SMaxime COQUELIN val = i2c_dev->scl_min_width_us * rate / 100000000; 33385b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH); 33485b4fab2SMaxime COQUELIN 33585b4fab2SMaxime COQUELIN /* Noise suppression max output data delay width */ 33685b4fab2SMaxime COQUELIN val = i2c_dev->sda_min_width_us * rate / 100000000; 33785b4fab2SMaxime COQUELIN writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT); 33885b4fab2SMaxime COQUELIN } 33985b4fab2SMaxime COQUELIN 34040027b2fSPeter Griffin static int st_i2c_recover_bus(struct i2c_adapter *i2c_adap) 34140027b2fSPeter Griffin { 34240027b2fSPeter Griffin struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 34340027b2fSPeter Griffin u32 ctl; 34440027b2fSPeter Griffin 34540027b2fSPeter Griffin dev_dbg(i2c_dev->dev, "Trying to recover bus\n"); 34640027b2fSPeter Griffin 34740027b2fSPeter Griffin /* 34840027b2fSPeter Griffin * SSP IP is dual role SPI/I2C to generate 9 clock pulses 34940027b2fSPeter Griffin * we switch to SPI node, 9 bit words and write a 0. This 35040027b2fSPeter Griffin * has been validate with a oscilloscope and is easier 35140027b2fSPeter Griffin * than switching to GPIO mode. 35240027b2fSPeter Griffin */ 35340027b2fSPeter Griffin 35440027b2fSPeter Griffin /* Disable interrupts */ 35540027b2fSPeter Griffin writel_relaxed(0, i2c_dev->base + SSC_IEN); 35640027b2fSPeter Griffin 35740027b2fSPeter Griffin st_i2c_hw_config(i2c_dev); 35840027b2fSPeter Griffin 35940027b2fSPeter Griffin ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO; 36040027b2fSPeter Griffin st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); 36140027b2fSPeter Griffin 36240027b2fSPeter Griffin st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM); 36340027b2fSPeter Griffin usleep_range(8000, 10000); 36440027b2fSPeter Griffin 36540027b2fSPeter Griffin writel_relaxed(0, i2c_dev->base + SSC_TBUF); 36640027b2fSPeter Griffin usleep_range(2000, 4000); 36740027b2fSPeter Griffin st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM); 36840027b2fSPeter Griffin 36940027b2fSPeter Griffin return 0; 37040027b2fSPeter Griffin } 37140027b2fSPeter Griffin 37285b4fab2SMaxime COQUELIN static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev) 37385b4fab2SMaxime COQUELIN { 37485b4fab2SMaxime COQUELIN u32 sta; 37540027b2fSPeter Griffin int i, ret; 37685b4fab2SMaxime COQUELIN 37785b4fab2SMaxime COQUELIN for (i = 0; i < 10; i++) { 37885b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 37985b4fab2SMaxime COQUELIN if (!(sta & SSC_STA_BUSY)) 38085b4fab2SMaxime COQUELIN return 0; 38185b4fab2SMaxime COQUELIN 38285b4fab2SMaxime COQUELIN usleep_range(2000, 4000); 38385b4fab2SMaxime COQUELIN } 38485b4fab2SMaxime COQUELIN 38585b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta); 38685b4fab2SMaxime COQUELIN 38740027b2fSPeter Griffin ret = i2c_recover_bus(&i2c_dev->adap); 38840027b2fSPeter Griffin if (ret) { 38940027b2fSPeter Griffin dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); 39040027b2fSPeter Griffin return ret; 39140027b2fSPeter Griffin } 39240027b2fSPeter Griffin 39385b4fab2SMaxime COQUELIN return -EBUSY; 39485b4fab2SMaxime COQUELIN } 39585b4fab2SMaxime COQUELIN 39685b4fab2SMaxime COQUELIN /** 39785b4fab2SMaxime COQUELIN * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO 39885b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 39985b4fab2SMaxime COQUELIN * @byte: Data to write in the Tx FIFO 40085b4fab2SMaxime COQUELIN */ 40185b4fab2SMaxime COQUELIN static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte) 40285b4fab2SMaxime COQUELIN { 40385b4fab2SMaxime COQUELIN u16 tbuf = byte << 1; 40485b4fab2SMaxime COQUELIN 40585b4fab2SMaxime COQUELIN writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF); 40685b4fab2SMaxime COQUELIN } 40785b4fab2SMaxime COQUELIN 40885b4fab2SMaxime COQUELIN /** 40985b4fab2SMaxime COQUELIN * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode 41085b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 41185b4fab2SMaxime COQUELIN * 41285b4fab2SMaxime COQUELIN * This functions fills the Tx FIFO with I2C transfert buffer when 41385b4fab2SMaxime COQUELIN * in write mode. 41485b4fab2SMaxime COQUELIN */ 41585b4fab2SMaxime COQUELIN static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev) 41685b4fab2SMaxime COQUELIN { 41785b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 41885b4fab2SMaxime COQUELIN u32 tx_fstat, sta; 41985b4fab2SMaxime COQUELIN int i; 42085b4fab2SMaxime COQUELIN 42185b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 42285b4fab2SMaxime COQUELIN if (sta & SSC_STA_TX_FIFO_FULL) 42385b4fab2SMaxime COQUELIN return; 42485b4fab2SMaxime COQUELIN 42585b4fab2SMaxime COQUELIN tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); 42685b4fab2SMaxime COQUELIN tx_fstat &= SSC_TX_FSTAT_STATUS; 42785b4fab2SMaxime COQUELIN 42885b4fab2SMaxime COQUELIN if (c->count < (SSC_TXFIFO_SIZE - tx_fstat)) 42985b4fab2SMaxime COQUELIN i = c->count; 43085b4fab2SMaxime COQUELIN else 43185b4fab2SMaxime COQUELIN i = SSC_TXFIFO_SIZE - tx_fstat; 43285b4fab2SMaxime COQUELIN 43385b4fab2SMaxime COQUELIN for (; i > 0; i--, c->count--, c->buf++) 43485b4fab2SMaxime COQUELIN st_i2c_write_tx_fifo(i2c_dev, *c->buf); 43585b4fab2SMaxime COQUELIN } 43685b4fab2SMaxime COQUELIN 43785b4fab2SMaxime COQUELIN /** 43885b4fab2SMaxime COQUELIN * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode 43985b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 44085b4fab2SMaxime COQUELIN * 44185b4fab2SMaxime COQUELIN * This functions fills the Tx FIFO with fixed pattern when 44285b4fab2SMaxime COQUELIN * in read mode to trigger clock. 44385b4fab2SMaxime COQUELIN */ 44485b4fab2SMaxime COQUELIN static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max) 44585b4fab2SMaxime COQUELIN { 44685b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 44785b4fab2SMaxime COQUELIN u32 tx_fstat, sta; 44885b4fab2SMaxime COQUELIN int i; 44985b4fab2SMaxime COQUELIN 45085b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 45185b4fab2SMaxime COQUELIN if (sta & SSC_STA_TX_FIFO_FULL) 45285b4fab2SMaxime COQUELIN return; 45385b4fab2SMaxime COQUELIN 45485b4fab2SMaxime COQUELIN tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); 45585b4fab2SMaxime COQUELIN tx_fstat &= SSC_TX_FSTAT_STATUS; 45685b4fab2SMaxime COQUELIN 45785b4fab2SMaxime COQUELIN if (max < (SSC_TXFIFO_SIZE - tx_fstat)) 45885b4fab2SMaxime COQUELIN i = max; 45985b4fab2SMaxime COQUELIN else 46085b4fab2SMaxime COQUELIN i = SSC_TXFIFO_SIZE - tx_fstat; 46185b4fab2SMaxime COQUELIN 46285b4fab2SMaxime COQUELIN for (; i > 0; i--, c->xfered++) 46385b4fab2SMaxime COQUELIN st_i2c_write_tx_fifo(i2c_dev, 0xff); 46485b4fab2SMaxime COQUELIN } 46585b4fab2SMaxime COQUELIN 46685b4fab2SMaxime COQUELIN static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev) 46785b4fab2SMaxime COQUELIN { 46885b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 46985b4fab2SMaxime COQUELIN u32 i, sta; 47085b4fab2SMaxime COQUELIN u16 rbuf; 47185b4fab2SMaxime COQUELIN 47285b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 47385b4fab2SMaxime COQUELIN if (sta & SSC_STA_RIR) { 47485b4fab2SMaxime COQUELIN i = SSC_RXFIFO_SIZE; 47585b4fab2SMaxime COQUELIN } else { 47685b4fab2SMaxime COQUELIN i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT); 47785b4fab2SMaxime COQUELIN i &= SSC_RX_FSTAT_STATUS; 47885b4fab2SMaxime COQUELIN } 47985b4fab2SMaxime COQUELIN 48085b4fab2SMaxime COQUELIN for (; (i > 0) && (c->count > 0); i--, c->count--) { 48185b4fab2SMaxime COQUELIN rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1; 48285b4fab2SMaxime COQUELIN *c->buf++ = (u8)rbuf & 0xff; 48385b4fab2SMaxime COQUELIN } 48485b4fab2SMaxime COQUELIN 48585b4fab2SMaxime COQUELIN if (i) { 48685b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i); 48785b4fab2SMaxime COQUELIN st_i2c_flush_rx_fifo(i2c_dev); 48885b4fab2SMaxime COQUELIN } 48985b4fab2SMaxime COQUELIN } 49085b4fab2SMaxime COQUELIN 49185b4fab2SMaxime COQUELIN /** 49285b4fab2SMaxime COQUELIN * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition 49385b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 49485b4fab2SMaxime COQUELIN */ 49585b4fab2SMaxime COQUELIN static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev) 49685b4fab2SMaxime COQUELIN { 49785b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 49885b4fab2SMaxime COQUELIN 49985b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN); 50085b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); 50185b4fab2SMaxime COQUELIN 50285b4fab2SMaxime COQUELIN if (c->stop) { 50385b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN); 50485b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 50585b4fab2SMaxime COQUELIN } else { 50685b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN); 50785b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG); 50885b4fab2SMaxime COQUELIN } 50985b4fab2SMaxime COQUELIN } 51085b4fab2SMaxime COQUELIN 51185b4fab2SMaxime COQUELIN /** 51285b4fab2SMaxime COQUELIN * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write 51385b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 51485b4fab2SMaxime COQUELIN */ 51585b4fab2SMaxime COQUELIN static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev) 51685b4fab2SMaxime COQUELIN { 51785b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 51885b4fab2SMaxime COQUELIN 51985b4fab2SMaxime COQUELIN st_i2c_flush_rx_fifo(i2c_dev); 52085b4fab2SMaxime COQUELIN 52185b4fab2SMaxime COQUELIN if (!c->count) 52285b4fab2SMaxime COQUELIN /* End of xfer, send stop or repstart */ 52385b4fab2SMaxime COQUELIN st_i2c_terminate_xfer(i2c_dev); 52485b4fab2SMaxime COQUELIN else 52585b4fab2SMaxime COQUELIN st_i2c_wr_fill_tx_fifo(i2c_dev); 52685b4fab2SMaxime COQUELIN } 52785b4fab2SMaxime COQUELIN 52885b4fab2SMaxime COQUELIN /** 52985b4fab2SMaxime COQUELIN * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read 53085b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 53185b4fab2SMaxime COQUELIN */ 53285b4fab2SMaxime COQUELIN static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev) 53385b4fab2SMaxime COQUELIN { 53485b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 53585b4fab2SMaxime COQUELIN u32 ien; 53685b4fab2SMaxime COQUELIN 53785b4fab2SMaxime COQUELIN /* Trash the address read back */ 53885b4fab2SMaxime COQUELIN if (!c->xfered) { 53985b4fab2SMaxime COQUELIN readl_relaxed(i2c_dev->base + SSC_RBUF); 54085b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB); 54185b4fab2SMaxime COQUELIN } else { 54285b4fab2SMaxime COQUELIN st_i2c_read_rx_fifo(i2c_dev); 54385b4fab2SMaxime COQUELIN } 54485b4fab2SMaxime COQUELIN 54585b4fab2SMaxime COQUELIN if (!c->count) { 54685b4fab2SMaxime COQUELIN /* End of xfer, send stop or repstart */ 54785b4fab2SMaxime COQUELIN st_i2c_terminate_xfer(i2c_dev); 54885b4fab2SMaxime COQUELIN } else if (c->count == 1) { 54985b4fab2SMaxime COQUELIN /* Penultimate byte to xfer, disable ACK gen. */ 55085b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG); 55185b4fab2SMaxime COQUELIN 55285b4fab2SMaxime COQUELIN /* Last received byte is to be handled by NACK interrupt */ 55385b4fab2SMaxime COQUELIN ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN; 55485b4fab2SMaxime COQUELIN writel_relaxed(ien, i2c_dev->base + SSC_IEN); 55585b4fab2SMaxime COQUELIN 55685b4fab2SMaxime COQUELIN st_i2c_rd_fill_tx_fifo(i2c_dev, c->count); 55785b4fab2SMaxime COQUELIN } else { 55885b4fab2SMaxime COQUELIN st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1); 55985b4fab2SMaxime COQUELIN } 56085b4fab2SMaxime COQUELIN } 56185b4fab2SMaxime COQUELIN 56285b4fab2SMaxime COQUELIN /** 56385b4fab2SMaxime COQUELIN * st_i2c_isr() - Interrupt routine 56485b4fab2SMaxime COQUELIN * @irq: interrupt number 56585b4fab2SMaxime COQUELIN * @data: Controller's private data 56685b4fab2SMaxime COQUELIN */ 56785b4fab2SMaxime COQUELIN static irqreturn_t st_i2c_isr_thread(int irq, void *data) 56885b4fab2SMaxime COQUELIN { 56985b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev = data; 57085b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 57185b4fab2SMaxime COQUELIN u32 sta, ien; 57285b4fab2SMaxime COQUELIN int it; 57385b4fab2SMaxime COQUELIN 57485b4fab2SMaxime COQUELIN ien = readl_relaxed(i2c_dev->base + SSC_IEN); 57585b4fab2SMaxime COQUELIN sta = readl_relaxed(i2c_dev->base + SSC_STA); 57685b4fab2SMaxime COQUELIN 57785b4fab2SMaxime COQUELIN /* Use __fls() to check error bits first */ 57885b4fab2SMaxime COQUELIN it = __fls(sta & ien); 57985b4fab2SMaxime COQUELIN if (it < 0) { 58085b4fab2SMaxime COQUELIN dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n", 58185b4fab2SMaxime COQUELIN sta, ien); 58285b4fab2SMaxime COQUELIN return IRQ_NONE; 58385b4fab2SMaxime COQUELIN } 58485b4fab2SMaxime COQUELIN 58585b4fab2SMaxime COQUELIN switch (1 << it) { 58685b4fab2SMaxime COQUELIN case SSC_STA_TE: 58785b4fab2SMaxime COQUELIN if (c->addr & I2C_M_RD) 58885b4fab2SMaxime COQUELIN st_i2c_handle_read(i2c_dev); 58985b4fab2SMaxime COQUELIN else 59085b4fab2SMaxime COQUELIN st_i2c_handle_write(i2c_dev); 59185b4fab2SMaxime COQUELIN break; 59285b4fab2SMaxime COQUELIN 59385b4fab2SMaxime COQUELIN case SSC_STA_STOP: 59485b4fab2SMaxime COQUELIN case SSC_STA_REPSTRT: 59585b4fab2SMaxime COQUELIN writel_relaxed(0, i2c_dev->base + SSC_IEN); 59685b4fab2SMaxime COQUELIN complete(&i2c_dev->complete); 59785b4fab2SMaxime COQUELIN break; 59885b4fab2SMaxime COQUELIN 59985b4fab2SMaxime COQUELIN case SSC_STA_NACK: 60085b4fab2SMaxime COQUELIN writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR); 60185b4fab2SMaxime COQUELIN 60285b4fab2SMaxime COQUELIN /* Last received byte handled by NACK interrupt */ 60385b4fab2SMaxime COQUELIN if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) { 60485b4fab2SMaxime COQUELIN st_i2c_handle_read(i2c_dev); 60585b4fab2SMaxime COQUELIN break; 60685b4fab2SMaxime COQUELIN } 60785b4fab2SMaxime COQUELIN 60885b4fab2SMaxime COQUELIN it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; 60985b4fab2SMaxime COQUELIN writel_relaxed(it, i2c_dev->base + SSC_IEN); 61085b4fab2SMaxime COQUELIN 61185b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 61285b4fab2SMaxime COQUELIN c->result = -EIO; 61385b4fab2SMaxime COQUELIN break; 61485b4fab2SMaxime COQUELIN 61585b4fab2SMaxime COQUELIN case SSC_STA_ARBL: 61685b4fab2SMaxime COQUELIN writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR); 61785b4fab2SMaxime COQUELIN 61885b4fab2SMaxime COQUELIN it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; 61985b4fab2SMaxime COQUELIN writel_relaxed(it, i2c_dev->base + SSC_IEN); 62085b4fab2SMaxime COQUELIN 62185b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); 6224fda9962SMaxime COQUELIN c->result = -EAGAIN; 62385b4fab2SMaxime COQUELIN break; 62485b4fab2SMaxime COQUELIN 62585b4fab2SMaxime COQUELIN default: 62685b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, 62785b4fab2SMaxime COQUELIN "it %d unhandled (sta=0x%04x)\n", it, sta); 62885b4fab2SMaxime COQUELIN } 62985b4fab2SMaxime COQUELIN 63085b4fab2SMaxime COQUELIN /* 63185b4fab2SMaxime COQUELIN * Read IEN register to ensure interrupt mask write is effective 63285b4fab2SMaxime COQUELIN * before re-enabling interrupt at GIC level, and thus avoid spurious 63385b4fab2SMaxime COQUELIN * interrupts. 63485b4fab2SMaxime COQUELIN */ 63585b4fab2SMaxime COQUELIN readl(i2c_dev->base + SSC_IEN); 63685b4fab2SMaxime COQUELIN 63785b4fab2SMaxime COQUELIN return IRQ_HANDLED; 63885b4fab2SMaxime COQUELIN } 63985b4fab2SMaxime COQUELIN 64085b4fab2SMaxime COQUELIN /** 64185b4fab2SMaxime COQUELIN * st_i2c_xfer_msg() - Transfer a single I2C message 64285b4fab2SMaxime COQUELIN * @i2c_dev: Controller's private data 64385b4fab2SMaxime COQUELIN * @msg: I2C message to transfer 64485b4fab2SMaxime COQUELIN * @is_first: first message of the sequence 64585b4fab2SMaxime COQUELIN * @is_last: last message of the sequence 64685b4fab2SMaxime COQUELIN */ 64785b4fab2SMaxime COQUELIN static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg, 64885b4fab2SMaxime COQUELIN bool is_first, bool is_last) 64985b4fab2SMaxime COQUELIN { 65085b4fab2SMaxime COQUELIN struct st_i2c_client *c = &i2c_dev->client; 65185b4fab2SMaxime COQUELIN u32 ctl, i2c, it; 65285b4fab2SMaxime COQUELIN unsigned long timeout; 65385b4fab2SMaxime COQUELIN int ret; 65485b4fab2SMaxime COQUELIN 655a51a79d5SWolfram Sang c->addr = i2c_8bit_addr_from_msg(msg); 65685b4fab2SMaxime COQUELIN c->buf = msg->buf; 65785b4fab2SMaxime COQUELIN c->count = msg->len; 65885b4fab2SMaxime COQUELIN c->xfered = 0; 65985b4fab2SMaxime COQUELIN c->result = 0; 66085b4fab2SMaxime COQUELIN c->stop = is_last; 66185b4fab2SMaxime COQUELIN 66213509c3aSLinus Torvalds reinit_completion(&i2c_dev->complete); 66385b4fab2SMaxime COQUELIN 66485b4fab2SMaxime COQUELIN ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO; 66585b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); 66685b4fab2SMaxime COQUELIN 66785b4fab2SMaxime COQUELIN i2c = SSC_I2C_TXENB; 66885b4fab2SMaxime COQUELIN if (c->addr & I2C_M_RD) 66985b4fab2SMaxime COQUELIN i2c |= SSC_I2C_ACKG; 67085b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c); 67185b4fab2SMaxime COQUELIN 67285b4fab2SMaxime COQUELIN /* Write slave address */ 67385b4fab2SMaxime COQUELIN st_i2c_write_tx_fifo(i2c_dev, c->addr); 67485b4fab2SMaxime COQUELIN 67585b4fab2SMaxime COQUELIN /* Pre-fill Tx fifo with data in case of write */ 67685b4fab2SMaxime COQUELIN if (!(c->addr & I2C_M_RD)) 67785b4fab2SMaxime COQUELIN st_i2c_wr_fill_tx_fifo(i2c_dev); 67885b4fab2SMaxime COQUELIN 67985b4fab2SMaxime COQUELIN it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN; 68085b4fab2SMaxime COQUELIN writel_relaxed(it, i2c_dev->base + SSC_IEN); 68185b4fab2SMaxime COQUELIN 68285b4fab2SMaxime COQUELIN if (is_first) { 68385b4fab2SMaxime COQUELIN ret = st_i2c_wait_free_bus(i2c_dev); 68485b4fab2SMaxime COQUELIN if (ret) 68585b4fab2SMaxime COQUELIN return ret; 68685b4fab2SMaxime COQUELIN 68785b4fab2SMaxime COQUELIN st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); 68885b4fab2SMaxime COQUELIN } 68985b4fab2SMaxime COQUELIN 69085b4fab2SMaxime COQUELIN timeout = wait_for_completion_timeout(&i2c_dev->complete, 69185b4fab2SMaxime COQUELIN i2c_dev->adap.timeout); 69285b4fab2SMaxime COQUELIN ret = c->result; 69385b4fab2SMaxime COQUELIN 69485b4fab2SMaxime COQUELIN if (!timeout) { 69585b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n", 69685b4fab2SMaxime COQUELIN c->addr); 69785b4fab2SMaxime COQUELIN ret = -ETIMEDOUT; 69885b4fab2SMaxime COQUELIN } 69985b4fab2SMaxime COQUELIN 70085b4fab2SMaxime COQUELIN i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG; 70185b4fab2SMaxime COQUELIN st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c); 70285b4fab2SMaxime COQUELIN 70385b4fab2SMaxime COQUELIN writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT, 70485b4fab2SMaxime COQUELIN i2c_dev->base + SSC_CLR); 70585b4fab2SMaxime COQUELIN 70685b4fab2SMaxime COQUELIN return ret; 70785b4fab2SMaxime COQUELIN } 70885b4fab2SMaxime COQUELIN 70985b4fab2SMaxime COQUELIN /** 71085b4fab2SMaxime COQUELIN * st_i2c_xfer() - Transfer a single I2C message 71185b4fab2SMaxime COQUELIN * @i2c_adap: Adapter pointer to the controller 71285b4fab2SMaxime COQUELIN * @msgs: Pointer to data to be written. 71385b4fab2SMaxime COQUELIN * @num: Number of messages to be executed 71485b4fab2SMaxime COQUELIN */ 71585b4fab2SMaxime COQUELIN static int st_i2c_xfer(struct i2c_adapter *i2c_adap, 71685b4fab2SMaxime COQUELIN struct i2c_msg msgs[], int num) 71785b4fab2SMaxime COQUELIN { 71885b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 71985b4fab2SMaxime COQUELIN int ret, i; 72085b4fab2SMaxime COQUELIN 72185b4fab2SMaxime COQUELIN i2c_dev->busy = true; 72285b4fab2SMaxime COQUELIN 72385b4fab2SMaxime COQUELIN ret = clk_prepare_enable(i2c_dev->clk); 72485b4fab2SMaxime COQUELIN if (ret) { 72585b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); 72685b4fab2SMaxime COQUELIN return ret; 72785b4fab2SMaxime COQUELIN } 72885b4fab2SMaxime COQUELIN 72985b4fab2SMaxime COQUELIN pinctrl_pm_select_default_state(i2c_dev->dev); 73085b4fab2SMaxime COQUELIN 73185b4fab2SMaxime COQUELIN st_i2c_hw_config(i2c_dev); 73285b4fab2SMaxime COQUELIN 73385b4fab2SMaxime COQUELIN for (i = 0; (i < num) && !ret; i++) 73485b4fab2SMaxime COQUELIN ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1); 73585b4fab2SMaxime COQUELIN 73685b4fab2SMaxime COQUELIN pinctrl_pm_select_idle_state(i2c_dev->dev); 73785b4fab2SMaxime COQUELIN 73885b4fab2SMaxime COQUELIN clk_disable_unprepare(i2c_dev->clk); 73985b4fab2SMaxime COQUELIN 74085b4fab2SMaxime COQUELIN i2c_dev->busy = false; 74185b4fab2SMaxime COQUELIN 74285b4fab2SMaxime COQUELIN return (ret < 0) ? ret : i; 74385b4fab2SMaxime COQUELIN } 74485b4fab2SMaxime COQUELIN 74585b4fab2SMaxime COQUELIN #ifdef CONFIG_PM_SLEEP 74685b4fab2SMaxime COQUELIN static int st_i2c_suspend(struct device *dev) 74785b4fab2SMaxime COQUELIN { 7489242e72aSMasahiro Yamada struct st_i2c_dev *i2c_dev = dev_get_drvdata(dev); 74985b4fab2SMaxime COQUELIN 75085b4fab2SMaxime COQUELIN if (i2c_dev->busy) 75185b4fab2SMaxime COQUELIN return -EBUSY; 75285b4fab2SMaxime COQUELIN 75385b4fab2SMaxime COQUELIN pinctrl_pm_select_sleep_state(dev); 75485b4fab2SMaxime COQUELIN 75585b4fab2SMaxime COQUELIN return 0; 75685b4fab2SMaxime COQUELIN } 75785b4fab2SMaxime COQUELIN 75885b4fab2SMaxime COQUELIN static int st_i2c_resume(struct device *dev) 75985b4fab2SMaxime COQUELIN { 76085b4fab2SMaxime COQUELIN pinctrl_pm_select_default_state(dev); 76185b4fab2SMaxime COQUELIN /* Go in idle state if available */ 76285b4fab2SMaxime COQUELIN pinctrl_pm_select_idle_state(dev); 76385b4fab2SMaxime COQUELIN 76485b4fab2SMaxime COQUELIN return 0; 76585b4fab2SMaxime COQUELIN } 76685b4fab2SMaxime COQUELIN 76785b4fab2SMaxime COQUELIN static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume); 76885b4fab2SMaxime COQUELIN #define ST_I2C_PM (&st_i2c_pm) 76985b4fab2SMaxime COQUELIN #else 77085b4fab2SMaxime COQUELIN #define ST_I2C_PM NULL 77185b4fab2SMaxime COQUELIN #endif 77285b4fab2SMaxime COQUELIN 77385b4fab2SMaxime COQUELIN static u32 st_i2c_func(struct i2c_adapter *adap) 77485b4fab2SMaxime COQUELIN { 77585b4fab2SMaxime COQUELIN return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 77685b4fab2SMaxime COQUELIN } 77785b4fab2SMaxime COQUELIN 77892d9d0dfSBhumika Goyal static const struct i2c_algorithm st_i2c_algo = { 77985b4fab2SMaxime COQUELIN .master_xfer = st_i2c_xfer, 78085b4fab2SMaxime COQUELIN .functionality = st_i2c_func, 78185b4fab2SMaxime COQUELIN }; 78285b4fab2SMaxime COQUELIN 78340027b2fSPeter Griffin static struct i2c_bus_recovery_info st_i2c_recovery_info = { 78440027b2fSPeter Griffin .recover_bus = st_i2c_recover_bus, 78540027b2fSPeter Griffin }; 78640027b2fSPeter Griffin 78785b4fab2SMaxime COQUELIN static int st_i2c_of_get_deglitch(struct device_node *np, 78885b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev) 78985b4fab2SMaxime COQUELIN { 79085b4fab2SMaxime COQUELIN int ret; 79185b4fab2SMaxime COQUELIN 79285b4fab2SMaxime COQUELIN ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us", 79385b4fab2SMaxime COQUELIN &i2c_dev->scl_min_width_us); 79485b4fab2SMaxime COQUELIN if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { 79585b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n"); 79685b4fab2SMaxime COQUELIN return ret; 79785b4fab2SMaxime COQUELIN } 79885b4fab2SMaxime COQUELIN 79985b4fab2SMaxime COQUELIN ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us", 80085b4fab2SMaxime COQUELIN &i2c_dev->sda_min_width_us); 80185b4fab2SMaxime COQUELIN if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { 80285b4fab2SMaxime COQUELIN dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n"); 80385b4fab2SMaxime COQUELIN return ret; 80485b4fab2SMaxime COQUELIN } 80585b4fab2SMaxime COQUELIN 80685b4fab2SMaxime COQUELIN return 0; 80785b4fab2SMaxime COQUELIN } 80885b4fab2SMaxime COQUELIN 80985b4fab2SMaxime COQUELIN static int st_i2c_probe(struct platform_device *pdev) 81085b4fab2SMaxime COQUELIN { 81185b4fab2SMaxime COQUELIN struct device_node *np = pdev->dev.of_node; 81285b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev; 81385b4fab2SMaxime COQUELIN struct resource *res; 81485b4fab2SMaxime COQUELIN u32 clk_rate; 81585b4fab2SMaxime COQUELIN struct i2c_adapter *adap; 81685b4fab2SMaxime COQUELIN int ret; 81785b4fab2SMaxime COQUELIN 81885b4fab2SMaxime COQUELIN i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 81985b4fab2SMaxime COQUELIN if (!i2c_dev) 82085b4fab2SMaxime COQUELIN return -ENOMEM; 82185b4fab2SMaxime COQUELIN 82285b4fab2SMaxime COQUELIN res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 82385b4fab2SMaxime COQUELIN i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 82485b4fab2SMaxime COQUELIN if (IS_ERR(i2c_dev->base)) 82585b4fab2SMaxime COQUELIN return PTR_ERR(i2c_dev->base); 82685b4fab2SMaxime COQUELIN 82785b4fab2SMaxime COQUELIN i2c_dev->irq = irq_of_parse_and_map(np, 0); 82885b4fab2SMaxime COQUELIN if (!i2c_dev->irq) { 82985b4fab2SMaxime COQUELIN dev_err(&pdev->dev, "IRQ missing or invalid\n"); 83085b4fab2SMaxime COQUELIN return -EINVAL; 83185b4fab2SMaxime COQUELIN } 83285b4fab2SMaxime COQUELIN 83385b4fab2SMaxime COQUELIN i2c_dev->clk = of_clk_get_by_name(np, "ssc"); 83485b4fab2SMaxime COQUELIN if (IS_ERR(i2c_dev->clk)) { 83585b4fab2SMaxime COQUELIN dev_err(&pdev->dev, "Unable to request clock\n"); 83685b4fab2SMaxime COQUELIN return PTR_ERR(i2c_dev->clk); 83785b4fab2SMaxime COQUELIN } 83885b4fab2SMaxime COQUELIN 83985b4fab2SMaxime COQUELIN i2c_dev->mode = I2C_MODE_STANDARD; 84085b4fab2SMaxime COQUELIN ret = of_property_read_u32(np, "clock-frequency", &clk_rate); 84185b4fab2SMaxime COQUELIN if ((!ret) && (clk_rate == 400000)) 84285b4fab2SMaxime COQUELIN i2c_dev->mode = I2C_MODE_FAST; 84385b4fab2SMaxime COQUELIN 84485b4fab2SMaxime COQUELIN i2c_dev->dev = &pdev->dev; 84585b4fab2SMaxime COQUELIN 84685b4fab2SMaxime COQUELIN ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq, 84785b4fab2SMaxime COQUELIN NULL, st_i2c_isr_thread, 84885b4fab2SMaxime COQUELIN IRQF_ONESHOT, pdev->name, i2c_dev); 84985b4fab2SMaxime COQUELIN if (ret) { 85085b4fab2SMaxime COQUELIN dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 85185b4fab2SMaxime COQUELIN return ret; 85285b4fab2SMaxime COQUELIN } 85385b4fab2SMaxime COQUELIN 85485b4fab2SMaxime COQUELIN pinctrl_pm_select_default_state(i2c_dev->dev); 85585b4fab2SMaxime COQUELIN /* In case idle state available, select it */ 85685b4fab2SMaxime COQUELIN pinctrl_pm_select_idle_state(i2c_dev->dev); 85785b4fab2SMaxime COQUELIN 85885b4fab2SMaxime COQUELIN ret = st_i2c_of_get_deglitch(np, i2c_dev); 85985b4fab2SMaxime COQUELIN if (ret) 86085b4fab2SMaxime COQUELIN return ret; 86185b4fab2SMaxime COQUELIN 86285b4fab2SMaxime COQUELIN adap = &i2c_dev->adap; 86385b4fab2SMaxime COQUELIN i2c_set_adapdata(adap, i2c_dev); 864a07f0ad7SDmitry V. Krivenok snprintf(adap->name, sizeof(adap->name), "ST I2C(%pa)", &res->start); 86585b4fab2SMaxime COQUELIN adap->owner = THIS_MODULE; 86685b4fab2SMaxime COQUELIN adap->timeout = 2 * HZ; 86785b4fab2SMaxime COQUELIN adap->retries = 0; 86885b4fab2SMaxime COQUELIN adap->algo = &st_i2c_algo; 86940027b2fSPeter Griffin adap->bus_recovery_info = &st_i2c_recovery_info; 87085b4fab2SMaxime COQUELIN adap->dev.parent = &pdev->dev; 87185b4fab2SMaxime COQUELIN adap->dev.of_node = pdev->dev.of_node; 87285b4fab2SMaxime COQUELIN 87385b4fab2SMaxime COQUELIN init_completion(&i2c_dev->complete); 87485b4fab2SMaxime COQUELIN 87585b4fab2SMaxime COQUELIN ret = i2c_add_adapter(adap); 876ea734404SWolfram Sang if (ret) 87785b4fab2SMaxime COQUELIN return ret; 87885b4fab2SMaxime COQUELIN 87985b4fab2SMaxime COQUELIN platform_set_drvdata(pdev, i2c_dev); 88085b4fab2SMaxime COQUELIN 88185b4fab2SMaxime COQUELIN dev_info(i2c_dev->dev, "%s initialized\n", adap->name); 88285b4fab2SMaxime COQUELIN 88385b4fab2SMaxime COQUELIN return 0; 88485b4fab2SMaxime COQUELIN } 88585b4fab2SMaxime COQUELIN 88685b4fab2SMaxime COQUELIN static int st_i2c_remove(struct platform_device *pdev) 88785b4fab2SMaxime COQUELIN { 88885b4fab2SMaxime COQUELIN struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 88985b4fab2SMaxime COQUELIN 89085b4fab2SMaxime COQUELIN i2c_del_adapter(&i2c_dev->adap); 89185b4fab2SMaxime COQUELIN 89285b4fab2SMaxime COQUELIN return 0; 89385b4fab2SMaxime COQUELIN } 89485b4fab2SMaxime COQUELIN 895eae45e5dSJingoo Han static const struct of_device_id st_i2c_match[] = { 89685b4fab2SMaxime COQUELIN { .compatible = "st,comms-ssc-i2c", }, 89785b4fab2SMaxime COQUELIN { .compatible = "st,comms-ssc4-i2c", }, 89885b4fab2SMaxime COQUELIN {}, 89985b4fab2SMaxime COQUELIN }; 90085b4fab2SMaxime COQUELIN MODULE_DEVICE_TABLE(of, st_i2c_match); 90185b4fab2SMaxime COQUELIN 90285b4fab2SMaxime COQUELIN static struct platform_driver st_i2c_driver = { 90385b4fab2SMaxime COQUELIN .driver = { 90485b4fab2SMaxime COQUELIN .name = "st-i2c", 90585b4fab2SMaxime COQUELIN .of_match_table = st_i2c_match, 90685b4fab2SMaxime COQUELIN .pm = ST_I2C_PM, 90785b4fab2SMaxime COQUELIN }, 90885b4fab2SMaxime COQUELIN .probe = st_i2c_probe, 90985b4fab2SMaxime COQUELIN .remove = st_i2c_remove, 91085b4fab2SMaxime COQUELIN }; 91185b4fab2SMaxime COQUELIN 91285b4fab2SMaxime COQUELIN module_platform_driver(st_i2c_driver); 91385b4fab2SMaxime COQUELIN 91485b4fab2SMaxime COQUELIN MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>"); 91585b4fab2SMaxime COQUELIN MODULE_DESCRIPTION("STMicroelectronics I2C driver"); 91685b4fab2SMaxime COQUELIN MODULE_LICENSE("GPL v2"); 917